Network.hh revision 10082:70f350b13ec0 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * The Network class is the base class for classes that implement the
31 * interconnection network between components (processor/cache
32 * components and memory/directory components).  The interconnection
33 * network as described here is not a physical network, but a
34 * programming concept used to implement all communication between
35 * components.  Thus parts of this 'network' will model the on-chip
36 * connections between cache controllers and directory controllers as
37 * well as the links between chip and network switches.
38 */
39
40#ifndef __MEM_RUBY_NETWORK_NETWORK_HH__
41#define __MEM_RUBY_NETWORK_NETWORK_HH__
42
43#include <iostream>
44#include <string>
45#include <vector>
46
47#include "mem/protocol/LinkDirection.hh"
48#include "mem/protocol/MessageSizeType.hh"
49#include "mem/ruby/common/TypeDefines.hh"
50#include "mem/ruby/network/Topology.hh"
51#include "mem/packet.hh"
52#include "params/RubyNetwork.hh"
53#include "sim/clocked_object.hh"
54
55class NetDest;
56class MessageBuffer;
57
58class Network : public ClockedObject
59{
60  public:
61    typedef RubyNetworkParams Params;
62    Network(const Params *p);
63    virtual ~Network() {}
64    const Params * params() const
65    { return dynamic_cast<const Params *>(_params);}
66
67    virtual void init();
68
69    static uint32_t getNumberOfVirtualNetworks() { return m_virtual_networks; }
70    static uint32_t MessageSizeType_to_int(MessageSizeType size_type);
71
72    // returns the queue requested for the given component
73    virtual MessageBuffer* getToNetQueue(NodeID id, bool ordered,
74        int netNumber, std::string vnet_type) = 0;
75    virtual MessageBuffer* getFromNetQueue(NodeID id, bool ordered,
76        int netNumber, std::string vnet_type) = 0;
77    virtual int getNumNodes() {return 1;}
78
79    virtual void makeOutLink(SwitchID src, NodeID dest, BasicLink* link,
80                             LinkDirection direction,
81                             const NetDest& routing_table_entry) = 0;
82    virtual void makeInLink(NodeID src, SwitchID dest, BasicLink* link,
83                            LinkDirection direction,
84                            const NetDest& routing_table_entry) = 0;
85    virtual void makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link,
86                                  LinkDirection direction,
87                                  const NetDest& routing_table_entry) = 0;
88
89    virtual void collateStats() = 0;
90    virtual void print(std::ostream& out) const = 0;
91
92    /*
93     * Virtual functions for functionally reading and writing packets in
94     * the network. Each network needs to implement these for functional
95     * accesses to work correctly.
96     */
97    virtual bool functionalRead(Packet *pkt)
98    { fatal("Functional read not implemented.\n"); }
99    virtual uint32_t functionalWrite(Packet *pkt)
100    { fatal("Functional write not implemented.\n"); }
101
102  protected:
103    // Private copy constructor and assignment operator
104    Network(const Network& obj);
105    Network& operator=(const Network& obj);
106
107    uint32_t m_nodes;
108    static uint32_t m_virtual_networks;
109    Topology* m_topology_ptr;
110    static uint32_t m_control_msg_size;
111    static uint32_t m_data_msg_size;
112
113    // vector of queues from the components
114    std::vector<std::vector<MessageBuffer*> > m_toNetQueues;
115    std::vector<std::vector<MessageBuffer*> > m_fromNetQueues;
116
117    std::vector<bool> m_in_use;
118    std::vector<bool> m_ordered;
119
120  private:
121    //! Callback class used for collating statistics from all the
122    //! controller of this type.
123    class StatsCallback : public Callback
124    {
125      private:
126        Network *ctr;
127
128      public:
129        virtual ~StatsCallback() {}
130
131        StatsCallback(Network *_ctr)
132            : ctr(_ctr)
133        {
134        }
135
136        void process() {ctr->collateStats();}
137    };
138};
139
140inline std::ostream&
141operator<<(std::ostream& out, const Network& obj)
142{
143    obj.print(out);
144    out << std::flush;
145    return out;
146}
147
148#endif // __MEM_RUBY_NETWORK_NETWORK_HH__
149