port_proxy.hh revision 12522:463b7803e8dd
1/* 2 * Copyright (c) 2011-2013, 2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andreas Hansson 38 */ 39 40/** 41 * @file 42 * PortProxy Object Declaration. 43 * 44 * Port proxies are used when non-structural entities need access to 45 * the memory system (or structural entities that want to peak into 46 * the memory system without making a real memory access). 47 * 48 * Proxy objects replace the previous FunctionalPort, TranslatingPort 49 * and VirtualPort objects, which provided the same functionality as 50 * the proxies, but were instances of ports not corresponding to real 51 * structural ports of the simulated system. Via the port proxies all 52 * the accesses go through an actual port (either the system port, 53 * e.g. for processes or initialisation, or a the data port of the 54 * CPU, e.g. for threads) and thus are transparent to a potentially 55 * distributed memory and automatically adhere to the memory map of 56 * the system. 57 */ 58 59#ifndef __MEM_PORT_PROXY_HH__ 60#define __MEM_PORT_PROXY_HH__ 61 62#include "config/the_isa.hh" 63#if THE_ISA != NULL_ISA 64 #include "arch/isa_traits.hh" 65#endif 66 67#include "mem/port.hh" 68#include "sim/byteswap.hh" 69 70/** 71 * This object is a proxy for a structural port, to be used for debug 72 * accesses. 73 * 74 * This proxy object is used when non structural entities 75 * (e.g. thread contexts, object file loaders) need access to the 76 * memory system. It calls the corresponding functions on the underlying 77 * structural port, and provides templatized convenience access functions. 78 * 79 * The addresses are interpreted as physical addresses. 80 * 81 * @sa SETranslatingProxy 82 * @sa FSTranslatingProxy 83 */ 84class PortProxy 85{ 86 private: 87 88 /** The actual physical port used by this proxy. */ 89 MasterPort &_port; 90 91 /** Granularity of any transactions issued through this proxy. */ 92 const unsigned int _cacheLineSize; 93 94 public: 95 PortProxy(MasterPort &port, unsigned int cacheLineSize) : 96 _port(port), _cacheLineSize(cacheLineSize) { } 97 virtual ~PortProxy() { } 98 99 /** 100 * Read size bytes memory at address and store in p. 101 */ 102 virtual void readBlob(Addr addr, uint8_t* p, int size) const; 103 104 /** 105 * Write size bytes from p to address. 106 */ 107 virtual void writeBlob(Addr addr, const uint8_t* p, int size) const; 108 109 /** 110 * Fill size bytes starting at addr with byte value val. 111 */ 112 virtual void memsetBlob(Addr addr, uint8_t v, int size) const; 113 114 /** 115 * Read sizeof(T) bytes from address and return as object T. 116 */ 117 template <typename T> 118 T read(Addr address) const; 119 120 /** 121 * Write object T to address. Writes sizeof(T) bytes. 122 */ 123 template <typename T> 124 void write(Addr address, T data) const; 125 126 /** 127 * Read sizeof(T) bytes from address and return as object T. 128 * Performs selected endianness transform. 129 */ 130 template <typename T> 131 T readGtoH(Addr address, ByteOrder guest_byte_order) const; 132 133 /** 134 * Write object T to address. Writes sizeof(T) bytes. 135 * Performs selected endianness transform. 136 */ 137 template <typename T> 138 void writeHtoG(Addr address, T data, ByteOrder guest_byte_order) const; 139 140#if THE_ISA != NULL_ISA 141 /** 142 * Read sizeof(T) bytes from address and return as object T. 143 * Performs Guest to Host endianness transform. 144 */ 145 template <typename T> 146 T readGtoH(Addr address) const; 147 148 /** 149 * Write object T to address. Writes sizeof(T) bytes. 150 * Performs Host to Guest endianness transform. 151 */ 152 template <typename T> 153 void writeHtoG(Addr address, T data) const; 154#endif 155}; 156 157 158template <typename T> 159T 160PortProxy::read(Addr address) const 161{ 162 T data; 163 readBlob(address, (uint8_t*)&data, sizeof(T)); 164 return data; 165} 166 167template <typename T> 168void 169PortProxy::write(Addr address, T data) const 170{ 171 writeBlob(address, (uint8_t*)&data, sizeof(T)); 172} 173 174template <typename T> 175T 176PortProxy::readGtoH(Addr address, ByteOrder byte_order) const 177{ 178 T data; 179 readBlob(address, (uint8_t*)&data, sizeof(T)); 180 return gtoh(data, byte_order); 181} 182 183template <typename T> 184void 185PortProxy::writeHtoG(Addr address, T data, ByteOrder byte_order) const 186{ 187 data = htog(data, byte_order); 188 writeBlob(address, (uint8_t*)&data, sizeof(T)); 189} 190 191#if THE_ISA != NULL_ISA 192template <typename T> 193T 194PortProxy::readGtoH(Addr address) const 195{ 196 T data; 197 readBlob(address, (uint8_t*)&data, sizeof(T)); 198 return TheISA::gtoh(data); 199} 200 201template <typename T> 202void 203PortProxy::writeHtoG(Addr address, T data) const 204{ 205 data = TheISA::htog(data); 206 writeBlob(address, (uint8_t*)&data, sizeof(T)); 207} 208#endif 209 210#endif // __MEM_PORT_PROXY_HH__ 211