page_table.hh revision 9676:83d5112e71dd 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31/**
32 * @file
33 * Declaration of a non-full system Page Table.
34 */
35
36#ifndef __MEM_PAGE_TABLE_HH__
37#define __MEM_PAGE_TABLE_HH__
38
39#include <string>
40
41#include "arch/isa_traits.hh"
42#include "arch/tlb.hh"
43#include "base/hashmap.hh"
44#include "base/types.hh"
45#include "config/the_isa.hh"
46#include "mem/request.hh"
47#include "sim/serialize.hh"
48
49/**
50 * Page Table Declaration.
51 */
52class PageTable
53{
54  protected:
55    typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable;
56    typedef PTable::iterator PTableItr;
57    PTable pTable;
58
59    struct cacheElement {
60        bool valid;
61        Addr vaddr;
62        TheISA::TlbEntry entry;
63    };
64
65    struct cacheElement pTableCache[3];
66
67    const Addr pageSize;
68    const Addr offsetMask;
69
70    const uint64_t pid;
71    const std::string _name;
72
73  public:
74
75    PageTable(const std::string &__name, uint64_t _pid,
76              Addr _pageSize = TheISA::VMPageSize);
77
78    ~PageTable();
79
80    // for DPRINTF compatibility
81    const std::string name() const { return _name; }
82
83    Addr pageAlign(Addr a)  { return (a & ~offsetMask); }
84    Addr pageOffset(Addr a) { return (a &  offsetMask); }
85
86    void map(Addr vaddr, Addr paddr, int64_t size, bool clobber = false);
87    void remap(Addr vaddr, int64_t size, Addr new_vaddr);
88    void unmap(Addr vaddr, int64_t size);
89
90    /**
91     * Check if any pages in a region are already allocated
92     * @param vaddr The starting virtual address of the region.
93     * @param size The length of the region.
94     * @return True if no pages in the region are mapped.
95     */
96    bool isUnmapped(Addr vaddr, int64_t size);
97
98    /**
99     * Lookup function
100     * @param vaddr The virtual address.
101     * @return entry The page table entry corresponding to vaddr.
102     */
103    bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
104
105    /**
106     * Translate function
107     * @param vaddr The virtual address.
108     * @param paddr Physical address from translation.
109     * @return True if translation exists
110     */
111    bool translate(Addr vaddr, Addr &paddr);
112
113    /**
114     * Simplified translate function (just check for translation)
115     * @param vaddr The virtual address.
116     * @return True if translation exists
117     */
118    bool translate(Addr vaddr) { Addr dummy; return translate(vaddr, dummy); }
119
120    /**
121     * Perform a translation on the memory request, fills in paddr
122     * field of req.
123     * @param req The memory request.
124     */
125    Fault translate(RequestPtr req);
126
127    /**
128     * Update the page table cache.
129     * @param vaddr virtual address (page aligned) to check
130     * @param pte page table entry to return
131     */
132    inline void updateCache(Addr vaddr, TheISA::TlbEntry entry)
133    {
134        pTableCache[2].entry = pTableCache[1].entry;
135        pTableCache[2].vaddr = pTableCache[1].vaddr;
136        pTableCache[2].valid = pTableCache[1].valid;
137
138        pTableCache[1].entry = pTableCache[0].entry;
139        pTableCache[1].vaddr = pTableCache[0].vaddr;
140        pTableCache[1].valid = pTableCache[0].valid;
141
142        pTableCache[0].entry = entry;
143        pTableCache[0].vaddr = vaddr;
144        pTableCache[0].valid = true;
145    }
146
147    /**
148     * Erase an entry from the page table cache.
149     * @param vaddr virtual address (page aligned) to check
150     */
151    inline void eraseCacheEntry(Addr vaddr)
152    {
153        // Invalidate cached entries if necessary
154        if (pTableCache[0].valid && pTableCache[0].vaddr == vaddr) {
155            pTableCache[0].valid = false;
156        } else if (pTableCache[1].valid && pTableCache[1].vaddr == vaddr) {
157            pTableCache[1].valid = false;
158        } else if (pTableCache[2].valid && pTableCache[2].vaddr == vaddr) {
159            pTableCache[2].valid = false;
160        }
161    }
162
163    void serialize(std::ostream &os);
164
165    void unserialize(Checkpoint *cp, const std::string &section);
166};
167
168#endif // __MEM_PAGE_TABLE_HH__
169