page_table.cc revision 8763:509e9bb84dfa 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Ron Dreslinski
30 *          Ali Saidi
31 */
32
33/**
34 * @file
35 * Definitions of page table.
36 */
37#include <fstream>
38#include <map>
39#include <string>
40
41#include "base/bitfield.hh"
42#include "base/intmath.hh"
43#include "base/trace.hh"
44#include "config/the_isa.hh"
45#include "debug/MMU.hh"
46#include "mem/page_table.hh"
47#include "sim/faults.hh"
48#include "sim/process.hh"
49#include "sim/sim_object.hh"
50#include "sim/system.hh"
51
52using namespace std;
53using namespace TheISA;
54
55PageTable::PageTable(
56#if !FULL_SYSTEM
57        Process *_process,
58#endif
59        Addr _pageSize)
60    : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize)))
61#if !FULL_SYSTEM
62      , process(_process)
63#endif
64{
65    assert(isPowerOf2(pageSize));
66    pTableCache[0].vaddr = 0;
67    pTableCache[1].vaddr = 0;
68    pTableCache[2].vaddr = 0;
69}
70
71PageTable::~PageTable()
72{
73}
74
75void
76PageTable::allocate(Addr vaddr, int64_t size)
77{
78    // starting address must be page aligned
79    assert(pageOffset(vaddr) == 0);
80
81    DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
82
83    for (; size > 0; size -= pageSize, vaddr += pageSize) {
84        PTableItr iter = pTable.find(vaddr);
85
86        if (iter != pTable.end()) {
87            // already mapped
88            fatal("PageTable::allocate: address 0x%x already mapped",
89                    vaddr);
90        }
91
92#if !FULL_SYSTEM
93        pTable[vaddr] = TheISA::TlbEntry(process->M5_pid, vaddr,
94                process->system->new_page());
95        updateCache(vaddr, pTable[vaddr]);
96#endif
97    }
98}
99
100void
101PageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr)
102{
103    assert(pageOffset(vaddr) == 0);
104    assert(pageOffset(new_vaddr) == 0);
105
106    DPRINTF(MMU, "moving pages from vaddr %08p to %08p, size = %d\n", vaddr,
107            new_vaddr, size);
108
109    for (; size > 0; size -= pageSize, vaddr += pageSize, new_vaddr += pageSize) {
110        PTableItr iter = pTable.find(vaddr);
111
112        assert(iter != pTable.end());
113
114        pTable[new_vaddr] = pTable[vaddr];
115        pTable.erase(vaddr);
116        pTable[new_vaddr].updateVaddr(new_vaddr);
117        updateCache(new_vaddr, pTable[new_vaddr]);
118    }
119}
120
121void
122PageTable::deallocate(Addr vaddr, int64_t size)
123{
124    assert(pageOffset(vaddr) == 0);
125
126    DPRINTF(MMU, "Deallocating page: %#x-%#x\n", vaddr, vaddr+ size);
127
128    for (; size > 0; size -= pageSize, vaddr += pageSize) {
129        PTableItr iter = pTable.find(vaddr);
130
131        assert(iter != pTable.end());
132
133        pTable.erase(vaddr);
134    }
135
136}
137
138bool
139PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry)
140{
141    Addr page_addr = pageAlign(vaddr);
142
143    if (pTableCache[0].vaddr == page_addr) {
144        entry = pTableCache[0].entry;
145        return true;
146    }
147    if (pTableCache[1].vaddr == page_addr) {
148        entry = pTableCache[1].entry;
149        return true;
150    }
151    if (pTableCache[2].vaddr == page_addr) {
152        entry = pTableCache[2].entry;
153        return true;
154    }
155
156    PTableItr iter = pTable.find(page_addr);
157
158    if (iter == pTable.end()) {
159        return false;
160    }
161
162    updateCache(page_addr, iter->second);
163    entry = iter->second;
164    return true;
165}
166
167bool
168PageTable::translate(Addr vaddr, Addr &paddr)
169{
170    TheISA::TlbEntry entry;
171    if (!lookup(vaddr, entry)) {
172        DPRINTF(MMU, "Couldn't Translate: %#x\n", vaddr);
173        return false;
174    }
175    paddr = pageOffset(vaddr) + entry.pageStart();
176    DPRINTF(MMU, "Translating: %#x->%#x\n", vaddr, paddr);
177    return true;
178}
179
180Fault
181PageTable::translate(RequestPtr req)
182{
183    Addr paddr;
184    assert(pageAlign(req->getVaddr() + req->getSize() - 1)
185           == pageAlign(req->getVaddr()));
186    if (!translate(req->getVaddr(), paddr)) {
187        return Fault(new GenericPageTableFault(req->getVaddr()));
188    }
189    req->setPaddr(paddr);
190    if ((paddr & (pageSize - 1)) + req->getSize() > pageSize) {
191        panic("Request spans page boundaries!\n");
192        return NoFault;
193    }
194    return NoFault;
195}
196
197void
198PageTable::serialize(std::ostream &os)
199{
200    paramOut(os, "ptable.size", pTable.size());
201
202    PTable::size_type count = 0;
203
204    PTableItr iter = pTable.begin();
205    PTableItr end = pTable.end();
206    while (iter != end) {
207#if !FULL_SYSTEM
208        os << "\n[" << csprintf("%s.Entry%d", process->name(), count) << "]\n";
209#endif
210
211        paramOut(os, "vaddr", iter->first);
212        iter->second.serialize(os);
213
214        ++iter;
215        ++count;
216    }
217    assert(count == pTable.size());
218}
219
220void
221PageTable::unserialize(Checkpoint *cp, const std::string &section)
222{
223    int i = 0, count;
224    paramIn(cp, section, "ptable.size", count);
225
226    pTable.clear();
227
228    while (i < count) {
229#if !FULL_SYSTEM
230        TheISA::TlbEntry *entry;
231        Addr vaddr;
232
233        paramIn(cp, csprintf("%s.Entry%d", process->name(), i), "vaddr", vaddr);
234        entry = new TheISA::TlbEntry();
235        entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i));
236        pTable[vaddr] = *entry;
237        ++i;
238#endif
239    }
240}
241
242