page_table.cc revision 8600:b0d7c64ada19 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Ron Dreslinski
30 *          Ali Saidi
31 */
32
33/**
34 * @file
35 * Definitions of page table.
36 */
37#include <fstream>
38#include <map>
39#include <string>
40
41#include "base/bitfield.hh"
42#include "base/intmath.hh"
43#include "base/trace.hh"
44#include "config/the_isa.hh"
45#include "debug/MMU.hh"
46#include "mem/page_table.hh"
47#include "sim/faults.hh"
48#include "sim/process.hh"
49#include "sim/sim_object.hh"
50#include "sim/system.hh"
51
52using namespace std;
53using namespace TheISA;
54
55PageTable::PageTable(Process *_process, Addr _pageSize)
56    : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
57      process(_process)
58{
59    assert(isPowerOf2(pageSize));
60    pTableCache[0].vaddr = 0;
61    pTableCache[1].vaddr = 0;
62    pTableCache[2].vaddr = 0;
63}
64
65PageTable::~PageTable()
66{
67}
68
69void
70PageTable::allocate(Addr vaddr, int64_t size, bool clobber)
71{
72    // starting address must be page aligned
73    assert(pageOffset(vaddr) == 0);
74
75    DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
76
77    for (; size > 0; size -= pageSize, vaddr += pageSize) {
78        if (!clobber && (pTable.find(vaddr) != pTable.end())) {
79            // already mapped
80            fatal("PageTable::allocate: address 0x%x already mapped", vaddr);
81        }
82
83        pTable[vaddr] = TheISA::TlbEntry(process->M5_pid, vaddr,
84                                         process->system->new_page());
85        updateCache(vaddr, pTable[vaddr]);
86    }
87}
88
89void
90PageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr)
91{
92    assert(pageOffset(vaddr) == 0);
93    assert(pageOffset(new_vaddr) == 0);
94
95    DPRINTF(MMU, "moving pages from vaddr %08p to %08p, size = %d\n", vaddr,
96            new_vaddr, size);
97
98    for (; size > 0; size -= pageSize, vaddr += pageSize, new_vaddr += pageSize) {
99        PTableItr iter = pTable.find(vaddr);
100
101        assert(iter != pTable.end());
102
103        pTable[new_vaddr] = pTable[vaddr];
104        pTable.erase(vaddr);
105        pTable[new_vaddr].updateVaddr(new_vaddr);
106        updateCache(new_vaddr, pTable[new_vaddr]);
107    }
108}
109
110void
111PageTable::deallocate(Addr vaddr, int64_t size)
112{
113    assert(pageOffset(vaddr) == 0);
114
115    DPRINTF(MMU, "Deallocating page: %#x-%#x\n", vaddr, vaddr+ size);
116
117    for (; size > 0; size -= pageSize, vaddr += pageSize) {
118        PTableItr iter = pTable.find(vaddr);
119
120        assert(iter != pTable.end());
121
122        pTable.erase(vaddr);
123    }
124
125}
126
127bool
128PageTable::isUnmapped(Addr vaddr, int64_t size)
129{
130    // starting address must be page aligned
131    assert(pageOffset(vaddr) == 0);
132
133    for (; size > 0; size -= pageSize, vaddr += pageSize) {
134        if (pTable.find(vaddr) != pTable.end()) {
135            return false;
136        }
137    }
138
139    return true;
140}
141
142bool
143PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry)
144{
145    Addr page_addr = pageAlign(vaddr);
146
147    if (pTableCache[0].vaddr == page_addr) {
148        entry = pTableCache[0].entry;
149        return true;
150    }
151    if (pTableCache[1].vaddr == page_addr) {
152        entry = pTableCache[1].entry;
153        return true;
154    }
155    if (pTableCache[2].vaddr == page_addr) {
156        entry = pTableCache[2].entry;
157        return true;
158    }
159
160    PTableItr iter = pTable.find(page_addr);
161
162    if (iter == pTable.end()) {
163        return false;
164    }
165
166    updateCache(page_addr, iter->second);
167    entry = iter->second;
168    return true;
169}
170
171bool
172PageTable::translate(Addr vaddr, Addr &paddr)
173{
174    TheISA::TlbEntry entry;
175    if (!lookup(vaddr, entry)) {
176        DPRINTF(MMU, "Couldn't Translate: %#x\n", vaddr);
177        return false;
178    }
179    paddr = pageOffset(vaddr) + entry.pageStart();
180    DPRINTF(MMU, "Translating: %#x->%#x\n", vaddr, paddr);
181    return true;
182}
183
184Fault
185PageTable::translate(RequestPtr req)
186{
187    Addr paddr;
188    assert(pageAlign(req->getVaddr() + req->getSize() - 1)
189           == pageAlign(req->getVaddr()));
190    if (!translate(req->getVaddr(), paddr)) {
191        return Fault(new GenericPageTableFault(req->getVaddr()));
192    }
193    req->setPaddr(paddr);
194    if ((paddr & (pageSize - 1)) + req->getSize() > pageSize) {
195        panic("Request spans page boundaries!\n");
196        return NoFault;
197    }
198    return NoFault;
199}
200
201void
202PageTable::serialize(std::ostream &os)
203{
204    paramOut(os, "ptable.size", pTable.size());
205
206    PTable::size_type count = 0;
207
208    PTableItr iter = pTable.begin();
209    PTableItr end = pTable.end();
210    while (iter != end) {
211        os << "\n[" << csprintf("%s.Entry%d", process->name(), count) << "]\n";
212
213        paramOut(os, "vaddr", iter->first);
214        iter->second.serialize(os);
215
216        ++iter;
217        ++count;
218    }
219    assert(count == pTable.size());
220}
221
222void
223PageTable::unserialize(Checkpoint *cp, const std::string &section)
224{
225    int i = 0, count;
226    paramIn(cp, section, "ptable.size", count);
227    Addr vaddr;
228    TheISA::TlbEntry *entry;
229
230    pTable.clear();
231
232    while(i < count) {
233        paramIn(cp, csprintf("%s.Entry%d", process->name(), i), "vaddr", vaddr);
234        entry = new TheISA::TlbEntry();
235        entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i));
236        pTable[vaddr] = *entry;
237        ++i;
238    }
239}
240
241