page_table.cc revision 4762:c94e103c83ad 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Ron Dreslinski
30 *          Ali Saidi
31 */
32
33/**
34 * @file
35 * Definitions of page table.
36 */
37#include <string>
38#include <map>
39#include <fstream>
40
41#include "arch/faults.hh"
42#include "base/bitfield.hh"
43#include "base/intmath.hh"
44#include "base/trace.hh"
45#include "mem/page_table.hh"
46#include "sim/sim_object.hh"
47#include "sim/system.hh"
48
49using namespace std;
50using namespace TheISA;
51
52PageTable::PageTable(System *_system, Addr _pageSize)
53    : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
54      system(_system)
55{
56    assert(isPowerOf2(pageSize));
57    pTableCache[0].vaddr = 0;
58    pTableCache[1].vaddr = 0;
59    pTableCache[2].vaddr = 0;
60}
61
62PageTable::~PageTable()
63{
64}
65
66Fault
67PageTable::page_check(Addr addr, int64_t size) const
68{
69    if (size < sizeof(uint64_t)) {
70        if (!isPowerOf2(size)) {
71            panic("Invalid request size!\n");
72            return genMachineCheckFault();
73        }
74
75        if ((size - 1) & addr)
76            return genAlignmentFault();
77    }
78    else {
79        if ((addr & (VMPageSize - 1)) + size > VMPageSize) {
80            panic("Invalid request size!\n");
81            return genMachineCheckFault();
82        }
83
84        if ((sizeof(uint64_t) - 1) & addr)
85            return genAlignmentFault();
86    }
87
88    return NoFault;
89}
90
91
92void
93PageTable::allocate(Addr vaddr, int64_t size)
94{
95    // starting address must be page aligned
96    assert(pageOffset(vaddr) == 0);
97
98    DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
99
100    for (; size > 0; size -= pageSize, vaddr += pageSize) {
101        m5::hash_map<Addr,Addr>::iterator iter = pTable.find(vaddr);
102
103        if (iter != pTable.end()) {
104            // already mapped
105            fatal("PageTable::allocate: address 0x%x already mapped", vaddr);
106        }
107
108        pTable[vaddr] = system->new_page();
109        updateCache(vaddr, pTable[vaddr]);
110    }
111}
112
113
114
115bool
116PageTable::translate(Addr vaddr, Addr &paddr)
117{
118    Addr page_addr = pageAlign(vaddr);
119    paddr = 0;
120
121    if (pTableCache[0].vaddr == page_addr) {
122        paddr = pTableCache[0].paddr + pageOffset(vaddr);
123        return true;
124    }
125    if (pTableCache[1].vaddr == page_addr) {
126        paddr = pTableCache[1].paddr + pageOffset(vaddr);
127        return true;
128    }
129    if (pTableCache[2].vaddr == page_addr) {
130        paddr = pTableCache[2].paddr + pageOffset(vaddr);
131        return true;
132    }
133
134    m5::hash_map<Addr,Addr>::iterator iter = pTable.find(page_addr);
135
136    if (iter == pTable.end()) {
137        return false;
138    }
139
140    updateCache(page_addr, iter->second);
141    paddr = iter->second + pageOffset(vaddr);
142    return true;
143}
144
145
146Fault
147PageTable::translate(RequestPtr &req)
148{
149    Addr paddr;
150    assert(pageAlign(req->getVaddr() + req->getSize() - 1)
151           == pageAlign(req->getVaddr()));
152    if (!translate(req->getVaddr(), paddr)) {
153        return Fault(new PageTableFault(req->getVaddr()));
154    }
155    req->setPaddr(paddr);
156    return page_check(req->getPaddr(), req->getSize());
157}
158
159void
160PageTable::serialize(std::ostream &os)
161{
162    paramOut(os, "ptable.size", pTable.size());
163
164    int count = 0;
165
166    m5::hash_map<Addr,Addr>::iterator iter = pTable.begin();
167    m5::hash_map<Addr,Addr>::iterator end = pTable.end();
168    while (iter != end) {
169        paramOut(os, csprintf("ptable.entry%dvaddr", count), iter->first);
170        paramOut(os, csprintf("ptable.entry%dpaddr", count), iter->second);
171
172        ++iter;
173        ++count;
174    }
175    assert(count == pTable.size());
176}
177
178void
179PageTable::unserialize(Checkpoint *cp, const std::string &section)
180{
181    int i = 0, count;
182    paramIn(cp, section, "ptable.size", count);
183    Addr vaddr, paddr;
184
185    pTable.clear();
186
187    while(i < count) {
188        paramIn(cp, section, csprintf("ptable.entry%dvaddr", i), vaddr);
189        paramIn(cp, section, csprintf("ptable.entry%dpaddr", i), paddr);
190        pTable[vaddr] = paddr;
191        ++i;
192   }
193
194}
195
196