page_table.cc revision 4521:0236d1cdb330 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Ron Dreslinski
30 *          Ali Saidi
31 */
32
33/**
34 * @file
35 * Definitions of page table.
36 */
37#include <string>
38#include <map>
39#include <fstream>
40
41#include "arch/faults.hh"
42#include "base/bitfield.hh"
43#include "base/intmath.hh"
44#include "base/trace.hh"
45#include "mem/page_table.hh"
46#include "sim/builder.hh"
47#include "sim/sim_object.hh"
48#include "sim/system.hh"
49
50using namespace std;
51using namespace TheISA;
52
53PageTable::PageTable(System *_system, Addr _pageSize)
54    : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
55      system(_system)
56{
57    assert(isPowerOf2(pageSize));
58    pTableCache[0].vaddr = 0;
59    pTableCache[1].vaddr = 0;
60    pTableCache[2].vaddr = 0;
61}
62
63PageTable::~PageTable()
64{
65}
66
67Fault
68PageTable::page_check(Addr addr, int64_t size) const
69{
70    if (size < sizeof(uint64_t)) {
71        if (!isPowerOf2(size)) {
72            panic("Invalid request size!\n");
73            return genMachineCheckFault();
74        }
75
76        if ((size - 1) & addr)
77            return genAlignmentFault();
78    }
79    else {
80        if ((addr & (VMPageSize - 1)) + size > VMPageSize) {
81            panic("Invalid request size!\n");
82            return genMachineCheckFault();
83        }
84
85        if ((sizeof(uint64_t) - 1) & addr)
86            return genAlignmentFault();
87    }
88
89    return NoFault;
90}
91
92
93void
94PageTable::allocate(Addr vaddr, int64_t size)
95{
96    // starting address must be page aligned
97    assert(pageOffset(vaddr) == 0);
98
99    DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
100
101    for (; size > 0; size -= pageSize, vaddr += pageSize) {
102        m5::hash_map<Addr,Addr>::iterator iter = pTable.find(vaddr);
103
104        if (iter != pTable.end()) {
105            // already mapped
106            fatal("PageTable::allocate: address 0x%x already mapped", vaddr);
107        }
108
109        pTable[vaddr] = system->new_page();
110        updateCache(vaddr, pTable[vaddr]);
111    }
112}
113
114
115
116bool
117PageTable::translate(Addr vaddr, Addr &paddr)
118{
119    Addr page_addr = pageAlign(vaddr);
120    paddr = 0;
121
122    if (pTableCache[0].vaddr == page_addr) {
123        paddr = pTableCache[0].paddr + pageOffset(vaddr);
124        return true;
125    }
126    if (pTableCache[1].vaddr == page_addr) {
127        paddr = pTableCache[1].paddr + pageOffset(vaddr);
128        return true;
129    }
130    if (pTableCache[2].vaddr == page_addr) {
131        paddr = pTableCache[2].paddr + pageOffset(vaddr);
132        return true;
133    }
134
135    m5::hash_map<Addr,Addr>::iterator iter = pTable.find(page_addr);
136
137    if (iter == pTable.end()) {
138        return false;
139    }
140
141    updateCache(page_addr, iter->second);
142    paddr = iter->second + pageOffset(vaddr);
143    return true;
144}
145
146
147Fault
148PageTable::translate(RequestPtr &req)
149{
150    Addr paddr;
151    assert(pageAlign(req->getVaddr() + req->getSize() - 1)
152           == pageAlign(req->getVaddr()));
153    if (!translate(req->getVaddr(), paddr)) {
154        return Fault(new PageTableFault(req->getVaddr()));
155    }
156    req->setPaddr(paddr);
157    return page_check(req->getPaddr(), req->getSize());
158}
159
160void
161PageTable::serialize(std::ostream &os)
162{
163    paramOut(os, "ptable.size", pTable.size());
164
165    int count = 0;
166
167    m5::hash_map<Addr,Addr>::iterator iter = pTable.begin();
168    m5::hash_map<Addr,Addr>::iterator end = pTable.end();
169    while (iter != end) {
170        paramOut(os, csprintf("ptable.entry%dvaddr", count), iter->first);
171        paramOut(os, csprintf("ptable.entry%dpaddr", count), iter->second);
172
173        ++iter;
174        ++count;
175    }
176    assert(count == pTable.size());
177}
178
179void
180PageTable::unserialize(Checkpoint *cp, const std::string &section)
181{
182    int i = 0, count;
183    paramIn(cp, section, "ptable.size", count);
184    Addr vaddr, paddr;
185
186    pTable.clear();
187
188    while(i < count) {
189        paramIn(cp, section, csprintf("ptable.entry%dvaddr", i), vaddr);
190        paramIn(cp, section, csprintf("ptable.entry%dpaddr", i), paddr);
191        pTable[vaddr] = paddr;
192        ++i;
193   }
194
195}
196
197