page_table.cc revision 12442:e003b72b46ac 
1/*
2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * Copyright (c) 2003 The Regents of The University of Michigan
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Steve Reinhardt
30 *          Ron Dreslinski
31 *          Ali Saidi
32 */
33
34/**
35 * @file
36 * Definitions of functional page table.
37 */
38#include "mem/page_table.hh"
39
40#include <string>
41
42#include "base/trace.hh"
43#include "config/the_isa.hh"
44#include "debug/MMU.hh"
45#include "sim/faults.hh"
46#include "sim/serialize.hh"
47
48using namespace std;
49using namespace TheISA;
50
51FuncPageTable::FuncPageTable(const std::string &__name,
52                             uint64_t _pid, Addr _pageSize)
53        : PageTableBase(__name, _pid, _pageSize)
54{
55}
56
57FuncPageTable::~FuncPageTable()
58{
59    for (auto &iter : pTable)
60        delete iter.second;
61}
62
63void
64FuncPageTable::map(Addr vaddr, Addr paddr, int64_t size, uint64_t flags)
65{
66    bool clobber = flags & Clobber;
67    // starting address must be page aligned
68    assert(pageOffset(vaddr) == 0);
69
70    DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
71
72    for (; size > 0; size -= pageSize, vaddr += pageSize, paddr += pageSize) {
73        auto it = pTable.find(vaddr);
74        if (it != pTable.end()) {
75            if (clobber) {
76                delete it->second;
77            } else {
78                // already mapped
79                fatal("FuncPageTable::allocate: addr %#x already mapped",
80                      vaddr);
81            }
82        } else {
83            it = pTable.emplace(vaddr, nullptr).first;
84        }
85
86        it->second = new TheISA::TlbEntry(pid, vaddr, paddr,
87                                         flags & Uncacheable,
88                                         flags & ReadOnly);
89        eraseCacheEntry(vaddr);
90        updateCache(vaddr, pTable[vaddr]);
91    }
92}
93
94void
95FuncPageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr)
96{
97    assert(pageOffset(vaddr) == 0);
98    assert(pageOffset(new_vaddr) == 0);
99
100    DPRINTF(MMU, "moving pages from vaddr %08p to %08p, size = %d\n", vaddr,
101            new_vaddr, size);
102
103    for (; size > 0;
104         size -= pageSize, vaddr += pageSize, new_vaddr += pageSize)
105    {
106        auto new_it = pTable.find(new_vaddr);
107        auto old_it = pTable.find(vaddr);
108        assert(old_it != pTable.end() && new_it == pTable.end());
109
110        new_it->second = old_it->second;
111        pTable.erase(old_it);
112        eraseCacheEntry(vaddr);
113        new_it->second->updateVaddr(new_vaddr);
114        updateCache(new_vaddr, new_it->second);
115    }
116}
117
118void
119FuncPageTable::getMappings(std::vector<std::pair<Addr, Addr>> *addr_maps)
120{
121    for (auto &iter : pTable)
122        addr_maps->push_back(make_pair(iter.first, iter.second->pageStart()));
123}
124
125void
126FuncPageTable::unmap(Addr vaddr, int64_t size)
127{
128    assert(pageOffset(vaddr) == 0);
129
130    DPRINTF(MMU, "Unmapping page: %#x-%#x\n", vaddr, vaddr+ size);
131
132    for (; size > 0; size -= pageSize, vaddr += pageSize) {
133        auto it = pTable.find(vaddr);
134        assert(it != pTable.end());
135        eraseCacheEntry(vaddr);
136        delete it->second;
137        pTable.erase(it);
138    }
139
140}
141
142bool
143FuncPageTable::isUnmapped(Addr vaddr, int64_t size)
144{
145    // starting address must be page aligned
146    assert(pageOffset(vaddr) == 0);
147
148    for (; size > 0; size -= pageSize, vaddr += pageSize) {
149        if (pTable.find(vaddr) != pTable.end()) {
150            return false;
151        }
152    }
153
154    return true;
155}
156
157bool
158FuncPageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry)
159{
160    Addr page_addr = pageAlign(vaddr);
161
162    if (pTableCache[0].entry && pTableCache[0].vaddr == page_addr) {
163        entry = *pTableCache[0].entry;
164        return true;
165    }
166    if (pTableCache[1].entry && pTableCache[1].vaddr == page_addr) {
167        entry = *pTableCache[1].entry;
168        return true;
169    }
170    if (pTableCache[2].entry && pTableCache[2].vaddr == page_addr) {
171        entry = *pTableCache[2].entry;
172        return true;
173    }
174
175    PTableItr iter = pTable.find(page_addr);
176
177    if (iter == pTable.end()) {
178        return false;
179    }
180
181    updateCache(page_addr, iter->second);
182    entry = *iter->second;
183    return true;
184}
185
186bool
187PageTableBase::translate(Addr vaddr, Addr &paddr)
188{
189    TheISA::TlbEntry entry;
190    if (!lookup(vaddr, entry)) {
191        DPRINTF(MMU, "Couldn't Translate: %#x\n", vaddr);
192        return false;
193    }
194    paddr = pageOffset(vaddr) + entry.pageStart();
195    DPRINTF(MMU, "Translating: %#x->%#x\n", vaddr, paddr);
196    return true;
197}
198
199Fault
200PageTableBase::translate(RequestPtr req)
201{
202    Addr paddr;
203    assert(pageAlign(req->getVaddr() + req->getSize() - 1)
204           == pageAlign(req->getVaddr()));
205    if (!translate(req->getVaddr(), paddr)) {
206        return Fault(new GenericPageTableFault(req->getVaddr()));
207    }
208    req->setPaddr(paddr);
209    if ((paddr & (pageSize - 1)) + req->getSize() > pageSize) {
210        panic("Request spans page boundaries!\n");
211        return NoFault;
212    }
213    return NoFault;
214}
215
216void
217FuncPageTable::serialize(CheckpointOut &cp) const
218{
219    paramOut(cp, "ptable.size", pTable.size());
220
221    PTable::size_type count = 0;
222    for (auto &pte : pTable) {
223        ScopedCheckpointSection sec(cp, csprintf("Entry%d", count++));
224
225        paramOut(cp, "vaddr", pte.first);
226        pte.second->serialize(cp);
227    }
228    assert(count == pTable.size());
229}
230
231void
232FuncPageTable::unserialize(CheckpointIn &cp)
233{
234    int count;
235    paramIn(cp, "ptable.size", count);
236
237    for (int i = 0; i < count; ++i) {
238        ScopedCheckpointSection sec(cp, csprintf("Entry%d", i));
239
240        TheISA::TlbEntry *entry = new TheISA::TlbEntry();
241        entry->unserialize(cp);
242
243        Addr vaddr;
244        paramIn(cp, "vaddr", vaddr);
245
246        pTable[vaddr] = entry;
247    }
248}
249
250