multi_level_page_table.hh revision 12446:c4ad23df356a
1/* 2 * Copyright (c) 2014 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Alexandru Dutu 29 */ 30 31/** 32 * @file 33 * Declaration of a multi-level page table. 34 */ 35 36#ifndef __MEM_MULTI_LEVEL_PAGE_TABLE_HH__ 37#define __MEM_MULTI_LEVEL_PAGE_TABLE_HH__ 38 39#include <string> 40 41#include "base/types.hh" 42#include "config/the_isa.hh" 43#include "mem/page_table.hh" 44 45class System; 46 47/** 48 * This class implements an in-memory multi-level page table that can be 49 * configured to follow ISA specifications. It can be used instead of the 50 * PageTable class in SE mode to allow CPU models (e.g. X86KvmCPU) 51 * to do a normal page table walk. 52 * 53 * To reduce memory required to store the page table, a multi-level page 54 * table stores its translations similarly with a radix tree. Let n be 55 * the number of levels and {Ln, Ln-1, ..., L1, L0} a set that specifies 56 * the number of entries for each level as base 2 logarithm values. A 57 * multi-level page table will store its translations at level 0 (the 58 * leaves of the tree) and it will be layed out in memory in the 59 * following way: 60 * 61 * +------------------------------+ 62 * level n |Ln-1_E0|Ln-1_E1|...|Ln-1_E2^Ln| 63 * +------------------------------+ 64 * / \ 65 * +------------------------+ +------------------------+ 66 * level n-1 |Ln-2_E0|...|Ln-2_E2^Ln-1| |Ln-2_E0|...|Ln-2_E2^Ln-1| 67 * +------------------------+ +------------------------+ 68 * / \ / \ 69 * . 70 * . 71 * . 72 * / / \ 73 * +------------------+ +------------+ +------------+ 74 * level 1 |L0_E1|...|L0_E2^L1| |...|L0_E2^L1| ... |...|L0_E2^L1| 75 * +------------------+ +------------+ +------------+ 76 * , where 77 * +------------------------------+ 78 * |Lk-1_E0|Lk-1_E1|...|Lk-1_E2^Lk| 79 * +------------------------------+ 80 * is a level k entry that holds 2^Lk entries in Lk-1 level. 81 * 82 * Essentially, a level n entry will contain 2^Ln level n-1 entries, 83 * a level n-1 entry will hold 2^Ln-1 level n-2 entries etc. 84 * 85 * The virtual address is split into offsets that index into the 86 * different levels of the page table. 87 * 88 * +--------------------------------+ 89 * |LnOffset|...|L1Offset|PageOffset| 90 * +--------------------------------+ 91 * 92 * For example L0Offset will be formed by the bits in range 93 * [log2(PageOffset), log2(PageOffset)+L0]. 94 * 95 * For every level of the page table, from n to 1, the base address 96 * of the entry is loaded, the offset in the virtual address for 97 * that particular level is used to index into the entry which 98 * will reveal the memory address of the entry in the next level. 99 * 100 * @see MultiLevelPageTable 101 */ 102template <class ISAOps> 103class MultiLevelPageTable : public FuncPageTable 104{ 105 /** 106 * ISA specific operations 107 */ 108 ISAOps pTableISAOps; 109 110 /** 111 * Pointer to System object 112 */ 113 System *system; 114 115 /** 116 * Physical address to the last level of the page table 117 */ 118 Addr basePtr; 119 120 /** 121 * Vector with sizes of all levels in base 2 logarithmic 122 */ 123 const std::vector<uint8_t> logLevelSize; 124 125 /** 126 * Number of levels contained by the page table 127 */ 128 const uint64_t numLevels; 129 130 /** 131 * Method for walking the page table 132 * 133 * @param vaddr Virtual address that is being looked-up 134 * @param allocate Specifies whether memory should be allocated while 135 * walking the page table 136 * @return PTE_addr The address of the found PTE 137 */ 138 void walk(Addr vaddr, bool allocate, Addr &PTE_addr); 139 140public: 141 MultiLevelPageTable(const std::string &__name, uint64_t _pid, 142 System *_sys, Addr pageSize); 143 ~MultiLevelPageTable(); 144 145 void initState(ThreadContext* tc) override; 146 147 void map(Addr vaddr, Addr paddr, int64_t size, 148 uint64_t flags = 0) override; 149 void remap(Addr vaddr, int64_t size, Addr new_vaddr) override; 150 void unmap(Addr vaddr, int64_t size) override; 151 void serialize(CheckpointOut &cp) const override; 152 void unserialize(CheckpointIn &cp) override; 153}; 154#endif // __MEM_MULTI_LEVEL_PAGE_TABLE_HH__ 155