multi_level_page_table.hh revision 11800:54436a1784dc 
1/*
2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Alexandru Dutu
29 */
30
31/**
32 * @file
33 * Declaration of a multi-level page table.
34 */
35
36#ifndef __MEM_MULTI_LEVEL_PAGE_TABLE_HH__
37#define __MEM_MULTI_LEVEL_PAGE_TABLE_HH__
38
39#include <string>
40
41#include "arch/tlb.hh"
42#include "base/types.hh"
43#include "config/the_isa.hh"
44#include "mem/page_table.hh"
45
46class System;
47
48/**
49 * This class implements an in-memory multi-level page table that can be
50 * configured to follow ISA specifications. It can be used instead of the
51 * PageTable class in SE mode to allow CPU models (e.g. X86KvmCPU)
52 * to do a normal page table walk.
53 *
54 * To reduce memory required to store the page table, a multi-level page
55 * table stores its translations similarly with a radix tree. Let n be
56 * the number of levels and {Ln, Ln-1, ..., L1, L0} a set that specifies
57 * the number of entries for each level as base 2 logarithm values. A
58 * multi-level page table will store its translations at level 0 (the
59 * leaves of the tree) and it will be layed out in memory in the
60 * following way:
61 *
62 *                              +------------------------------+
63 * level n                      |Ln-1_E0|Ln-1_E1|...|Ln-1_E2^Ln|
64 *                              +------------------------------+
65 *                                 /       \
66 *            +------------------------+   +------------------------+
67 * level n-1  |Ln-2_E0|...|Ln-2_E2^Ln-1|   |Ln-2_E0|...|Ln-2_E2^Ln-1|
68 *            +------------------------+   +------------------------+
69 *                /            \             /              \
70 *                                  .
71 *                                  .
72 *                                  .
73 *               /                      /               \
74 *          +------------------+   +------------+     +------------+
75 * level 1  |L0_E1|...|L0_E2^L1|   |...|L0_E2^L1| ... |...|L0_E2^L1|
76 *          +------------------+   +------------+     +------------+
77 * , where
78 * +------------------------------+
79 * |Lk-1_E0|Lk-1_E1|...|Lk-1_E2^Lk|
80 * +------------------------------+
81 * is a level k entry that holds 2^Lk entries in Lk-1 level.
82 *
83 * Essentially, a level n entry will contain 2^Ln level n-1 entries,
84 * a level n-1 entry will hold 2^Ln-1 level n-2 entries etc.
85 *
86 * The virtual address is split into offsets that index into the
87 * different levels of the page table.
88 *
89 * +--------------------------------+
90 * |LnOffset|...|L1Offset|PageOffset|
91 * +--------------------------------+
92 *
93 * For example L0Offset will be formed by the bits in range
94 * [log2(PageOffset), log2(PageOffset)+L0].
95 *
96 * For every level of the page table, from n to 1, the base address
97 * of the entry is loaded, the offset in the virtual address for
98 * that particular level is used to index into the entry which
99 * will reveal the memory address of the entry in the next level.
100 *
101 * @see MultiLevelPageTable
102 */
103template <class ISAOps>
104class MultiLevelPageTable : public PageTableBase
105{
106    /**
107     * ISA specific operations
108     */
109    ISAOps pTableISAOps;
110
111    /**
112     * Pointer to System object
113     */
114    System *system;
115
116    /**
117     * Physical address to the last level of the page table
118     */
119    Addr basePtr;
120
121    /**
122     * Vector with sizes of all levels in base 2 logarithmic
123     */
124    const std::vector<uint8_t> logLevelSize;
125
126    /**
127     * Number of levels contained by the page table
128     */
129    const uint64_t numLevels;
130
131    /**
132     * Method for walking the page table
133     *
134     * @param vaddr Virtual address that is being looked-up
135     * @param allocate Specifies whether memory should be allocated while
136     *                  walking the page table
137     * @return PTE_addr The address of the found PTE
138     * @retval true if the page table walk has succeded, false otherwhise
139     */
140    bool walk(Addr vaddr, bool allocate, Addr &PTE_addr);
141
142public:
143    MultiLevelPageTable(const std::string &__name, uint64_t _pid,
144                        System *_sys);
145    ~MultiLevelPageTable();
146
147    void initState(ThreadContext* tc) override;
148
149    void map(Addr vaddr, Addr paddr, int64_t size,
150             uint64_t flags = 0) override;
151    void remap(Addr vaddr, int64_t size, Addr new_vaddr) override;
152    void unmap(Addr vaddr, int64_t size) override;
153    bool isUnmapped(Addr vaddr, int64_t size) override;
154    bool lookup(Addr vaddr, TheISA::TlbEntry &entry) override;
155    void serialize(CheckpointOut &cp) const override;
156    void unserialize(CheckpointIn &cp) override;
157};
158#endif // __MEM_MULTI_LEVEL_PAGE_TABLE_HH__
159