multi_level_page_table.hh revision 12432
12686Sksewell@umich.edu/* 22686Sksewell@umich.edu * Copyright (c) 2014 Advanced Micro Devices, Inc. 32686Sksewell@umich.edu * All rights reserved. 42686Sksewell@umich.edu * 52686Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 62686Sksewell@umich.edu * modification, are permitted provided that the following conditions are 72686Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 82686Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 92686Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 102686Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 112686Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 122686Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 132686Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 142686Sksewell@umich.edu * this software without specific prior written permission. 152686Sksewell@umich.edu * 162686Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172686Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182686Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192686Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202686Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212686Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222686Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232686Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242686Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252686Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262686Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272706Sksewell@umich.edu * 282706Sksewell@umich.edu * Authors: Alexandru Dutu 292686Sksewell@umich.edu */ 302686Sksewell@umich.edu 314661Sksewell@umich.edu/** 322686Sksewell@umich.edu * @file 334661Sksewell@umich.edu * Declaration of a multi-level page table. 344661Sksewell@umich.edu */ 354661Sksewell@umich.edu 364661Sksewell@umich.edu#ifndef __MEM_MULTI_LEVEL_PAGE_TABLE_HH__ 374661Sksewell@umich.edu#define __MEM_MULTI_LEVEL_PAGE_TABLE_HH__ 384661Sksewell@umich.edu 392980Sgblack@eecs.umich.edu#include <string> 402686Sksewell@umich.edu 412686Sksewell@umich.edu#include "base/types.hh" 424661Sksewell@umich.edu#include "config/the_isa.hh" 432686Sksewell@umich.edu#include "mem/page_table.hh" 442686Sksewell@umich.edu 452686Sksewell@umich.educlass System; 462686Sksewell@umich.edu 472686Sksewell@umich.edu/** 482686Sksewell@umich.edu * This class implements an in-memory multi-level page table that can be 492686Sksewell@umich.edu * configured to follow ISA specifications. It can be used instead of the 502686Sksewell@umich.edu * PageTable class in SE mode to allow CPU models (e.g. X86KvmCPU) 512686Sksewell@umich.edu * to do a normal page table walk. 522686Sksewell@umich.edu * 532686Sksewell@umich.edu * To reduce memory required to store the page table, a multi-level page 542686Sksewell@umich.edu * table stores its translations similarly with a radix tree. Let n be 552686Sksewell@umich.edu * the number of levels and {Ln, Ln-1, ..., L1, L0} a set that specifies 562686Sksewell@umich.edu * the number of entries for each level as base 2 logarithm values. A 572686Sksewell@umich.edu * multi-level page table will store its translations at level 0 (the 582686Sksewell@umich.edu * leaves of the tree) and it will be layed out in memory in the 592686Sksewell@umich.edu * following way: 602686Sksewell@umich.edu * 612686Sksewell@umich.edu * +------------------------------+ 622686Sksewell@umich.edu * level n |Ln-1_E0|Ln-1_E1|...|Ln-1_E2^Ln| 632686Sksewell@umich.edu * +------------------------------+ 642686Sksewell@umich.edu * / \ 652686Sksewell@umich.edu * +------------------------+ +------------------------+ 662686Sksewell@umich.edu * level n-1 |Ln-2_E0|...|Ln-2_E2^Ln-1| |Ln-2_E0|...|Ln-2_E2^Ln-1| 672686Sksewell@umich.edu * +------------------------+ +------------------------+ 682686Sksewell@umich.edu * / \ / \ 692686Sksewell@umich.edu * . 702686Sksewell@umich.edu * . 712686Sksewell@umich.edu * . 722686Sksewell@umich.edu * / / \ 732686Sksewell@umich.edu * +------------------+ +------------+ +------------+ 742686Sksewell@umich.edu * level 1 |L0_E1|...|L0_E2^L1| |...|L0_E2^L1| ... |...|L0_E2^L1| 752686Sksewell@umich.edu * +------------------+ +------------+ +------------+ 762686Sksewell@umich.edu * , where 772686Sksewell@umich.edu * +------------------------------+ 782686Sksewell@umich.edu * |Lk-1_E0|Lk-1_E1|...|Lk-1_E2^Lk| 792686Sksewell@umich.edu * +------------------------------+ 802686Sksewell@umich.edu * is a level k entry that holds 2^Lk entries in Lk-1 level. 812686Sksewell@umich.edu * 822686Sksewell@umich.edu * Essentially, a level n entry will contain 2^Ln level n-1 entries, 832686Sksewell@umich.edu * a level n-1 entry will hold 2^Ln-1 level n-2 entries etc. 842686Sksewell@umich.edu * 852686Sksewell@umich.edu * The virtual address is split into offsets that index into the 862686Sksewell@umich.edu * different levels of the page table. 872686Sksewell@umich.edu * 882686Sksewell@umich.edu * +--------------------------------+ 892686Sksewell@umich.edu * |LnOffset|...|L1Offset|PageOffset| 902686Sksewell@umich.edu * +--------------------------------+ 912686Sksewell@umich.edu * 922686Sksewell@umich.edu * For example L0Offset will be formed by the bits in range 932686Sksewell@umich.edu * [log2(PageOffset), log2(PageOffset)+L0]. 942686Sksewell@umich.edu * 952686Sksewell@umich.edu * For every level of the page table, from n to 1, the base address 962686Sksewell@umich.edu * of the entry is loaded, the offset in the virtual address for 972686Sksewell@umich.edu * that particular level is used to index into the entry which 982686Sksewell@umich.edu * will reveal the memory address of the entry in the next level. 992686Sksewell@umich.edu * 1002686Sksewell@umich.edu * @see MultiLevelPageTable 1012686Sksewell@umich.edu */ 1022686Sksewell@umich.edutemplate <class ISAOps> 1032686Sksewell@umich.educlass MultiLevelPageTable : public PageTableBase 1042686Sksewell@umich.edu{ 1052686Sksewell@umich.edu /** 1062686Sksewell@umich.edu * ISA specific operations 1072686Sksewell@umich.edu */ 1082686Sksewell@umich.edu ISAOps pTableISAOps; 1092686Sksewell@umich.edu 1102686Sksewell@umich.edu /** 1112686Sksewell@umich.edu * Pointer to System object 1122686Sksewell@umich.edu */ 1132686Sksewell@umich.edu System *system; 1142686Sksewell@umich.edu 1152686Sksewell@umich.edu /** 1162686Sksewell@umich.edu * Physical address to the last level of the page table 1172686Sksewell@umich.edu */ 1182686Sksewell@umich.edu Addr basePtr; 1192686Sksewell@umich.edu 1202686Sksewell@umich.edu /** 1212686Sksewell@umich.edu * Vector with sizes of all levels in base 2 logarithmic 1222686Sksewell@umich.edu */ 1232686Sksewell@umich.edu const std::vector<uint8_t> logLevelSize; 1242686Sksewell@umich.edu 1252686Sksewell@umich.edu /** 1262686Sksewell@umich.edu * Number of levels contained by the page table 1272686Sksewell@umich.edu */ 1282686Sksewell@umich.edu const uint64_t numLevels; 1292686Sksewell@umich.edu 1302686Sksewell@umich.edu /** 1312686Sksewell@umich.edu * Method for walking the page table 1322686Sksewell@umich.edu * 1332686Sksewell@umich.edu * @param vaddr Virtual address that is being looked-up 1342686Sksewell@umich.edu * @param allocate Specifies whether memory should be allocated while 1352686Sksewell@umich.edu * walking the page table 1362686Sksewell@umich.edu * @return PTE_addr The address of the found PTE 1372686Sksewell@umich.edu * @retval true if the page table walk has succeded, false otherwhise 1382686Sksewell@umich.edu */ 1392686Sksewell@umich.edu bool walk(Addr vaddr, bool allocate, Addr &PTE_addr); 1402686Sksewell@umich.edu 1412686Sksewell@umich.edupublic: 1422686Sksewell@umich.edu MultiLevelPageTable(const std::string &__name, uint64_t _pid, 1432686Sksewell@umich.edu System *_sys, Addr pageSize); 1442686Sksewell@umich.edu ~MultiLevelPageTable(); 1452686Sksewell@umich.edu 1462686Sksewell@umich.edu void initState(ThreadContext* tc) override; 1472686Sksewell@umich.edu 1482686Sksewell@umich.edu void map(Addr vaddr, Addr paddr, int64_t size, 1492686Sksewell@umich.edu uint64_t flags = 0) override; 1502686Sksewell@umich.edu void remap(Addr vaddr, int64_t size, Addr new_vaddr) override; 1512686Sksewell@umich.edu void unmap(Addr vaddr, int64_t size) override; 1522686Sksewell@umich.edu bool isUnmapped(Addr vaddr, int64_t size) override; 1532686Sksewell@umich.edu bool lookup(Addr vaddr, TheISA::TlbEntry &entry) override; 1542686Sksewell@umich.edu void serialize(CheckpointOut &cp) const override; 1552686Sksewell@umich.edu void unserialize(CheckpointIn &cp) override; 1562686Sksewell@umich.edu}; 1572686Sksewell@umich.edu#endif // __MEM_MULTI_LEVEL_PAGE_TABLE_HH__ 1582686Sksewell@umich.edu