multi_level_page_table.hh revision 11800
110923SN/A/* 210923SN/A * Copyright (c) 2014 Advanced Micro Devices, Inc. 310923SN/A * All rights reserved. 410923SN/A * 510923SN/A * Redistribution and use in source and binary forms, with or without 610923SN/A * modification, are permitted provided that the following conditions are 710923SN/A * met: redistributions of source code must retain the above copyright 810923SN/A * notice, this list of conditions and the following disclaimer; 910923SN/A * redistributions in binary form must reproduce the above copyright 1010923SN/A * notice, this list of conditions and the following disclaimer in the 1110923SN/A * documentation and/or other materials provided with the distribution; 1210923SN/A * neither the name of the copyright holders nor the names of its 1310923SN/A * contributors may be used to endorse or promote products derived from 1410923SN/A * this software without specific prior written permission. 1510923SN/A * 1610923SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710923SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810923SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910923SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010923SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110923SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210923SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310923SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410923SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510923SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610923SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710923SN/A * 2810923SN/A * Authors: Alexandru Dutu 2910923SN/A */ 3010923SN/A 3110923SN/A/** 3210923SN/A * @file 3310923SN/A * Declaration of a multi-level page table. 3410923SN/A */ 3510923SN/A 3610923SN/A#ifndef __MEM_MULTI_LEVEL_PAGE_TABLE_HH__ 3710923SN/A#define __MEM_MULTI_LEVEL_PAGE_TABLE_HH__ 3811290Sgabor.dozsa@arm.com 3910923SN/A#include <string> 4010923SN/A 4110923SN/A#include "arch/tlb.hh" 4211290Sgabor.dozsa@arm.com#include "base/types.hh" 4310923SN/A#include "config/the_isa.hh" 4410923SN/A#include "mem/page_table.hh" 4511263Sandreas.sandberg@arm.com 4610923SN/Aclass System; 4710923SN/A 4810923SN/A/** 4911290Sgabor.dozsa@arm.com * This class implements an in-memory multi-level page table that can be 5010923SN/A * configured to follow ISA specifications. It can be used instead of the 5110923SN/A * PageTable class in SE mode to allow CPU models (e.g. X86KvmCPU) 5210923SN/A * to do a normal page table walk. 5310923SN/A * 5410923SN/A * To reduce memory required to store the page table, a multi-level page 5510923SN/A * table stores its translations similarly with a radix tree. Let n be 5611290Sgabor.dozsa@arm.com * the number of levels and {Ln, Ln-1, ..., L1, L0} a set that specifies 5710923SN/A * the number of entries for each level as base 2 logarithm values. A 5810923SN/A * multi-level page table will store its translations at level 0 (the 5911290Sgabor.dozsa@arm.com * leaves of the tree) and it will be layed out in memory in the 6011290Sgabor.dozsa@arm.com * following way: 6111290Sgabor.dozsa@arm.com * 6211290Sgabor.dozsa@arm.com * +------------------------------+ 6311290Sgabor.dozsa@arm.com * level n |Ln-1_E0|Ln-1_E1|...|Ln-1_E2^Ln| 6411290Sgabor.dozsa@arm.com * +------------------------------+ 6511290Sgabor.dozsa@arm.com * / \ 6611290Sgabor.dozsa@arm.com * +------------------------+ +------------------------+ 6710923SN/A * level n-1 |Ln-2_E0|...|Ln-2_E2^Ln-1| |Ln-2_E0|...|Ln-2_E2^Ln-1| 6810923SN/A * +------------------------+ +------------------------+ 6910923SN/A * / \ / \ 7010923SN/A * . 7110923SN/A * . 7210923SN/A * . 7310923SN/A * / / \ 7410923SN/A * +------------------+ +------------+ +------------+ 7510923SN/A * level 1 |L0_E1|...|L0_E2^L1| |...|L0_E2^L1| ... |...|L0_E2^L1| 7610923SN/A * +------------------+ +------------+ +------------+ 7711290Sgabor.dozsa@arm.com * , where 7810923SN/A * +------------------------------+ 7911290Sgabor.dozsa@arm.com * |Lk-1_E0|Lk-1_E1|...|Lk-1_E2^Lk| 8011290Sgabor.dozsa@arm.com * +------------------------------+ 8110923SN/A * is a level k entry that holds 2^Lk entries in Lk-1 level. 8210923SN/A * 8311290Sgabor.dozsa@arm.com * Essentially, a level n entry will contain 2^Ln level n-1 entries, 8411290Sgabor.dozsa@arm.com * a level n-1 entry will hold 2^Ln-1 level n-2 entries etc. 8511290Sgabor.dozsa@arm.com * 8611290Sgabor.dozsa@arm.com * The virtual address is split into offsets that index into the 8711290Sgabor.dozsa@arm.com * different levels of the page table. 8811290Sgabor.dozsa@arm.com * 8911290Sgabor.dozsa@arm.com * +--------------------------------+ 9011290Sgabor.dozsa@arm.com * |LnOffset|...|L1Offset|PageOffset| 9111290Sgabor.dozsa@arm.com * +--------------------------------+ 9211290Sgabor.dozsa@arm.com * 9311290Sgabor.dozsa@arm.com * For example L0Offset will be formed by the bits in range 9411290Sgabor.dozsa@arm.com * [log2(PageOffset), log2(PageOffset)+L0]. 9511290Sgabor.dozsa@arm.com * 9611290Sgabor.dozsa@arm.com * For every level of the page table, from n to 1, the base address 9711290Sgabor.dozsa@arm.com * of the entry is loaded, the offset in the virtual address for 9811290Sgabor.dozsa@arm.com * that particular level is used to index into the entry which 9911290Sgabor.dozsa@arm.com * will reveal the memory address of the entry in the next level. 10011290Sgabor.dozsa@arm.com * 10111290Sgabor.dozsa@arm.com * @see MultiLevelPageTable 10211290Sgabor.dozsa@arm.com */ 10311290Sgabor.dozsa@arm.comtemplate <class ISAOps> 10411290Sgabor.dozsa@arm.comclass MultiLevelPageTable : public PageTableBase 10511290Sgabor.dozsa@arm.com{ 10611290Sgabor.dozsa@arm.com /** 10711290Sgabor.dozsa@arm.com * ISA specific operations 10811290Sgabor.dozsa@arm.com */ 10911290Sgabor.dozsa@arm.com ISAOps pTableISAOps; 11011290Sgabor.dozsa@arm.com 11111290Sgabor.dozsa@arm.com /** 11211290Sgabor.dozsa@arm.com * Pointer to System object 11311290Sgabor.dozsa@arm.com */ 11411290Sgabor.dozsa@arm.com System *system; 11511290Sgabor.dozsa@arm.com 11611290Sgabor.dozsa@arm.com /** 11711290Sgabor.dozsa@arm.com * Physical address to the last level of the page table 11811290Sgabor.dozsa@arm.com */ 11911290Sgabor.dozsa@arm.com Addr basePtr; 12011290Sgabor.dozsa@arm.com 12111290Sgabor.dozsa@arm.com /** 12211290Sgabor.dozsa@arm.com * Vector with sizes of all levels in base 2 logarithmic 12311290Sgabor.dozsa@arm.com */ 12411290Sgabor.dozsa@arm.com const std::vector<uint8_t> logLevelSize; 12511290Sgabor.dozsa@arm.com 12611290Sgabor.dozsa@arm.com /** 12711290Sgabor.dozsa@arm.com * Number of levels contained by the page table 12811290Sgabor.dozsa@arm.com */ 12911290Sgabor.dozsa@arm.com const uint64_t numLevels; 13011290Sgabor.dozsa@arm.com 13111290Sgabor.dozsa@arm.com /** 13211290Sgabor.dozsa@arm.com * Method for walking the page table 13311290Sgabor.dozsa@arm.com * 13411290Sgabor.dozsa@arm.com * @param vaddr Virtual address that is being looked-up 13511290Sgabor.dozsa@arm.com * @param allocate Specifies whether memory should be allocated while 13611290Sgabor.dozsa@arm.com * walking the page table 13711290Sgabor.dozsa@arm.com * @return PTE_addr The address of the found PTE 13811290Sgabor.dozsa@arm.com * @retval true if the page table walk has succeded, false otherwhise 13911290Sgabor.dozsa@arm.com */ 14011290Sgabor.dozsa@arm.com bool walk(Addr vaddr, bool allocate, Addr &PTE_addr); 14111290Sgabor.dozsa@arm.com 14211290Sgabor.dozsa@arm.compublic: 14311290Sgabor.dozsa@arm.com MultiLevelPageTable(const std::string &__name, uint64_t _pid, 14411290Sgabor.dozsa@arm.com System *_sys); 14511290Sgabor.dozsa@arm.com ~MultiLevelPageTable(); 14611290Sgabor.dozsa@arm.com 14711290Sgabor.dozsa@arm.com void initState(ThreadContext* tc) override; 14811290Sgabor.dozsa@arm.com 14911290Sgabor.dozsa@arm.com void map(Addr vaddr, Addr paddr, int64_t size, 15011290Sgabor.dozsa@arm.com uint64_t flags = 0) override; 15111290Sgabor.dozsa@arm.com void remap(Addr vaddr, int64_t size, Addr new_vaddr) override; 15211290Sgabor.dozsa@arm.com void unmap(Addr vaddr, int64_t size) override; 15311290Sgabor.dozsa@arm.com bool isUnmapped(Addr vaddr, int64_t size) override; 15411290Sgabor.dozsa@arm.com bool lookup(Addr vaddr, TheISA::TlbEntry &entry) override; 15511290Sgabor.dozsa@arm.com void serialize(CheckpointOut &cp) const override; 15611290Sgabor.dozsa@arm.com void unserialize(CheckpointIn &cp) override; 15711290Sgabor.dozsa@arm.com}; 15811290Sgabor.dozsa@arm.com#endif // __MEM_MULTI_LEVEL_PAGE_TABLE_HH__ 15911290Sgabor.dozsa@arm.com