multi_level_page_table.hh revision 10556
110298Salexandru.dutu@amd.com/*
210298Salexandru.dutu@amd.com * Copyright (c) 2014 Advanced Micro Devices, Inc.
310298Salexandru.dutu@amd.com * All rights reserved.
410298Salexandru.dutu@amd.com *
510298Salexandru.dutu@amd.com * Redistribution and use in source and binary forms, with or without
610298Salexandru.dutu@amd.com * modification, are permitted provided that the following conditions are
710298Salexandru.dutu@amd.com * met: redistributions of source code must retain the above copyright
810298Salexandru.dutu@amd.com * notice, this list of conditions and the following disclaimer;
910298Salexandru.dutu@amd.com * redistributions in binary form must reproduce the above copyright
1010298Salexandru.dutu@amd.com * notice, this list of conditions and the following disclaimer in the
1110298Salexandru.dutu@amd.com * documentation and/or other materials provided with the distribution;
1210298Salexandru.dutu@amd.com * neither the name of the copyright holders nor the names of its
1310298Salexandru.dutu@amd.com * contributors may be used to endorse or promote products derived from
1410298Salexandru.dutu@amd.com * this software without specific prior written permission.
1510298Salexandru.dutu@amd.com *
1610298Salexandru.dutu@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1710298Salexandru.dutu@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1810298Salexandru.dutu@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
1910298Salexandru.dutu@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2010298Salexandru.dutu@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2110298Salexandru.dutu@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2210298Salexandru.dutu@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2310298Salexandru.dutu@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2410298Salexandru.dutu@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2510298Salexandru.dutu@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2610298Salexandru.dutu@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2710298Salexandru.dutu@amd.com *
2810298Salexandru.dutu@amd.com * Authors: Alexandru Dutu
2910298Salexandru.dutu@amd.com */
3010298Salexandru.dutu@amd.com
3110298Salexandru.dutu@amd.com/**
3210298Salexandru.dutu@amd.com * @file
3310298Salexandru.dutu@amd.com * Declaration of a multi-level page table.
3410298Salexandru.dutu@amd.com */
3510298Salexandru.dutu@amd.com
3610298Salexandru.dutu@amd.com#ifndef __MEM_MULTI_LEVEL_PAGE_TABLE_HH__
3710298Salexandru.dutu@amd.com#define __MEM_MULTI_LEVEL_PAGE_TABLE_HH__
3810298Salexandru.dutu@amd.com
3910298Salexandru.dutu@amd.com#include <string>
4010298Salexandru.dutu@amd.com
4110298Salexandru.dutu@amd.com#include "arch/isa_traits.hh"
4210298Salexandru.dutu@amd.com#include "arch/tlb.hh"
4310298Salexandru.dutu@amd.com#include "base/types.hh"
4410298Salexandru.dutu@amd.com#include "config/the_isa.hh"
4510298Salexandru.dutu@amd.com#include "mem/page_table.hh"
4610298Salexandru.dutu@amd.com#include "sim/serialize.hh"
4710298Salexandru.dutu@amd.com#include "sim/system.hh"
4810298Salexandru.dutu@amd.com
4910298Salexandru.dutu@amd.com/**
5010298Salexandru.dutu@amd.com * This class implements an in-memory multi-level page table that can be
5110298Salexandru.dutu@amd.com * configured to follow ISA specifications. It can be used instead of the
5210298Salexandru.dutu@amd.com * PageTable class in SE mode to allow CPU models (e.g. X86KvmCPU)
5310298Salexandru.dutu@amd.com * to do a normal page table walk.
5410298Salexandru.dutu@amd.com *
5510298Salexandru.dutu@amd.com * To reduce memory required to store the page table, a multi-level page
5610298Salexandru.dutu@amd.com * table stores its translations similarly with a radix tree. Let n be
5710298Salexandru.dutu@amd.com * the number of levels and {Ln, Ln-1, ..., L1, L0} a set that specifies
5810298Salexandru.dutu@amd.com * the number of entries for each level as base 2 logarithm values. A
5910298Salexandru.dutu@amd.com * multi-level page table will store its translations at level 0 (the
6010298Salexandru.dutu@amd.com * leaves of the tree) and it will be layed out in memory in the
6110298Salexandru.dutu@amd.com * following way:
6210298Salexandru.dutu@amd.com *
6310298Salexandru.dutu@amd.com *                              +------------------------------+
6410298Salexandru.dutu@amd.com * level n                      |Ln-1_E0|Ln-1_E1|...|Ln-1_E2^Ln|
6510298Salexandru.dutu@amd.com *                              +------------------------------+
6610298Salexandru.dutu@amd.com *                                 /       \
6710298Salexandru.dutu@amd.com *            +------------------------+   +------------------------+
6810298Salexandru.dutu@amd.com * level n-1  |Ln-2_E0|...|Ln-2_E2^Ln-1|   |Ln-2_E0|...|Ln-2_E2^Ln-1|
6910298Salexandru.dutu@amd.com *            +------------------------+   +------------------------+
7010298Salexandru.dutu@amd.com *                /            \             /              \
7110298Salexandru.dutu@amd.com *                                  .
7210298Salexandru.dutu@amd.com *                                  .
7310298Salexandru.dutu@amd.com *                                  .
7410298Salexandru.dutu@amd.com *               /                      /               \
7510298Salexandru.dutu@amd.com *          +------------------+   +------------+     +------------+
7610298Salexandru.dutu@amd.com * level 1  |L0_E1|...|L0_E2^L1|   |...|L0_E2^L1| ... |...|L0_E2^L1|
7710298Salexandru.dutu@amd.com *          +------------------+   +------------+     +------------+
7810298Salexandru.dutu@amd.com * , where
7910298Salexandru.dutu@amd.com * +------------------------------+
8010298Salexandru.dutu@amd.com * |Lk-1_E0|Lk-1_E1|...|Lk-1_E2^Lk|
8110298Salexandru.dutu@amd.com * +------------------------------+
8210298Salexandru.dutu@amd.com * is a level k entry that holds 2^Lk entries in Lk-1 level.
8310298Salexandru.dutu@amd.com *
8410298Salexandru.dutu@amd.com * Essentially, a level n entry will contain 2^Ln level n-1 entries,
8510298Salexandru.dutu@amd.com * a level n-1 entry will hold 2^Ln-1 level n-2 entries etc.
8610298Salexandru.dutu@amd.com *
8710298Salexandru.dutu@amd.com * The virtual address is split into offsets that index into the
8810298Salexandru.dutu@amd.com * different levels of the page table.
8910298Salexandru.dutu@amd.com *
9010298Salexandru.dutu@amd.com * +--------------------------------+
9110298Salexandru.dutu@amd.com * |LnOffset|...|L1Offset|PageOffset|
9210298Salexandru.dutu@amd.com * +--------------------------------+
9310298Salexandru.dutu@amd.com *
9410298Salexandru.dutu@amd.com * For example L0Offset will be formed by the bits in range
9510298Salexandru.dutu@amd.com * [log2(PageOffset), log2(PageOffset)+L0].
9610298Salexandru.dutu@amd.com *
9710298Salexandru.dutu@amd.com * For every level of the page table, from n to 1, the base address
9810298Salexandru.dutu@amd.com * of the entry is loaded, the offset in the virtual address for
9910298Salexandru.dutu@amd.com * that particular level is used to index into the entry which
10010298Salexandru.dutu@amd.com * will reveal the memory address of the entry in the next level.
10110298Salexandru.dutu@amd.com *
10210298Salexandru.dutu@amd.com * @see MultiLevelPageTable
10310298Salexandru.dutu@amd.com */
10410298Salexandru.dutu@amd.comtemplate <class ISAOps>
10510298Salexandru.dutu@amd.comclass MultiLevelPageTable : public PageTableBase
10610298Salexandru.dutu@amd.com{
10710298Salexandru.dutu@amd.com    /**
10810298Salexandru.dutu@amd.com     * ISA specific operations
10910298Salexandru.dutu@amd.com     */
11010298Salexandru.dutu@amd.com    ISAOps pTableISAOps;
11110298Salexandru.dutu@amd.com
11210298Salexandru.dutu@amd.com    /**
11310298Salexandru.dutu@amd.com     * Pointer to System object
11410298Salexandru.dutu@amd.com     */
11510298Salexandru.dutu@amd.com    System *system;
11610298Salexandru.dutu@amd.com
11710298Salexandru.dutu@amd.com    /**
11810298Salexandru.dutu@amd.com     * Physical address to the last level of the page table
11910298Salexandru.dutu@amd.com     */
12010298Salexandru.dutu@amd.com    Addr basePtr;
12110298Salexandru.dutu@amd.com
12210298Salexandru.dutu@amd.com    /**
12310298Salexandru.dutu@amd.com     * Vector with sizes of all levels in base 2 logarithmic
12410298Salexandru.dutu@amd.com     */
12510298Salexandru.dutu@amd.com    const std::vector<uint8_t> logLevelSize;
12610298Salexandru.dutu@amd.com
12710298Salexandru.dutu@amd.com    /**
12810298Salexandru.dutu@amd.com     * Number of levels contained by the page table
12910298Salexandru.dutu@amd.com     */
13010298Salexandru.dutu@amd.com    const uint64_t numLevels;
13110298Salexandru.dutu@amd.com
13210298Salexandru.dutu@amd.com    /**
13310298Salexandru.dutu@amd.com     * Method for walking the page table
13410298Salexandru.dutu@amd.com     *
13510298Salexandru.dutu@amd.com     * @param vaddr Virtual address that is being looked-up
13610298Salexandru.dutu@amd.com     * @param allocate Specifies whether memory should be allocated while
13710298Salexandru.dutu@amd.com     *                  walking the page table
13810298Salexandru.dutu@amd.com     * @return PTE_addr The address of the found PTE
13910298Salexandru.dutu@amd.com     * @retval true if the page table walk has succeded, false otherwhise
14010298Salexandru.dutu@amd.com     */
14110298Salexandru.dutu@amd.com    bool walk(Addr vaddr, bool allocate, Addr &PTE_addr);
14210298Salexandru.dutu@amd.com
14310298Salexandru.dutu@amd.compublic:
14410556Salexandru.dutu@amd.com    MultiLevelPageTable(const std::string &__name, uint64_t _pid,
14510556Salexandru.dutu@amd.com                        System *_sys);
14610298Salexandru.dutu@amd.com    ~MultiLevelPageTable();
14710298Salexandru.dutu@amd.com
14810298Salexandru.dutu@amd.com    void initState(ThreadContext* tc);
14910298Salexandru.dutu@amd.com
15010298Salexandru.dutu@amd.com    void map(Addr vaddr, Addr paddr, int64_t size, bool clobber = false);
15110298Salexandru.dutu@amd.com    void remap(Addr vaddr, int64_t size, Addr new_vaddr);
15210298Salexandru.dutu@amd.com    void unmap(Addr vaddr, int64_t size);
15310298Salexandru.dutu@amd.com    bool isUnmapped(Addr vaddr, int64_t size);
15410298Salexandru.dutu@amd.com    bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
15510298Salexandru.dutu@amd.com    void serialize(std::ostream &os);
15610298Salexandru.dutu@amd.com    void unserialize(Checkpoint *cp, const std::string &section);
15710298Salexandru.dutu@amd.com};
15810298Salexandru.dutu@amd.com#endif // __MEM_MULTI_LEVEL_PAGE_TABLE_HH__
159