dramsim2.hh revision 10066:06a33d872798
1/* 2 * Copyright (c) 2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andreas Hansson 38 */ 39 40/** 41 * @file 42 * DRAMSim2 43 */ 44#ifndef __MEM_DRAMSIM2_HH__ 45#define __MEM_DRAMSIM2_HH__ 46 47#include <queue> 48 49#include "base/hashmap.hh" 50#include "mem/abstract_mem.hh" 51#include "mem/dramsim2_wrapper.hh" 52#include "mem/qport.hh" 53#include "params/DRAMSim2.hh" 54 55class DRAMSim2 : public AbstractMemory 56{ 57 private: 58 59 /** 60 * The memory port has to deal with its own flow control to avoid 61 * having unbounded storage that is implicitly created in the port 62 * itself. 63 */ 64 class MemoryPort : public SlavePort 65 { 66 67 private: 68 69 DRAMSim2& memory; 70 71 public: 72 73 MemoryPort(const std::string& _name, DRAMSim2& _memory); 74 75 protected: 76 77 Tick recvAtomic(PacketPtr pkt); 78 79 void recvFunctional(PacketPtr pkt); 80 81 bool recvTimingReq(PacketPtr pkt); 82 83 void recvRetry(); 84 85 AddrRangeList getAddrRanges() const; 86 87 }; 88 89 MemoryPort port; 90 91 /** 92 * The actual DRAMSim2 wrapper 93 */ 94 DRAMSim2Wrapper wrapper; 95 96 /** 97 * Is the connected port waiting for a retry from us 98 */ 99 bool retryReq; 100 101 /** 102 * Are we waiting for a retry for sending a response. 103 */ 104 bool retryResp; 105 106 /** 107 * Keep track of what packets are outstanding per 108 * address, and do so separately for reads and writes. This is 109 * done so that we can return the right packet on completion from 110 * DRAMSim. 111 */ 112 m5::hash_map<Addr, std::queue<PacketPtr> > outstandingReads; 113 m5::hash_map<Addr, std::queue<PacketPtr> > outstandingWrites; 114 115 /** 116 * Count the number of outstanding transactions so that we can 117 * block any further requests until there is space in DRAMSim2 and 118 * the sending queue we need to buffer the response packets. 119 */ 120 unsigned int nbrOutstandingReads; 121 unsigned int nbrOutstandingWrites; 122 123 /** 124 * Queue to hold response packets until we can send them 125 * back. This is needed as DRAMSim2 unconditionally passes 126 * responses back without any flow control. 127 */ 128 std::deque<PacketPtr> responseQueue; 129 130 /** 131 * If we need to drain, keep the drain manager around until we're 132 * done here. 133 */ 134 DrainManager *drainManager; 135 136 unsigned int nbrOutstanding() const; 137 138 /** 139 * When a packet is ready, use the "access()" method in 140 * AbstractMemory to actually create the response packet, and send 141 * it back to the outside world requestor. 142 * 143 * @param pkt The packet from the outside world 144 */ 145 void accessAndRespond(PacketPtr pkt); 146 147 void sendResponse(); 148 149 /** 150 * Event to schedule sending of responses 151 */ 152 EventWrapper<DRAMSim2, &DRAMSim2::sendResponse> sendResponseEvent; 153 154 /** 155 * Progress the controller one clock cycle. 156 */ 157 void tick(); 158 159 /** 160 * Event to schedule clock ticks 161 */ 162 EventWrapper<DRAMSim2, &DRAMSim2::tick> tickEvent; 163 164 /** @todo this is a temporary workaround until the 4-phase code is 165 * committed. upstream caches needs this packet until true is returned, so 166 * hold onto it for deletion until a subsequent call 167 */ 168 std::vector<PacketPtr> pendingDelete; 169 170 public: 171 172 typedef DRAMSim2Params Params; 173 DRAMSim2(const Params *p); 174 175 /** 176 * Read completion callback. 177 * 178 * @param id Channel id of the responder 179 * @param addr Address of the request 180 * @param cycle Internal cycle count of DRAMSim2 181 */ 182 void readComplete(unsigned id, uint64_t addr, uint64_t cycle); 183 184 /** 185 * Write completion callback. 186 * 187 * @param id Channel id of the responder 188 * @param addr Address of the request 189 * @param cycle Internal cycle count of DRAMSim2 190 */ 191 void writeComplete(unsigned id, uint64_t addr, uint64_t cycle); 192 193 unsigned int drain(DrainManager* dm); 194 195 virtual BaseSlavePort& getSlavePort(const std::string& if_name, 196 PortID idx = InvalidPortID); 197 198 virtual void init(); 199 virtual void startup(); 200 201 protected: 202 203 Tick recvAtomic(PacketPtr pkt); 204 void recvFunctional(PacketPtr pkt); 205 bool recvTimingReq(PacketPtr pkt); 206 void recvRetry(); 207 208}; 209 210#endif // __MEM_DRAMSIM2_HH__ 211