dramsim2.cc revision 10066:06a33d872798
1/* 2 * Copyright (c) 2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andreas Hansson 38 */ 39 40#include "DRAMSim2/Callback.h" 41#include "base/callback.hh" 42#include "base/trace.hh" 43#include "debug/DRAMSim2.hh" 44#include "debug/Drain.hh" 45#include "mem/dramsim2.hh" 46#include "sim/system.hh" 47 48DRAMSim2::DRAMSim2(const Params* p) : 49 AbstractMemory(p), 50 port(name() + ".port", *this), 51 wrapper(p->deviceConfigFile, p->systemConfigFile, p->filePath, 52 p->traceFile, p->range.size() / 1024 / 1024, p->enableDebug), 53 retryReq(false), retryResp(false), 54 nbrOutstandingReads(0), nbrOutstandingWrites(0), 55 drainManager(NULL), 56 sendResponseEvent(this), tickEvent(this) 57{ 58 DPRINTF(DRAMSim2, 59 "Instantiated DRAMSim2 with clock %d ns and queue size %d\n", 60 wrapper.clockPeriod(), wrapper.queueSize()); 61 62 DRAMSim::TransactionCompleteCB* read_cb = 63 new DRAMSim::Callback<DRAMSim2, void, unsigned, uint64_t, uint64_t>( 64 this, &DRAMSim2::readComplete); 65 DRAMSim::TransactionCompleteCB* write_cb = 66 new DRAMSim::Callback<DRAMSim2, void, unsigned, uint64_t, uint64_t>( 67 this, &DRAMSim2::writeComplete); 68 wrapper.setCallbacks(read_cb, write_cb); 69 70 // Register a callback to compensate for the destructor not 71 // being called. The callback prints the DRAMSim2 stats. 72 Callback* cb = new MakeCallback<DRAMSim2Wrapper, 73 &DRAMSim2Wrapper::printStats>(wrapper); 74 registerExitCallback(cb); 75} 76 77void 78DRAMSim2::init() 79{ 80 if (!port.isConnected()) { 81 fatal("DRAMSim2 %s is unconnected!\n", name()); 82 } else { 83 port.sendRangeChange(); 84 } 85 86 if (system()->cacheLineSize() != wrapper.burstSize()) 87 fatal("DRAMSim2 burst size %d does not match cache line size %d\n", 88 wrapper.burstSize(), system()->cacheLineSize()); 89} 90 91void 92DRAMSim2::startup() 93{ 94 // kick off the clock ticks 95 schedule(tickEvent, clockEdge()); 96} 97 98void 99DRAMSim2::sendResponse() 100{ 101 assert(!retryResp); 102 assert(!responseQueue.empty()); 103 104 DPRINTF(DRAMSim2, "Attempting to send response\n"); 105 106 bool success = port.sendTimingResp(responseQueue.front()); 107 if (success) { 108 responseQueue.pop_front(); 109 110 DPRINTF(DRAMSim2, "Have %d read, %d write, %d responses outstanding\n", 111 nbrOutstandingReads, nbrOutstandingWrites, 112 responseQueue.size()); 113 114 if (!responseQueue.empty() && !sendResponseEvent.scheduled()) 115 schedule(sendResponseEvent, curTick()); 116 117 // check if we were asked to drain and if we are now done 118 if (drainManager && nbrOutstanding() == 0) { 119 drainManager->signalDrainDone(); 120 drainManager = NULL; 121 } 122 } else { 123 retryResp = true; 124 125 DPRINTF(DRAMSim2, "Waiting for response retry\n"); 126 127 assert(!sendResponseEvent.scheduled()); 128 } 129} 130 131unsigned int 132DRAMSim2::nbrOutstanding() const 133{ 134 return nbrOutstandingReads + nbrOutstandingWrites + responseQueue.size(); 135} 136 137void 138DRAMSim2::tick() 139{ 140 wrapper.tick(); 141 142 // is the connected port waiting for a retry, if so check the 143 // state and send a retry if conditions have changed 144 if (retryReq && nbrOutstanding() < wrapper.queueSize()) { 145 retryReq = false; 146 port.sendRetry(); 147 } 148 149 schedule(tickEvent, curTick() + wrapper.clockPeriod() * SimClock::Int::ns); 150} 151 152Tick 153DRAMSim2::recvAtomic(PacketPtr pkt) 154{ 155 access(pkt); 156 157 // 50 ns is just an arbitrary value at this point 158 return pkt->memInhibitAsserted() ? 0 : 50000; 159} 160 161void 162DRAMSim2::recvFunctional(PacketPtr pkt) 163{ 164 pkt->pushLabel(name()); 165 166 functionalAccess(pkt); 167 168 // potentially update the packets in our response queue as well 169 for (auto i = responseQueue.begin(); i != responseQueue.end(); ++i) 170 pkt->checkFunctional(*i); 171 172 pkt->popLabel(); 173} 174 175bool 176DRAMSim2::recvTimingReq(PacketPtr pkt) 177{ 178 // we should never see a new request while in retry 179 assert(!retryReq); 180 181 // @todo temporary hack to deal with memory corruption issues until 182 // 4-phase transactions are complete 183 for (int x = 0; x < pendingDelete.size(); x++) 184 delete pendingDelete[x]; 185 pendingDelete.clear(); 186 187 if (pkt->memInhibitAsserted()) { 188 // snooper will supply based on copy of packet 189 // still target's responsibility to delete packet 190 pendingDelete.push_back(pkt); 191 return true; 192 } 193 194 // if we cannot accept we need to send a retry once progress can 195 // be made 196 bool can_accept = nbrOutstanding() < wrapper.queueSize(); 197 198 // keep track of the transaction 199 if (pkt->isRead()) { 200 if (can_accept) { 201 outstandingReads[pkt->getAddr()].push(pkt); 202 203 // we count a transaction as outstanding until it has left the 204 // queue in the controller, and the response has been sent 205 // back, note that this will differ for reads and writes 206 ++nbrOutstandingReads; 207 } 208 } else if (pkt->isWrite()) { 209 if (can_accept) { 210 outstandingWrites[pkt->getAddr()].push(pkt); 211 212 ++nbrOutstandingWrites; 213 214 // perform the access for writes 215 accessAndRespond(pkt); 216 } 217 } else { 218 // keep it simple and just respond if necessary 219 accessAndRespond(pkt); 220 return true; 221 } 222 223 if (can_accept) { 224 // we should never have a situation when we think there is space, 225 // and there isn't 226 assert(wrapper.canAccept()); 227 228 DPRINTF(DRAMSim2, "Enqueueing address %lld\n", pkt->getAddr()); 229 230 // @todo what about the granularity here, implicit assumption that 231 // a transaction matches the burst size of the memory (which we 232 // cannot determine without parsing the ini file ourselves) 233 wrapper.enqueue(pkt->isWrite(), pkt->getAddr()); 234 235 return true; 236 } else { 237 retryReq = true; 238 return false; 239 } 240} 241 242void 243DRAMSim2::recvRetry() 244{ 245 DPRINTF(DRAMSim2, "Retrying\n"); 246 247 assert(retryResp); 248 retryResp = false; 249 sendResponse(); 250} 251 252void 253DRAMSim2::accessAndRespond(PacketPtr pkt) 254{ 255 DPRINTF(DRAMSim2, "Access for address %lld\n", pkt->getAddr()); 256 257 bool needsResponse = pkt->needsResponse(); 258 259 // do the actual memory access which also turns the packet into a 260 // response 261 access(pkt); 262 263 // turn packet around to go back to requester if response expected 264 if (needsResponse) { 265 // access already turned the packet into a response 266 assert(pkt->isResponse()); 267 268 // @todo someone should pay for this 269 pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; 270 271 DPRINTF(DRAMSim2, "Queuing response for address %lld\n", 272 pkt->getAddr()); 273 274 // queue it to be sent back 275 responseQueue.push_back(pkt); 276 277 // if we are not already waiting for a retry, or are scheduled 278 // to send a response, schedule an event 279 if (!retryResp && !sendResponseEvent.scheduled()) 280 schedule(sendResponseEvent, curTick()); 281 } else { 282 // @todo the packet is going to be deleted, and the DRAMPacket 283 // is still having a pointer to it 284 pendingDelete.push_back(pkt); 285 } 286} 287 288void DRAMSim2::readComplete(unsigned id, uint64_t addr, uint64_t cycle) 289{ 290 assert(cycle == divCeil(curTick(), 291 wrapper.clockPeriod() * SimClock::Int::ns)); 292 293 DPRINTF(DRAMSim2, "Read to address %lld complete\n", addr); 294 295 // get the outstanding reads for the address in question 296 auto p = outstandingReads.find(addr); 297 assert(p != outstandingReads.end()); 298 299 // first in first out, which is not necessarily true, but it is 300 // the best we can do at this point 301 PacketPtr pkt = p->second.front(); 302 p->second.pop(); 303 304 if (p->second.empty()) 305 outstandingReads.erase(p); 306 307 // no need to check for drain here as the next call will add a 308 // response to the response queue straight away 309 assert(nbrOutstandingReads != 0); 310 --nbrOutstandingReads; 311 312 // perform the actual memory access 313 accessAndRespond(pkt); 314} 315 316void DRAMSim2::writeComplete(unsigned id, uint64_t addr, uint64_t cycle) 317{ 318 assert(cycle == divCeil(curTick(), 319 wrapper.clockPeriod() * SimClock::Int::ns)); 320 321 DPRINTF(DRAMSim2, "Write to address %lld complete\n", addr); 322 323 // get the outstanding reads for the address in question 324 auto p = outstandingWrites.find(addr); 325 assert(p != outstandingWrites.end()); 326 327 // we have already responded, and this is only to keep track of 328 // what is outstanding 329 p->second.pop(); 330 if (p->second.empty()) 331 outstandingWrites.erase(p); 332 333 assert(nbrOutstandingWrites != 0); 334 --nbrOutstandingWrites; 335 336 // check if we were asked to drain and if we are now done 337 if (drainManager && nbrOutstanding() == 0) { 338 drainManager->signalDrainDone(); 339 drainManager = NULL; 340 } 341} 342 343BaseSlavePort& 344DRAMSim2::getSlavePort(const std::string &if_name, PortID idx) 345{ 346 if (if_name != "port") { 347 return MemObject::getSlavePort(if_name, idx); 348 } else { 349 return port; 350 } 351} 352 353unsigned int 354DRAMSim2::drain(DrainManager* dm) 355{ 356 // check our outstanding reads and writes and if any they need to 357 // drain 358 if (nbrOutstanding() != 0) { 359 setDrainState(Drainable::Draining); 360 drainManager = dm; 361 return 1; 362 } else { 363 setDrainState(Drainable::Drained); 364 return 0; 365 } 366} 367 368DRAMSim2::MemoryPort::MemoryPort(const std::string& _name, 369 DRAMSim2& _memory) 370 : SlavePort(_name, &_memory), memory(_memory) 371{ } 372 373AddrRangeList 374DRAMSim2::MemoryPort::getAddrRanges() const 375{ 376 AddrRangeList ranges; 377 ranges.push_back(memory.getAddrRange()); 378 return ranges; 379} 380 381Tick 382DRAMSim2::MemoryPort::recvAtomic(PacketPtr pkt) 383{ 384 return memory.recvAtomic(pkt); 385} 386 387void 388DRAMSim2::MemoryPort::recvFunctional(PacketPtr pkt) 389{ 390 memory.recvFunctional(pkt); 391} 392 393bool 394DRAMSim2::MemoryPort::recvTimingReq(PacketPtr pkt) 395{ 396 // pass it to the memory controller 397 return memory.recvTimingReq(pkt); 398} 399 400void 401DRAMSim2::MemoryPort::recvRetry() 402{ 403 memory.recvRetry(); 404} 405 406DRAMSim2* 407DRAMSim2Params::create() 408{ 409 return new DRAMSim2(this); 410} 411