dram_ctrl.hh revision 10287:4966471a1ba1
19243SN/A/* 211675Swendy.elsasser@arm.com * Copyright (c) 2012-2014 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 4310618SOmar.Naji@arm.com */ 4411555Sjungma@eit.uni-kl.de 4511678Swendy.elsasser@arm.com/** 4612266Sradhika.jagtap@arm.com * @file 479243SN/A * DRAMCtrl declaration 489243SN/A */ 499243SN/A 509243SN/A#ifndef __MEM_DRAM_CTRL_HH__ 5110146Sandreas.hansson@arm.com#define __MEM_DRAM_CTRL_HH__ 529243SN/A 539243SN/A#include <deque> 5410146Sandreas.hansson@arm.com 5510146Sandreas.hansson@arm.com#include "base/statistics.hh" 569243SN/A#include "enums/AddrMap.hh" 579488SN/A#include "enums/MemSched.hh" 5810618SOmar.Naji@arm.com#include "enums/PageManage.hh" 5910889Sandreas.hansson@arm.com#include "mem/abstract_mem.hh" 609488SN/A#include "mem/qport.hh" 6111677Swendy.elsasser@arm.com#include "params/DRAMCtrl.hh" 629243SN/A#include "sim/eventq.hh" 639243SN/A 649243SN/A/** 659243SN/A * The DRAM controller is a single-channel memory controller capturing 669243SN/A * the most important timing constraints associated with a 679243SN/A * contemporary DRAM. For multi-channel memory systems, the controller 6810146Sandreas.hansson@arm.com * is combined with a crossbar model, with the channel address 699243SN/A * interleaving taking part in the crossbar. 7010432SOmar.Naji@arm.com * 719243SN/A * As a basic design principle, this controller 729243SN/A * model is not cycle callable, but instead uses events to: 1) decide 7310287Sandreas.hansson@arm.com * when new decisions can be made, 2) when resources become available, 7410287Sandreas.hansson@arm.com * 3) when things are to be considered done, and 4) when to send 7510287Sandreas.hansson@arm.com * things back. Through these simple principles, the model delivers 7610287Sandreas.hansson@arm.com * high performance, and lots of flexibility, allowing users to 7710287Sandreas.hansson@arm.com * evaluate the system impact of a wide range of memory technologies, 789243SN/A * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC. 7910287Sandreas.hansson@arm.com * 8010287Sandreas.hansson@arm.com * For more details, please see Hansson et al, "Simulating DRAM 8110287Sandreas.hansson@arm.com * controllers for future system architecture exploration", 8210287Sandreas.hansson@arm.com * Proc. ISPASS, 2014. If you use this model as part of your research 8310287Sandreas.hansson@arm.com * please cite the paper. 8410287Sandreas.hansson@arm.com */ 8510287Sandreas.hansson@arm.comclass DRAMCtrl : public AbstractMemory 8610287Sandreas.hansson@arm.com{ 8710287Sandreas.hansson@arm.com 8810287Sandreas.hansson@arm.com private: 8910287Sandreas.hansson@arm.com 9010287Sandreas.hansson@arm.com // For now, make use of a queued slave port to avoid dealing with 9110287Sandreas.hansson@arm.com // flow control for the responses being sent back 9211678Swendy.elsasser@arm.com class MemoryPort : public QueuedSlavePort 9311678Swendy.elsasser@arm.com { 9411678Swendy.elsasser@arm.com 9511678Swendy.elsasser@arm.com SlavePacketQueue queue; 969243SN/A DRAMCtrl& memory; 9710146Sandreas.hansson@arm.com 989243SN/A public: 999243SN/A 1009243SN/A MemoryPort(const std::string& name, DRAMCtrl& _memory); 1019243SN/A 1029243SN/A protected: 1039243SN/A 1049243SN/A Tick recvAtomic(PacketPtr pkt); 1059243SN/A 1069243SN/A void recvFunctional(PacketPtr pkt); 10710713Sandreas.hansson@arm.com 10810146Sandreas.hansson@arm.com bool recvTimingReq(PacketPtr); 1099243SN/A 1109243SN/A virtual AddrRangeList getAddrRanges() const; 1119243SN/A 11210146Sandreas.hansson@arm.com }; 1139243SN/A 1149243SN/A /** 1159243SN/A * Our incoming port, for a multi-ported controller add a crossbar 1169243SN/A * in front of it 1179243SN/A */ 1189243SN/A MemoryPort port; 1199243SN/A 1209243SN/A /** 1219243SN/A * Remember if we have to retry a request when available. 1229243SN/A */ 1239243SN/A bool retryRdReq; 1249243SN/A bool retryWrReq; 1259243SN/A 1269243SN/A /** 1279243SN/A * Bus state used to control the read/write switching and drive 1289243SN/A * the scheduling of the next request. 1299243SN/A */ 1309243SN/A enum BusState { 1319243SN/A READ = 0, 1329243SN/A READ_TO_WRITE, 13310619Sandreas.hansson@arm.com WRITE, 13410619Sandreas.hansson@arm.com WRITE_TO_READ 13510619Sandreas.hansson@arm.com }; 13610619Sandreas.hansson@arm.com 13710619Sandreas.hansson@arm.com BusState busState; 1389243SN/A 1399243SN/A /** List to keep track of activate ticks */ 1409243SN/A std::vector<std::deque<Tick>> actTicks; 1419243SN/A 1429243SN/A /** 1439243SN/A * A basic class to track the bank state, i.e. what row is 14410206Sandreas.hansson@arm.com * currently open (if any), when is the bank free to accept a new 14510206Sandreas.hansson@arm.com * column (read/write) command, when can it be precharged, and 1469243SN/A * when can it be activated. 14710206Sandreas.hansson@arm.com * 14810206Sandreas.hansson@arm.com * The bank also keeps track of how many bytes have been accessed 14910206Sandreas.hansson@arm.com * in the open row since it was opened. 15010206Sandreas.hansson@arm.com */ 15110206Sandreas.hansson@arm.com class Bank 15210206Sandreas.hansson@arm.com { 1539243SN/A 15411678Swendy.elsasser@arm.com public: 15511678Swendy.elsasser@arm.com 15611678Swendy.elsasser@arm.com static const uint32_t NO_ROW = -1; 1579243SN/A 15811675Swendy.elsasser@arm.com uint32_t openRow; 15911675Swendy.elsasser@arm.com uint8_t rank; 16011675Swendy.elsasser@arm.com uint8_t bank; 16111675Swendy.elsasser@arm.com 16211675Swendy.elsasser@arm.com Tick colAllowedAt; 16311675Swendy.elsasser@arm.com Tick preAllowedAt; 16411675Swendy.elsasser@arm.com Tick actAllowedAt; 16511675Swendy.elsasser@arm.com 16611675Swendy.elsasser@arm.com uint32_t rowAccesses; 16711675Swendy.elsasser@arm.com uint32_t bytesAccessed; 16811675Swendy.elsasser@arm.com 16911675Swendy.elsasser@arm.com Bank() : 17011675Swendy.elsasser@arm.com openRow(NO_ROW), rank(0), bank(0), 17111675Swendy.elsasser@arm.com colAllowedAt(0), preAllowedAt(0), actAllowedAt(0), 17211675Swendy.elsasser@arm.com rowAccesses(0), bytesAccessed(0) 17310210Sandreas.hansson@arm.com { } 17410210Sandreas.hansson@arm.com }; 17510211Sandreas.hansson@arm.com 17610211Sandreas.hansson@arm.com /** 17710210Sandreas.hansson@arm.com * A burst helper helps organize and manage a packet that is larger than 17810210Sandreas.hansson@arm.com * the DRAM burst size. A system packet that is larger than the burst size 17910210Sandreas.hansson@arm.com * is split into multiple DRAM packets and all those DRAM packets point to 1809243SN/A * a single burst helper such that we know when the whole packet is served. 1819243SN/A */ 1829243SN/A class BurstHelper { 1839243SN/A 1849243SN/A public: 1859243SN/A 18610207Sandreas.hansson@arm.com /** Number of DRAM bursts requred for a system packet **/ 1879243SN/A const unsigned int burstCount; 1889243SN/A 18910246Sandreas.hansson@arm.com /** Number of DRAM bursts serviced so far for a system packet **/ 19010394Swendy.elsasser@arm.com unsigned int burstsServiced; 1919243SN/A 19210211Sandreas.hansson@arm.com BurstHelper(unsigned int _burstCount) 19310210Sandreas.hansson@arm.com : burstCount(_burstCount), burstsServiced(0) 1949969SN/A { } 1959243SN/A }; 19610141SN/A 1979727SN/A /** 1989727SN/A * A DRAM packet stores packets along with the timestamp of when 1999727SN/A * the packet entered the queue, and also the decoded address. 20010618SOmar.Naji@arm.com */ 20110246Sandreas.hansson@arm.com class DRAMPacket { 20210141SN/A 2039243SN/A public: 2049243SN/A 2059243SN/A /** When did request enter the controller */ 20610618SOmar.Naji@arm.com const Tick entryTime; 20710618SOmar.Naji@arm.com 20811678Swendy.elsasser@arm.com /** When will request leave the controller */ 20911678Swendy.elsasser@arm.com Tick readyTime; 21011678Swendy.elsasser@arm.com 21111678Swendy.elsasser@arm.com /** This comes from the outside world */ 21211678Swendy.elsasser@arm.com const PacketPtr pkt; 21311678Swendy.elsasser@arm.com 21411678Swendy.elsasser@arm.com const bool isRead; 21511678Swendy.elsasser@arm.com 21611678Swendy.elsasser@arm.com /** Will be populated by address decoder */ 21711678Swendy.elsasser@arm.com const uint8_t rank; 21811678Swendy.elsasser@arm.com const uint8_t bank; 21911678Swendy.elsasser@arm.com const uint32_t row; 22011678Swendy.elsasser@arm.com 22111678Swendy.elsasser@arm.com /** 22211678Swendy.elsasser@arm.com * Bank id is calculated considering banks in all the ranks 22311678Swendy.elsasser@arm.com * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and 22411678Swendy.elsasser@arm.com * bankId = 8 --> rank1, bank0 22511678Swendy.elsasser@arm.com */ 22611678Swendy.elsasser@arm.com const uint16_t bankId; 22711678Swendy.elsasser@arm.com 22811678Swendy.elsasser@arm.com /** 22911678Swendy.elsasser@arm.com * The starting address of the DRAM packet. 23011678Swendy.elsasser@arm.com * This address could be unaligned to burst size boundaries. The 23111678Swendy.elsasser@arm.com * reason is to keep the address offset so we can accurately check 23211678Swendy.elsasser@arm.com * incoming read packets with packets in the write queue. 23311678Swendy.elsasser@arm.com */ 23411678Swendy.elsasser@arm.com Addr addr; 23511678Swendy.elsasser@arm.com 23611678Swendy.elsasser@arm.com /** 23711678Swendy.elsasser@arm.com * The size of this dram packet in bytes 23811678Swendy.elsasser@arm.com * It is always equal or smaller than DRAM burst size 23911678Swendy.elsasser@arm.com */ 24011678Swendy.elsasser@arm.com unsigned int size; 24111678Swendy.elsasser@arm.com 24211678Swendy.elsasser@arm.com /** 24311678Swendy.elsasser@arm.com * A pointer to the BurstHelper if this DRAMPacket is a split packet 24411678Swendy.elsasser@arm.com * If not a split packet (common case), this is set to NULL 24511678Swendy.elsasser@arm.com */ 24611678Swendy.elsasser@arm.com BurstHelper* burstHelper; 24711678Swendy.elsasser@arm.com Bank& bankRef; 24811678Swendy.elsasser@arm.com 24911678Swendy.elsasser@arm.com DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank, 25011678Swendy.elsasser@arm.com uint32_t _row, uint16_t bank_id, Addr _addr, 25111678Swendy.elsasser@arm.com unsigned int _size, Bank& bank_ref) 25211678Swendy.elsasser@arm.com : entryTime(curTick()), readyTime(curTick()), 25311678Swendy.elsasser@arm.com pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row), 25411678Swendy.elsasser@arm.com bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL), 25511678Swendy.elsasser@arm.com bankRef(bank_ref) 25611678Swendy.elsasser@arm.com { } 25711678Swendy.elsasser@arm.com 25811678Swendy.elsasser@arm.com }; 25911678Swendy.elsasser@arm.com 26011678Swendy.elsasser@arm.com /** 26111678Swendy.elsasser@arm.com * Bunch of things requires to setup "events" in gem5 26211678Swendy.elsasser@arm.com * When event "respondEvent" occurs for example, the method 26311678Swendy.elsasser@arm.com * processRespondEvent is called; no parameters are allowed 26411678Swendy.elsasser@arm.com * in these methods 26511678Swendy.elsasser@arm.com */ 26611678Swendy.elsasser@arm.com void processNextReqEvent(); 26711678Swendy.elsasser@arm.com EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent; 26811678Swendy.elsasser@arm.com 26911678Swendy.elsasser@arm.com void processRespondEvent(); 27011678Swendy.elsasser@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent; 27111678Swendy.elsasser@arm.com 27211678Swendy.elsasser@arm.com void processActivateEvent(); 27311678Swendy.elsasser@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processActivateEvent> activateEvent; 27411678Swendy.elsasser@arm.com 27511678Swendy.elsasser@arm.com void processPrechargeEvent(); 27611678Swendy.elsasser@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processPrechargeEvent> prechargeEvent; 27711678Swendy.elsasser@arm.com 27811678Swendy.elsasser@arm.com void processRefreshEvent(); 27911678Swendy.elsasser@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processRefreshEvent> refreshEvent; 28011678Swendy.elsasser@arm.com 28111678Swendy.elsasser@arm.com void processPowerEvent(); 28211678Swendy.elsasser@arm.com EventWrapper<DRAMCtrl,&DRAMCtrl::processPowerEvent> powerEvent; 28311678Swendy.elsasser@arm.com 28410618SOmar.Naji@arm.com /** 28510618SOmar.Naji@arm.com * Check if the read queue has room for more entries 28610618SOmar.Naji@arm.com * 28710618SOmar.Naji@arm.com * @param pktCount The number of entries needed in the read queue 28810618SOmar.Naji@arm.com * @return true if read queue is full, false otherwise 28910618SOmar.Naji@arm.com */ 29010618SOmar.Naji@arm.com bool readQueueFull(unsigned int pktCount) const; 29110618SOmar.Naji@arm.com 29210618SOmar.Naji@arm.com /** 29310618SOmar.Naji@arm.com * Check if the write queue has room for more entries 29410618SOmar.Naji@arm.com * 29510618SOmar.Naji@arm.com * @param pktCount The number of entries needed in the write queue 29610618SOmar.Naji@arm.com * @return true if write queue is full, false otherwise 29710618SOmar.Naji@arm.com */ 29810618SOmar.Naji@arm.com bool writeQueueFull(unsigned int pktCount) const; 29910618SOmar.Naji@arm.com 30010618SOmar.Naji@arm.com /** 30110618SOmar.Naji@arm.com * When a new read comes in, first check if the write q has a 30211678Swendy.elsasser@arm.com * pending request to the same address.\ If not, decode the 30310618SOmar.Naji@arm.com * address to populate rank/bank/row, create one or mutliple 30410618SOmar.Naji@arm.com * "dram_pkt", and push them to the back of the read queue.\ 30510618SOmar.Naji@arm.com * If this is the only 30610618SOmar.Naji@arm.com * read request in the system, schedule an event to start 30711678Swendy.elsasser@arm.com * servicing it. 30810618SOmar.Naji@arm.com * 30911678Swendy.elsasser@arm.com * @param pkt The request packet from the outside world 31010618SOmar.Naji@arm.com * @param pktCount The number of DRAM bursts the pkt 31110618SOmar.Naji@arm.com * translate to. If pkt size is larger then one full burst, 31210618SOmar.Naji@arm.com * then pktCount is greater than one. 31310618SOmar.Naji@arm.com */ 31410618SOmar.Naji@arm.com void addToReadQueue(PacketPtr pkt, unsigned int pktCount); 31510618SOmar.Naji@arm.com 31610618SOmar.Naji@arm.com /** 31710618SOmar.Naji@arm.com * Decode the incoming pkt, create a dram_pkt and push to the 31810618SOmar.Naji@arm.com * back of the write queue. \If the write q length is more than 31910618SOmar.Naji@arm.com * the threshold specified by the user, ie the queue is beginning 32010618SOmar.Naji@arm.com * to get full, stop reads, and start draining writes. 32110618SOmar.Naji@arm.com * 32210618SOmar.Naji@arm.com * @param pkt The request packet from the outside world 32310618SOmar.Naji@arm.com * @param pktCount The number of DRAM bursts the pkt 32410618SOmar.Naji@arm.com * translate to. If pkt size is larger then one full burst, 32510618SOmar.Naji@arm.com * then pktCount is greater than one. 32610618SOmar.Naji@arm.com */ 32710618SOmar.Naji@arm.com void addToWriteQueue(PacketPtr pkt, unsigned int pktCount); 32810618SOmar.Naji@arm.com 32910618SOmar.Naji@arm.com /** 33010618SOmar.Naji@arm.com * Actually do the DRAM access - figure out the latency it 33110618SOmar.Naji@arm.com * will take to service the req based on bank state, channel state etc 33210618SOmar.Naji@arm.com * and then update those states to account for this request.\ Based 33310618SOmar.Naji@arm.com * on this, update the packet's "readyTime" and move it to the 33410618SOmar.Naji@arm.com * response q from where it will eventually go back to the outside 33510618SOmar.Naji@arm.com * world. 33610618SOmar.Naji@arm.com * 33710618SOmar.Naji@arm.com * @param pkt The DRAM packet created from the outside world pkt 33810618SOmar.Naji@arm.com */ 33910618SOmar.Naji@arm.com void doDRAMAccess(DRAMPacket* dram_pkt); 34011678Swendy.elsasser@arm.com 34111678Swendy.elsasser@arm.com /** 34211678Swendy.elsasser@arm.com * When a packet reaches its "readyTime" in the response Q, 34311678Swendy.elsasser@arm.com * use the "access()" method in AbstractMemory to actually 34411678Swendy.elsasser@arm.com * create the response packet, and send it back to the outside 34511678Swendy.elsasser@arm.com * world requestor. 34611678Swendy.elsasser@arm.com * 34711678Swendy.elsasser@arm.com * @param pkt The packet from the outside world 34811678Swendy.elsasser@arm.com * @param static_latency Static latency to add before sending the packet 34911678Swendy.elsasser@arm.com */ 35011678Swendy.elsasser@arm.com void accessAndRespond(PacketPtr pkt, Tick static_latency); 35111678Swendy.elsasser@arm.com 35211678Swendy.elsasser@arm.com /** 35311678Swendy.elsasser@arm.com * Address decoder to figure out physical mapping onto ranks, 35411678Swendy.elsasser@arm.com * banks, and rows. This function is called multiple times on the same 35510618SOmar.Naji@arm.com * system packet if the pakcet is larger than burst of the memory. The 35610618SOmar.Naji@arm.com * dramPktAddr is used for the offset within the packet. 35710618SOmar.Naji@arm.com * 35810618SOmar.Naji@arm.com * @param pkt The packet from the outside world 35911678Swendy.elsasser@arm.com * @param dramPktAddr The starting address of the DRAM packet 36011678Swendy.elsasser@arm.com * @param size The size of the DRAM packet in bytes 36111678Swendy.elsasser@arm.com * @param isRead Is the request for a read or a write to DRAM 36211678Swendy.elsasser@arm.com * @return A DRAMPacket pointer with the decoded information 36311678Swendy.elsasser@arm.com */ 36411678Swendy.elsasser@arm.com DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size, 36510618SOmar.Naji@arm.com bool isRead); 36610618SOmar.Naji@arm.com 36710618SOmar.Naji@arm.com /** 36810618SOmar.Naji@arm.com * The memory schduler/arbiter - picks which request needs to 36910618SOmar.Naji@arm.com * go next, based on the specified policy such as FCFS or FR-FCFS 37010618SOmar.Naji@arm.com * and moves it to the head of the queue. 37110618SOmar.Naji@arm.com */ 37210618SOmar.Naji@arm.com void chooseNext(std::deque<DRAMPacket*>& queue); 37310618SOmar.Naji@arm.com 37410618SOmar.Naji@arm.com /** 37510618SOmar.Naji@arm.com * For FR-FCFS policy reorder the read/write queue depending on row buffer 37610618SOmar.Naji@arm.com * hits and earliest banks available in DRAM 37710618SOmar.Naji@arm.com */ 37810618SOmar.Naji@arm.com void reorderQueue(std::deque<DRAMPacket*>& queue); 37910618SOmar.Naji@arm.com 38010618SOmar.Naji@arm.com /** 38110618SOmar.Naji@arm.com * Find which are the earliest banks ready to issue an activate 38210618SOmar.Naji@arm.com * for the enqueued requests. Assumes maximum of 64 banks per DIMM 38310618SOmar.Naji@arm.com * 38410618SOmar.Naji@arm.com * @param Queued requests to consider 38510618SOmar.Naji@arm.com * @return One-hot encoded mask of bank indices 38611678Swendy.elsasser@arm.com */ 38711678Swendy.elsasser@arm.com uint64_t minBankActAt(const std::deque<DRAMPacket*>& queue) const; 38811678Swendy.elsasser@arm.com 38911678Swendy.elsasser@arm.com /** 39011678Swendy.elsasser@arm.com * Keep track of when row activations happen, in order to enforce 39111678Swendy.elsasser@arm.com * the maximum number of activations in the activation window. The 39211678Swendy.elsasser@arm.com * method updates the time that the banks become available based 39311678Swendy.elsasser@arm.com * on the current limits. 39411678Swendy.elsasser@arm.com * 39511678Swendy.elsasser@arm.com * @param bank Reference to the bank 39611678Swendy.elsasser@arm.com * @param act_tick Time when the activation takes place 39711678Swendy.elsasser@arm.com * @param row Index of the row 39811678Swendy.elsasser@arm.com */ 39911678Swendy.elsasser@arm.com void activateBank(Bank& bank, Tick act_tick, uint32_t row); 40011678Swendy.elsasser@arm.com 40110618SOmar.Naji@arm.com /** 40210618SOmar.Naji@arm.com * Precharge a given bank and also update when the precharge is 40310618SOmar.Naji@arm.com * done. This will also deal with any stats related to the 40410618SOmar.Naji@arm.com * accesses to the open page. 40511678Swendy.elsasser@arm.com * 40611678Swendy.elsasser@arm.com * @param bank_ref The bank to precharge 40711678Swendy.elsasser@arm.com * @param pre_at Time when the precharge takes place 40811678Swendy.elsasser@arm.com * @param trace Is this an auto precharge then do not add to trace 40911678Swendy.elsasser@arm.com */ 41011678Swendy.elsasser@arm.com void prechargeBank(Bank& bank_ref, Tick pre_at, bool trace = true); 41111678Swendy.elsasser@arm.com 41211678Swendy.elsasser@arm.com /** 41311678Swendy.elsasser@arm.com * Used for debugging to observe the contents of the queues. 41411678Swendy.elsasser@arm.com */ 41511678Swendy.elsasser@arm.com void printQs() const; 41611678Swendy.elsasser@arm.com 41711678Swendy.elsasser@arm.com /** 41811678Swendy.elsasser@arm.com * The controller's main read and write queues 41911678Swendy.elsasser@arm.com */ 42011678Swendy.elsasser@arm.com std::deque<DRAMPacket*> readQueue; 42111678Swendy.elsasser@arm.com std::deque<DRAMPacket*> writeQueue; 42211678Swendy.elsasser@arm.com 42311678Swendy.elsasser@arm.com /** 42411678Swendy.elsasser@arm.com * Response queue where read packets wait after we're done working 42511678Swendy.elsasser@arm.com * with them, but it's not time to send the response yet. The 42611678Swendy.elsasser@arm.com * responses are stored seperately mostly to keep the code clean 42710618SOmar.Naji@arm.com * and help with events scheduling. For all logical purposes such 42810618SOmar.Naji@arm.com * as sizing the read queue, this and the main read queue need to 42910618SOmar.Naji@arm.com * be added together. 43010618SOmar.Naji@arm.com */ 43110618SOmar.Naji@arm.com std::deque<DRAMPacket*> respQueue; 43210618SOmar.Naji@arm.com 43311675Swendy.elsasser@arm.com /** 43411675Swendy.elsasser@arm.com * If we need to drain, keep the drain manager around until we're 43511675Swendy.elsasser@arm.com * done here. 43611675Swendy.elsasser@arm.com */ 43711675Swendy.elsasser@arm.com DrainManager *drainManager; 43811675Swendy.elsasser@arm.com 43911675Swendy.elsasser@arm.com /** 44011675Swendy.elsasser@arm.com * Multi-dimensional vector of banks, first dimension is ranks, 44110618SOmar.Naji@arm.com * second is bank 44210618SOmar.Naji@arm.com */ 44310618SOmar.Naji@arm.com std::vector<std::vector<Bank> > banks; 44410618SOmar.Naji@arm.com 44510618SOmar.Naji@arm.com /** 44610618SOmar.Naji@arm.com * The following are basic design parameters of the memory 44710618SOmar.Naji@arm.com * controller, and are initialized based on parameter values. 44810618SOmar.Naji@arm.com * The rowsPerBank is determined based on the capacity, number of 44910618SOmar.Naji@arm.com * ranks and banks, the burst size, and the row buffer size. 45010618SOmar.Naji@arm.com */ 45110618SOmar.Naji@arm.com const uint32_t deviceBusWidth; 45210618SOmar.Naji@arm.com const uint32_t burstLength; 45310618SOmar.Naji@arm.com const uint32_t deviceRowBufferSize; 45410618SOmar.Naji@arm.com const uint32_t devicesPerRank; 45512081Sspwilson2@wisc.edu const uint32_t burstSize; 45610618SOmar.Naji@arm.com const uint32_t rowBufferSize; 45710618SOmar.Naji@arm.com const uint32_t columnsPerRowBuffer; 45810618SOmar.Naji@arm.com const uint32_t columnsPerStripe; 45910618SOmar.Naji@arm.com const uint32_t ranksPerChannel; 46010618SOmar.Naji@arm.com const uint32_t banksPerRank; 46110618SOmar.Naji@arm.com const uint32_t channels; 46210618SOmar.Naji@arm.com uint32_t rowsPerBank; 46310618SOmar.Naji@arm.com const uint32_t readBufferSize; 46410618SOmar.Naji@arm.com const uint32_t writeBufferSize; 46510618SOmar.Naji@arm.com const uint32_t writeHighThreshold; 46610618SOmar.Naji@arm.com const uint32_t writeLowThreshold; 46710618SOmar.Naji@arm.com const uint32_t minWritesPerSwitch; 46810618SOmar.Naji@arm.com uint32_t writesThisTime; 46910618SOmar.Naji@arm.com uint32_t readsThisTime; 47010618SOmar.Naji@arm.com 47110619Sandreas.hansson@arm.com /** 47210619Sandreas.hansson@arm.com * Basic memory timing parameters initialized based on parameter 47310619Sandreas.hansson@arm.com * values. 47410619Sandreas.hansson@arm.com */ 47510619Sandreas.hansson@arm.com const Tick M5_CLASS_VAR_USED tCK; 47612266Sradhika.jagtap@arm.com const Tick tWTR; 47712266Sradhika.jagtap@arm.com const Tick tRTW; 47810618SOmar.Naji@arm.com const Tick tBURST; 47910618SOmar.Naji@arm.com const Tick tRCD; 48010618SOmar.Naji@arm.com const Tick tCL; 48112266Sradhika.jagtap@arm.com const Tick tRP; 48210618SOmar.Naji@arm.com const Tick tRAS; 48310618SOmar.Naji@arm.com const Tick tWR; 48411676Swendy.elsasser@arm.com const Tick tRTP; 48511676Swendy.elsasser@arm.com const Tick tRFC; 48611676Swendy.elsasser@arm.com const Tick tREFI; 48711676Swendy.elsasser@arm.com const Tick tRRD; 48811676Swendy.elsasser@arm.com const Tick tXAW; 48911676Swendy.elsasser@arm.com const uint32_t activationLimit; 49011676Swendy.elsasser@arm.com 49111676Swendy.elsasser@arm.com /** 49211676Swendy.elsasser@arm.com * Memory controller configuration initialized based on parameter 49311678Swendy.elsasser@arm.com * values. 49411678Swendy.elsasser@arm.com */ 49511678Swendy.elsasser@arm.com Enums::MemSched memSchedPolicy; 49611678Swendy.elsasser@arm.com Enums::AddrMap addrMapping; 49711678Swendy.elsasser@arm.com Enums::PageManage pageMgmt; 49811678Swendy.elsasser@arm.com 49911678Swendy.elsasser@arm.com /** 50011678Swendy.elsasser@arm.com * Max column accesses (read and write) per row, before forefully 50111678Swendy.elsasser@arm.com * closing it. 50211678Swendy.elsasser@arm.com */ 50311678Swendy.elsasser@arm.com const uint32_t maxAccessesPerRow; 50411678Swendy.elsasser@arm.com 50511678Swendy.elsasser@arm.com /** 50611678Swendy.elsasser@arm.com * Pipeline latency of the controller frontend. The frontend 50711678Swendy.elsasser@arm.com * contribution is added to writes (that complete when they are in 50811678Swendy.elsasser@arm.com * the write buffer) and reads that are serviced the write buffer. 50911678Swendy.elsasser@arm.com */ 51011678Swendy.elsasser@arm.com const Tick frontendLatency; 51111678Swendy.elsasser@arm.com 51211678Swendy.elsasser@arm.com /** 51311678Swendy.elsasser@arm.com * Pipeline latency of the backend and PHY. Along with the 51411678Swendy.elsasser@arm.com * frontend contribution, this latency is added to reads serviced 51511678Swendy.elsasser@arm.com * by the DRAM. 51610618SOmar.Naji@arm.com */ 51710618SOmar.Naji@arm.com const Tick backendLatency; 51810618SOmar.Naji@arm.com 51910618SOmar.Naji@arm.com /** 52010618SOmar.Naji@arm.com * Till when has the main data bus been spoken for already? 52111675Swendy.elsasser@arm.com */ 52211675Swendy.elsasser@arm.com Tick busBusyUntil; 52311675Swendy.elsasser@arm.com 52411675Swendy.elsasser@arm.com /** 52511675Swendy.elsasser@arm.com * Keep track of when a refresh is due. 52611675Swendy.elsasser@arm.com */ 52711675Swendy.elsasser@arm.com Tick refreshDueAt; 52811675Swendy.elsasser@arm.com 52910618SOmar.Naji@arm.com /** 53010618SOmar.Naji@arm.com * The refresh state is used to control the progress of the 53110618SOmar.Naji@arm.com * refresh scheduling. When normal operation is in progress the 53210618SOmar.Naji@arm.com * refresh state is idle. From there, it progresses to the refresh 53310618SOmar.Naji@arm.com * drain state once tREFI has passed. The refresh drain state 53411677Swendy.elsasser@arm.com * captures the DRAM row active state, as it will stay there until 53511677Swendy.elsasser@arm.com * all ongoing accesses complete. Thereafter all banks are 53611677Swendy.elsasser@arm.com * precharged, and lastly, the DRAM is refreshed. 53711677Swendy.elsasser@arm.com */ 53811677Swendy.elsasser@arm.com enum RefreshState { 53911678Swendy.elsasser@arm.com REF_IDLE = 0, 54012266Sradhika.jagtap@arm.com REF_DRAIN, 54112266Sradhika.jagtap@arm.com REF_PRE, 54212266Sradhika.jagtap@arm.com REF_RUN 54312266Sradhika.jagtap@arm.com }; 54412266Sradhika.jagtap@arm.com 54511678Swendy.elsasser@arm.com RefreshState refreshState; 54611678Swendy.elsasser@arm.com 54711678Swendy.elsasser@arm.com /** 54811678Swendy.elsasser@arm.com * The power state captures the different operational states of 54911678Swendy.elsasser@arm.com * the DRAM and interacts with the bus read/write state machine, 55011678Swendy.elsasser@arm.com * and the refresh state machine. In the idle state all banks are 55111678Swendy.elsasser@arm.com * precharged. From there we either go to an auto refresh (as 55211678Swendy.elsasser@arm.com * determined by the refresh state machine), or to a precharge 55311678Swendy.elsasser@arm.com * power down mode. From idle the memory can also go to the active 55411678Swendy.elsasser@arm.com * state (with one or more banks active), and in turn from there 55511678Swendy.elsasser@arm.com * to active power down. At the moment we do not capture the deep 55611678Swendy.elsasser@arm.com * power down and self-refresh state. 55711678Swendy.elsasser@arm.com */ 55811678Swendy.elsasser@arm.com enum PowerState { 55911678Swendy.elsasser@arm.com PWR_IDLE = 0, 56011678Swendy.elsasser@arm.com PWR_REF, 56111678Swendy.elsasser@arm.com PWR_PRE_PDN, 56212084Sspwilson2@wisc.edu PWR_ACT, 56311678Swendy.elsasser@arm.com PWR_ACT_PDN 56410618SOmar.Naji@arm.com }; 56512084Sspwilson2@wisc.edu 56610618SOmar.Naji@arm.com /** 56710618SOmar.Naji@arm.com * Since we are taking decisions out of order, we need to keep 56812084Sspwilson2@wisc.edu * track of what power transition is happening at what time, such 56910618SOmar.Naji@arm.com * that we can go back in time and change history. For example, if 57010618SOmar.Naji@arm.com * we precharge all banks and schedule going to the idle state, we 57112084Sspwilson2@wisc.edu * might at a later point decide to activate a bank before the 57210618SOmar.Naji@arm.com * transition to idle would have taken place. 57310618SOmar.Naji@arm.com */ 57412084Sspwilson2@wisc.edu PowerState pwrStateTrans; 57510618SOmar.Naji@arm.com 57611678Swendy.elsasser@arm.com /** 57712084Sspwilson2@wisc.edu * Current power state. 57811678Swendy.elsasser@arm.com */ 57910618SOmar.Naji@arm.com PowerState pwrState; 58010618SOmar.Naji@arm.com 58112266Sradhika.jagtap@arm.com /** 58212266Sradhika.jagtap@arm.com * Schedule a power state transition in the future, and 58312266Sradhika.jagtap@arm.com * potentially override an already scheduled transition. 58412266Sradhika.jagtap@arm.com * 58512266Sradhika.jagtap@arm.com * @param pwr_state Power state to transition to 58612266Sradhika.jagtap@arm.com * @param tick Tick when transition should take place 58711677Swendy.elsasser@arm.com */ 58811677Swendy.elsasser@arm.com void schedulePowerEvent(PowerState pwr_state, Tick tick); 58911677Swendy.elsasser@arm.com 59011677Swendy.elsasser@arm.com Tick prevArrival; 59111677Swendy.elsasser@arm.com 59211677Swendy.elsasser@arm.com /** 59311677Swendy.elsasser@arm.com * The soonest you have to start thinking about the next request 59411677Swendy.elsasser@arm.com * is the longest access time that can occur before 59512266Sradhika.jagtap@arm.com * busBusyUntil. Assuming you need to precharge, open a new row, 59612266Sradhika.jagtap@arm.com * and access, it is tRP + tRCD + tCL. 59712266Sradhika.jagtap@arm.com */ 59812266Sradhika.jagtap@arm.com Tick nextReqTime; 59912266Sradhika.jagtap@arm.com 60012266Sradhika.jagtap@arm.com // All statistics that the model needs to capture 60112266Sradhika.jagtap@arm.com Stats::Scalar readReqs; 60212266Sradhika.jagtap@arm.com Stats::Scalar writeReqs; 60312266Sradhika.jagtap@arm.com Stats::Scalar readBursts; 60412266Sradhika.jagtap@arm.com Stats::Scalar writeBursts; 60512266Sradhika.jagtap@arm.com Stats::Scalar bytesReadDRAM; 60612266Sradhika.jagtap@arm.com Stats::Scalar bytesReadWrQ; 60712266Sradhika.jagtap@arm.com Stats::Scalar bytesWritten; 60812266Sradhika.jagtap@arm.com Stats::Scalar bytesReadSys; 60912266Sradhika.jagtap@arm.com Stats::Scalar bytesWrittenSys; 61012266Sradhika.jagtap@arm.com Stats::Scalar servicedByWrQ; 61112266Sradhika.jagtap@arm.com Stats::Scalar mergedWrBursts; 61212266Sradhika.jagtap@arm.com Stats::Scalar neitherReadNorWrite; 61312266Sradhika.jagtap@arm.com Stats::Vector perBankRdBursts; 61412266Sradhika.jagtap@arm.com Stats::Vector perBankWrBursts; 61512266Sradhika.jagtap@arm.com Stats::Scalar numRdRetry; 61612266Sradhika.jagtap@arm.com Stats::Scalar numWrRetry; 61712266Sradhika.jagtap@arm.com Stats::Scalar totGap; 61812266Sradhika.jagtap@arm.com Stats::Vector readPktSize; 6199243SN/A Stats::Vector writePktSize; 6209831SN/A Stats::Vector rdQLenPdf; 6219831SN/A Stats::Vector wrQLenPdf; 6229831SN/A Stats::Histogram bytesPerActivate; 6239831SN/A Stats::Histogram rdPerTurnAround; 6249831SN/A Stats::Histogram wrPerTurnAround; 6259831SN/A 6269831SN/A // Latencies summed over all requests 6279831SN/A Stats::Scalar totQLat; 6289831SN/A Stats::Scalar totMemAccLat; 6299831SN/A Stats::Scalar totBusLat; 6309831SN/A 6319831SN/A // Average latencies per request 6329831SN/A Stats::Formula avgQLat; 6339831SN/A Stats::Formula avgBusLat; 6349831SN/A Stats::Formula avgMemAccLat; 6359831SN/A 6369831SN/A // Average bandwidth 63710618SOmar.Naji@arm.com Stats::Formula avgRdBW; 6389831SN/A Stats::Formula avgWrBW; 6399831SN/A Stats::Formula avgRdBWSys; 6409831SN/A Stats::Formula avgWrBWSys; 6419243SN/A Stats::Formula peakBW; 6429243SN/A Stats::Formula busUtil; 6439243SN/A Stats::Formula busUtilRead; 6449243SN/A Stats::Formula busUtilWrite; 6459243SN/A 6469243SN/A // Average queue lengths 6479243SN/A Stats::Average avgRdQLen; 6489243SN/A Stats::Average avgWrQLen; 6499243SN/A 6509243SN/A // Row hit count and rate 6519243SN/A Stats::Scalar readRowHits; 6529243SN/A Stats::Scalar writeRowHits; 6539243SN/A Stats::Formula readRowHitRate; 6549243SN/A Stats::Formula writeRowHitRate; 6559243SN/A Stats::Formula avgGap; 6569243SN/A 6579966SN/A // DRAM Power Calculation 6589966SN/A Stats::Formula pageHitRate; 6599243SN/A Stats::Vector pwrStateTime; 6609243SN/A 6619967SN/A // Track when we transitioned to the current power state 66210245Sandreas.hansson@arm.com Tick pwrStateTick; 6639831SN/A 6649831SN/A // To track number of banks which are currently active 6659967SN/A unsigned int numBanksActive; 6669967SN/A 6679967SN/A /** @todo this is a temporary workaround until the 4-phase code is 6689967SN/A * committed. upstream caches needs this packet until true is returned, so 6699967SN/A * hold onto it for deletion until a subsequent call 6709967SN/A */ 6719967SN/A std::vector<PacketPtr> pendingDelete; 6729831SN/A 6739831SN/A public: 6749831SN/A 6759831SN/A void regStats(); 6769831SN/A 6779832SN/A DRAMCtrl(const DRAMCtrlParams* p); 6789831SN/A 6799831SN/A unsigned int drain(DrainManager* dm); 6809831SN/A 6819831SN/A virtual BaseSlavePort& getSlavePort(const std::string& if_name, 6829831SN/A PortID idx = InvalidPortID); 6839832SN/A 6849831SN/A virtual void init(); 6859831SN/A virtual void startup(); 6869831SN/A 6879831SN/A protected: 6889831SN/A 6899831SN/A Tick recvAtomic(PacketPtr pkt); 6909967SN/A void recvFunctional(PacketPtr pkt); 69110618SOmar.Naji@arm.com bool recvTimingReq(PacketPtr pkt); 6929243SN/A 6939967SN/A}; 69410245Sandreas.hansson@arm.com 69510618SOmar.Naji@arm.com#endif //__MEM_DRAM_CTRL_HH__ 6969243SN/A