dram_ctrl.hh revision 14038
19243SN/A/* 212706Swendy.elsasser@arm.com * Copyright (c) 2012-2018 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 4310618SOmar.Naji@arm.com * Omar Naji 4411555Sjungma@eit.uni-kl.de * Matthias Jung 4511678Swendy.elsasser@arm.com * Wendy Elsasser 4612266Sradhika.jagtap@arm.com * Radhika Jagtap 479243SN/A */ 489243SN/A 499243SN/A/** 509243SN/A * @file 5110146Sandreas.hansson@arm.com * DRAMCtrl declaration 529243SN/A */ 539243SN/A 5410146Sandreas.hansson@arm.com#ifndef __MEM_DRAM_CTRL_HH__ 5510146Sandreas.hansson@arm.com#define __MEM_DRAM_CTRL_HH__ 569243SN/A 579488SN/A#include <deque> 5810618SOmar.Naji@arm.com#include <string> 5910889Sandreas.hansson@arm.com#include <unordered_set> 6012969SMatteo.Andreozzi@arm.com#include <vector> 619488SN/A 6211677Swendy.elsasser@arm.com#include "base/callback.hh" 639243SN/A#include "base/statistics.hh" 649243SN/A#include "enums/AddrMap.hh" 659243SN/A#include "enums/MemSched.hh" 669243SN/A#include "enums/PageManage.hh" 6712969SMatteo.Andreozzi@arm.com#include "mem/drampower.hh" 6812969SMatteo.Andreozzi@arm.com#include "mem/qos/mem_ctrl.hh" 699243SN/A#include "mem/qport.hh" 7010146Sandreas.hansson@arm.com#include "params/DRAMCtrl.hh" 719243SN/A#include "sim/eventq.hh" 729243SN/A 739243SN/A/** 7410287Sandreas.hansson@arm.com * The DRAM controller is a single-channel memory controller capturing 7510287Sandreas.hansson@arm.com * the most important timing constraints associated with a 7610287Sandreas.hansson@arm.com * contemporary DRAM. For multi-channel memory systems, the controller 7710287Sandreas.hansson@arm.com * is combined with a crossbar model, with the channel address 7810287Sandreas.hansson@arm.com * interleaving taking part in the crossbar. 799243SN/A * 8010287Sandreas.hansson@arm.com * As a basic design principle, this controller 8110287Sandreas.hansson@arm.com * model is not cycle callable, but instead uses events to: 1) decide 8210287Sandreas.hansson@arm.com * when new decisions can be made, 2) when resources become available, 8310287Sandreas.hansson@arm.com * 3) when things are to be considered done, and 4) when to send 8410287Sandreas.hansson@arm.com * things back. Through these simple principles, the model delivers 8510287Sandreas.hansson@arm.com * high performance, and lots of flexibility, allowing users to 8610287Sandreas.hansson@arm.com * evaluate the system impact of a wide range of memory technologies, 8710287Sandreas.hansson@arm.com * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC. 8810287Sandreas.hansson@arm.com * 8910287Sandreas.hansson@arm.com * For more details, please see Hansson et al, "Simulating DRAM 9010287Sandreas.hansson@arm.com * controllers for future system architecture exploration", 9110287Sandreas.hansson@arm.com * Proc. ISPASS, 2014. If you use this model as part of your research 9210287Sandreas.hansson@arm.com * please cite the paper. 9311678Swendy.elsasser@arm.com * 9411678Swendy.elsasser@arm.com * The low-power functionality implements a staggered powerdown 9511678Swendy.elsasser@arm.com * similar to that described in "Optimized Active and Power-Down Mode 9611678Swendy.elsasser@arm.com * Refresh Control in 3D-DRAMs" by Jung et al, VLSI-SoC, 2014. 979243SN/A */ 9812969SMatteo.Andreozzi@arm.comclass DRAMCtrl : public QoS::MemCtrl 999243SN/A{ 1009243SN/A 1019243SN/A private: 1029243SN/A 1039243SN/A // For now, make use of a queued slave port to avoid dealing with 1049243SN/A // flow control for the responses being sent back 1059243SN/A class MemoryPort : public QueuedSlavePort 1069243SN/A { 1079243SN/A 10810713Sandreas.hansson@arm.com RespPacketQueue queue; 10910146Sandreas.hansson@arm.com DRAMCtrl& memory; 1109243SN/A 1119243SN/A public: 1129243SN/A 11310146Sandreas.hansson@arm.com MemoryPort(const std::string& name, DRAMCtrl& _memory); 1149243SN/A 1159243SN/A protected: 1169243SN/A 1179243SN/A Tick recvAtomic(PacketPtr pkt); 1189243SN/A 1199243SN/A void recvFunctional(PacketPtr pkt); 1209243SN/A 1219243SN/A bool recvTimingReq(PacketPtr); 1229243SN/A 1239243SN/A virtual AddrRangeList getAddrRanges() const; 1249243SN/A 1259243SN/A }; 1269243SN/A 1279243SN/A /** 1289243SN/A * Our incoming port, for a multi-ported controller add a crossbar 1299243SN/A * in front of it 1309243SN/A */ 1319243SN/A MemoryPort port; 1329243SN/A 1339243SN/A /** 13412969SMatteo.Andreozzi@arm.com * Remember if the memory system is in timing mode 13510619Sandreas.hansson@arm.com */ 13610619Sandreas.hansson@arm.com bool isTimingMode; 13710619Sandreas.hansson@arm.com 13810619Sandreas.hansson@arm.com /** 1399243SN/A * Remember if we have to retry a request when available. 1409243SN/A */ 1419243SN/A bool retryRdReq; 1429243SN/A bool retryWrReq; 1439243SN/A 14412969SMatteo.Andreozzi@arm.com /**/ 14511678Swendy.elsasser@arm.com 1469243SN/A /** 14711675Swendy.elsasser@arm.com * Simple structure to hold the values needed to keep track of 14811675Swendy.elsasser@arm.com * commands for DRAMPower 14911675Swendy.elsasser@arm.com */ 15011675Swendy.elsasser@arm.com struct Command { 15111675Swendy.elsasser@arm.com Data::MemCommand::cmds type; 15211675Swendy.elsasser@arm.com uint8_t bank; 15311675Swendy.elsasser@arm.com Tick timeStamp; 15411675Swendy.elsasser@arm.com 15511675Swendy.elsasser@arm.com constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank, 15611675Swendy.elsasser@arm.com Tick time_stamp) 15711675Swendy.elsasser@arm.com : type(_type), bank(_bank), timeStamp(time_stamp) 15811675Swendy.elsasser@arm.com { } 15911675Swendy.elsasser@arm.com }; 16011675Swendy.elsasser@arm.com 16111675Swendy.elsasser@arm.com /** 16210210Sandreas.hansson@arm.com * A basic class to track the bank state, i.e. what row is 16310210Sandreas.hansson@arm.com * currently open (if any), when is the bank free to accept a new 16410211Sandreas.hansson@arm.com * column (read/write) command, when can it be precharged, and 16510211Sandreas.hansson@arm.com * when can it be activated. 16610210Sandreas.hansson@arm.com * 16710210Sandreas.hansson@arm.com * The bank also keeps track of how many bytes have been accessed 16810210Sandreas.hansson@arm.com * in the open row since it was opened. 1699243SN/A */ 1709243SN/A class Bank 1719243SN/A { 1729243SN/A 1739243SN/A public: 1749243SN/A 17510207Sandreas.hansson@arm.com static const uint32_t NO_ROW = -1; 1769243SN/A 1779243SN/A uint32_t openRow; 17810246Sandreas.hansson@arm.com uint8_t bank; 17910394Swendy.elsasser@arm.com uint8_t bankgr; 1809243SN/A 18112706Swendy.elsasser@arm.com Tick rdAllowedAt; 18212706Swendy.elsasser@arm.com Tick wrAllowedAt; 18310210Sandreas.hansson@arm.com Tick preAllowedAt; 1849969SN/A Tick actAllowedAt; 1859243SN/A 18610141SN/A uint32_t rowAccesses; 1879727SN/A uint32_t bytesAccessed; 1889727SN/A 1899727SN/A Bank() : 19010618SOmar.Naji@arm.com openRow(NO_ROW), bank(0), bankgr(0), 19112706Swendy.elsasser@arm.com rdAllowedAt(0), wrAllowedAt(0), preAllowedAt(0), actAllowedAt(0), 19210141SN/A rowAccesses(0), bytesAccessed(0) 1939243SN/A { } 1949243SN/A }; 1959243SN/A 19610618SOmar.Naji@arm.com 19710618SOmar.Naji@arm.com /** 19811678Swendy.elsasser@arm.com * The power state captures the different operational states of 19911678Swendy.elsasser@arm.com * the DRAM and interacts with the bus read/write state machine, 20011678Swendy.elsasser@arm.com * and the refresh state machine. 20111678Swendy.elsasser@arm.com * 20211678Swendy.elsasser@arm.com * PWR_IDLE : The idle state in which all banks are closed 20311678Swendy.elsasser@arm.com * From here can transition to: PWR_REF, PWR_ACT, 20411678Swendy.elsasser@arm.com * PWR_PRE_PDN 20511678Swendy.elsasser@arm.com * 20611678Swendy.elsasser@arm.com * PWR_REF : Auto-refresh state. Will transition when refresh is 20711678Swendy.elsasser@arm.com * complete based on power state prior to PWR_REF 20811678Swendy.elsasser@arm.com * From here can transition to: PWR_IDLE, PWR_PRE_PDN, 20911678Swendy.elsasser@arm.com * PWR_SREF 21011678Swendy.elsasser@arm.com * 21111678Swendy.elsasser@arm.com * PWR_SREF : Self-refresh state. Entered after refresh if 21211678Swendy.elsasser@arm.com * previous state was PWR_PRE_PDN 21311678Swendy.elsasser@arm.com * From here can transition to: PWR_IDLE 21411678Swendy.elsasser@arm.com * 21511678Swendy.elsasser@arm.com * PWR_PRE_PDN : Precharge power down state 21611678Swendy.elsasser@arm.com * From here can transition to: PWR_REF, PWR_IDLE 21711678Swendy.elsasser@arm.com * 21811678Swendy.elsasser@arm.com * PWR_ACT : Activate state in which one or more banks are open 21911678Swendy.elsasser@arm.com * From here can transition to: PWR_IDLE, PWR_ACT_PDN 22011678Swendy.elsasser@arm.com * 22111678Swendy.elsasser@arm.com * PWR_ACT_PDN : Activate power down state 22211678Swendy.elsasser@arm.com * From here can transition to: PWR_ACT 22311678Swendy.elsasser@arm.com */ 22411678Swendy.elsasser@arm.com enum PowerState { 22511678Swendy.elsasser@arm.com PWR_IDLE = 0, 22611678Swendy.elsasser@arm.com PWR_REF, 22711678Swendy.elsasser@arm.com PWR_SREF, 22811678Swendy.elsasser@arm.com PWR_PRE_PDN, 22911678Swendy.elsasser@arm.com PWR_ACT, 23011678Swendy.elsasser@arm.com PWR_ACT_PDN 23111678Swendy.elsasser@arm.com }; 23211678Swendy.elsasser@arm.com 23311678Swendy.elsasser@arm.com /** 23411678Swendy.elsasser@arm.com * The refresh state is used to control the progress of the 23511678Swendy.elsasser@arm.com * refresh scheduling. When normal operation is in progress the 23611678Swendy.elsasser@arm.com * refresh state is idle. Once tREFI has elasped, a refresh event 23711678Swendy.elsasser@arm.com * is triggered to start the following STM transitions which are 23811678Swendy.elsasser@arm.com * used to issue a refresh and return back to normal operation 23911678Swendy.elsasser@arm.com * 24011678Swendy.elsasser@arm.com * REF_IDLE : IDLE state used during normal operation 24111678Swendy.elsasser@arm.com * From here can transition to: REF_DRAIN 24211678Swendy.elsasser@arm.com * 24311678Swendy.elsasser@arm.com * REF_SREF_EXIT : Exiting a self-refresh; refresh event scheduled 24411678Swendy.elsasser@arm.com * after self-refresh exit completes 24511678Swendy.elsasser@arm.com * From here can transition to: REF_DRAIN 24611678Swendy.elsasser@arm.com * 24711678Swendy.elsasser@arm.com * REF_DRAIN : Drain state in which on going accesses complete. 24811678Swendy.elsasser@arm.com * From here can transition to: REF_PD_EXIT 24911678Swendy.elsasser@arm.com * 25011678Swendy.elsasser@arm.com * REF_PD_EXIT : Evaluate pwrState and issue wakeup if needed 25111678Swendy.elsasser@arm.com * Next state dependent on whether banks are open 25211678Swendy.elsasser@arm.com * From here can transition to: REF_PRE, REF_START 25311678Swendy.elsasser@arm.com * 25411678Swendy.elsasser@arm.com * REF_PRE : Close (precharge) all open banks 25511678Swendy.elsasser@arm.com * From here can transition to: REF_START 25611678Swendy.elsasser@arm.com * 25711678Swendy.elsasser@arm.com * REF_START : Issue refresh command and update DRAMPower stats 25811678Swendy.elsasser@arm.com * From here can transition to: REF_RUN 25911678Swendy.elsasser@arm.com * 26011678Swendy.elsasser@arm.com * REF_RUN : Refresh running, waiting for tRFC to expire 26111678Swendy.elsasser@arm.com * From here can transition to: REF_IDLE, REF_SREF_EXIT 26211678Swendy.elsasser@arm.com */ 26311678Swendy.elsasser@arm.com enum RefreshState { 26411678Swendy.elsasser@arm.com REF_IDLE = 0, 26511678Swendy.elsasser@arm.com REF_DRAIN, 26611678Swendy.elsasser@arm.com REF_PD_EXIT, 26711678Swendy.elsasser@arm.com REF_SREF_EXIT, 26811678Swendy.elsasser@arm.com REF_PRE, 26911678Swendy.elsasser@arm.com REF_START, 27011678Swendy.elsasser@arm.com REF_RUN 27111678Swendy.elsasser@arm.com }; 27211678Swendy.elsasser@arm.com 27311678Swendy.elsasser@arm.com /** 27410618SOmar.Naji@arm.com * Rank class includes a vector of banks. Refresh and Power state 27510618SOmar.Naji@arm.com * machines are defined per rank. Events required to change the 27610618SOmar.Naji@arm.com * state of the refresh and power state machine are scheduled per 27710618SOmar.Naji@arm.com * rank. This class allows the implementation of rank-wise refresh 27810618SOmar.Naji@arm.com * and rank-wise power-down. 27910618SOmar.Naji@arm.com */ 28010618SOmar.Naji@arm.com class Rank : public EventManager 28110618SOmar.Naji@arm.com { 28210618SOmar.Naji@arm.com 28310618SOmar.Naji@arm.com private: 28410618SOmar.Naji@arm.com 28510618SOmar.Naji@arm.com /** 28610618SOmar.Naji@arm.com * A reference to the parent DRAMCtrl instance 28710618SOmar.Naji@arm.com */ 28810618SOmar.Naji@arm.com DRAMCtrl& memory; 28910618SOmar.Naji@arm.com 29010618SOmar.Naji@arm.com /** 29110618SOmar.Naji@arm.com * Since we are taking decisions out of order, we need to keep 29211678Swendy.elsasser@arm.com * track of what power transition is happening at what time 29310618SOmar.Naji@arm.com */ 29410618SOmar.Naji@arm.com PowerState pwrStateTrans; 29510618SOmar.Naji@arm.com 29610618SOmar.Naji@arm.com /** 29711678Swendy.elsasser@arm.com * Previous low-power state, which will be re-entered after refresh. 29810618SOmar.Naji@arm.com */ 29911678Swendy.elsasser@arm.com PowerState pwrStatePostRefresh; 30010618SOmar.Naji@arm.com 30110618SOmar.Naji@arm.com /** 30210618SOmar.Naji@arm.com * Track when we transitioned to the current power state 30310618SOmar.Naji@arm.com */ 30410618SOmar.Naji@arm.com Tick pwrStateTick; 30510618SOmar.Naji@arm.com 30610618SOmar.Naji@arm.com /** 30710618SOmar.Naji@arm.com * Keep track of when a refresh is due. 30810618SOmar.Naji@arm.com */ 30910618SOmar.Naji@arm.com Tick refreshDueAt; 31010618SOmar.Naji@arm.com 31110618SOmar.Naji@arm.com /* 31210618SOmar.Naji@arm.com * Command energies 31310618SOmar.Naji@arm.com */ 31410618SOmar.Naji@arm.com Stats::Scalar actEnergy; 31510618SOmar.Naji@arm.com Stats::Scalar preEnergy; 31610618SOmar.Naji@arm.com Stats::Scalar readEnergy; 31710618SOmar.Naji@arm.com Stats::Scalar writeEnergy; 31810618SOmar.Naji@arm.com Stats::Scalar refreshEnergy; 31910618SOmar.Naji@arm.com 32010618SOmar.Naji@arm.com /* 32110618SOmar.Naji@arm.com * Active Background Energy 32210618SOmar.Naji@arm.com */ 32310618SOmar.Naji@arm.com Stats::Scalar actBackEnergy; 32410618SOmar.Naji@arm.com 32510618SOmar.Naji@arm.com /* 32610618SOmar.Naji@arm.com * Precharge Background Energy 32710618SOmar.Naji@arm.com */ 32810618SOmar.Naji@arm.com Stats::Scalar preBackEnergy; 32910618SOmar.Naji@arm.com 33011678Swendy.elsasser@arm.com /* 33111678Swendy.elsasser@arm.com * Active Power-Down Energy 33211678Swendy.elsasser@arm.com */ 33311678Swendy.elsasser@arm.com Stats::Scalar actPowerDownEnergy; 33411678Swendy.elsasser@arm.com 33511678Swendy.elsasser@arm.com /* 33611678Swendy.elsasser@arm.com * Precharge Power-Down Energy 33711678Swendy.elsasser@arm.com */ 33811678Swendy.elsasser@arm.com Stats::Scalar prePowerDownEnergy; 33911678Swendy.elsasser@arm.com 34011678Swendy.elsasser@arm.com /* 34111678Swendy.elsasser@arm.com * self Refresh Energy 34211678Swendy.elsasser@arm.com */ 34311678Swendy.elsasser@arm.com Stats::Scalar selfRefreshEnergy; 34411678Swendy.elsasser@arm.com 34510618SOmar.Naji@arm.com Stats::Scalar totalEnergy; 34610618SOmar.Naji@arm.com Stats::Scalar averagePower; 34710618SOmar.Naji@arm.com 34810618SOmar.Naji@arm.com /** 34911678Swendy.elsasser@arm.com * Stat to track total DRAM idle time 35011678Swendy.elsasser@arm.com * 35111678Swendy.elsasser@arm.com */ 35211678Swendy.elsasser@arm.com Stats::Scalar totalIdleTime; 35311678Swendy.elsasser@arm.com 35411678Swendy.elsasser@arm.com /** 35510618SOmar.Naji@arm.com * Track time spent in each power state. 35610618SOmar.Naji@arm.com */ 35710618SOmar.Naji@arm.com Stats::Vector pwrStateTime; 35810618SOmar.Naji@arm.com 35910618SOmar.Naji@arm.com /** 36010618SOmar.Naji@arm.com * Function to update Power Stats 36110618SOmar.Naji@arm.com */ 36210618SOmar.Naji@arm.com void updatePowerStats(); 36310618SOmar.Naji@arm.com 36410618SOmar.Naji@arm.com /** 36510618SOmar.Naji@arm.com * Schedule a power state transition in the future, and 36610618SOmar.Naji@arm.com * potentially override an already scheduled transition. 36710618SOmar.Naji@arm.com * 36810618SOmar.Naji@arm.com * @param pwr_state Power state to transition to 36910618SOmar.Naji@arm.com * @param tick Tick when transition should take place 37010618SOmar.Naji@arm.com */ 37110618SOmar.Naji@arm.com void schedulePowerEvent(PowerState pwr_state, Tick tick); 37210618SOmar.Naji@arm.com 37310618SOmar.Naji@arm.com public: 37410618SOmar.Naji@arm.com 37510618SOmar.Naji@arm.com /** 37611678Swendy.elsasser@arm.com * Current power state. 37711678Swendy.elsasser@arm.com */ 37811678Swendy.elsasser@arm.com PowerState pwrState; 37911678Swendy.elsasser@arm.com 38011678Swendy.elsasser@arm.com /** 38111678Swendy.elsasser@arm.com * current refresh state 38211678Swendy.elsasser@arm.com */ 38311678Swendy.elsasser@arm.com RefreshState refreshState; 38411678Swendy.elsasser@arm.com 38511678Swendy.elsasser@arm.com /** 38611678Swendy.elsasser@arm.com * rank is in or transitioning to power-down or self-refresh 38711678Swendy.elsasser@arm.com */ 38811678Swendy.elsasser@arm.com bool inLowPowerState; 38911678Swendy.elsasser@arm.com 39011678Swendy.elsasser@arm.com /** 39110618SOmar.Naji@arm.com * Current Rank index 39210618SOmar.Naji@arm.com */ 39310618SOmar.Naji@arm.com uint8_t rank; 39410618SOmar.Naji@arm.com 39511678Swendy.elsasser@arm.com /** 39611678Swendy.elsasser@arm.com * Track number of packets in read queue going to this rank 39711678Swendy.elsasser@arm.com */ 39811678Swendy.elsasser@arm.com uint32_t readEntries; 39911678Swendy.elsasser@arm.com 40011678Swendy.elsasser@arm.com /** 40111678Swendy.elsasser@arm.com * Track number of packets in write queue going to this rank 40211678Swendy.elsasser@arm.com */ 40311678Swendy.elsasser@arm.com uint32_t writeEntries; 40411678Swendy.elsasser@arm.com 40511678Swendy.elsasser@arm.com /** 40611678Swendy.elsasser@arm.com * Number of ACT, RD, and WR events currently scheduled 40711678Swendy.elsasser@arm.com * Incremented when a refresh event is started as well 40811678Swendy.elsasser@arm.com * Used to determine when a low-power state can be entered 40911678Swendy.elsasser@arm.com */ 41011678Swendy.elsasser@arm.com uint8_t outstandingEvents; 41111678Swendy.elsasser@arm.com 41211678Swendy.elsasser@arm.com /** 41311678Swendy.elsasser@arm.com * delay power-down and self-refresh exit until this requirement is met 41411678Swendy.elsasser@arm.com */ 41511678Swendy.elsasser@arm.com Tick wakeUpAllowedAt; 41611678Swendy.elsasser@arm.com 41710618SOmar.Naji@arm.com /** 41810618SOmar.Naji@arm.com * One DRAMPower instance per rank 41910618SOmar.Naji@arm.com */ 42010618SOmar.Naji@arm.com DRAMPower power; 42110618SOmar.Naji@arm.com 42210618SOmar.Naji@arm.com /** 42312969SMatteo.Andreozzi@arm.com * List of commands issued, to be sent to DRAMPpower at refresh 42411675Swendy.elsasser@arm.com * and stats dump. Keep commands here since commands to different 42511675Swendy.elsasser@arm.com * banks are added out of order. Will only pass commands up to 42611675Swendy.elsasser@arm.com * curTick() to DRAMPower after sorting. 42711675Swendy.elsasser@arm.com */ 42811675Swendy.elsasser@arm.com std::vector<Command> cmdList; 42911675Swendy.elsasser@arm.com 43011675Swendy.elsasser@arm.com /** 43110618SOmar.Naji@arm.com * Vector of Banks. Each rank is made of several devices which in 43210618SOmar.Naji@arm.com * term are made from several banks. 43310618SOmar.Naji@arm.com */ 43410618SOmar.Naji@arm.com std::vector<Bank> banks; 43510618SOmar.Naji@arm.com 43610618SOmar.Naji@arm.com /** 43710618SOmar.Naji@arm.com * To track number of banks which are currently active for 43810618SOmar.Naji@arm.com * this rank. 43910618SOmar.Naji@arm.com */ 44010618SOmar.Naji@arm.com unsigned int numBanksActive; 44110618SOmar.Naji@arm.com 44210618SOmar.Naji@arm.com /** List to keep track of activate ticks */ 44310618SOmar.Naji@arm.com std::deque<Tick> actTicks; 44410618SOmar.Naji@arm.com 44512081Sspwilson2@wisc.edu Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p, int rank); 44610618SOmar.Naji@arm.com 44710618SOmar.Naji@arm.com const std::string name() const 44810618SOmar.Naji@arm.com { 44910618SOmar.Naji@arm.com return csprintf("%s_%d", memory.name(), rank); 45010618SOmar.Naji@arm.com } 45110618SOmar.Naji@arm.com 45210618SOmar.Naji@arm.com /** 45310618SOmar.Naji@arm.com * Kick off accounting for power and refresh states and 45410618SOmar.Naji@arm.com * schedule initial refresh. 45510618SOmar.Naji@arm.com * 45610618SOmar.Naji@arm.com * @param ref_tick Tick for first refresh 45710618SOmar.Naji@arm.com */ 45810618SOmar.Naji@arm.com void startup(Tick ref_tick); 45910618SOmar.Naji@arm.com 46010618SOmar.Naji@arm.com /** 46110619Sandreas.hansson@arm.com * Stop the refresh events. 46210619Sandreas.hansson@arm.com */ 46310619Sandreas.hansson@arm.com void suspend(); 46410619Sandreas.hansson@arm.com 46510619Sandreas.hansson@arm.com /** 46612266Sradhika.jagtap@arm.com * Check if there is no refresh and no preparation of refresh ongoing 46712266Sradhika.jagtap@arm.com * i.e. the refresh state machine is in idle 46810618SOmar.Naji@arm.com * 46910618SOmar.Naji@arm.com * @param Return true if the rank is idle from a refresh point of view 47010618SOmar.Naji@arm.com */ 47112266Sradhika.jagtap@arm.com bool inRefIdleState() const { return refreshState == REF_IDLE; } 47210618SOmar.Naji@arm.com 47310618SOmar.Naji@arm.com /** 47411676Swendy.elsasser@arm.com * Check if the current rank has all banks closed and is not 47511676Swendy.elsasser@arm.com * in a low power state 47611676Swendy.elsasser@arm.com * 47711676Swendy.elsasser@arm.com * @param Return true if the rank is idle from a bank 47811676Swendy.elsasser@arm.com * and power point of view 47911676Swendy.elsasser@arm.com */ 48011676Swendy.elsasser@arm.com bool inPwrIdleState() const { return pwrState == PWR_IDLE; } 48111676Swendy.elsasser@arm.com 48211676Swendy.elsasser@arm.com /** 48311678Swendy.elsasser@arm.com * Trigger a self-refresh exit if there are entries enqueued 48411678Swendy.elsasser@arm.com * Exit if there are any read entries regardless of the bus state. 48511678Swendy.elsasser@arm.com * If we are currently issuing write commands, exit if we have any 48611678Swendy.elsasser@arm.com * write commands enqueued as well. 48711678Swendy.elsasser@arm.com * Could expand this in the future to analyze state of entire queue 48811678Swendy.elsasser@arm.com * if needed. 48911678Swendy.elsasser@arm.com * 49011678Swendy.elsasser@arm.com * @return boolean indicating self-refresh exit should be scheduled 49111678Swendy.elsasser@arm.com */ 49211678Swendy.elsasser@arm.com bool forceSelfRefreshExit() const { 49311678Swendy.elsasser@arm.com return (readEntries != 0) || 49411678Swendy.elsasser@arm.com ((memory.busStateNext == WRITE) && (writeEntries != 0)); 49511678Swendy.elsasser@arm.com } 49611678Swendy.elsasser@arm.com 49711678Swendy.elsasser@arm.com /** 49812705Swendy.elsasser@arm.com * Check if the command queue of current rank is idle 49911678Swendy.elsasser@arm.com * 50012705Swendy.elsasser@arm.com * @param Return true if the there are no commands in Q. 50112705Swendy.elsasser@arm.com * Bus direction determines queue checked. 50211678Swendy.elsasser@arm.com */ 50312705Swendy.elsasser@arm.com bool isQueueEmpty() const; 50411678Swendy.elsasser@arm.com 50511678Swendy.elsasser@arm.com /** 50610618SOmar.Naji@arm.com * Let the rank check if it was waiting for requests to drain 50710618SOmar.Naji@arm.com * to allow it to transition states. 50810618SOmar.Naji@arm.com */ 50910618SOmar.Naji@arm.com void checkDrainDone(); 51010618SOmar.Naji@arm.com 51111675Swendy.elsasser@arm.com /** 51211675Swendy.elsasser@arm.com * Push command out of cmdList queue that are scheduled at 51311675Swendy.elsasser@arm.com * or before curTick() to DRAMPower library 51411675Swendy.elsasser@arm.com * All commands before curTick are guaranteed to be complete 51511675Swendy.elsasser@arm.com * and can safely be flushed. 51611675Swendy.elsasser@arm.com */ 51711675Swendy.elsasser@arm.com void flushCmdList(); 51811675Swendy.elsasser@arm.com 51910618SOmar.Naji@arm.com /* 52010618SOmar.Naji@arm.com * Function to register Stats 52110618SOmar.Naji@arm.com */ 52210618SOmar.Naji@arm.com void regStats(); 52310618SOmar.Naji@arm.com 52411677Swendy.elsasser@arm.com /** 52511677Swendy.elsasser@arm.com * Computes stats just prior to dump event 52611677Swendy.elsasser@arm.com */ 52711677Swendy.elsasser@arm.com void computeStats(); 52811677Swendy.elsasser@arm.com 52911678Swendy.elsasser@arm.com /** 53012266Sradhika.jagtap@arm.com * Reset stats on a stats event 53112266Sradhika.jagtap@arm.com */ 53212266Sradhika.jagtap@arm.com void resetStats(); 53312266Sradhika.jagtap@arm.com 53412266Sradhika.jagtap@arm.com /** 53511678Swendy.elsasser@arm.com * Schedule a transition to power-down (sleep) 53611678Swendy.elsasser@arm.com * 53711678Swendy.elsasser@arm.com * @param pwr_state Power state to transition to 53811678Swendy.elsasser@arm.com * @param tick Absolute tick when transition should take place 53911678Swendy.elsasser@arm.com */ 54011678Swendy.elsasser@arm.com void powerDownSleep(PowerState pwr_state, Tick tick); 54111678Swendy.elsasser@arm.com 54211678Swendy.elsasser@arm.com /** 54311678Swendy.elsasser@arm.com * schedule and event to wake-up from power-down or self-refresh 54411678Swendy.elsasser@arm.com * and update bank timing parameters 54511678Swendy.elsasser@arm.com * 54611678Swendy.elsasser@arm.com * @param exit_delay Relative tick defining the delay required between 54711678Swendy.elsasser@arm.com * low-power exit and the next command 54811678Swendy.elsasser@arm.com */ 54911678Swendy.elsasser@arm.com void scheduleWakeUpEvent(Tick exit_delay); 55011678Swendy.elsasser@arm.com 55111678Swendy.elsasser@arm.com void processWriteDoneEvent(); 55212084Sspwilson2@wisc.edu EventFunctionWrapper writeDoneEvent; 55311678Swendy.elsasser@arm.com 55410618SOmar.Naji@arm.com void processActivateEvent(); 55512084Sspwilson2@wisc.edu EventFunctionWrapper activateEvent; 55610618SOmar.Naji@arm.com 55710618SOmar.Naji@arm.com void processPrechargeEvent(); 55812084Sspwilson2@wisc.edu EventFunctionWrapper prechargeEvent; 55910618SOmar.Naji@arm.com 56010618SOmar.Naji@arm.com void processRefreshEvent(); 56112084Sspwilson2@wisc.edu EventFunctionWrapper refreshEvent; 56210618SOmar.Naji@arm.com 56310618SOmar.Naji@arm.com void processPowerEvent(); 56412084Sspwilson2@wisc.edu EventFunctionWrapper powerEvent; 56510618SOmar.Naji@arm.com 56611678Swendy.elsasser@arm.com void processWakeUpEvent(); 56712084Sspwilson2@wisc.edu EventFunctionWrapper wakeUpEvent; 56811678Swendy.elsasser@arm.com 56910618SOmar.Naji@arm.com }; 57010618SOmar.Naji@arm.com 57112266Sradhika.jagtap@arm.com /** 57212266Sradhika.jagtap@arm.com * Define the process to compute stats on a stats dump event, e.g. on 57312266Sradhika.jagtap@arm.com * simulation exit or intermediate stats dump. This is defined per rank 57412266Sradhika.jagtap@arm.com * as the per rank stats are based on state transition and periodically 57512266Sradhika.jagtap@arm.com * updated, requiring re-sync at exit. 57612266Sradhika.jagtap@arm.com */ 57711677Swendy.elsasser@arm.com class RankDumpCallback : public Callback 57811677Swendy.elsasser@arm.com { 57911677Swendy.elsasser@arm.com Rank *ranks; 58011677Swendy.elsasser@arm.com public: 58111677Swendy.elsasser@arm.com RankDumpCallback(Rank *r) : ranks(r) {} 58211677Swendy.elsasser@arm.com virtual void process() { ranks->computeStats(); }; 58311677Swendy.elsasser@arm.com }; 58411677Swendy.elsasser@arm.com 58512266Sradhika.jagtap@arm.com /** Define a process to clear power lib counters on a stats reset */ 58612266Sradhika.jagtap@arm.com class RankResetCallback : public Callback 58712266Sradhika.jagtap@arm.com { 58812266Sradhika.jagtap@arm.com private: 58912266Sradhika.jagtap@arm.com /** Pointer to the rank, thus we instantiate per rank */ 59012266Sradhika.jagtap@arm.com Rank *rank; 59112266Sradhika.jagtap@arm.com 59212266Sradhika.jagtap@arm.com public: 59312266Sradhika.jagtap@arm.com RankResetCallback(Rank *r) : rank(r) {} 59412266Sradhika.jagtap@arm.com virtual void process() { rank->resetStats(); }; 59512266Sradhika.jagtap@arm.com }; 59612266Sradhika.jagtap@arm.com 59712266Sradhika.jagtap@arm.com /** Define a process to store the time on a stats reset */ 59812266Sradhika.jagtap@arm.com class MemResetCallback : public Callback 59912266Sradhika.jagtap@arm.com { 60012266Sradhika.jagtap@arm.com private: 60112266Sradhika.jagtap@arm.com /** A reference to the DRAMCtrl instance */ 60212266Sradhika.jagtap@arm.com DRAMCtrl *mem; 60312266Sradhika.jagtap@arm.com 60412266Sradhika.jagtap@arm.com public: 60512266Sradhika.jagtap@arm.com MemResetCallback(DRAMCtrl *_mem) : mem(_mem) {} 60612266Sradhika.jagtap@arm.com virtual void process() { mem->lastStatsResetTick = curTick(); }; 60712266Sradhika.jagtap@arm.com }; 60812266Sradhika.jagtap@arm.com 6099243SN/A /** 6109831SN/A * A burst helper helps organize and manage a packet that is larger than 6119831SN/A * the DRAM burst size. A system packet that is larger than the burst size 6129831SN/A * is split into multiple DRAM packets and all those DRAM packets point to 6139831SN/A * a single burst helper such that we know when the whole packet is served. 6149831SN/A */ 6159831SN/A class BurstHelper { 6169831SN/A 6179831SN/A public: 6189831SN/A 6199831SN/A /** Number of DRAM bursts requred for a system packet **/ 6209831SN/A const unsigned int burstCount; 6219831SN/A 6229831SN/A /** Number of DRAM bursts serviced so far for a system packet **/ 6239831SN/A unsigned int burstsServiced; 6249831SN/A 6259831SN/A BurstHelper(unsigned int _burstCount) 6269831SN/A : burstCount(_burstCount), burstsServiced(0) 62710618SOmar.Naji@arm.com { } 6289831SN/A }; 6299831SN/A 6309831SN/A /** 6319243SN/A * A DRAM packet stores packets along with the timestamp of when 6329243SN/A * the packet entered the queue, and also the decoded address. 6339243SN/A */ 6349243SN/A class DRAMPacket { 6359243SN/A 6369243SN/A public: 6379243SN/A 6389243SN/A /** When did request enter the controller */ 6399243SN/A const Tick entryTime; 6409243SN/A 6419243SN/A /** When will request leave the controller */ 6429243SN/A Tick readyTime; 6439243SN/A 6449243SN/A /** This comes from the outside world */ 6459243SN/A const PacketPtr pkt; 6469243SN/A 64712969SMatteo.Andreozzi@arm.com /** MasterID associated with the packet */ 64812969SMatteo.Andreozzi@arm.com const MasterID _masterId; 64912969SMatteo.Andreozzi@arm.com 65012969SMatteo.Andreozzi@arm.com const bool read; 6519966SN/A 6529243SN/A /** Will be populated by address decoder */ 6539243SN/A const uint8_t rank; 6549967SN/A const uint8_t bank; 65510245Sandreas.hansson@arm.com const uint32_t row; 6569831SN/A 6579831SN/A /** 6589967SN/A * Bank id is calculated considering banks in all the ranks 6599967SN/A * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and 6609967SN/A * bankId = 8 --> rank1, bank0 6619967SN/A */ 6629967SN/A const uint16_t bankId; 6639967SN/A 6649967SN/A /** 6659831SN/A * The starting address of the DRAM packet. 6669831SN/A * This address could be unaligned to burst size boundaries. The 6679831SN/A * reason is to keep the address offset so we can accurately check 6689831SN/A * incoming read packets with packets in the write queue. 6699831SN/A */ 6709832SN/A Addr addr; 6719831SN/A 6729831SN/A /** 6739831SN/A * The size of this dram packet in bytes 6749831SN/A * It is always equal or smaller than DRAM burst size 6759831SN/A */ 6769832SN/A unsigned int size; 6779831SN/A 6789831SN/A /** 6799831SN/A * A pointer to the BurstHelper if this DRAMPacket is a split packet 6809831SN/A * If not a split packet (common case), this is set to NULL 6819831SN/A */ 6829831SN/A BurstHelper* burstHelper; 6839967SN/A Bank& bankRef; 68410618SOmar.Naji@arm.com Rank& rankRef; 6859243SN/A 68612969SMatteo.Andreozzi@arm.com /** 68712969SMatteo.Andreozzi@arm.com * QoS value of the encapsulated packet read at queuing time 68812969SMatteo.Andreozzi@arm.com */ 68912969SMatteo.Andreozzi@arm.com uint8_t _qosValue; 69012969SMatteo.Andreozzi@arm.com 69112969SMatteo.Andreozzi@arm.com /** 69212969SMatteo.Andreozzi@arm.com * Set the packet QoS value 69312969SMatteo.Andreozzi@arm.com * (interface compatibility with Packet) 69412969SMatteo.Andreozzi@arm.com */ 69512969SMatteo.Andreozzi@arm.com inline void qosValue(const uint8_t qv) { _qosValue = qv; } 69612969SMatteo.Andreozzi@arm.com 69712969SMatteo.Andreozzi@arm.com /** 69812969SMatteo.Andreozzi@arm.com * Get the packet QoS value 69912969SMatteo.Andreozzi@arm.com * (interface compatibility with Packet) 70012969SMatteo.Andreozzi@arm.com */ 70112969SMatteo.Andreozzi@arm.com inline uint8_t qosValue() const { return _qosValue; } 70212969SMatteo.Andreozzi@arm.com 70312969SMatteo.Andreozzi@arm.com /** 70412969SMatteo.Andreozzi@arm.com * Get the packet MasterID 70512969SMatteo.Andreozzi@arm.com * (interface compatibility with Packet) 70612969SMatteo.Andreozzi@arm.com */ 70712969SMatteo.Andreozzi@arm.com inline MasterID masterId() const { return _masterId; } 70812969SMatteo.Andreozzi@arm.com 70912969SMatteo.Andreozzi@arm.com /** 71012969SMatteo.Andreozzi@arm.com * Get the packet size 71112969SMatteo.Andreozzi@arm.com * (interface compatibility with Packet) 71212969SMatteo.Andreozzi@arm.com */ 71312969SMatteo.Andreozzi@arm.com inline unsigned int getSize() const { return size; } 71412969SMatteo.Andreozzi@arm.com 71512969SMatteo.Andreozzi@arm.com /** 71612969SMatteo.Andreozzi@arm.com * Get the packet address 71712969SMatteo.Andreozzi@arm.com * (interface compatibility with Packet) 71812969SMatteo.Andreozzi@arm.com */ 71912969SMatteo.Andreozzi@arm.com inline Addr getAddr() const { return addr; } 72012969SMatteo.Andreozzi@arm.com 72112969SMatteo.Andreozzi@arm.com /** 72212969SMatteo.Andreozzi@arm.com * Return true if its a read packet 72312969SMatteo.Andreozzi@arm.com * (interface compatibility with Packet) 72412969SMatteo.Andreozzi@arm.com */ 72512969SMatteo.Andreozzi@arm.com inline bool isRead() const { return read; } 72612969SMatteo.Andreozzi@arm.com 72712969SMatteo.Andreozzi@arm.com /** 72812969SMatteo.Andreozzi@arm.com * Return true if its a write packet 72912969SMatteo.Andreozzi@arm.com * (interface compatibility with Packet) 73012969SMatteo.Andreozzi@arm.com */ 73112969SMatteo.Andreozzi@arm.com inline bool isWrite() const { return !read; } 73212969SMatteo.Andreozzi@arm.com 73312969SMatteo.Andreozzi@arm.com 7349967SN/A DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank, 73510245Sandreas.hansson@arm.com uint32_t _row, uint16_t bank_id, Addr _addr, 73610618SOmar.Naji@arm.com unsigned int _size, Bank& bank_ref, Rank& rank_ref) 73712969SMatteo.Andreozzi@arm.com : entryTime(curTick()), readyTime(curTick()), pkt(_pkt), 73812969SMatteo.Andreozzi@arm.com _masterId(pkt->masterId()), 73912969SMatteo.Andreozzi@arm.com read(is_read), rank(_rank), bank(_bank), row(_row), 7409967SN/A bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL), 74112969SMatteo.Andreozzi@arm.com bankRef(bank_ref), rankRef(rank_ref), _qosValue(_pkt->qosValue()) 7429243SN/A { } 7439243SN/A 7449243SN/A }; 7459243SN/A 74612969SMatteo.Andreozzi@arm.com // The DRAM packets are store in a multiple dequeue structure, 74712969SMatteo.Andreozzi@arm.com // based on their QoS priority 74812969SMatteo.Andreozzi@arm.com typedef std::deque<DRAMPacket*> DRAMPacketQueue; 74912969SMatteo.Andreozzi@arm.com 7509243SN/A /** 7519243SN/A * Bunch of things requires to setup "events" in gem5 75210206Sandreas.hansson@arm.com * When event "respondEvent" occurs for example, the method 75310206Sandreas.hansson@arm.com * processRespondEvent is called; no parameters are allowed 7549243SN/A * in these methods 7559243SN/A */ 75610208Sandreas.hansson@arm.com void processNextReqEvent(); 75712084Sspwilson2@wisc.edu EventFunctionWrapper nextReqEvent; 75810208Sandreas.hansson@arm.com 7599243SN/A void processRespondEvent(); 76012084Sspwilson2@wisc.edu EventFunctionWrapper respondEvent; 7619243SN/A 7629243SN/A /** 7639243SN/A * Check if the read queue has room for more entries 7649243SN/A * 7659831SN/A * @param pktCount The number of entries needed in the read queue 7669243SN/A * @return true if read queue is full, false otherwise 7679243SN/A */ 7689831SN/A bool readQueueFull(unsigned int pktCount) const; 7699243SN/A 7709243SN/A /** 7719243SN/A * Check if the write queue has room for more entries 7729243SN/A * 7739831SN/A * @param pktCount The number of entries needed in the write queue 7749243SN/A * @return true if write queue is full, false otherwise 7759243SN/A */ 7769831SN/A bool writeQueueFull(unsigned int pktCount) const; 7779243SN/A 7789243SN/A /** 7799243SN/A * When a new read comes in, first check if the write q has a 7809243SN/A * pending request to the same address.\ If not, decode the 7819831SN/A * address to populate rank/bank/row, create one or mutliple 7829831SN/A * "dram_pkt", and push them to the back of the read queue.\ 7839831SN/A * If this is the only 7849243SN/A * read request in the system, schedule an event to start 7859243SN/A * servicing it. 7869243SN/A * 7879243SN/A * @param pkt The request packet from the outside world 7889831SN/A * @param pktCount The number of DRAM bursts the pkt 7899831SN/A * translate to. If pkt size is larger then one full burst, 7909831SN/A * then pktCount is greater than one. 7919243SN/A */ 7929831SN/A void addToReadQueue(PacketPtr pkt, unsigned int pktCount); 7939243SN/A 7949243SN/A /** 7959243SN/A * Decode the incoming pkt, create a dram_pkt and push to the 7969243SN/A * back of the write queue. \If the write q length is more than 7979243SN/A * the threshold specified by the user, ie the queue is beginning 7989243SN/A * to get full, stop reads, and start draining writes. 7999243SN/A * 8009243SN/A * @param pkt The request packet from the outside world 8019831SN/A * @param pktCount The number of DRAM bursts the pkt 8029831SN/A * translate to. If pkt size is larger then one full burst, 8039831SN/A * then pktCount is greater than one. 8049243SN/A */ 8059831SN/A void addToWriteQueue(PacketPtr pkt, unsigned int pktCount); 8069243SN/A 8079243SN/A /** 8089243SN/A * Actually do the DRAM access - figure out the latency it 8099243SN/A * will take to service the req based on bank state, channel state etc 8109243SN/A * and then update those states to account for this request.\ Based 8119243SN/A * on this, update the packet's "readyTime" and move it to the 8129243SN/A * response q from where it will eventually go back to the outside 8139243SN/A * world. 8149243SN/A * 8159243SN/A * @param pkt The DRAM packet created from the outside world pkt 8169243SN/A */ 8179243SN/A void doDRAMAccess(DRAMPacket* dram_pkt); 8189243SN/A 8199243SN/A /** 8209243SN/A * When a packet reaches its "readyTime" in the response Q, 8219243SN/A * use the "access()" method in AbstractMemory to actually 8229243SN/A * create the response packet, and send it back to the outside 8239243SN/A * world requestor. 8249243SN/A * 8259243SN/A * @param pkt The packet from the outside world 8269726SN/A * @param static_latency Static latency to add before sending the packet 8279243SN/A */ 8289726SN/A void accessAndRespond(PacketPtr pkt, Tick static_latency); 8299243SN/A 8309243SN/A /** 8319243SN/A * Address decoder to figure out physical mapping onto ranks, 8329831SN/A * banks, and rows. This function is called multiple times on the same 8339831SN/A * system packet if the pakcet is larger than burst of the memory. The 8349831SN/A * dramPktAddr is used for the offset within the packet. 8359243SN/A * 8369243SN/A * @param pkt The packet from the outside world 8379831SN/A * @param dramPktAddr The starting address of the DRAM packet 8389831SN/A * @param size The size of the DRAM packet in bytes 8399966SN/A * @param isRead Is the request for a read or a write to DRAM 8409243SN/A * @return A DRAMPacket pointer with the decoded information 8419243SN/A */ 84213857Sodanrc@yahoo.com.br DRAMPacket* decodeAddr(const PacketPtr pkt, Addr dramPktAddr, 84313857Sodanrc@yahoo.com.br unsigned int size, bool isRead) const; 8449243SN/A 8459243SN/A /** 84610206Sandreas.hansson@arm.com * The memory schduler/arbiter - picks which request needs to 8479567SN/A * go next, based on the specified policy such as FCFS or FR-FCFS 84810206Sandreas.hansson@arm.com * and moves it to the head of the queue. 84910393Swendy.elsasser@arm.com * Prioritizes accesses to the same rank as previous burst unless 85010393Swendy.elsasser@arm.com * controller is switching command type. 85110393Swendy.elsasser@arm.com * 85210393Swendy.elsasser@arm.com * @param queue Queued requests to consider 85310890Swendy.elsasser@arm.com * @param extra_col_delay Any extra delay due to a read/write switch 85412969SMatteo.Andreozzi@arm.com * @return an iterator to the selected packet, else queue.end() 8559243SN/A */ 85612969SMatteo.Andreozzi@arm.com DRAMPacketQueue::iterator chooseNext(DRAMPacketQueue& queue, 85712969SMatteo.Andreozzi@arm.com Tick extra_col_delay); 8589243SN/A 8599243SN/A /** 8609974SN/A * For FR-FCFS policy reorder the read/write queue depending on row buffer 86110890Swendy.elsasser@arm.com * hits and earliest bursts available in DRAM 86210393Swendy.elsasser@arm.com * 86310393Swendy.elsasser@arm.com * @param queue Queued requests to consider 86410890Swendy.elsasser@arm.com * @param extra_col_delay Any extra delay due to a read/write switch 86512969SMatteo.Andreozzi@arm.com * @return an iterator to the selected packet, else queue.end() 8669974SN/A */ 86712969SMatteo.Andreozzi@arm.com DRAMPacketQueue::iterator chooseNextFRFCFS(DRAMPacketQueue& queue, 86812969SMatteo.Andreozzi@arm.com Tick extra_col_delay); 8699974SN/A 8709974SN/A /** 87110211Sandreas.hansson@arm.com * Find which are the earliest banks ready to issue an activate 87212706Swendy.elsasser@arm.com * for the enqueued requests. Assumes maximum of 32 banks per rank 87310393Swendy.elsasser@arm.com * Also checks if the bank is already prepped. 8749967SN/A * 87510393Swendy.elsasser@arm.com * @param queue Queued requests to consider 87612706Swendy.elsasser@arm.com * @param min_col_at time of seamless burst command 8779967SN/A * @return One-hot encoded mask of bank indices 87810890Swendy.elsasser@arm.com * @return boolean indicating burst can issue seamlessly, with no gaps 8799967SN/A */ 88012969SMatteo.Andreozzi@arm.com std::pair<std::vector<uint32_t>, bool> 88112969SMatteo.Andreozzi@arm.com minBankPrep(const DRAMPacketQueue& queue, Tick min_col_at) const; 8829488SN/A 8839488SN/A /** 8849488SN/A * Keep track of when row activations happen, in order to enforce 8859488SN/A * the maximum number of activations in the activation window. The 8869488SN/A * method updates the time that the banks become available based 8879488SN/A * on the current limits. 88810210Sandreas.hansson@arm.com * 88910618SOmar.Naji@arm.com * @param rank_ref Reference to the rank 89010618SOmar.Naji@arm.com * @param bank_ref Reference to the bank 89110210Sandreas.hansson@arm.com * @param act_tick Time when the activation takes place 89210210Sandreas.hansson@arm.com * @param row Index of the row 8939488SN/A */ 89410618SOmar.Naji@arm.com void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick, 89510618SOmar.Naji@arm.com uint32_t row); 89610207Sandreas.hansson@arm.com 89710207Sandreas.hansson@arm.com /** 89810207Sandreas.hansson@arm.com * Precharge a given bank and also update when the precharge is 89910207Sandreas.hansson@arm.com * done. This will also deal with any stats related to the 90010207Sandreas.hansson@arm.com * accesses to the open page. 90110207Sandreas.hansson@arm.com * 90210618SOmar.Naji@arm.com * @param rank_ref The rank to precharge 90310247Sandreas.hansson@arm.com * @param bank_ref The bank to precharge 90410211Sandreas.hansson@arm.com * @param pre_at Time when the precharge takes place 90510247Sandreas.hansson@arm.com * @param trace Is this an auto precharge then do not add to trace 90610207Sandreas.hansson@arm.com */ 90710618SOmar.Naji@arm.com void prechargeBank(Rank& rank_ref, Bank& bank_ref, 90810618SOmar.Naji@arm.com Tick pre_at, bool trace = true); 9099488SN/A 91010143SN/A /** 91110143SN/A * Used for debugging to observe the contents of the queues. 91210143SN/A */ 9139243SN/A void printQs() const; 9149243SN/A 9159243SN/A /** 91610889Sandreas.hansson@arm.com * Burst-align an address. 91710889Sandreas.hansson@arm.com * 91810889Sandreas.hansson@arm.com * @param addr The potentially unaligned address 91910889Sandreas.hansson@arm.com * 92010889Sandreas.hansson@arm.com * @return An address aligned to a DRAM burst 92110889Sandreas.hansson@arm.com */ 92210889Sandreas.hansson@arm.com Addr burstAlign(Addr addr) const { return (addr & ~(Addr(burstSize - 1))); } 92310889Sandreas.hansson@arm.com 92410889Sandreas.hansson@arm.com /** 92512969SMatteo.Andreozzi@arm.com * The controller's main read and write queues, with support for QoS reordering 9269243SN/A */ 92712969SMatteo.Andreozzi@arm.com std::vector<DRAMPacketQueue> readQueue; 92812969SMatteo.Andreozzi@arm.com std::vector<DRAMPacketQueue> writeQueue; 9299243SN/A 9309243SN/A /** 93110889Sandreas.hansson@arm.com * To avoid iterating over the write queue to check for 93210889Sandreas.hansson@arm.com * overlapping transactions, maintain a set of burst addresses 93310889Sandreas.hansson@arm.com * that are currently queued. Since we merge writes to the same 93410889Sandreas.hansson@arm.com * location we never have more than one address to the same burst 93510889Sandreas.hansson@arm.com * address. 93610889Sandreas.hansson@arm.com */ 93710889Sandreas.hansson@arm.com std::unordered_set<Addr> isInWriteQueue; 93810889Sandreas.hansson@arm.com 93910889Sandreas.hansson@arm.com /** 9409243SN/A * Response queue where read packets wait after we're done working 9419567SN/A * with them, but it's not time to send the response yet. The 94212969SMatteo.Andreozzi@arm.com * responses are stored separately mostly to keep the code clean 9439567SN/A * and help with events scheduling. For all logical purposes such 9449567SN/A * as sizing the read queue, this and the main read queue need to 9459567SN/A * be added together. 9469243SN/A */ 9479833SN/A std::deque<DRAMPacket*> respQueue; 9489243SN/A 9499567SN/A /** 95010618SOmar.Naji@arm.com * Vector of ranks 9519243SN/A */ 95210618SOmar.Naji@arm.com std::vector<Rank*> ranks; 9539243SN/A 9549243SN/A /** 9559243SN/A * The following are basic design parameters of the memory 9569831SN/A * controller, and are initialized based on parameter values. 9579831SN/A * The rowsPerBank is determined based on the capacity, number of 9589831SN/A * ranks and banks, the burst size, and the row buffer size. 9599243SN/A */ 96010489SOmar.Naji@arm.com const uint32_t deviceSize; 9619831SN/A const uint32_t deviceBusWidth; 9629831SN/A const uint32_t burstLength; 9639831SN/A const uint32_t deviceRowBufferSize; 9649831SN/A const uint32_t devicesPerRank; 9659831SN/A const uint32_t burstSize; 9669831SN/A const uint32_t rowBufferSize; 96710140SN/A const uint32_t columnsPerRowBuffer; 96810286Sandreas.hansson@arm.com const uint32_t columnsPerStripe; 9699243SN/A const uint32_t ranksPerChannel; 97010394Swendy.elsasser@arm.com const uint32_t bankGroupsPerRank; 97110394Swendy.elsasser@arm.com const bool bankGroupArch; 9729243SN/A const uint32_t banksPerRank; 9739566SN/A const uint32_t channels; 9749243SN/A uint32_t rowsPerBank; 9759243SN/A const uint32_t readBufferSize; 9769243SN/A const uint32_t writeBufferSize; 97710140SN/A const uint32_t writeHighThreshold; 97810140SN/A const uint32_t writeLowThreshold; 97910140SN/A const uint32_t minWritesPerSwitch; 98010140SN/A uint32_t writesThisTime; 98110147Sandreas.hansson@arm.com uint32_t readsThisTime; 9829243SN/A 9839243SN/A /** 9849243SN/A * Basic memory timing parameters initialized based on parameter 9859243SN/A * values. 9869243SN/A */ 98710286Sandreas.hansson@arm.com const Tick M5_CLASS_VAR_USED tCK; 98810206Sandreas.hansson@arm.com const Tick tRTW; 98910393Swendy.elsasser@arm.com const Tick tCS; 9909243SN/A const Tick tBURST; 99112706Swendy.elsasser@arm.com const Tick tCCD_L_WR; 99210394Swendy.elsasser@arm.com const Tick tCCD_L; 9939243SN/A const Tick tRCD; 9949243SN/A const Tick tCL; 9959243SN/A const Tick tRP; 9969963SN/A const Tick tRAS; 99710210Sandreas.hansson@arm.com const Tick tWR; 99810212Sandreas.hansson@arm.com const Tick tRTP; 9999243SN/A const Tick tRFC; 10009243SN/A const Tick tREFI; 10019971SN/A const Tick tRRD; 100210394Swendy.elsasser@arm.com const Tick tRRD_L; 10039488SN/A const Tick tXAW; 100411673SOmar.Naji@arm.com const Tick tXP; 100511673SOmar.Naji@arm.com const Tick tXS; 10069488SN/A const uint32_t activationLimit; 100712706Swendy.elsasser@arm.com const Tick rankToRankDly; 100812706Swendy.elsasser@arm.com const Tick wrToRdDly; 100912706Swendy.elsasser@arm.com const Tick rdToWrDly; 10109243SN/A 10119243SN/A /** 10129243SN/A * Memory controller configuration initialized based on parameter 10139243SN/A * values. 10149243SN/A */ 10159243SN/A Enums::MemSched memSchedPolicy; 10169243SN/A Enums::AddrMap addrMapping; 10179243SN/A Enums::PageManage pageMgmt; 10189243SN/A 10199243SN/A /** 102012969SMatteo.Andreozzi@arm.com * Max column accesses (read and write) per row, before forcefully 102110141SN/A * closing it. 102210141SN/A */ 102310141SN/A const uint32_t maxAccessesPerRow; 102410141SN/A 102510141SN/A /** 10269726SN/A * Pipeline latency of the controller frontend. The frontend 10279726SN/A * contribution is added to writes (that complete when they are in 10289726SN/A * the write buffer) and reads that are serviced the write buffer. 10299726SN/A */ 10309726SN/A const Tick frontendLatency; 10319726SN/A 10329726SN/A /** 10339726SN/A * Pipeline latency of the backend and PHY. Along with the 10349726SN/A * frontend contribution, this latency is added to reads serviced 10359726SN/A * by the DRAM. 10369726SN/A */ 10379726SN/A const Tick backendLatency; 10389726SN/A 10399726SN/A /** 104012706Swendy.elsasser@arm.com * Till when must we wait before issuing next RD/WR burst? 10419243SN/A */ 104212706Swendy.elsasser@arm.com Tick nextBurstAt; 10439243SN/A 10449243SN/A Tick prevArrival; 10459243SN/A 104610206Sandreas.hansson@arm.com /** 104710206Sandreas.hansson@arm.com * The soonest you have to start thinking about the next request 104810206Sandreas.hansson@arm.com * is the longest access time that can occur before 104912706Swendy.elsasser@arm.com * nextBurstAt. Assuming you need to precharge, open a new row, 105010206Sandreas.hansson@arm.com * and access, it is tRP + tRCD + tCL. 105110206Sandreas.hansson@arm.com */ 105210206Sandreas.hansson@arm.com Tick nextReqTime; 10539972SN/A 10549243SN/A // All statistics that the model needs to capture 10559243SN/A Stats::Scalar readReqs; 10569243SN/A Stats::Scalar writeReqs; 10579831SN/A Stats::Scalar readBursts; 10589831SN/A Stats::Scalar writeBursts; 10599975SN/A Stats::Scalar bytesReadDRAM; 10609975SN/A Stats::Scalar bytesReadWrQ; 10619243SN/A Stats::Scalar bytesWritten; 10629977SN/A Stats::Scalar bytesReadSys; 10639977SN/A Stats::Scalar bytesWrittenSys; 10649243SN/A Stats::Scalar servicedByWrQ; 10659977SN/A Stats::Scalar mergedWrBursts; 10669243SN/A Stats::Scalar neitherReadNorWrite; 10679977SN/A Stats::Vector perBankRdBursts; 10689977SN/A Stats::Vector perBankWrBursts; 10699243SN/A Stats::Scalar numRdRetry; 10709243SN/A Stats::Scalar numWrRetry; 10719243SN/A Stats::Scalar totGap; 10729243SN/A Stats::Vector readPktSize; 10739243SN/A Stats::Vector writePktSize; 10749243SN/A Stats::Vector rdQLenPdf; 10759243SN/A Stats::Vector wrQLenPdf; 10769727SN/A Stats::Histogram bytesPerActivate; 107710147Sandreas.hansson@arm.com Stats::Histogram rdPerTurnAround; 107810147Sandreas.hansson@arm.com Stats::Histogram wrPerTurnAround; 10799243SN/A 108012969SMatteo.Andreozzi@arm.com // per-master bytes read and written to memory 108112969SMatteo.Andreozzi@arm.com Stats::Vector masterReadBytes; 108212969SMatteo.Andreozzi@arm.com Stats::Vector masterWriteBytes; 108312969SMatteo.Andreozzi@arm.com 108412969SMatteo.Andreozzi@arm.com // per-master bytes read and written to memory rate 108512969SMatteo.Andreozzi@arm.com Stats::Formula masterReadRate; 108612969SMatteo.Andreozzi@arm.com Stats::Formula masterWriteRate; 108712969SMatteo.Andreozzi@arm.com 108812969SMatteo.Andreozzi@arm.com // per-master read and write serviced memory accesses 108912969SMatteo.Andreozzi@arm.com Stats::Vector masterReadAccesses; 109012969SMatteo.Andreozzi@arm.com Stats::Vector masterWriteAccesses; 109112969SMatteo.Andreozzi@arm.com 109212969SMatteo.Andreozzi@arm.com // per-master read and write total memory access latency 109312969SMatteo.Andreozzi@arm.com Stats::Vector masterReadTotalLat; 109412969SMatteo.Andreozzi@arm.com Stats::Vector masterWriteTotalLat; 109512969SMatteo.Andreozzi@arm.com 109612969SMatteo.Andreozzi@arm.com // per-master raed and write average memory access latency 109712969SMatteo.Andreozzi@arm.com Stats::Formula masterReadAvgLat; 109812969SMatteo.Andreozzi@arm.com Stats::Formula masterWriteAvgLat; 109912969SMatteo.Andreozzi@arm.com 11009243SN/A // Latencies summed over all requests 11019243SN/A Stats::Scalar totQLat; 11029243SN/A Stats::Scalar totMemAccLat; 11039243SN/A Stats::Scalar totBusLat; 11049243SN/A 11059243SN/A // Average latencies per request 11069243SN/A Stats::Formula avgQLat; 11079243SN/A Stats::Formula avgBusLat; 11089243SN/A Stats::Formula avgMemAccLat; 11099243SN/A 11109243SN/A // Average bandwidth 11119243SN/A Stats::Formula avgRdBW; 11129243SN/A Stats::Formula avgWrBW; 11139977SN/A Stats::Formula avgRdBWSys; 11149977SN/A Stats::Formula avgWrBWSys; 11159243SN/A Stats::Formula peakBW; 11169243SN/A Stats::Formula busUtil; 11179975SN/A Stats::Formula busUtilRead; 11189975SN/A Stats::Formula busUtilWrite; 11199243SN/A 11209243SN/A // Average queue lengths 11219243SN/A Stats::Average avgRdQLen; 11229243SN/A Stats::Average avgWrQLen; 11239243SN/A 11249243SN/A // Row hit count and rate 11259243SN/A Stats::Scalar readRowHits; 11269243SN/A Stats::Scalar writeRowHits; 11279243SN/A Stats::Formula readRowHitRate; 11289243SN/A Stats::Formula writeRowHitRate; 11299243SN/A Stats::Formula avgGap; 11309243SN/A 11319975SN/A // DRAM Power Calculation 11329975SN/A Stats::Formula pageHitRate; 11339975SN/A 113410393Swendy.elsasser@arm.com // Holds the value of the rank of burst issued 113510393Swendy.elsasser@arm.com uint8_t activeRank; 113610393Swendy.elsasser@arm.com 113710432SOmar.Naji@arm.com // timestamp offset 113810432SOmar.Naji@arm.com uint64_t timeStampOffset; 113910432SOmar.Naji@arm.com 114012266Sradhika.jagtap@arm.com /** The time when stats were last reset used to calculate average power */ 114112266Sradhika.jagtap@arm.com Tick lastStatsResetTick; 114212266Sradhika.jagtap@arm.com 114314038Smatthew.poremba@amd.com /** Enable or disable DRAM powerdown states. */ 114414038Smatthew.poremba@amd.com bool enableDRAMPowerdown; 114514038Smatthew.poremba@amd.com 114611190Sandreas.hansson@arm.com /** 114711190Sandreas.hansson@arm.com * Upstream caches need this packet until true is returned, so 114811190Sandreas.hansson@arm.com * hold it for deletion until a subsequent call 11499349SN/A */ 115011190Sandreas.hansson@arm.com std::unique_ptr<Packet> pendingDelete; 11519349SN/A 115210432SOmar.Naji@arm.com /** 115310618SOmar.Naji@arm.com * This function increments the energy when called. If stats are 115410618SOmar.Naji@arm.com * dumped periodically, note accumulated energy values will 115510618SOmar.Naji@arm.com * appear in the stats (even if the stats are reset). This is a 115610618SOmar.Naji@arm.com * result of the energy values coming from DRAMPower, and there 115710618SOmar.Naji@arm.com * is currently no support for resetting the state. 115810618SOmar.Naji@arm.com * 115912969SMatteo.Andreozzi@arm.com * @param rank Current rank 116010618SOmar.Naji@arm.com */ 116110618SOmar.Naji@arm.com void updatePowerStats(Rank& rank_ref); 116210432SOmar.Naji@arm.com 116310432SOmar.Naji@arm.com /** 116411675Swendy.elsasser@arm.com * Function for sorting Command structures based on timeStamp 116510432SOmar.Naji@arm.com * 116611675Swendy.elsasser@arm.com * @param a Memory Command 116711675Swendy.elsasser@arm.com * @param next Memory Command 116811675Swendy.elsasser@arm.com * @return true if timeStamp of Command 1 < timeStamp of Command 2 116910432SOmar.Naji@arm.com */ 117011675Swendy.elsasser@arm.com static bool sortTime(const Command& cmd, const Command& cmd_next) { 117111675Swendy.elsasser@arm.com return cmd.timeStamp < cmd_next.timeStamp; 117210432SOmar.Naji@arm.com }; 117310432SOmar.Naji@arm.com 11749243SN/A public: 11759243SN/A 117611169Sandreas.hansson@arm.com void regStats() override; 11779243SN/A 117810146Sandreas.hansson@arm.com DRAMCtrl(const DRAMCtrlParams* p); 11799243SN/A 118011168Sandreas.hansson@arm.com DrainState drain() override; 11819243SN/A 118213784Sgabeblack@google.com Port &getPort(const std::string &if_name, 118313784Sgabeblack@google.com PortID idx=InvalidPortID) override; 11849243SN/A 118511168Sandreas.hansson@arm.com virtual void init() override; 118611168Sandreas.hansson@arm.com virtual void startup() override; 118711168Sandreas.hansson@arm.com virtual void drainResume() override; 11889243SN/A 118911676Swendy.elsasser@arm.com /** 119011676Swendy.elsasser@arm.com * Return true once refresh is complete for all ranks and there are no 119111676Swendy.elsasser@arm.com * additional commands enqueued. (only evaluated when draining) 119211676Swendy.elsasser@arm.com * This will ensure that all banks are closed, power state is IDLE, and 119311676Swendy.elsasser@arm.com * power stats have been updated 119411676Swendy.elsasser@arm.com * 119511676Swendy.elsasser@arm.com * @return true if all ranks have refreshed, with no commands enqueued 119611676Swendy.elsasser@arm.com * 119711676Swendy.elsasser@arm.com */ 119811676Swendy.elsasser@arm.com bool allRanksDrained() const; 119911676Swendy.elsasser@arm.com 12009243SN/A protected: 12019243SN/A 12029243SN/A Tick recvAtomic(PacketPtr pkt); 12039243SN/A void recvFunctional(PacketPtr pkt); 12049243SN/A bool recvTimingReq(PacketPtr pkt); 12059243SN/A 12069243SN/A}; 12079243SN/A 120810146Sandreas.hansson@arm.com#endif //__MEM_DRAM_CTRL_HH__ 1209