dram_ctrl.hh revision 12706
19243SN/A/* 212706Swendy.elsasser@arm.com * Copyright (c) 2012-2018 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 4310618SOmar.Naji@arm.com * Omar Naji 4411555Sjungma@eit.uni-kl.de * Matthias Jung 4511678Swendy.elsasser@arm.com * Wendy Elsasser 4612266Sradhika.jagtap@arm.com * Radhika Jagtap 479243SN/A */ 489243SN/A 499243SN/A/** 509243SN/A * @file 5110146Sandreas.hansson@arm.com * DRAMCtrl declaration 529243SN/A */ 539243SN/A 5410146Sandreas.hansson@arm.com#ifndef __MEM_DRAM_CTRL_HH__ 5510146Sandreas.hansson@arm.com#define __MEM_DRAM_CTRL_HH__ 569243SN/A 579488SN/A#include <deque> 5810618SOmar.Naji@arm.com#include <string> 5910889Sandreas.hansson@arm.com#include <unordered_set> 609488SN/A 6111677Swendy.elsasser@arm.com#include "base/callback.hh" 629243SN/A#include "base/statistics.hh" 639243SN/A#include "enums/AddrMap.hh" 649243SN/A#include "enums/MemSched.hh" 659243SN/A#include "enums/PageManage.hh" 669243SN/A#include "mem/abstract_mem.hh" 679243SN/A#include "mem/qport.hh" 6810146Sandreas.hansson@arm.com#include "params/DRAMCtrl.hh" 699243SN/A#include "sim/eventq.hh" 7010432SOmar.Naji@arm.com#include "mem/drampower.hh" 719243SN/A 729243SN/A/** 7310287Sandreas.hansson@arm.com * The DRAM controller is a single-channel memory controller capturing 7410287Sandreas.hansson@arm.com * the most important timing constraints associated with a 7510287Sandreas.hansson@arm.com * contemporary DRAM. For multi-channel memory systems, the controller 7610287Sandreas.hansson@arm.com * is combined with a crossbar model, with the channel address 7710287Sandreas.hansson@arm.com * interleaving taking part in the crossbar. 789243SN/A * 7910287Sandreas.hansson@arm.com * As a basic design principle, this controller 8010287Sandreas.hansson@arm.com * model is not cycle callable, but instead uses events to: 1) decide 8110287Sandreas.hansson@arm.com * when new decisions can be made, 2) when resources become available, 8210287Sandreas.hansson@arm.com * 3) when things are to be considered done, and 4) when to send 8310287Sandreas.hansson@arm.com * things back. Through these simple principles, the model delivers 8410287Sandreas.hansson@arm.com * high performance, and lots of flexibility, allowing users to 8510287Sandreas.hansson@arm.com * evaluate the system impact of a wide range of memory technologies, 8610287Sandreas.hansson@arm.com * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC. 8710287Sandreas.hansson@arm.com * 8810287Sandreas.hansson@arm.com * For more details, please see Hansson et al, "Simulating DRAM 8910287Sandreas.hansson@arm.com * controllers for future system architecture exploration", 9010287Sandreas.hansson@arm.com * Proc. ISPASS, 2014. If you use this model as part of your research 9110287Sandreas.hansson@arm.com * please cite the paper. 9211678Swendy.elsasser@arm.com * 9311678Swendy.elsasser@arm.com * The low-power functionality implements a staggered powerdown 9411678Swendy.elsasser@arm.com * similar to that described in "Optimized Active and Power-Down Mode 9511678Swendy.elsasser@arm.com * Refresh Control in 3D-DRAMs" by Jung et al, VLSI-SoC, 2014. 969243SN/A */ 9710146Sandreas.hansson@arm.comclass DRAMCtrl : public AbstractMemory 989243SN/A{ 999243SN/A 1009243SN/A private: 1019243SN/A 1029243SN/A // For now, make use of a queued slave port to avoid dealing with 1039243SN/A // flow control for the responses being sent back 1049243SN/A class MemoryPort : public QueuedSlavePort 1059243SN/A { 1069243SN/A 10710713Sandreas.hansson@arm.com RespPacketQueue queue; 10810146Sandreas.hansson@arm.com DRAMCtrl& memory; 1099243SN/A 1109243SN/A public: 1119243SN/A 11210146Sandreas.hansson@arm.com MemoryPort(const std::string& name, DRAMCtrl& _memory); 1139243SN/A 1149243SN/A protected: 1159243SN/A 1169243SN/A Tick recvAtomic(PacketPtr pkt); 1179243SN/A 1189243SN/A void recvFunctional(PacketPtr pkt); 1199243SN/A 1209243SN/A bool recvTimingReq(PacketPtr); 1219243SN/A 1229243SN/A virtual AddrRangeList getAddrRanges() const; 1239243SN/A 1249243SN/A }; 1259243SN/A 1269243SN/A /** 1279243SN/A * Our incoming port, for a multi-ported controller add a crossbar 1289243SN/A * in front of it 1299243SN/A */ 1309243SN/A MemoryPort port; 1319243SN/A 1329243SN/A /** 13310619Sandreas.hansson@arm.com * Remeber if the memory system is in timing mode 13410619Sandreas.hansson@arm.com */ 13510619Sandreas.hansson@arm.com bool isTimingMode; 13610619Sandreas.hansson@arm.com 13710619Sandreas.hansson@arm.com /** 1389243SN/A * Remember if we have to retry a request when available. 1399243SN/A */ 1409243SN/A bool retryRdReq; 1419243SN/A bool retryWrReq; 1429243SN/A 1439243SN/A /** 14410206Sandreas.hansson@arm.com * Bus state used to control the read/write switching and drive 14510206Sandreas.hansson@arm.com * the scheduling of the next request. 1469243SN/A */ 14710206Sandreas.hansson@arm.com enum BusState { 14810206Sandreas.hansson@arm.com READ = 0, 14910206Sandreas.hansson@arm.com WRITE, 15010206Sandreas.hansson@arm.com }; 15110206Sandreas.hansson@arm.com 15210206Sandreas.hansson@arm.com BusState busState; 1539243SN/A 15411678Swendy.elsasser@arm.com /* bus state for next request event triggered */ 15511678Swendy.elsasser@arm.com BusState busStateNext; 15611678Swendy.elsasser@arm.com 1579243SN/A /** 15811675Swendy.elsasser@arm.com * Simple structure to hold the values needed to keep track of 15911675Swendy.elsasser@arm.com * commands for DRAMPower 16011675Swendy.elsasser@arm.com */ 16111675Swendy.elsasser@arm.com struct Command { 16211675Swendy.elsasser@arm.com Data::MemCommand::cmds type; 16311675Swendy.elsasser@arm.com uint8_t bank; 16411675Swendy.elsasser@arm.com Tick timeStamp; 16511675Swendy.elsasser@arm.com 16611675Swendy.elsasser@arm.com constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank, 16711675Swendy.elsasser@arm.com Tick time_stamp) 16811675Swendy.elsasser@arm.com : type(_type), bank(_bank), timeStamp(time_stamp) 16911675Swendy.elsasser@arm.com { } 17011675Swendy.elsasser@arm.com }; 17111675Swendy.elsasser@arm.com 17211675Swendy.elsasser@arm.com /** 17310210Sandreas.hansson@arm.com * A basic class to track the bank state, i.e. what row is 17410210Sandreas.hansson@arm.com * currently open (if any), when is the bank free to accept a new 17510211Sandreas.hansson@arm.com * column (read/write) command, when can it be precharged, and 17610211Sandreas.hansson@arm.com * when can it be activated. 17710210Sandreas.hansson@arm.com * 17810210Sandreas.hansson@arm.com * The bank also keeps track of how many bytes have been accessed 17910210Sandreas.hansson@arm.com * in the open row since it was opened. 1809243SN/A */ 1819243SN/A class Bank 1829243SN/A { 1839243SN/A 1849243SN/A public: 1859243SN/A 18610207Sandreas.hansson@arm.com static const uint32_t NO_ROW = -1; 1879243SN/A 1889243SN/A uint32_t openRow; 18910246Sandreas.hansson@arm.com uint8_t bank; 19010394Swendy.elsasser@arm.com uint8_t bankgr; 1919243SN/A 19212706Swendy.elsasser@arm.com Tick rdAllowedAt; 19312706Swendy.elsasser@arm.com Tick wrAllowedAt; 19410210Sandreas.hansson@arm.com Tick preAllowedAt; 1959969SN/A Tick actAllowedAt; 1969243SN/A 19710141SN/A uint32_t rowAccesses; 1989727SN/A uint32_t bytesAccessed; 1999727SN/A 2009727SN/A Bank() : 20110618SOmar.Naji@arm.com openRow(NO_ROW), bank(0), bankgr(0), 20212706Swendy.elsasser@arm.com rdAllowedAt(0), wrAllowedAt(0), preAllowedAt(0), actAllowedAt(0), 20310141SN/A rowAccesses(0), bytesAccessed(0) 2049243SN/A { } 2059243SN/A }; 2069243SN/A 20710618SOmar.Naji@arm.com 20810618SOmar.Naji@arm.com /** 20911678Swendy.elsasser@arm.com * The power state captures the different operational states of 21011678Swendy.elsasser@arm.com * the DRAM and interacts with the bus read/write state machine, 21111678Swendy.elsasser@arm.com * and the refresh state machine. 21211678Swendy.elsasser@arm.com * 21311678Swendy.elsasser@arm.com * PWR_IDLE : The idle state in which all banks are closed 21411678Swendy.elsasser@arm.com * From here can transition to: PWR_REF, PWR_ACT, 21511678Swendy.elsasser@arm.com * PWR_PRE_PDN 21611678Swendy.elsasser@arm.com * 21711678Swendy.elsasser@arm.com * PWR_REF : Auto-refresh state. Will transition when refresh is 21811678Swendy.elsasser@arm.com * complete based on power state prior to PWR_REF 21911678Swendy.elsasser@arm.com * From here can transition to: PWR_IDLE, PWR_PRE_PDN, 22011678Swendy.elsasser@arm.com * PWR_SREF 22111678Swendy.elsasser@arm.com * 22211678Swendy.elsasser@arm.com * PWR_SREF : Self-refresh state. Entered after refresh if 22311678Swendy.elsasser@arm.com * previous state was PWR_PRE_PDN 22411678Swendy.elsasser@arm.com * From here can transition to: PWR_IDLE 22511678Swendy.elsasser@arm.com * 22611678Swendy.elsasser@arm.com * PWR_PRE_PDN : Precharge power down state 22711678Swendy.elsasser@arm.com * From here can transition to: PWR_REF, PWR_IDLE 22811678Swendy.elsasser@arm.com * 22911678Swendy.elsasser@arm.com * PWR_ACT : Activate state in which one or more banks are open 23011678Swendy.elsasser@arm.com * From here can transition to: PWR_IDLE, PWR_ACT_PDN 23111678Swendy.elsasser@arm.com * 23211678Swendy.elsasser@arm.com * PWR_ACT_PDN : Activate power down state 23311678Swendy.elsasser@arm.com * From here can transition to: PWR_ACT 23411678Swendy.elsasser@arm.com */ 23511678Swendy.elsasser@arm.com enum PowerState { 23611678Swendy.elsasser@arm.com PWR_IDLE = 0, 23711678Swendy.elsasser@arm.com PWR_REF, 23811678Swendy.elsasser@arm.com PWR_SREF, 23911678Swendy.elsasser@arm.com PWR_PRE_PDN, 24011678Swendy.elsasser@arm.com PWR_ACT, 24111678Swendy.elsasser@arm.com PWR_ACT_PDN 24211678Swendy.elsasser@arm.com }; 24311678Swendy.elsasser@arm.com 24411678Swendy.elsasser@arm.com /** 24511678Swendy.elsasser@arm.com * The refresh state is used to control the progress of the 24611678Swendy.elsasser@arm.com * refresh scheduling. When normal operation is in progress the 24711678Swendy.elsasser@arm.com * refresh state is idle. Once tREFI has elasped, a refresh event 24811678Swendy.elsasser@arm.com * is triggered to start the following STM transitions which are 24911678Swendy.elsasser@arm.com * used to issue a refresh and return back to normal operation 25011678Swendy.elsasser@arm.com * 25111678Swendy.elsasser@arm.com * REF_IDLE : IDLE state used during normal operation 25211678Swendy.elsasser@arm.com * From here can transition to: REF_DRAIN 25311678Swendy.elsasser@arm.com * 25411678Swendy.elsasser@arm.com * REF_SREF_EXIT : Exiting a self-refresh; refresh event scheduled 25511678Swendy.elsasser@arm.com * after self-refresh exit completes 25611678Swendy.elsasser@arm.com * From here can transition to: REF_DRAIN 25711678Swendy.elsasser@arm.com * 25811678Swendy.elsasser@arm.com * REF_DRAIN : Drain state in which on going accesses complete. 25911678Swendy.elsasser@arm.com * From here can transition to: REF_PD_EXIT 26011678Swendy.elsasser@arm.com * 26111678Swendy.elsasser@arm.com * REF_PD_EXIT : Evaluate pwrState and issue wakeup if needed 26211678Swendy.elsasser@arm.com * Next state dependent on whether banks are open 26311678Swendy.elsasser@arm.com * From here can transition to: REF_PRE, REF_START 26411678Swendy.elsasser@arm.com * 26511678Swendy.elsasser@arm.com * REF_PRE : Close (precharge) all open banks 26611678Swendy.elsasser@arm.com * From here can transition to: REF_START 26711678Swendy.elsasser@arm.com * 26811678Swendy.elsasser@arm.com * REF_START : Issue refresh command and update DRAMPower stats 26911678Swendy.elsasser@arm.com * From here can transition to: REF_RUN 27011678Swendy.elsasser@arm.com * 27111678Swendy.elsasser@arm.com * REF_RUN : Refresh running, waiting for tRFC to expire 27211678Swendy.elsasser@arm.com * From here can transition to: REF_IDLE, REF_SREF_EXIT 27311678Swendy.elsasser@arm.com */ 27411678Swendy.elsasser@arm.com enum RefreshState { 27511678Swendy.elsasser@arm.com REF_IDLE = 0, 27611678Swendy.elsasser@arm.com REF_DRAIN, 27711678Swendy.elsasser@arm.com REF_PD_EXIT, 27811678Swendy.elsasser@arm.com REF_SREF_EXIT, 27911678Swendy.elsasser@arm.com REF_PRE, 28011678Swendy.elsasser@arm.com REF_START, 28111678Swendy.elsasser@arm.com REF_RUN 28211678Swendy.elsasser@arm.com }; 28311678Swendy.elsasser@arm.com 28411678Swendy.elsasser@arm.com /** 28510618SOmar.Naji@arm.com * Rank class includes a vector of banks. Refresh and Power state 28610618SOmar.Naji@arm.com * machines are defined per rank. Events required to change the 28710618SOmar.Naji@arm.com * state of the refresh and power state machine are scheduled per 28810618SOmar.Naji@arm.com * rank. This class allows the implementation of rank-wise refresh 28910618SOmar.Naji@arm.com * and rank-wise power-down. 29010618SOmar.Naji@arm.com */ 29110618SOmar.Naji@arm.com class Rank : public EventManager 29210618SOmar.Naji@arm.com { 29310618SOmar.Naji@arm.com 29410618SOmar.Naji@arm.com private: 29510618SOmar.Naji@arm.com 29610618SOmar.Naji@arm.com /** 29710618SOmar.Naji@arm.com * A reference to the parent DRAMCtrl instance 29810618SOmar.Naji@arm.com */ 29910618SOmar.Naji@arm.com DRAMCtrl& memory; 30010618SOmar.Naji@arm.com 30110618SOmar.Naji@arm.com /** 30210618SOmar.Naji@arm.com * Since we are taking decisions out of order, we need to keep 30311678Swendy.elsasser@arm.com * track of what power transition is happening at what time 30410618SOmar.Naji@arm.com */ 30510618SOmar.Naji@arm.com PowerState pwrStateTrans; 30610618SOmar.Naji@arm.com 30710618SOmar.Naji@arm.com /** 30811678Swendy.elsasser@arm.com * Previous low-power state, which will be re-entered after refresh. 30910618SOmar.Naji@arm.com */ 31011678Swendy.elsasser@arm.com PowerState pwrStatePostRefresh; 31110618SOmar.Naji@arm.com 31210618SOmar.Naji@arm.com /** 31310618SOmar.Naji@arm.com * Track when we transitioned to the current power state 31410618SOmar.Naji@arm.com */ 31510618SOmar.Naji@arm.com Tick pwrStateTick; 31610618SOmar.Naji@arm.com 31710618SOmar.Naji@arm.com /** 31810618SOmar.Naji@arm.com * Keep track of when a refresh is due. 31910618SOmar.Naji@arm.com */ 32010618SOmar.Naji@arm.com Tick refreshDueAt; 32110618SOmar.Naji@arm.com 32210618SOmar.Naji@arm.com /* 32310618SOmar.Naji@arm.com * Command energies 32410618SOmar.Naji@arm.com */ 32510618SOmar.Naji@arm.com Stats::Scalar actEnergy; 32610618SOmar.Naji@arm.com Stats::Scalar preEnergy; 32710618SOmar.Naji@arm.com Stats::Scalar readEnergy; 32810618SOmar.Naji@arm.com Stats::Scalar writeEnergy; 32910618SOmar.Naji@arm.com Stats::Scalar refreshEnergy; 33010618SOmar.Naji@arm.com 33110618SOmar.Naji@arm.com /* 33210618SOmar.Naji@arm.com * Active Background Energy 33310618SOmar.Naji@arm.com */ 33410618SOmar.Naji@arm.com Stats::Scalar actBackEnergy; 33510618SOmar.Naji@arm.com 33610618SOmar.Naji@arm.com /* 33710618SOmar.Naji@arm.com * Precharge Background Energy 33810618SOmar.Naji@arm.com */ 33910618SOmar.Naji@arm.com Stats::Scalar preBackEnergy; 34010618SOmar.Naji@arm.com 34111678Swendy.elsasser@arm.com /* 34211678Swendy.elsasser@arm.com * Active Power-Down Energy 34311678Swendy.elsasser@arm.com */ 34411678Swendy.elsasser@arm.com Stats::Scalar actPowerDownEnergy; 34511678Swendy.elsasser@arm.com 34611678Swendy.elsasser@arm.com /* 34711678Swendy.elsasser@arm.com * Precharge Power-Down Energy 34811678Swendy.elsasser@arm.com */ 34911678Swendy.elsasser@arm.com Stats::Scalar prePowerDownEnergy; 35011678Swendy.elsasser@arm.com 35111678Swendy.elsasser@arm.com /* 35211678Swendy.elsasser@arm.com * self Refresh Energy 35311678Swendy.elsasser@arm.com */ 35411678Swendy.elsasser@arm.com Stats::Scalar selfRefreshEnergy; 35511678Swendy.elsasser@arm.com 35610618SOmar.Naji@arm.com Stats::Scalar totalEnergy; 35710618SOmar.Naji@arm.com Stats::Scalar averagePower; 35810618SOmar.Naji@arm.com 35910618SOmar.Naji@arm.com /** 36011678Swendy.elsasser@arm.com * Stat to track total DRAM idle time 36111678Swendy.elsasser@arm.com * 36211678Swendy.elsasser@arm.com */ 36311678Swendy.elsasser@arm.com Stats::Scalar totalIdleTime; 36411678Swendy.elsasser@arm.com 36511678Swendy.elsasser@arm.com /** 36610618SOmar.Naji@arm.com * Track time spent in each power state. 36710618SOmar.Naji@arm.com */ 36810618SOmar.Naji@arm.com Stats::Vector pwrStateTime; 36910618SOmar.Naji@arm.com 37010618SOmar.Naji@arm.com /** 37110618SOmar.Naji@arm.com * Function to update Power Stats 37210618SOmar.Naji@arm.com */ 37310618SOmar.Naji@arm.com void updatePowerStats(); 37410618SOmar.Naji@arm.com 37510618SOmar.Naji@arm.com /** 37610618SOmar.Naji@arm.com * Schedule a power state transition in the future, and 37710618SOmar.Naji@arm.com * potentially override an already scheduled transition. 37810618SOmar.Naji@arm.com * 37910618SOmar.Naji@arm.com * @param pwr_state Power state to transition to 38010618SOmar.Naji@arm.com * @param tick Tick when transition should take place 38110618SOmar.Naji@arm.com */ 38210618SOmar.Naji@arm.com void schedulePowerEvent(PowerState pwr_state, Tick tick); 38310618SOmar.Naji@arm.com 38410618SOmar.Naji@arm.com public: 38510618SOmar.Naji@arm.com 38610618SOmar.Naji@arm.com /** 38711678Swendy.elsasser@arm.com * Current power state. 38811678Swendy.elsasser@arm.com */ 38911678Swendy.elsasser@arm.com PowerState pwrState; 39011678Swendy.elsasser@arm.com 39111678Swendy.elsasser@arm.com /** 39211678Swendy.elsasser@arm.com * current refresh state 39311678Swendy.elsasser@arm.com */ 39411678Swendy.elsasser@arm.com RefreshState refreshState; 39511678Swendy.elsasser@arm.com 39611678Swendy.elsasser@arm.com /** 39711678Swendy.elsasser@arm.com * rank is in or transitioning to power-down or self-refresh 39811678Swendy.elsasser@arm.com */ 39911678Swendy.elsasser@arm.com bool inLowPowerState; 40011678Swendy.elsasser@arm.com 40111678Swendy.elsasser@arm.com /** 40210618SOmar.Naji@arm.com * Current Rank index 40310618SOmar.Naji@arm.com */ 40410618SOmar.Naji@arm.com uint8_t rank; 40510618SOmar.Naji@arm.com 40611678Swendy.elsasser@arm.com /** 40711678Swendy.elsasser@arm.com * Track number of packets in read queue going to this rank 40811678Swendy.elsasser@arm.com */ 40911678Swendy.elsasser@arm.com uint32_t readEntries; 41011678Swendy.elsasser@arm.com 41111678Swendy.elsasser@arm.com /** 41211678Swendy.elsasser@arm.com * Track number of packets in write queue going to this rank 41311678Swendy.elsasser@arm.com */ 41411678Swendy.elsasser@arm.com uint32_t writeEntries; 41511678Swendy.elsasser@arm.com 41611678Swendy.elsasser@arm.com /** 41711678Swendy.elsasser@arm.com * Number of ACT, RD, and WR events currently scheduled 41811678Swendy.elsasser@arm.com * Incremented when a refresh event is started as well 41911678Swendy.elsasser@arm.com * Used to determine when a low-power state can be entered 42011678Swendy.elsasser@arm.com */ 42111678Swendy.elsasser@arm.com uint8_t outstandingEvents; 42211678Swendy.elsasser@arm.com 42311678Swendy.elsasser@arm.com /** 42411678Swendy.elsasser@arm.com * delay power-down and self-refresh exit until this requirement is met 42511678Swendy.elsasser@arm.com */ 42611678Swendy.elsasser@arm.com Tick wakeUpAllowedAt; 42711678Swendy.elsasser@arm.com 42810618SOmar.Naji@arm.com /** 42910618SOmar.Naji@arm.com * One DRAMPower instance per rank 43010618SOmar.Naji@arm.com */ 43110618SOmar.Naji@arm.com DRAMPower power; 43210618SOmar.Naji@arm.com 43310618SOmar.Naji@arm.com /** 43411675Swendy.elsasser@arm.com * List of comamnds issued, to be sent to DRAMPpower at refresh 43511675Swendy.elsasser@arm.com * and stats dump. Keep commands here since commands to different 43611675Swendy.elsasser@arm.com * banks are added out of order. Will only pass commands up to 43711675Swendy.elsasser@arm.com * curTick() to DRAMPower after sorting. 43811675Swendy.elsasser@arm.com */ 43911675Swendy.elsasser@arm.com std::vector<Command> cmdList; 44011675Swendy.elsasser@arm.com 44111675Swendy.elsasser@arm.com /** 44210618SOmar.Naji@arm.com * Vector of Banks. Each rank is made of several devices which in 44310618SOmar.Naji@arm.com * term are made from several banks. 44410618SOmar.Naji@arm.com */ 44510618SOmar.Naji@arm.com std::vector<Bank> banks; 44610618SOmar.Naji@arm.com 44710618SOmar.Naji@arm.com /** 44810618SOmar.Naji@arm.com * To track number of banks which are currently active for 44910618SOmar.Naji@arm.com * this rank. 45010618SOmar.Naji@arm.com */ 45110618SOmar.Naji@arm.com unsigned int numBanksActive; 45210618SOmar.Naji@arm.com 45310618SOmar.Naji@arm.com /** List to keep track of activate ticks */ 45410618SOmar.Naji@arm.com std::deque<Tick> actTicks; 45510618SOmar.Naji@arm.com 45612081Sspwilson2@wisc.edu Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p, int rank); 45710618SOmar.Naji@arm.com 45810618SOmar.Naji@arm.com const std::string name() const 45910618SOmar.Naji@arm.com { 46010618SOmar.Naji@arm.com return csprintf("%s_%d", memory.name(), rank); 46110618SOmar.Naji@arm.com } 46210618SOmar.Naji@arm.com 46310618SOmar.Naji@arm.com /** 46410618SOmar.Naji@arm.com * Kick off accounting for power and refresh states and 46510618SOmar.Naji@arm.com * schedule initial refresh. 46610618SOmar.Naji@arm.com * 46710618SOmar.Naji@arm.com * @param ref_tick Tick for first refresh 46810618SOmar.Naji@arm.com */ 46910618SOmar.Naji@arm.com void startup(Tick ref_tick); 47010618SOmar.Naji@arm.com 47110618SOmar.Naji@arm.com /** 47210619Sandreas.hansson@arm.com * Stop the refresh events. 47310619Sandreas.hansson@arm.com */ 47410619Sandreas.hansson@arm.com void suspend(); 47510619Sandreas.hansson@arm.com 47610619Sandreas.hansson@arm.com /** 47712266Sradhika.jagtap@arm.com * Check if there is no refresh and no preparation of refresh ongoing 47812266Sradhika.jagtap@arm.com * i.e. the refresh state machine is in idle 47910618SOmar.Naji@arm.com * 48010618SOmar.Naji@arm.com * @param Return true if the rank is idle from a refresh point of view 48110618SOmar.Naji@arm.com */ 48212266Sradhika.jagtap@arm.com bool inRefIdleState() const { return refreshState == REF_IDLE; } 48310618SOmar.Naji@arm.com 48410618SOmar.Naji@arm.com /** 48511676Swendy.elsasser@arm.com * Check if the current rank has all banks closed and is not 48611676Swendy.elsasser@arm.com * in a low power state 48711676Swendy.elsasser@arm.com * 48811676Swendy.elsasser@arm.com * @param Return true if the rank is idle from a bank 48911676Swendy.elsasser@arm.com * and power point of view 49011676Swendy.elsasser@arm.com */ 49111676Swendy.elsasser@arm.com bool inPwrIdleState() const { return pwrState == PWR_IDLE; } 49211676Swendy.elsasser@arm.com 49311676Swendy.elsasser@arm.com /** 49411678Swendy.elsasser@arm.com * Trigger a self-refresh exit if there are entries enqueued 49511678Swendy.elsasser@arm.com * Exit if there are any read entries regardless of the bus state. 49611678Swendy.elsasser@arm.com * If we are currently issuing write commands, exit if we have any 49711678Swendy.elsasser@arm.com * write commands enqueued as well. 49811678Swendy.elsasser@arm.com * Could expand this in the future to analyze state of entire queue 49911678Swendy.elsasser@arm.com * if needed. 50011678Swendy.elsasser@arm.com * 50111678Swendy.elsasser@arm.com * @return boolean indicating self-refresh exit should be scheduled 50211678Swendy.elsasser@arm.com */ 50311678Swendy.elsasser@arm.com bool forceSelfRefreshExit() const { 50411678Swendy.elsasser@arm.com return (readEntries != 0) || 50511678Swendy.elsasser@arm.com ((memory.busStateNext == WRITE) && (writeEntries != 0)); 50611678Swendy.elsasser@arm.com } 50711678Swendy.elsasser@arm.com 50811678Swendy.elsasser@arm.com /** 50912705Swendy.elsasser@arm.com * Check if the command queue of current rank is idle 51011678Swendy.elsasser@arm.com * 51112705Swendy.elsasser@arm.com * @param Return true if the there are no commands in Q. 51212705Swendy.elsasser@arm.com * Bus direction determines queue checked. 51311678Swendy.elsasser@arm.com */ 51412705Swendy.elsasser@arm.com bool isQueueEmpty() const; 51511678Swendy.elsasser@arm.com 51611678Swendy.elsasser@arm.com /** 51710618SOmar.Naji@arm.com * Let the rank check if it was waiting for requests to drain 51810618SOmar.Naji@arm.com * to allow it to transition states. 51910618SOmar.Naji@arm.com */ 52010618SOmar.Naji@arm.com void checkDrainDone(); 52110618SOmar.Naji@arm.com 52211675Swendy.elsasser@arm.com /** 52311675Swendy.elsasser@arm.com * Push command out of cmdList queue that are scheduled at 52411675Swendy.elsasser@arm.com * or before curTick() to DRAMPower library 52511675Swendy.elsasser@arm.com * All commands before curTick are guaranteed to be complete 52611675Swendy.elsasser@arm.com * and can safely be flushed. 52711675Swendy.elsasser@arm.com */ 52811675Swendy.elsasser@arm.com void flushCmdList(); 52911675Swendy.elsasser@arm.com 53010618SOmar.Naji@arm.com /* 53110618SOmar.Naji@arm.com * Function to register Stats 53210618SOmar.Naji@arm.com */ 53310618SOmar.Naji@arm.com void regStats(); 53410618SOmar.Naji@arm.com 53511677Swendy.elsasser@arm.com /** 53611677Swendy.elsasser@arm.com * Computes stats just prior to dump event 53711677Swendy.elsasser@arm.com */ 53811677Swendy.elsasser@arm.com void computeStats(); 53911677Swendy.elsasser@arm.com 54011678Swendy.elsasser@arm.com /** 54112266Sradhika.jagtap@arm.com * Reset stats on a stats event 54212266Sradhika.jagtap@arm.com */ 54312266Sradhika.jagtap@arm.com void resetStats(); 54412266Sradhika.jagtap@arm.com 54512266Sradhika.jagtap@arm.com /** 54611678Swendy.elsasser@arm.com * Schedule a transition to power-down (sleep) 54711678Swendy.elsasser@arm.com * 54811678Swendy.elsasser@arm.com * @param pwr_state Power state to transition to 54911678Swendy.elsasser@arm.com * @param tick Absolute tick when transition should take place 55011678Swendy.elsasser@arm.com */ 55111678Swendy.elsasser@arm.com void powerDownSleep(PowerState pwr_state, Tick tick); 55211678Swendy.elsasser@arm.com 55311678Swendy.elsasser@arm.com /** 55411678Swendy.elsasser@arm.com * schedule and event to wake-up from power-down or self-refresh 55511678Swendy.elsasser@arm.com * and update bank timing parameters 55611678Swendy.elsasser@arm.com * 55711678Swendy.elsasser@arm.com * @param exit_delay Relative tick defining the delay required between 55811678Swendy.elsasser@arm.com * low-power exit and the next command 55911678Swendy.elsasser@arm.com */ 56011678Swendy.elsasser@arm.com void scheduleWakeUpEvent(Tick exit_delay); 56111678Swendy.elsasser@arm.com 56211678Swendy.elsasser@arm.com void processWriteDoneEvent(); 56312084Sspwilson2@wisc.edu EventFunctionWrapper writeDoneEvent; 56411678Swendy.elsasser@arm.com 56510618SOmar.Naji@arm.com void processActivateEvent(); 56612084Sspwilson2@wisc.edu EventFunctionWrapper activateEvent; 56710618SOmar.Naji@arm.com 56810618SOmar.Naji@arm.com void processPrechargeEvent(); 56912084Sspwilson2@wisc.edu EventFunctionWrapper prechargeEvent; 57010618SOmar.Naji@arm.com 57110618SOmar.Naji@arm.com void processRefreshEvent(); 57212084Sspwilson2@wisc.edu EventFunctionWrapper refreshEvent; 57310618SOmar.Naji@arm.com 57410618SOmar.Naji@arm.com void processPowerEvent(); 57512084Sspwilson2@wisc.edu EventFunctionWrapper powerEvent; 57610618SOmar.Naji@arm.com 57711678Swendy.elsasser@arm.com void processWakeUpEvent(); 57812084Sspwilson2@wisc.edu EventFunctionWrapper wakeUpEvent; 57911678Swendy.elsasser@arm.com 58010618SOmar.Naji@arm.com }; 58110618SOmar.Naji@arm.com 58212266Sradhika.jagtap@arm.com /** 58312266Sradhika.jagtap@arm.com * Define the process to compute stats on a stats dump event, e.g. on 58412266Sradhika.jagtap@arm.com * simulation exit or intermediate stats dump. This is defined per rank 58512266Sradhika.jagtap@arm.com * as the per rank stats are based on state transition and periodically 58612266Sradhika.jagtap@arm.com * updated, requiring re-sync at exit. 58712266Sradhika.jagtap@arm.com */ 58811677Swendy.elsasser@arm.com class RankDumpCallback : public Callback 58911677Swendy.elsasser@arm.com { 59011677Swendy.elsasser@arm.com Rank *ranks; 59111677Swendy.elsasser@arm.com public: 59211677Swendy.elsasser@arm.com RankDumpCallback(Rank *r) : ranks(r) {} 59311677Swendy.elsasser@arm.com virtual void process() { ranks->computeStats(); }; 59411677Swendy.elsasser@arm.com }; 59511677Swendy.elsasser@arm.com 59612266Sradhika.jagtap@arm.com /** Define a process to clear power lib counters on a stats reset */ 59712266Sradhika.jagtap@arm.com class RankResetCallback : public Callback 59812266Sradhika.jagtap@arm.com { 59912266Sradhika.jagtap@arm.com private: 60012266Sradhika.jagtap@arm.com /** Pointer to the rank, thus we instantiate per rank */ 60112266Sradhika.jagtap@arm.com Rank *rank; 60212266Sradhika.jagtap@arm.com 60312266Sradhika.jagtap@arm.com public: 60412266Sradhika.jagtap@arm.com RankResetCallback(Rank *r) : rank(r) {} 60512266Sradhika.jagtap@arm.com virtual void process() { rank->resetStats(); }; 60612266Sradhika.jagtap@arm.com }; 60712266Sradhika.jagtap@arm.com 60812266Sradhika.jagtap@arm.com /** Define a process to store the time on a stats reset */ 60912266Sradhika.jagtap@arm.com class MemResetCallback : public Callback 61012266Sradhika.jagtap@arm.com { 61112266Sradhika.jagtap@arm.com private: 61212266Sradhika.jagtap@arm.com /** A reference to the DRAMCtrl instance */ 61312266Sradhika.jagtap@arm.com DRAMCtrl *mem; 61412266Sradhika.jagtap@arm.com 61512266Sradhika.jagtap@arm.com public: 61612266Sradhika.jagtap@arm.com MemResetCallback(DRAMCtrl *_mem) : mem(_mem) {} 61712266Sradhika.jagtap@arm.com virtual void process() { mem->lastStatsResetTick = curTick(); }; 61812266Sradhika.jagtap@arm.com }; 61912266Sradhika.jagtap@arm.com 6209243SN/A /** 6219831SN/A * A burst helper helps organize and manage a packet that is larger than 6229831SN/A * the DRAM burst size. A system packet that is larger than the burst size 6239831SN/A * is split into multiple DRAM packets and all those DRAM packets point to 6249831SN/A * a single burst helper such that we know when the whole packet is served. 6259831SN/A */ 6269831SN/A class BurstHelper { 6279831SN/A 6289831SN/A public: 6299831SN/A 6309831SN/A /** Number of DRAM bursts requred for a system packet **/ 6319831SN/A const unsigned int burstCount; 6329831SN/A 6339831SN/A /** Number of DRAM bursts serviced so far for a system packet **/ 6349831SN/A unsigned int burstsServiced; 6359831SN/A 6369831SN/A BurstHelper(unsigned int _burstCount) 6379831SN/A : burstCount(_burstCount), burstsServiced(0) 63810618SOmar.Naji@arm.com { } 6399831SN/A }; 6409831SN/A 6419831SN/A /** 6429243SN/A * A DRAM packet stores packets along with the timestamp of when 6439243SN/A * the packet entered the queue, and also the decoded address. 6449243SN/A */ 6459243SN/A class DRAMPacket { 6469243SN/A 6479243SN/A public: 6489243SN/A 6499243SN/A /** When did request enter the controller */ 6509243SN/A const Tick entryTime; 6519243SN/A 6529243SN/A /** When will request leave the controller */ 6539243SN/A Tick readyTime; 6549243SN/A 6559243SN/A /** This comes from the outside world */ 6569243SN/A const PacketPtr pkt; 6579243SN/A 6589966SN/A const bool isRead; 6599966SN/A 6609243SN/A /** Will be populated by address decoder */ 6619243SN/A const uint8_t rank; 6629967SN/A const uint8_t bank; 66310245Sandreas.hansson@arm.com const uint32_t row; 6649831SN/A 6659831SN/A /** 6669967SN/A * Bank id is calculated considering banks in all the ranks 6679967SN/A * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and 6689967SN/A * bankId = 8 --> rank1, bank0 6699967SN/A */ 6709967SN/A const uint16_t bankId; 6719967SN/A 6729967SN/A /** 6739831SN/A * The starting address of the DRAM packet. 6749831SN/A * This address could be unaligned to burst size boundaries. The 6759831SN/A * reason is to keep the address offset so we can accurately check 6769831SN/A * incoming read packets with packets in the write queue. 6779831SN/A */ 6789832SN/A Addr addr; 6799831SN/A 6809831SN/A /** 6819831SN/A * The size of this dram packet in bytes 6829831SN/A * It is always equal or smaller than DRAM burst size 6839831SN/A */ 6849832SN/A unsigned int size; 6859831SN/A 6869831SN/A /** 6879831SN/A * A pointer to the BurstHelper if this DRAMPacket is a split packet 6889831SN/A * If not a split packet (common case), this is set to NULL 6899831SN/A */ 6909831SN/A BurstHelper* burstHelper; 6919967SN/A Bank& bankRef; 69210618SOmar.Naji@arm.com Rank& rankRef; 6939243SN/A 6949967SN/A DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank, 69510245Sandreas.hansson@arm.com uint32_t _row, uint16_t bank_id, Addr _addr, 69610618SOmar.Naji@arm.com unsigned int _size, Bank& bank_ref, Rank& rank_ref) 6979243SN/A : entryTime(curTick()), readyTime(curTick()), 6989967SN/A pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row), 6999967SN/A bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL), 70010618SOmar.Naji@arm.com bankRef(bank_ref), rankRef(rank_ref) 7019243SN/A { } 7029243SN/A 7039243SN/A }; 7049243SN/A 7059243SN/A /** 7069243SN/A * Bunch of things requires to setup "events" in gem5 70710206Sandreas.hansson@arm.com * When event "respondEvent" occurs for example, the method 70810206Sandreas.hansson@arm.com * processRespondEvent is called; no parameters are allowed 7099243SN/A * in these methods 7109243SN/A */ 71110208Sandreas.hansson@arm.com void processNextReqEvent(); 71212084Sspwilson2@wisc.edu EventFunctionWrapper nextReqEvent; 71310208Sandreas.hansson@arm.com 7149243SN/A void processRespondEvent(); 71512084Sspwilson2@wisc.edu EventFunctionWrapper respondEvent; 7169243SN/A 7179243SN/A /** 7189243SN/A * Check if the read queue has room for more entries 7199243SN/A * 7209831SN/A * @param pktCount The number of entries needed in the read queue 7219243SN/A * @return true if read queue is full, false otherwise 7229243SN/A */ 7239831SN/A bool readQueueFull(unsigned int pktCount) const; 7249243SN/A 7259243SN/A /** 7269243SN/A * Check if the write queue has room for more entries 7279243SN/A * 7289831SN/A * @param pktCount The number of entries needed in the write queue 7299243SN/A * @return true if write queue is full, false otherwise 7309243SN/A */ 7319831SN/A bool writeQueueFull(unsigned int pktCount) const; 7329243SN/A 7339243SN/A /** 7349243SN/A * When a new read comes in, first check if the write q has a 7359243SN/A * pending request to the same address.\ If not, decode the 7369831SN/A * address to populate rank/bank/row, create one or mutliple 7379831SN/A * "dram_pkt", and push them to the back of the read queue.\ 7389831SN/A * If this is the only 7399243SN/A * read request in the system, schedule an event to start 7409243SN/A * servicing it. 7419243SN/A * 7429243SN/A * @param pkt The request packet from the outside world 7439831SN/A * @param pktCount The number of DRAM bursts the pkt 7449831SN/A * translate to. If pkt size is larger then one full burst, 7459831SN/A * then pktCount is greater than one. 7469243SN/A */ 7479831SN/A void addToReadQueue(PacketPtr pkt, unsigned int pktCount); 7489243SN/A 7499243SN/A /** 7509243SN/A * Decode the incoming pkt, create a dram_pkt and push to the 7519243SN/A * back of the write queue. \If the write q length is more than 7529243SN/A * the threshold specified by the user, ie the queue is beginning 7539243SN/A * to get full, stop reads, and start draining writes. 7549243SN/A * 7559243SN/A * @param pkt The request packet from the outside world 7569831SN/A * @param pktCount The number of DRAM bursts the pkt 7579831SN/A * translate to. If pkt size is larger then one full burst, 7589831SN/A * then pktCount is greater than one. 7599243SN/A */ 7609831SN/A void addToWriteQueue(PacketPtr pkt, unsigned int pktCount); 7619243SN/A 7629243SN/A /** 7639243SN/A * Actually do the DRAM access - figure out the latency it 7649243SN/A * will take to service the req based on bank state, channel state etc 7659243SN/A * and then update those states to account for this request.\ Based 7669243SN/A * on this, update the packet's "readyTime" and move it to the 7679243SN/A * response q from where it will eventually go back to the outside 7689243SN/A * world. 7699243SN/A * 7709243SN/A * @param pkt The DRAM packet created from the outside world pkt 7719243SN/A */ 7729243SN/A void doDRAMAccess(DRAMPacket* dram_pkt); 7739243SN/A 7749243SN/A /** 7759243SN/A * When a packet reaches its "readyTime" in the response Q, 7769243SN/A * use the "access()" method in AbstractMemory to actually 7779243SN/A * create the response packet, and send it back to the outside 7789243SN/A * world requestor. 7799243SN/A * 7809243SN/A * @param pkt The packet from the outside world 7819726SN/A * @param static_latency Static latency to add before sending the packet 7829243SN/A */ 7839726SN/A void accessAndRespond(PacketPtr pkt, Tick static_latency); 7849243SN/A 7859243SN/A /** 7869243SN/A * Address decoder to figure out physical mapping onto ranks, 7879831SN/A * banks, and rows. This function is called multiple times on the same 7889831SN/A * system packet if the pakcet is larger than burst of the memory. The 7899831SN/A * dramPktAddr is used for the offset within the packet. 7909243SN/A * 7919243SN/A * @param pkt The packet from the outside world 7929831SN/A * @param dramPktAddr The starting address of the DRAM packet 7939831SN/A * @param size The size of the DRAM packet in bytes 7949966SN/A * @param isRead Is the request for a read or a write to DRAM 7959243SN/A * @return A DRAMPacket pointer with the decoded information 7969243SN/A */ 79710143SN/A DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size, 79810143SN/A bool isRead); 7999243SN/A 8009243SN/A /** 80110206Sandreas.hansson@arm.com * The memory schduler/arbiter - picks which request needs to 8029567SN/A * go next, based on the specified policy such as FCFS or FR-FCFS 80310206Sandreas.hansson@arm.com * and moves it to the head of the queue. 80410393Swendy.elsasser@arm.com * Prioritizes accesses to the same rank as previous burst unless 80510393Swendy.elsasser@arm.com * controller is switching command type. 80610393Swendy.elsasser@arm.com * 80710393Swendy.elsasser@arm.com * @param queue Queued requests to consider 80810890Swendy.elsasser@arm.com * @param extra_col_delay Any extra delay due to a read/write switch 80910618SOmar.Naji@arm.com * @return true if a packet is scheduled to a rank which is available else 81010618SOmar.Naji@arm.com * false 8119243SN/A */ 81210890Swendy.elsasser@arm.com bool chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay); 8139243SN/A 8149243SN/A /** 8159974SN/A * For FR-FCFS policy reorder the read/write queue depending on row buffer 81610890Swendy.elsasser@arm.com * hits and earliest bursts available in DRAM 81710393Swendy.elsasser@arm.com * 81810393Swendy.elsasser@arm.com * @param queue Queued requests to consider 81910890Swendy.elsasser@arm.com * @param extra_col_delay Any extra delay due to a read/write switch 82010618SOmar.Naji@arm.com * @return true if a packet is scheduled to a rank which is available else 82110618SOmar.Naji@arm.com * false 8229974SN/A */ 82310890Swendy.elsasser@arm.com bool reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay); 8249974SN/A 8259974SN/A /** 82610211Sandreas.hansson@arm.com * Find which are the earliest banks ready to issue an activate 82712706Swendy.elsasser@arm.com * for the enqueued requests. Assumes maximum of 32 banks per rank 82810393Swendy.elsasser@arm.com * Also checks if the bank is already prepped. 8299967SN/A * 83010393Swendy.elsasser@arm.com * @param queue Queued requests to consider 83112706Swendy.elsasser@arm.com * @param min_col_at time of seamless burst command 8329967SN/A * @return One-hot encoded mask of bank indices 83310890Swendy.elsasser@arm.com * @return boolean indicating burst can issue seamlessly, with no gaps 8349967SN/A */ 83512706Swendy.elsasser@arm.com std::pair<std::vector<uint32_t>, bool> minBankPrep( 83612706Swendy.elsasser@arm.com const std::deque<DRAMPacket*>& queue, 83710890Swendy.elsasser@arm.com Tick min_col_at) const; 8389488SN/A 8399488SN/A /** 8409488SN/A * Keep track of when row activations happen, in order to enforce 8419488SN/A * the maximum number of activations in the activation window. The 8429488SN/A * method updates the time that the banks become available based 8439488SN/A * on the current limits. 84410210Sandreas.hansson@arm.com * 84510618SOmar.Naji@arm.com * @param rank_ref Reference to the rank 84610618SOmar.Naji@arm.com * @param bank_ref Reference to the bank 84710210Sandreas.hansson@arm.com * @param act_tick Time when the activation takes place 84810210Sandreas.hansson@arm.com * @param row Index of the row 8499488SN/A */ 85010618SOmar.Naji@arm.com void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick, 85110618SOmar.Naji@arm.com uint32_t row); 85210207Sandreas.hansson@arm.com 85310207Sandreas.hansson@arm.com /** 85410207Sandreas.hansson@arm.com * Precharge a given bank and also update when the precharge is 85510207Sandreas.hansson@arm.com * done. This will also deal with any stats related to the 85610207Sandreas.hansson@arm.com * accesses to the open page. 85710207Sandreas.hansson@arm.com * 85810618SOmar.Naji@arm.com * @param rank_ref The rank to precharge 85910247Sandreas.hansson@arm.com * @param bank_ref The bank to precharge 86010211Sandreas.hansson@arm.com * @param pre_at Time when the precharge takes place 86110247Sandreas.hansson@arm.com * @param trace Is this an auto precharge then do not add to trace 86210207Sandreas.hansson@arm.com */ 86310618SOmar.Naji@arm.com void prechargeBank(Rank& rank_ref, Bank& bank_ref, 86410618SOmar.Naji@arm.com Tick pre_at, bool trace = true); 8659488SN/A 86610143SN/A /** 86710143SN/A * Used for debugging to observe the contents of the queues. 86810143SN/A */ 8699243SN/A void printQs() const; 8709243SN/A 8719243SN/A /** 87210889Sandreas.hansson@arm.com * Burst-align an address. 87310889Sandreas.hansson@arm.com * 87410889Sandreas.hansson@arm.com * @param addr The potentially unaligned address 87510889Sandreas.hansson@arm.com * 87610889Sandreas.hansson@arm.com * @return An address aligned to a DRAM burst 87710889Sandreas.hansson@arm.com */ 87810889Sandreas.hansson@arm.com Addr burstAlign(Addr addr) const { return (addr & ~(Addr(burstSize - 1))); } 87910889Sandreas.hansson@arm.com 88010889Sandreas.hansson@arm.com /** 8819243SN/A * The controller's main read and write queues 8829243SN/A */ 8839833SN/A std::deque<DRAMPacket*> readQueue; 8849833SN/A std::deque<DRAMPacket*> writeQueue; 8859243SN/A 8869243SN/A /** 88710889Sandreas.hansson@arm.com * To avoid iterating over the write queue to check for 88810889Sandreas.hansson@arm.com * overlapping transactions, maintain a set of burst addresses 88910889Sandreas.hansson@arm.com * that are currently queued. Since we merge writes to the same 89010889Sandreas.hansson@arm.com * location we never have more than one address to the same burst 89110889Sandreas.hansson@arm.com * address. 89210889Sandreas.hansson@arm.com */ 89310889Sandreas.hansson@arm.com std::unordered_set<Addr> isInWriteQueue; 89410889Sandreas.hansson@arm.com 89510889Sandreas.hansson@arm.com /** 8969243SN/A * Response queue where read packets wait after we're done working 8979567SN/A * with them, but it's not time to send the response yet. The 8989567SN/A * responses are stored seperately mostly to keep the code clean 8999567SN/A * and help with events scheduling. For all logical purposes such 9009567SN/A * as sizing the read queue, this and the main read queue need to 9019567SN/A * be added together. 9029243SN/A */ 9039833SN/A std::deque<DRAMPacket*> respQueue; 9049243SN/A 9059567SN/A /** 90610618SOmar.Naji@arm.com * Vector of ranks 9079243SN/A */ 90810618SOmar.Naji@arm.com std::vector<Rank*> ranks; 9099243SN/A 9109243SN/A /** 9119243SN/A * The following are basic design parameters of the memory 9129831SN/A * controller, and are initialized based on parameter values. 9139831SN/A * The rowsPerBank is determined based on the capacity, number of 9149831SN/A * ranks and banks, the burst size, and the row buffer size. 9159243SN/A */ 91610489SOmar.Naji@arm.com const uint32_t deviceSize; 9179831SN/A const uint32_t deviceBusWidth; 9189831SN/A const uint32_t burstLength; 9199831SN/A const uint32_t deviceRowBufferSize; 9209831SN/A const uint32_t devicesPerRank; 9219831SN/A const uint32_t burstSize; 9229831SN/A const uint32_t rowBufferSize; 92310140SN/A const uint32_t columnsPerRowBuffer; 92410286Sandreas.hansson@arm.com const uint32_t columnsPerStripe; 9259243SN/A const uint32_t ranksPerChannel; 92610394Swendy.elsasser@arm.com const uint32_t bankGroupsPerRank; 92710394Swendy.elsasser@arm.com const bool bankGroupArch; 9289243SN/A const uint32_t banksPerRank; 9299566SN/A const uint32_t channels; 9309243SN/A uint32_t rowsPerBank; 9319243SN/A const uint32_t readBufferSize; 9329243SN/A const uint32_t writeBufferSize; 93310140SN/A const uint32_t writeHighThreshold; 93410140SN/A const uint32_t writeLowThreshold; 93510140SN/A const uint32_t minWritesPerSwitch; 93610140SN/A uint32_t writesThisTime; 93710147Sandreas.hansson@arm.com uint32_t readsThisTime; 9389243SN/A 9399243SN/A /** 9409243SN/A * Basic memory timing parameters initialized based on parameter 9419243SN/A * values. 9429243SN/A */ 94310286Sandreas.hansson@arm.com const Tick M5_CLASS_VAR_USED tCK; 94410206Sandreas.hansson@arm.com const Tick tRTW; 94510393Swendy.elsasser@arm.com const Tick tCS; 9469243SN/A const Tick tBURST; 94712706Swendy.elsasser@arm.com const Tick tCCD_L_WR; 94810394Swendy.elsasser@arm.com const Tick tCCD_L; 9499243SN/A const Tick tRCD; 9509243SN/A const Tick tCL; 9519243SN/A const Tick tRP; 9529963SN/A const Tick tRAS; 95310210Sandreas.hansson@arm.com const Tick tWR; 95410212Sandreas.hansson@arm.com const Tick tRTP; 9559243SN/A const Tick tRFC; 9569243SN/A const Tick tREFI; 9579971SN/A const Tick tRRD; 95810394Swendy.elsasser@arm.com const Tick tRRD_L; 9599488SN/A const Tick tXAW; 96011673SOmar.Naji@arm.com const Tick tXP; 96111673SOmar.Naji@arm.com const Tick tXS; 9629488SN/A const uint32_t activationLimit; 96312706Swendy.elsasser@arm.com const Tick rankToRankDly; 96412706Swendy.elsasser@arm.com const Tick wrToRdDly; 96512706Swendy.elsasser@arm.com const Tick rdToWrDly; 9669243SN/A 9679243SN/A /** 9689243SN/A * Memory controller configuration initialized based on parameter 9699243SN/A * values. 9709243SN/A */ 9719243SN/A Enums::MemSched memSchedPolicy; 9729243SN/A Enums::AddrMap addrMapping; 9739243SN/A Enums::PageManage pageMgmt; 9749243SN/A 9759243SN/A /** 97610141SN/A * Max column accesses (read and write) per row, before forefully 97710141SN/A * closing it. 97810141SN/A */ 97910141SN/A const uint32_t maxAccessesPerRow; 98010141SN/A 98110141SN/A /** 9829726SN/A * Pipeline latency of the controller frontend. The frontend 9839726SN/A * contribution is added to writes (that complete when they are in 9849726SN/A * the write buffer) and reads that are serviced the write buffer. 9859726SN/A */ 9869726SN/A const Tick frontendLatency; 9879726SN/A 9889726SN/A /** 9899726SN/A * Pipeline latency of the backend and PHY. Along with the 9909726SN/A * frontend contribution, this latency is added to reads serviced 9919726SN/A * by the DRAM. 9929726SN/A */ 9939726SN/A const Tick backendLatency; 9949726SN/A 9959726SN/A /** 99612706Swendy.elsasser@arm.com * Till when must we wait before issuing next RD/WR burst? 9979243SN/A */ 99812706Swendy.elsasser@arm.com Tick nextBurstAt; 9999243SN/A 10009243SN/A Tick prevArrival; 10019243SN/A 100210206Sandreas.hansson@arm.com /** 100310206Sandreas.hansson@arm.com * The soonest you have to start thinking about the next request 100410206Sandreas.hansson@arm.com * is the longest access time that can occur before 100512706Swendy.elsasser@arm.com * nextBurstAt. Assuming you need to precharge, open a new row, 100610206Sandreas.hansson@arm.com * and access, it is tRP + tRCD + tCL. 100710206Sandreas.hansson@arm.com */ 100810206Sandreas.hansson@arm.com Tick nextReqTime; 10099972SN/A 10109243SN/A // All statistics that the model needs to capture 10119243SN/A Stats::Scalar readReqs; 10129243SN/A Stats::Scalar writeReqs; 10139831SN/A Stats::Scalar readBursts; 10149831SN/A Stats::Scalar writeBursts; 10159975SN/A Stats::Scalar bytesReadDRAM; 10169975SN/A Stats::Scalar bytesReadWrQ; 10179243SN/A Stats::Scalar bytesWritten; 10189977SN/A Stats::Scalar bytesReadSys; 10199977SN/A Stats::Scalar bytesWrittenSys; 10209243SN/A Stats::Scalar servicedByWrQ; 10219977SN/A Stats::Scalar mergedWrBursts; 10229243SN/A Stats::Scalar neitherReadNorWrite; 10239977SN/A Stats::Vector perBankRdBursts; 10249977SN/A Stats::Vector perBankWrBursts; 10259243SN/A Stats::Scalar numRdRetry; 10269243SN/A Stats::Scalar numWrRetry; 10279243SN/A Stats::Scalar totGap; 10289243SN/A Stats::Vector readPktSize; 10299243SN/A Stats::Vector writePktSize; 10309243SN/A Stats::Vector rdQLenPdf; 10319243SN/A Stats::Vector wrQLenPdf; 10329727SN/A Stats::Histogram bytesPerActivate; 103310147Sandreas.hansson@arm.com Stats::Histogram rdPerTurnAround; 103410147Sandreas.hansson@arm.com Stats::Histogram wrPerTurnAround; 10359243SN/A 10369243SN/A // Latencies summed over all requests 10379243SN/A Stats::Scalar totQLat; 10389243SN/A Stats::Scalar totMemAccLat; 10399243SN/A Stats::Scalar totBusLat; 10409243SN/A 10419243SN/A // Average latencies per request 10429243SN/A Stats::Formula avgQLat; 10439243SN/A Stats::Formula avgBusLat; 10449243SN/A Stats::Formula avgMemAccLat; 10459243SN/A 10469243SN/A // Average bandwidth 10479243SN/A Stats::Formula avgRdBW; 10489243SN/A Stats::Formula avgWrBW; 10499977SN/A Stats::Formula avgRdBWSys; 10509977SN/A Stats::Formula avgWrBWSys; 10519243SN/A Stats::Formula peakBW; 10529243SN/A Stats::Formula busUtil; 10539975SN/A Stats::Formula busUtilRead; 10549975SN/A Stats::Formula busUtilWrite; 10559243SN/A 10569243SN/A // Average queue lengths 10579243SN/A Stats::Average avgRdQLen; 10589243SN/A Stats::Average avgWrQLen; 10599243SN/A 10609243SN/A // Row hit count and rate 10619243SN/A Stats::Scalar readRowHits; 10629243SN/A Stats::Scalar writeRowHits; 10639243SN/A Stats::Formula readRowHitRate; 10649243SN/A Stats::Formula writeRowHitRate; 10659243SN/A Stats::Formula avgGap; 10669243SN/A 10679975SN/A // DRAM Power Calculation 10689975SN/A Stats::Formula pageHitRate; 10699975SN/A 107010393Swendy.elsasser@arm.com // Holds the value of the rank of burst issued 107110393Swendy.elsasser@arm.com uint8_t activeRank; 107210393Swendy.elsasser@arm.com 107310432SOmar.Naji@arm.com // timestamp offset 107410432SOmar.Naji@arm.com uint64_t timeStampOffset; 107510432SOmar.Naji@arm.com 107612266Sradhika.jagtap@arm.com /** The time when stats were last reset used to calculate average power */ 107712266Sradhika.jagtap@arm.com Tick lastStatsResetTick; 107812266Sradhika.jagtap@arm.com 107911190Sandreas.hansson@arm.com /** 108011190Sandreas.hansson@arm.com * Upstream caches need this packet until true is returned, so 108111190Sandreas.hansson@arm.com * hold it for deletion until a subsequent call 10829349SN/A */ 108311190Sandreas.hansson@arm.com std::unique_ptr<Packet> pendingDelete; 10849349SN/A 108510432SOmar.Naji@arm.com /** 108610618SOmar.Naji@arm.com * This function increments the energy when called. If stats are 108710618SOmar.Naji@arm.com * dumped periodically, note accumulated energy values will 108810618SOmar.Naji@arm.com * appear in the stats (even if the stats are reset). This is a 108910618SOmar.Naji@arm.com * result of the energy values coming from DRAMPower, and there 109010618SOmar.Naji@arm.com * is currently no support for resetting the state. 109110618SOmar.Naji@arm.com * 109210618SOmar.Naji@arm.com * @param rank Currrent rank 109310618SOmar.Naji@arm.com */ 109410618SOmar.Naji@arm.com void updatePowerStats(Rank& rank_ref); 109510432SOmar.Naji@arm.com 109610432SOmar.Naji@arm.com /** 109711675Swendy.elsasser@arm.com * Function for sorting Command structures based on timeStamp 109810432SOmar.Naji@arm.com * 109911675Swendy.elsasser@arm.com * @param a Memory Command 110011675Swendy.elsasser@arm.com * @param next Memory Command 110111675Swendy.elsasser@arm.com * @return true if timeStamp of Command 1 < timeStamp of Command 2 110210432SOmar.Naji@arm.com */ 110311675Swendy.elsasser@arm.com static bool sortTime(const Command& cmd, const Command& cmd_next) { 110411675Swendy.elsasser@arm.com return cmd.timeStamp < cmd_next.timeStamp; 110510432SOmar.Naji@arm.com }; 110610432SOmar.Naji@arm.com 11079243SN/A public: 11089243SN/A 110911169Sandreas.hansson@arm.com void regStats() override; 11109243SN/A 111110146Sandreas.hansson@arm.com DRAMCtrl(const DRAMCtrlParams* p); 11129243SN/A 111311168Sandreas.hansson@arm.com DrainState drain() override; 11149243SN/A 11159294SN/A virtual BaseSlavePort& getSlavePort(const std::string& if_name, 111611169Sandreas.hansson@arm.com PortID idx = InvalidPortID) override; 11179243SN/A 111811168Sandreas.hansson@arm.com virtual void init() override; 111911168Sandreas.hansson@arm.com virtual void startup() override; 112011168Sandreas.hansson@arm.com virtual void drainResume() override; 11219243SN/A 112211676Swendy.elsasser@arm.com /** 112311676Swendy.elsasser@arm.com * Return true once refresh is complete for all ranks and there are no 112411676Swendy.elsasser@arm.com * additional commands enqueued. (only evaluated when draining) 112511676Swendy.elsasser@arm.com * This will ensure that all banks are closed, power state is IDLE, and 112611676Swendy.elsasser@arm.com * power stats have been updated 112711676Swendy.elsasser@arm.com * 112811676Swendy.elsasser@arm.com * @return true if all ranks have refreshed, with no commands enqueued 112911676Swendy.elsasser@arm.com * 113011676Swendy.elsasser@arm.com */ 113111676Swendy.elsasser@arm.com bool allRanksDrained() const; 113211676Swendy.elsasser@arm.com 11339243SN/A protected: 11349243SN/A 11359243SN/A Tick recvAtomic(PacketPtr pkt); 11369243SN/A void recvFunctional(PacketPtr pkt); 11379243SN/A bool recvTimingReq(PacketPtr pkt); 11389243SN/A 11399243SN/A}; 11409243SN/A 114110146Sandreas.hansson@arm.com#endif //__MEM_DRAM_CTRL_HH__ 1142