dram_ctrl.hh revision 11677
19243SN/A/* 211675Swendy.elsasser@arm.com * Copyright (c) 2012-2016 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 4310618SOmar.Naji@arm.com * Omar Naji 4411555Sjungma@eit.uni-kl.de * Matthias Jung 459243SN/A */ 469243SN/A 479243SN/A/** 489243SN/A * @file 4910146Sandreas.hansson@arm.com * DRAMCtrl declaration 509243SN/A */ 519243SN/A 5210146Sandreas.hansson@arm.com#ifndef __MEM_DRAM_CTRL_HH__ 5310146Sandreas.hansson@arm.com#define __MEM_DRAM_CTRL_HH__ 549243SN/A 559488SN/A#include <deque> 5610618SOmar.Naji@arm.com#include <string> 5710889Sandreas.hansson@arm.com#include <unordered_set> 589488SN/A 5911677Swendy.elsasser@arm.com#include "base/callback.hh" 609243SN/A#include "base/statistics.hh" 619243SN/A#include "enums/AddrMap.hh" 629243SN/A#include "enums/MemSched.hh" 639243SN/A#include "enums/PageManage.hh" 649243SN/A#include "mem/abstract_mem.hh" 659243SN/A#include "mem/qport.hh" 6610146Sandreas.hansson@arm.com#include "params/DRAMCtrl.hh" 679243SN/A#include "sim/eventq.hh" 6810432SOmar.Naji@arm.com#include "mem/drampower.hh" 699243SN/A 709243SN/A/** 7110287Sandreas.hansson@arm.com * The DRAM controller is a single-channel memory controller capturing 7210287Sandreas.hansson@arm.com * the most important timing constraints associated with a 7310287Sandreas.hansson@arm.com * contemporary DRAM. For multi-channel memory systems, the controller 7410287Sandreas.hansson@arm.com * is combined with a crossbar model, with the channel address 7510287Sandreas.hansson@arm.com * interleaving taking part in the crossbar. 769243SN/A * 7710287Sandreas.hansson@arm.com * As a basic design principle, this controller 7810287Sandreas.hansson@arm.com * model is not cycle callable, but instead uses events to: 1) decide 7910287Sandreas.hansson@arm.com * when new decisions can be made, 2) when resources become available, 8010287Sandreas.hansson@arm.com * 3) when things are to be considered done, and 4) when to send 8110287Sandreas.hansson@arm.com * things back. Through these simple principles, the model delivers 8210287Sandreas.hansson@arm.com * high performance, and lots of flexibility, allowing users to 8310287Sandreas.hansson@arm.com * evaluate the system impact of a wide range of memory technologies, 8410287Sandreas.hansson@arm.com * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC. 8510287Sandreas.hansson@arm.com * 8610287Sandreas.hansson@arm.com * For more details, please see Hansson et al, "Simulating DRAM 8710287Sandreas.hansson@arm.com * controllers for future system architecture exploration", 8810287Sandreas.hansson@arm.com * Proc. ISPASS, 2014. If you use this model as part of your research 8910287Sandreas.hansson@arm.com * please cite the paper. 909243SN/A */ 9110146Sandreas.hansson@arm.comclass DRAMCtrl : public AbstractMemory 929243SN/A{ 939243SN/A 949243SN/A private: 959243SN/A 969243SN/A // For now, make use of a queued slave port to avoid dealing with 979243SN/A // flow control for the responses being sent back 989243SN/A class MemoryPort : public QueuedSlavePort 999243SN/A { 1009243SN/A 10110713Sandreas.hansson@arm.com RespPacketQueue queue; 10210146Sandreas.hansson@arm.com DRAMCtrl& memory; 1039243SN/A 1049243SN/A public: 1059243SN/A 10610146Sandreas.hansson@arm.com MemoryPort(const std::string& name, DRAMCtrl& _memory); 1079243SN/A 1089243SN/A protected: 1099243SN/A 1109243SN/A Tick recvAtomic(PacketPtr pkt); 1119243SN/A 1129243SN/A void recvFunctional(PacketPtr pkt); 1139243SN/A 1149243SN/A bool recvTimingReq(PacketPtr); 1159243SN/A 1169243SN/A virtual AddrRangeList getAddrRanges() const; 1179243SN/A 1189243SN/A }; 1199243SN/A 1209243SN/A /** 1219243SN/A * Our incoming port, for a multi-ported controller add a crossbar 1229243SN/A * in front of it 1239243SN/A */ 1249243SN/A MemoryPort port; 1259243SN/A 1269243SN/A /** 12710619Sandreas.hansson@arm.com * Remeber if the memory system is in timing mode 12810619Sandreas.hansson@arm.com */ 12910619Sandreas.hansson@arm.com bool isTimingMode; 13010619Sandreas.hansson@arm.com 13110619Sandreas.hansson@arm.com /** 1329243SN/A * Remember if we have to retry a request when available. 1339243SN/A */ 1349243SN/A bool retryRdReq; 1359243SN/A bool retryWrReq; 1369243SN/A 1379243SN/A /** 13810206Sandreas.hansson@arm.com * Bus state used to control the read/write switching and drive 13910206Sandreas.hansson@arm.com * the scheduling of the next request. 1409243SN/A */ 14110206Sandreas.hansson@arm.com enum BusState { 14210206Sandreas.hansson@arm.com READ = 0, 14310206Sandreas.hansson@arm.com READ_TO_WRITE, 14410206Sandreas.hansson@arm.com WRITE, 14510206Sandreas.hansson@arm.com WRITE_TO_READ 14610206Sandreas.hansson@arm.com }; 14710206Sandreas.hansson@arm.com 14810206Sandreas.hansson@arm.com BusState busState; 1499243SN/A 1509243SN/A /** 15111675Swendy.elsasser@arm.com * Simple structure to hold the values needed to keep track of 15211675Swendy.elsasser@arm.com * commands for DRAMPower 15311675Swendy.elsasser@arm.com */ 15411675Swendy.elsasser@arm.com struct Command { 15511675Swendy.elsasser@arm.com Data::MemCommand::cmds type; 15611675Swendy.elsasser@arm.com uint8_t bank; 15711675Swendy.elsasser@arm.com Tick timeStamp; 15811675Swendy.elsasser@arm.com 15911675Swendy.elsasser@arm.com constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank, 16011675Swendy.elsasser@arm.com Tick time_stamp) 16111675Swendy.elsasser@arm.com : type(_type), bank(_bank), timeStamp(time_stamp) 16211675Swendy.elsasser@arm.com { } 16311675Swendy.elsasser@arm.com }; 16411675Swendy.elsasser@arm.com 16511675Swendy.elsasser@arm.com /** 16610210Sandreas.hansson@arm.com * A basic class to track the bank state, i.e. what row is 16710210Sandreas.hansson@arm.com * currently open (if any), when is the bank free to accept a new 16810211Sandreas.hansson@arm.com * column (read/write) command, when can it be precharged, and 16910211Sandreas.hansson@arm.com * when can it be activated. 17010210Sandreas.hansson@arm.com * 17110210Sandreas.hansson@arm.com * The bank also keeps track of how many bytes have been accessed 17210210Sandreas.hansson@arm.com * in the open row since it was opened. 1739243SN/A */ 1749243SN/A class Bank 1759243SN/A { 1769243SN/A 1779243SN/A public: 1789243SN/A 17910207Sandreas.hansson@arm.com static const uint32_t NO_ROW = -1; 1809243SN/A 1819243SN/A uint32_t openRow; 18210246Sandreas.hansson@arm.com uint8_t bank; 18310394Swendy.elsasser@arm.com uint8_t bankgr; 1849243SN/A 18510211Sandreas.hansson@arm.com Tick colAllowedAt; 18610210Sandreas.hansson@arm.com Tick preAllowedAt; 1879969SN/A Tick actAllowedAt; 1889243SN/A 18910141SN/A uint32_t rowAccesses; 1909727SN/A uint32_t bytesAccessed; 1919727SN/A 1929727SN/A Bank() : 19310618SOmar.Naji@arm.com openRow(NO_ROW), bank(0), bankgr(0), 19410246Sandreas.hansson@arm.com colAllowedAt(0), preAllowedAt(0), actAllowedAt(0), 19510141SN/A rowAccesses(0), bytesAccessed(0) 1969243SN/A { } 1979243SN/A }; 1989243SN/A 19910618SOmar.Naji@arm.com 20010618SOmar.Naji@arm.com /** 20110618SOmar.Naji@arm.com * Rank class includes a vector of banks. Refresh and Power state 20210618SOmar.Naji@arm.com * machines are defined per rank. Events required to change the 20310618SOmar.Naji@arm.com * state of the refresh and power state machine are scheduled per 20410618SOmar.Naji@arm.com * rank. This class allows the implementation of rank-wise refresh 20510618SOmar.Naji@arm.com * and rank-wise power-down. 20610618SOmar.Naji@arm.com */ 20710618SOmar.Naji@arm.com class Rank : public EventManager 20810618SOmar.Naji@arm.com { 20910618SOmar.Naji@arm.com 21010618SOmar.Naji@arm.com private: 21110618SOmar.Naji@arm.com 21210618SOmar.Naji@arm.com /** 21310618SOmar.Naji@arm.com * The power state captures the different operational states of 21410618SOmar.Naji@arm.com * the DRAM and interacts with the bus read/write state machine, 21510618SOmar.Naji@arm.com * and the refresh state machine. In the idle state all banks are 21610618SOmar.Naji@arm.com * precharged. From there we either go to an auto refresh (as 21710618SOmar.Naji@arm.com * determined by the refresh state machine), or to a precharge 21810618SOmar.Naji@arm.com * power down mode. From idle the memory can also go to the active 21910618SOmar.Naji@arm.com * state (with one or more banks active), and in turn from there 22010618SOmar.Naji@arm.com * to active power down. At the moment we do not capture the deep 22110618SOmar.Naji@arm.com * power down and self-refresh state. 22210618SOmar.Naji@arm.com */ 22310618SOmar.Naji@arm.com enum PowerState { 22410618SOmar.Naji@arm.com PWR_IDLE = 0, 22510618SOmar.Naji@arm.com PWR_REF, 22610618SOmar.Naji@arm.com PWR_PRE_PDN, 22710618SOmar.Naji@arm.com PWR_ACT, 22810618SOmar.Naji@arm.com PWR_ACT_PDN 22910618SOmar.Naji@arm.com }; 23010618SOmar.Naji@arm.com 23110618SOmar.Naji@arm.com /** 23210618SOmar.Naji@arm.com * The refresh state is used to control the progress of the 23310618SOmar.Naji@arm.com * refresh scheduling. When normal operation is in progress the 23410618SOmar.Naji@arm.com * refresh state is idle. From there, it progresses to the refresh 23510618SOmar.Naji@arm.com * drain state once tREFI has passed. The refresh drain state 23610618SOmar.Naji@arm.com * captures the DRAM row active state, as it will stay there until 23710618SOmar.Naji@arm.com * all ongoing accesses complete. Thereafter all banks are 23810618SOmar.Naji@arm.com * precharged, and lastly, the DRAM is refreshed. 23910618SOmar.Naji@arm.com */ 24010618SOmar.Naji@arm.com enum RefreshState { 24110618SOmar.Naji@arm.com REF_IDLE = 0, 24210618SOmar.Naji@arm.com REF_DRAIN, 24310618SOmar.Naji@arm.com REF_PRE, 24410618SOmar.Naji@arm.com REF_RUN 24510618SOmar.Naji@arm.com }; 24610618SOmar.Naji@arm.com 24710618SOmar.Naji@arm.com /** 24810618SOmar.Naji@arm.com * A reference to the parent DRAMCtrl instance 24910618SOmar.Naji@arm.com */ 25010618SOmar.Naji@arm.com DRAMCtrl& memory; 25110618SOmar.Naji@arm.com 25210618SOmar.Naji@arm.com /** 25310618SOmar.Naji@arm.com * Since we are taking decisions out of order, we need to keep 25410618SOmar.Naji@arm.com * track of what power transition is happening at what time, such 25510618SOmar.Naji@arm.com * that we can go back in time and change history. For example, if 25610618SOmar.Naji@arm.com * we precharge all banks and schedule going to the idle state, we 25710618SOmar.Naji@arm.com * might at a later point decide to activate a bank before the 25810618SOmar.Naji@arm.com * transition to idle would have taken place. 25910618SOmar.Naji@arm.com */ 26010618SOmar.Naji@arm.com PowerState pwrStateTrans; 26110618SOmar.Naji@arm.com 26210618SOmar.Naji@arm.com /** 26310618SOmar.Naji@arm.com * Current power state. 26410618SOmar.Naji@arm.com */ 26510618SOmar.Naji@arm.com PowerState pwrState; 26610618SOmar.Naji@arm.com 26710618SOmar.Naji@arm.com /** 26810618SOmar.Naji@arm.com * Track when we transitioned to the current power state 26910618SOmar.Naji@arm.com */ 27010618SOmar.Naji@arm.com Tick pwrStateTick; 27110618SOmar.Naji@arm.com 27210618SOmar.Naji@arm.com /** 27310618SOmar.Naji@arm.com * current refresh state 27410618SOmar.Naji@arm.com */ 27510618SOmar.Naji@arm.com RefreshState refreshState; 27610618SOmar.Naji@arm.com 27710618SOmar.Naji@arm.com /** 27810618SOmar.Naji@arm.com * Keep track of when a refresh is due. 27910618SOmar.Naji@arm.com */ 28010618SOmar.Naji@arm.com Tick refreshDueAt; 28110618SOmar.Naji@arm.com 28210618SOmar.Naji@arm.com /* 28310618SOmar.Naji@arm.com * Command energies 28410618SOmar.Naji@arm.com */ 28510618SOmar.Naji@arm.com Stats::Scalar actEnergy; 28610618SOmar.Naji@arm.com Stats::Scalar preEnergy; 28710618SOmar.Naji@arm.com Stats::Scalar readEnergy; 28810618SOmar.Naji@arm.com Stats::Scalar writeEnergy; 28910618SOmar.Naji@arm.com Stats::Scalar refreshEnergy; 29010618SOmar.Naji@arm.com 29110618SOmar.Naji@arm.com /* 29210618SOmar.Naji@arm.com * Active Background Energy 29310618SOmar.Naji@arm.com */ 29410618SOmar.Naji@arm.com Stats::Scalar actBackEnergy; 29510618SOmar.Naji@arm.com 29610618SOmar.Naji@arm.com /* 29710618SOmar.Naji@arm.com * Precharge Background Energy 29810618SOmar.Naji@arm.com */ 29910618SOmar.Naji@arm.com Stats::Scalar preBackEnergy; 30010618SOmar.Naji@arm.com 30110618SOmar.Naji@arm.com Stats::Scalar totalEnergy; 30210618SOmar.Naji@arm.com Stats::Scalar averagePower; 30310618SOmar.Naji@arm.com 30410618SOmar.Naji@arm.com /** 30510618SOmar.Naji@arm.com * Track time spent in each power state. 30610618SOmar.Naji@arm.com */ 30710618SOmar.Naji@arm.com Stats::Vector pwrStateTime; 30810618SOmar.Naji@arm.com 30910618SOmar.Naji@arm.com /** 31010618SOmar.Naji@arm.com * Function to update Power Stats 31110618SOmar.Naji@arm.com */ 31210618SOmar.Naji@arm.com void updatePowerStats(); 31310618SOmar.Naji@arm.com 31410618SOmar.Naji@arm.com /** 31510618SOmar.Naji@arm.com * Schedule a power state transition in the future, and 31610618SOmar.Naji@arm.com * potentially override an already scheduled transition. 31710618SOmar.Naji@arm.com * 31810618SOmar.Naji@arm.com * @param pwr_state Power state to transition to 31910618SOmar.Naji@arm.com * @param tick Tick when transition should take place 32010618SOmar.Naji@arm.com */ 32110618SOmar.Naji@arm.com void schedulePowerEvent(PowerState pwr_state, Tick tick); 32210618SOmar.Naji@arm.com 32310618SOmar.Naji@arm.com public: 32410618SOmar.Naji@arm.com 32510618SOmar.Naji@arm.com /** 32610618SOmar.Naji@arm.com * Current Rank index 32710618SOmar.Naji@arm.com */ 32810618SOmar.Naji@arm.com uint8_t rank; 32910618SOmar.Naji@arm.com 33010618SOmar.Naji@arm.com /** 33110618SOmar.Naji@arm.com * One DRAMPower instance per rank 33210618SOmar.Naji@arm.com */ 33310618SOmar.Naji@arm.com DRAMPower power; 33410618SOmar.Naji@arm.com 33510618SOmar.Naji@arm.com /** 33611675Swendy.elsasser@arm.com * List of comamnds issued, to be sent to DRAMPpower at refresh 33711675Swendy.elsasser@arm.com * and stats dump. Keep commands here since commands to different 33811675Swendy.elsasser@arm.com * banks are added out of order. Will only pass commands up to 33911675Swendy.elsasser@arm.com * curTick() to DRAMPower after sorting. 34011675Swendy.elsasser@arm.com */ 34111675Swendy.elsasser@arm.com std::vector<Command> cmdList; 34211675Swendy.elsasser@arm.com 34311675Swendy.elsasser@arm.com /** 34410618SOmar.Naji@arm.com * Vector of Banks. Each rank is made of several devices which in 34510618SOmar.Naji@arm.com * term are made from several banks. 34610618SOmar.Naji@arm.com */ 34710618SOmar.Naji@arm.com std::vector<Bank> banks; 34810618SOmar.Naji@arm.com 34910618SOmar.Naji@arm.com /** 35010618SOmar.Naji@arm.com * To track number of banks which are currently active for 35110618SOmar.Naji@arm.com * this rank. 35210618SOmar.Naji@arm.com */ 35310618SOmar.Naji@arm.com unsigned int numBanksActive; 35410618SOmar.Naji@arm.com 35510618SOmar.Naji@arm.com /** List to keep track of activate ticks */ 35610618SOmar.Naji@arm.com std::deque<Tick> actTicks; 35710618SOmar.Naji@arm.com 35810618SOmar.Naji@arm.com Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p); 35910618SOmar.Naji@arm.com 36010618SOmar.Naji@arm.com const std::string name() const 36110618SOmar.Naji@arm.com { 36210618SOmar.Naji@arm.com return csprintf("%s_%d", memory.name(), rank); 36310618SOmar.Naji@arm.com } 36410618SOmar.Naji@arm.com 36510618SOmar.Naji@arm.com /** 36610618SOmar.Naji@arm.com * Kick off accounting for power and refresh states and 36710618SOmar.Naji@arm.com * schedule initial refresh. 36810618SOmar.Naji@arm.com * 36910618SOmar.Naji@arm.com * @param ref_tick Tick for first refresh 37010618SOmar.Naji@arm.com */ 37110618SOmar.Naji@arm.com void startup(Tick ref_tick); 37210618SOmar.Naji@arm.com 37310618SOmar.Naji@arm.com /** 37410619Sandreas.hansson@arm.com * Stop the refresh events. 37510619Sandreas.hansson@arm.com */ 37610619Sandreas.hansson@arm.com void suspend(); 37710619Sandreas.hansson@arm.com 37810619Sandreas.hansson@arm.com /** 37910618SOmar.Naji@arm.com * Check if the current rank is available for scheduling. 38010618SOmar.Naji@arm.com * 38110618SOmar.Naji@arm.com * @param Return true if the rank is idle from a refresh point of view 38210618SOmar.Naji@arm.com */ 38310618SOmar.Naji@arm.com bool isAvailable() const { return refreshState == REF_IDLE; } 38410618SOmar.Naji@arm.com 38510618SOmar.Naji@arm.com /** 38611676Swendy.elsasser@arm.com * Check if the current rank has all banks closed and is not 38711676Swendy.elsasser@arm.com * in a low power state 38811676Swendy.elsasser@arm.com * 38911676Swendy.elsasser@arm.com * @param Return true if the rank is idle from a bank 39011676Swendy.elsasser@arm.com * and power point of view 39111676Swendy.elsasser@arm.com */ 39211676Swendy.elsasser@arm.com bool inPwrIdleState() const { return pwrState == PWR_IDLE; } 39311676Swendy.elsasser@arm.com 39411676Swendy.elsasser@arm.com /** 39510618SOmar.Naji@arm.com * Let the rank check if it was waiting for requests to drain 39610618SOmar.Naji@arm.com * to allow it to transition states. 39710618SOmar.Naji@arm.com */ 39810618SOmar.Naji@arm.com void checkDrainDone(); 39910618SOmar.Naji@arm.com 40011675Swendy.elsasser@arm.com /** 40111675Swendy.elsasser@arm.com * Push command out of cmdList queue that are scheduled at 40211675Swendy.elsasser@arm.com * or before curTick() to DRAMPower library 40311675Swendy.elsasser@arm.com * All commands before curTick are guaranteed to be complete 40411675Swendy.elsasser@arm.com * and can safely be flushed. 40511675Swendy.elsasser@arm.com */ 40611675Swendy.elsasser@arm.com void flushCmdList(); 40711675Swendy.elsasser@arm.com 40810618SOmar.Naji@arm.com /* 40910618SOmar.Naji@arm.com * Function to register Stats 41010618SOmar.Naji@arm.com */ 41110618SOmar.Naji@arm.com void regStats(); 41210618SOmar.Naji@arm.com 41311677Swendy.elsasser@arm.com /** 41411677Swendy.elsasser@arm.com * Computes stats just prior to dump event 41511677Swendy.elsasser@arm.com */ 41611677Swendy.elsasser@arm.com void computeStats(); 41711677Swendy.elsasser@arm.com 41810618SOmar.Naji@arm.com void processActivateEvent(); 41910618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processActivateEvent> 42010618SOmar.Naji@arm.com activateEvent; 42110618SOmar.Naji@arm.com 42210618SOmar.Naji@arm.com void processPrechargeEvent(); 42310618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processPrechargeEvent> 42410618SOmar.Naji@arm.com prechargeEvent; 42510618SOmar.Naji@arm.com 42610618SOmar.Naji@arm.com void processRefreshEvent(); 42710618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processRefreshEvent> 42810618SOmar.Naji@arm.com refreshEvent; 42910618SOmar.Naji@arm.com 43010618SOmar.Naji@arm.com void processPowerEvent(); 43110618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processPowerEvent> 43210618SOmar.Naji@arm.com powerEvent; 43310618SOmar.Naji@arm.com 43410618SOmar.Naji@arm.com }; 43510618SOmar.Naji@arm.com 43611677Swendy.elsasser@arm.com // define the process to compute stats on simulation exit 43711677Swendy.elsasser@arm.com // defined per rank as the per rank stats are based on state 43811677Swendy.elsasser@arm.com // transition and periodically updated, requiring re-sync at 43911677Swendy.elsasser@arm.com // exit. 44011677Swendy.elsasser@arm.com class RankDumpCallback : public Callback 44111677Swendy.elsasser@arm.com { 44211677Swendy.elsasser@arm.com Rank *ranks; 44311677Swendy.elsasser@arm.com public: 44411677Swendy.elsasser@arm.com RankDumpCallback(Rank *r) : ranks(r) {} 44511677Swendy.elsasser@arm.com virtual void process() { ranks->computeStats(); }; 44611677Swendy.elsasser@arm.com }; 44711677Swendy.elsasser@arm.com 4489243SN/A /** 4499831SN/A * A burst helper helps organize and manage a packet that is larger than 4509831SN/A * the DRAM burst size. A system packet that is larger than the burst size 4519831SN/A * is split into multiple DRAM packets and all those DRAM packets point to 4529831SN/A * a single burst helper such that we know when the whole packet is served. 4539831SN/A */ 4549831SN/A class BurstHelper { 4559831SN/A 4569831SN/A public: 4579831SN/A 4589831SN/A /** Number of DRAM bursts requred for a system packet **/ 4599831SN/A const unsigned int burstCount; 4609831SN/A 4619831SN/A /** Number of DRAM bursts serviced so far for a system packet **/ 4629831SN/A unsigned int burstsServiced; 4639831SN/A 4649831SN/A BurstHelper(unsigned int _burstCount) 4659831SN/A : burstCount(_burstCount), burstsServiced(0) 46610618SOmar.Naji@arm.com { } 4679831SN/A }; 4689831SN/A 4699831SN/A /** 4709243SN/A * A DRAM packet stores packets along with the timestamp of when 4719243SN/A * the packet entered the queue, and also the decoded address. 4729243SN/A */ 4739243SN/A class DRAMPacket { 4749243SN/A 4759243SN/A public: 4769243SN/A 4779243SN/A /** When did request enter the controller */ 4789243SN/A const Tick entryTime; 4799243SN/A 4809243SN/A /** When will request leave the controller */ 4819243SN/A Tick readyTime; 4829243SN/A 4839243SN/A /** This comes from the outside world */ 4849243SN/A const PacketPtr pkt; 4859243SN/A 4869966SN/A const bool isRead; 4879966SN/A 4889243SN/A /** Will be populated by address decoder */ 4899243SN/A const uint8_t rank; 4909967SN/A const uint8_t bank; 49110245Sandreas.hansson@arm.com const uint32_t row; 4929831SN/A 4939831SN/A /** 4949967SN/A * Bank id is calculated considering banks in all the ranks 4959967SN/A * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and 4969967SN/A * bankId = 8 --> rank1, bank0 4979967SN/A */ 4989967SN/A const uint16_t bankId; 4999967SN/A 5009967SN/A /** 5019831SN/A * The starting address of the DRAM packet. 5029831SN/A * This address could be unaligned to burst size boundaries. The 5039831SN/A * reason is to keep the address offset so we can accurately check 5049831SN/A * incoming read packets with packets in the write queue. 5059831SN/A */ 5069832SN/A Addr addr; 5079831SN/A 5089831SN/A /** 5099831SN/A * The size of this dram packet in bytes 5109831SN/A * It is always equal or smaller than DRAM burst size 5119831SN/A */ 5129832SN/A unsigned int size; 5139831SN/A 5149831SN/A /** 5159831SN/A * A pointer to the BurstHelper if this DRAMPacket is a split packet 5169831SN/A * If not a split packet (common case), this is set to NULL 5179831SN/A */ 5189831SN/A BurstHelper* burstHelper; 5199967SN/A Bank& bankRef; 52010618SOmar.Naji@arm.com Rank& rankRef; 5219243SN/A 5229967SN/A DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank, 52310245Sandreas.hansson@arm.com uint32_t _row, uint16_t bank_id, Addr _addr, 52410618SOmar.Naji@arm.com unsigned int _size, Bank& bank_ref, Rank& rank_ref) 5259243SN/A : entryTime(curTick()), readyTime(curTick()), 5269967SN/A pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row), 5279967SN/A bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL), 52810618SOmar.Naji@arm.com bankRef(bank_ref), rankRef(rank_ref) 5299243SN/A { } 5309243SN/A 5319243SN/A }; 5329243SN/A 5339243SN/A /** 5349243SN/A * Bunch of things requires to setup "events" in gem5 53510206Sandreas.hansson@arm.com * When event "respondEvent" occurs for example, the method 53610206Sandreas.hansson@arm.com * processRespondEvent is called; no parameters are allowed 5379243SN/A * in these methods 5389243SN/A */ 53910208Sandreas.hansson@arm.com void processNextReqEvent(); 54010208Sandreas.hansson@arm.com EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent; 54110208Sandreas.hansson@arm.com 5429243SN/A void processRespondEvent(); 54310146Sandreas.hansson@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent; 5449243SN/A 5459243SN/A /** 5469243SN/A * Check if the read queue has room for more entries 5479243SN/A * 5489831SN/A * @param pktCount The number of entries needed in the read queue 5499243SN/A * @return true if read queue is full, false otherwise 5509243SN/A */ 5519831SN/A bool readQueueFull(unsigned int pktCount) const; 5529243SN/A 5539243SN/A /** 5549243SN/A * Check if the write queue has room for more entries 5559243SN/A * 5569831SN/A * @param pktCount The number of entries needed in the write queue 5579243SN/A * @return true if write queue is full, false otherwise 5589243SN/A */ 5599831SN/A bool writeQueueFull(unsigned int pktCount) const; 5609243SN/A 5619243SN/A /** 5629243SN/A * When a new read comes in, first check if the write q has a 5639243SN/A * pending request to the same address.\ If not, decode the 5649831SN/A * address to populate rank/bank/row, create one or mutliple 5659831SN/A * "dram_pkt", and push them to the back of the read queue.\ 5669831SN/A * If this is the only 5679243SN/A * read request in the system, schedule an event to start 5689243SN/A * servicing it. 5699243SN/A * 5709243SN/A * @param pkt The request packet from the outside world 5719831SN/A * @param pktCount The number of DRAM bursts the pkt 5729831SN/A * translate to. If pkt size is larger then one full burst, 5739831SN/A * then pktCount is greater than one. 5749243SN/A */ 5759831SN/A void addToReadQueue(PacketPtr pkt, unsigned int pktCount); 5769243SN/A 5779243SN/A /** 5789243SN/A * Decode the incoming pkt, create a dram_pkt and push to the 5799243SN/A * back of the write queue. \If the write q length is more than 5809243SN/A * the threshold specified by the user, ie the queue is beginning 5819243SN/A * to get full, stop reads, and start draining writes. 5829243SN/A * 5839243SN/A * @param pkt The request packet from the outside world 5849831SN/A * @param pktCount The number of DRAM bursts the pkt 5859831SN/A * translate to. If pkt size is larger then one full burst, 5869831SN/A * then pktCount is greater than one. 5879243SN/A */ 5889831SN/A void addToWriteQueue(PacketPtr pkt, unsigned int pktCount); 5899243SN/A 5909243SN/A /** 5919243SN/A * Actually do the DRAM access - figure out the latency it 5929243SN/A * will take to service the req based on bank state, channel state etc 5939243SN/A * and then update those states to account for this request.\ Based 5949243SN/A * on this, update the packet's "readyTime" and move it to the 5959243SN/A * response q from where it will eventually go back to the outside 5969243SN/A * world. 5979243SN/A * 5989243SN/A * @param pkt The DRAM packet created from the outside world pkt 5999243SN/A */ 6009243SN/A void doDRAMAccess(DRAMPacket* dram_pkt); 6019243SN/A 6029243SN/A /** 6039243SN/A * When a packet reaches its "readyTime" in the response Q, 6049243SN/A * use the "access()" method in AbstractMemory to actually 6059243SN/A * create the response packet, and send it back to the outside 6069243SN/A * world requestor. 6079243SN/A * 6089243SN/A * @param pkt The packet from the outside world 6099726SN/A * @param static_latency Static latency to add before sending the packet 6109243SN/A */ 6119726SN/A void accessAndRespond(PacketPtr pkt, Tick static_latency); 6129243SN/A 6139243SN/A /** 6149243SN/A * Address decoder to figure out physical mapping onto ranks, 6159831SN/A * banks, and rows. This function is called multiple times on the same 6169831SN/A * system packet if the pakcet is larger than burst of the memory. The 6179831SN/A * dramPktAddr is used for the offset within the packet. 6189243SN/A * 6199243SN/A * @param pkt The packet from the outside world 6209831SN/A * @param dramPktAddr The starting address of the DRAM packet 6219831SN/A * @param size The size of the DRAM packet in bytes 6229966SN/A * @param isRead Is the request for a read or a write to DRAM 6239243SN/A * @return A DRAMPacket pointer with the decoded information 6249243SN/A */ 62510143SN/A DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size, 62610143SN/A bool isRead); 6279243SN/A 6289243SN/A /** 62910206Sandreas.hansson@arm.com * The memory schduler/arbiter - picks which request needs to 6309567SN/A * go next, based on the specified policy such as FCFS or FR-FCFS 63110206Sandreas.hansson@arm.com * and moves it to the head of the queue. 63210393Swendy.elsasser@arm.com * Prioritizes accesses to the same rank as previous burst unless 63310393Swendy.elsasser@arm.com * controller is switching command type. 63410393Swendy.elsasser@arm.com * 63510393Swendy.elsasser@arm.com * @param queue Queued requests to consider 63610890Swendy.elsasser@arm.com * @param extra_col_delay Any extra delay due to a read/write switch 63710618SOmar.Naji@arm.com * @return true if a packet is scheduled to a rank which is available else 63810618SOmar.Naji@arm.com * false 6399243SN/A */ 64010890Swendy.elsasser@arm.com bool chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay); 6419243SN/A 6429243SN/A /** 6439974SN/A * For FR-FCFS policy reorder the read/write queue depending on row buffer 64410890Swendy.elsasser@arm.com * hits and earliest bursts available in DRAM 64510393Swendy.elsasser@arm.com * 64610393Swendy.elsasser@arm.com * @param queue Queued requests to consider 64710890Swendy.elsasser@arm.com * @param extra_col_delay Any extra delay due to a read/write switch 64810618SOmar.Naji@arm.com * @return true if a packet is scheduled to a rank which is available else 64910618SOmar.Naji@arm.com * false 6509974SN/A */ 65110890Swendy.elsasser@arm.com bool reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay); 6529974SN/A 6539974SN/A /** 65410211Sandreas.hansson@arm.com * Find which are the earliest banks ready to issue an activate 65510211Sandreas.hansson@arm.com * for the enqueued requests. Assumes maximum of 64 banks per DIMM 65610393Swendy.elsasser@arm.com * Also checks if the bank is already prepped. 6579967SN/A * 65810393Swendy.elsasser@arm.com * @param queue Queued requests to consider 65910890Swendy.elsasser@arm.com * @param time of seamless burst command 6609967SN/A * @return One-hot encoded mask of bank indices 66110890Swendy.elsasser@arm.com * @return boolean indicating burst can issue seamlessly, with no gaps 6629967SN/A */ 66310890Swendy.elsasser@arm.com std::pair<uint64_t, bool> minBankPrep(const std::deque<DRAMPacket*>& queue, 66410890Swendy.elsasser@arm.com Tick min_col_at) const; 6659488SN/A 6669488SN/A /** 6679488SN/A * Keep track of when row activations happen, in order to enforce 6689488SN/A * the maximum number of activations in the activation window. The 6699488SN/A * method updates the time that the banks become available based 6709488SN/A * on the current limits. 67110210Sandreas.hansson@arm.com * 67210618SOmar.Naji@arm.com * @param rank_ref Reference to the rank 67310618SOmar.Naji@arm.com * @param bank_ref Reference to the bank 67410210Sandreas.hansson@arm.com * @param act_tick Time when the activation takes place 67510210Sandreas.hansson@arm.com * @param row Index of the row 6769488SN/A */ 67710618SOmar.Naji@arm.com void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick, 67810618SOmar.Naji@arm.com uint32_t row); 67910207Sandreas.hansson@arm.com 68010207Sandreas.hansson@arm.com /** 68110207Sandreas.hansson@arm.com * Precharge a given bank and also update when the precharge is 68210207Sandreas.hansson@arm.com * done. This will also deal with any stats related to the 68310207Sandreas.hansson@arm.com * accesses to the open page. 68410207Sandreas.hansson@arm.com * 68510618SOmar.Naji@arm.com * @param rank_ref The rank to precharge 68610247Sandreas.hansson@arm.com * @param bank_ref The bank to precharge 68710211Sandreas.hansson@arm.com * @param pre_at Time when the precharge takes place 68810247Sandreas.hansson@arm.com * @param trace Is this an auto precharge then do not add to trace 68910207Sandreas.hansson@arm.com */ 69010618SOmar.Naji@arm.com void prechargeBank(Rank& rank_ref, Bank& bank_ref, 69110618SOmar.Naji@arm.com Tick pre_at, bool trace = true); 6929488SN/A 69310143SN/A /** 69410143SN/A * Used for debugging to observe the contents of the queues. 69510143SN/A */ 6969243SN/A void printQs() const; 6979243SN/A 6989243SN/A /** 69910889Sandreas.hansson@arm.com * Burst-align an address. 70010889Sandreas.hansson@arm.com * 70110889Sandreas.hansson@arm.com * @param addr The potentially unaligned address 70210889Sandreas.hansson@arm.com * 70310889Sandreas.hansson@arm.com * @return An address aligned to a DRAM burst 70410889Sandreas.hansson@arm.com */ 70510889Sandreas.hansson@arm.com Addr burstAlign(Addr addr) const { return (addr & ~(Addr(burstSize - 1))); } 70610889Sandreas.hansson@arm.com 70710889Sandreas.hansson@arm.com /** 7089243SN/A * The controller's main read and write queues 7099243SN/A */ 7109833SN/A std::deque<DRAMPacket*> readQueue; 7119833SN/A std::deque<DRAMPacket*> writeQueue; 7129243SN/A 7139243SN/A /** 71410889Sandreas.hansson@arm.com * To avoid iterating over the write queue to check for 71510889Sandreas.hansson@arm.com * overlapping transactions, maintain a set of burst addresses 71610889Sandreas.hansson@arm.com * that are currently queued. Since we merge writes to the same 71710889Sandreas.hansson@arm.com * location we never have more than one address to the same burst 71810889Sandreas.hansson@arm.com * address. 71910889Sandreas.hansson@arm.com */ 72010889Sandreas.hansson@arm.com std::unordered_set<Addr> isInWriteQueue; 72110889Sandreas.hansson@arm.com 72210889Sandreas.hansson@arm.com /** 7239243SN/A * Response queue where read packets wait after we're done working 7249567SN/A * with them, but it's not time to send the response yet. The 7259567SN/A * responses are stored seperately mostly to keep the code clean 7269567SN/A * and help with events scheduling. For all logical purposes such 7279567SN/A * as sizing the read queue, this and the main read queue need to 7289567SN/A * be added together. 7299243SN/A */ 7309833SN/A std::deque<DRAMPacket*> respQueue; 7319243SN/A 7329567SN/A /** 73310618SOmar.Naji@arm.com * Vector of ranks 7349243SN/A */ 73510618SOmar.Naji@arm.com std::vector<Rank*> ranks; 7369243SN/A 7379243SN/A /** 7389243SN/A * The following are basic design parameters of the memory 7399831SN/A * controller, and are initialized based on parameter values. 7409831SN/A * The rowsPerBank is determined based on the capacity, number of 7419831SN/A * ranks and banks, the burst size, and the row buffer size. 7429243SN/A */ 74310489SOmar.Naji@arm.com const uint32_t deviceSize; 7449831SN/A const uint32_t deviceBusWidth; 7459831SN/A const uint32_t burstLength; 7469831SN/A const uint32_t deviceRowBufferSize; 7479831SN/A const uint32_t devicesPerRank; 7489831SN/A const uint32_t burstSize; 7499831SN/A const uint32_t rowBufferSize; 75010140SN/A const uint32_t columnsPerRowBuffer; 75110286Sandreas.hansson@arm.com const uint32_t columnsPerStripe; 7529243SN/A const uint32_t ranksPerChannel; 75310394Swendy.elsasser@arm.com const uint32_t bankGroupsPerRank; 75410394Swendy.elsasser@arm.com const bool bankGroupArch; 7559243SN/A const uint32_t banksPerRank; 7569566SN/A const uint32_t channels; 7579243SN/A uint32_t rowsPerBank; 7589243SN/A const uint32_t readBufferSize; 7599243SN/A const uint32_t writeBufferSize; 76010140SN/A const uint32_t writeHighThreshold; 76110140SN/A const uint32_t writeLowThreshold; 76210140SN/A const uint32_t minWritesPerSwitch; 76310140SN/A uint32_t writesThisTime; 76410147Sandreas.hansson@arm.com uint32_t readsThisTime; 7659243SN/A 7669243SN/A /** 7679243SN/A * Basic memory timing parameters initialized based on parameter 7689243SN/A * values. 7699243SN/A */ 77010286Sandreas.hansson@arm.com const Tick M5_CLASS_VAR_USED tCK; 7719243SN/A const Tick tWTR; 77210206Sandreas.hansson@arm.com const Tick tRTW; 77310393Swendy.elsasser@arm.com const Tick tCS; 7749243SN/A const Tick tBURST; 77510394Swendy.elsasser@arm.com const Tick tCCD_L; 7769243SN/A const Tick tRCD; 7779243SN/A const Tick tCL; 7789243SN/A const Tick tRP; 7799963SN/A const Tick tRAS; 78010210Sandreas.hansson@arm.com const Tick tWR; 78110212Sandreas.hansson@arm.com const Tick tRTP; 7829243SN/A const Tick tRFC; 7839243SN/A const Tick tREFI; 7849971SN/A const Tick tRRD; 78510394Swendy.elsasser@arm.com const Tick tRRD_L; 7869488SN/A const Tick tXAW; 78711673SOmar.Naji@arm.com const Tick tXP; 78811673SOmar.Naji@arm.com const Tick tXS; 7899488SN/A const uint32_t activationLimit; 7909243SN/A 7919243SN/A /** 7929243SN/A * Memory controller configuration initialized based on parameter 7939243SN/A * values. 7949243SN/A */ 7959243SN/A Enums::MemSched memSchedPolicy; 7969243SN/A Enums::AddrMap addrMapping; 7979243SN/A Enums::PageManage pageMgmt; 7989243SN/A 7999243SN/A /** 80010141SN/A * Max column accesses (read and write) per row, before forefully 80110141SN/A * closing it. 80210141SN/A */ 80310141SN/A const uint32_t maxAccessesPerRow; 80410141SN/A 80510141SN/A /** 8069726SN/A * Pipeline latency of the controller frontend. The frontend 8079726SN/A * contribution is added to writes (that complete when they are in 8089726SN/A * the write buffer) and reads that are serviced the write buffer. 8099726SN/A */ 8109726SN/A const Tick frontendLatency; 8119726SN/A 8129726SN/A /** 8139726SN/A * Pipeline latency of the backend and PHY. Along with the 8149726SN/A * frontend contribution, this latency is added to reads serviced 8159726SN/A * by the DRAM. 8169726SN/A */ 8179726SN/A const Tick backendLatency; 8189726SN/A 8199726SN/A /** 8209243SN/A * Till when has the main data bus been spoken for already? 8219243SN/A */ 8229243SN/A Tick busBusyUntil; 8239243SN/A 8249243SN/A Tick prevArrival; 8259243SN/A 82610206Sandreas.hansson@arm.com /** 82710206Sandreas.hansson@arm.com * The soonest you have to start thinking about the next request 82810206Sandreas.hansson@arm.com * is the longest access time that can occur before 82910206Sandreas.hansson@arm.com * busBusyUntil. Assuming you need to precharge, open a new row, 83010206Sandreas.hansson@arm.com * and access, it is tRP + tRCD + tCL. 83110206Sandreas.hansson@arm.com */ 83210206Sandreas.hansson@arm.com Tick nextReqTime; 8339972SN/A 8349243SN/A // All statistics that the model needs to capture 8359243SN/A Stats::Scalar readReqs; 8369243SN/A Stats::Scalar writeReqs; 8379831SN/A Stats::Scalar readBursts; 8389831SN/A Stats::Scalar writeBursts; 8399975SN/A Stats::Scalar bytesReadDRAM; 8409975SN/A Stats::Scalar bytesReadWrQ; 8419243SN/A Stats::Scalar bytesWritten; 8429977SN/A Stats::Scalar bytesReadSys; 8439977SN/A Stats::Scalar bytesWrittenSys; 8449243SN/A Stats::Scalar servicedByWrQ; 8459977SN/A Stats::Scalar mergedWrBursts; 8469243SN/A Stats::Scalar neitherReadNorWrite; 8479977SN/A Stats::Vector perBankRdBursts; 8489977SN/A Stats::Vector perBankWrBursts; 8499243SN/A Stats::Scalar numRdRetry; 8509243SN/A Stats::Scalar numWrRetry; 8519243SN/A Stats::Scalar totGap; 8529243SN/A Stats::Vector readPktSize; 8539243SN/A Stats::Vector writePktSize; 8549243SN/A Stats::Vector rdQLenPdf; 8559243SN/A Stats::Vector wrQLenPdf; 8569727SN/A Stats::Histogram bytesPerActivate; 85710147Sandreas.hansson@arm.com Stats::Histogram rdPerTurnAround; 85810147Sandreas.hansson@arm.com Stats::Histogram wrPerTurnAround; 8599243SN/A 8609243SN/A // Latencies summed over all requests 8619243SN/A Stats::Scalar totQLat; 8629243SN/A Stats::Scalar totMemAccLat; 8639243SN/A Stats::Scalar totBusLat; 8649243SN/A 8659243SN/A // Average latencies per request 8669243SN/A Stats::Formula avgQLat; 8679243SN/A Stats::Formula avgBusLat; 8689243SN/A Stats::Formula avgMemAccLat; 8699243SN/A 8709243SN/A // Average bandwidth 8719243SN/A Stats::Formula avgRdBW; 8729243SN/A Stats::Formula avgWrBW; 8739977SN/A Stats::Formula avgRdBWSys; 8749977SN/A Stats::Formula avgWrBWSys; 8759243SN/A Stats::Formula peakBW; 8769243SN/A Stats::Formula busUtil; 8779975SN/A Stats::Formula busUtilRead; 8789975SN/A Stats::Formula busUtilWrite; 8799243SN/A 8809243SN/A // Average queue lengths 8819243SN/A Stats::Average avgRdQLen; 8829243SN/A Stats::Average avgWrQLen; 8839243SN/A 8849243SN/A // Row hit count and rate 8859243SN/A Stats::Scalar readRowHits; 8869243SN/A Stats::Scalar writeRowHits; 8879243SN/A Stats::Formula readRowHitRate; 8889243SN/A Stats::Formula writeRowHitRate; 8899243SN/A Stats::Formula avgGap; 8909243SN/A 8919975SN/A // DRAM Power Calculation 8929975SN/A Stats::Formula pageHitRate; 8939975SN/A 89410393Swendy.elsasser@arm.com // Holds the value of the rank of burst issued 89510393Swendy.elsasser@arm.com uint8_t activeRank; 89610393Swendy.elsasser@arm.com 89710432SOmar.Naji@arm.com // timestamp offset 89810432SOmar.Naji@arm.com uint64_t timeStampOffset; 89910432SOmar.Naji@arm.com 90011190Sandreas.hansson@arm.com /** 90111190Sandreas.hansson@arm.com * Upstream caches need this packet until true is returned, so 90211190Sandreas.hansson@arm.com * hold it for deletion until a subsequent call 9039349SN/A */ 90411190Sandreas.hansson@arm.com std::unique_ptr<Packet> pendingDelete; 9059349SN/A 90610432SOmar.Naji@arm.com /** 90710618SOmar.Naji@arm.com * This function increments the energy when called. If stats are 90810618SOmar.Naji@arm.com * dumped periodically, note accumulated energy values will 90910618SOmar.Naji@arm.com * appear in the stats (even if the stats are reset). This is a 91010618SOmar.Naji@arm.com * result of the energy values coming from DRAMPower, and there 91110618SOmar.Naji@arm.com * is currently no support for resetting the state. 91210618SOmar.Naji@arm.com * 91310618SOmar.Naji@arm.com * @param rank Currrent rank 91410618SOmar.Naji@arm.com */ 91510618SOmar.Naji@arm.com void updatePowerStats(Rank& rank_ref); 91610432SOmar.Naji@arm.com 91710432SOmar.Naji@arm.com /** 91811675Swendy.elsasser@arm.com * Function for sorting Command structures based on timeStamp 91910432SOmar.Naji@arm.com * 92011675Swendy.elsasser@arm.com * @param a Memory Command 92111675Swendy.elsasser@arm.com * @param next Memory Command 92211675Swendy.elsasser@arm.com * @return true if timeStamp of Command 1 < timeStamp of Command 2 92310432SOmar.Naji@arm.com */ 92411675Swendy.elsasser@arm.com static bool sortTime(const Command& cmd, const Command& cmd_next) { 92511675Swendy.elsasser@arm.com return cmd.timeStamp < cmd_next.timeStamp; 92610432SOmar.Naji@arm.com }; 92710432SOmar.Naji@arm.com 9289243SN/A public: 9299243SN/A 93011169Sandreas.hansson@arm.com void regStats() override; 9319243SN/A 93210146Sandreas.hansson@arm.com DRAMCtrl(const DRAMCtrlParams* p); 9339243SN/A 93411168Sandreas.hansson@arm.com DrainState drain() override; 9359243SN/A 9369294SN/A virtual BaseSlavePort& getSlavePort(const std::string& if_name, 93711169Sandreas.hansson@arm.com PortID idx = InvalidPortID) override; 9389243SN/A 93911168Sandreas.hansson@arm.com virtual void init() override; 94011168Sandreas.hansson@arm.com virtual void startup() override; 94111168Sandreas.hansson@arm.com virtual void drainResume() override; 9429243SN/A 94311676Swendy.elsasser@arm.com /** 94411676Swendy.elsasser@arm.com * Return true once refresh is complete for all ranks and there are no 94511676Swendy.elsasser@arm.com * additional commands enqueued. (only evaluated when draining) 94611676Swendy.elsasser@arm.com * This will ensure that all banks are closed, power state is IDLE, and 94711676Swendy.elsasser@arm.com * power stats have been updated 94811676Swendy.elsasser@arm.com * 94911676Swendy.elsasser@arm.com * @return true if all ranks have refreshed, with no commands enqueued 95011676Swendy.elsasser@arm.com * 95111676Swendy.elsasser@arm.com */ 95211676Swendy.elsasser@arm.com bool allRanksDrained() const; 95311676Swendy.elsasser@arm.com 9549243SN/A protected: 9559243SN/A 9569243SN/A Tick recvAtomic(PacketPtr pkt); 9579243SN/A void recvFunctional(PacketPtr pkt); 9589243SN/A bool recvTimingReq(PacketPtr pkt); 9599243SN/A 9609243SN/A}; 9619243SN/A 96210146Sandreas.hansson@arm.com#endif //__MEM_DRAM_CTRL_HH__ 963