dram_ctrl.hh revision 10713
19243SN/A/* 210206Sandreas.hansson@arm.com * Copyright (c) 2012-2014 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 4310618SOmar.Naji@arm.com * Omar Naji 449243SN/A */ 459243SN/A 469243SN/A/** 479243SN/A * @file 4810146Sandreas.hansson@arm.com * DRAMCtrl declaration 499243SN/A */ 509243SN/A 5110146Sandreas.hansson@arm.com#ifndef __MEM_DRAM_CTRL_HH__ 5210146Sandreas.hansson@arm.com#define __MEM_DRAM_CTRL_HH__ 539243SN/A 549488SN/A#include <deque> 5510618SOmar.Naji@arm.com#include <string> 569488SN/A 579243SN/A#include "base/statistics.hh" 589243SN/A#include "enums/AddrMap.hh" 599243SN/A#include "enums/MemSched.hh" 609243SN/A#include "enums/PageManage.hh" 619243SN/A#include "mem/abstract_mem.hh" 629243SN/A#include "mem/qport.hh" 6310146Sandreas.hansson@arm.com#include "params/DRAMCtrl.hh" 649243SN/A#include "sim/eventq.hh" 6510432SOmar.Naji@arm.com#include "mem/drampower.hh" 669243SN/A 679243SN/A/** 6810287Sandreas.hansson@arm.com * The DRAM controller is a single-channel memory controller capturing 6910287Sandreas.hansson@arm.com * the most important timing constraints associated with a 7010287Sandreas.hansson@arm.com * contemporary DRAM. For multi-channel memory systems, the controller 7110287Sandreas.hansson@arm.com * is combined with a crossbar model, with the channel address 7210287Sandreas.hansson@arm.com * interleaving taking part in the crossbar. 739243SN/A * 7410287Sandreas.hansson@arm.com * As a basic design principle, this controller 7510287Sandreas.hansson@arm.com * model is not cycle callable, but instead uses events to: 1) decide 7610287Sandreas.hansson@arm.com * when new decisions can be made, 2) when resources become available, 7710287Sandreas.hansson@arm.com * 3) when things are to be considered done, and 4) when to send 7810287Sandreas.hansson@arm.com * things back. Through these simple principles, the model delivers 7910287Sandreas.hansson@arm.com * high performance, and lots of flexibility, allowing users to 8010287Sandreas.hansson@arm.com * evaluate the system impact of a wide range of memory technologies, 8110287Sandreas.hansson@arm.com * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC. 8210287Sandreas.hansson@arm.com * 8310287Sandreas.hansson@arm.com * For more details, please see Hansson et al, "Simulating DRAM 8410287Sandreas.hansson@arm.com * controllers for future system architecture exploration", 8510287Sandreas.hansson@arm.com * Proc. ISPASS, 2014. If you use this model as part of your research 8610287Sandreas.hansson@arm.com * please cite the paper. 879243SN/A */ 8810146Sandreas.hansson@arm.comclass DRAMCtrl : public AbstractMemory 899243SN/A{ 909243SN/A 919243SN/A private: 929243SN/A 939243SN/A // For now, make use of a queued slave port to avoid dealing with 949243SN/A // flow control for the responses being sent back 959243SN/A class MemoryPort : public QueuedSlavePort 969243SN/A { 979243SN/A 9810713Sandreas.hansson@arm.com RespPacketQueue queue; 9910146Sandreas.hansson@arm.com DRAMCtrl& memory; 1009243SN/A 1019243SN/A public: 1029243SN/A 10310146Sandreas.hansson@arm.com MemoryPort(const std::string& name, DRAMCtrl& _memory); 1049243SN/A 1059243SN/A protected: 1069243SN/A 1079243SN/A Tick recvAtomic(PacketPtr pkt); 1089243SN/A 1099243SN/A void recvFunctional(PacketPtr pkt); 1109243SN/A 1119243SN/A bool recvTimingReq(PacketPtr); 1129243SN/A 1139243SN/A virtual AddrRangeList getAddrRanges() const; 1149243SN/A 1159243SN/A }; 1169243SN/A 1179243SN/A /** 1189243SN/A * Our incoming port, for a multi-ported controller add a crossbar 1199243SN/A * in front of it 1209243SN/A */ 1219243SN/A MemoryPort port; 1229243SN/A 1239243SN/A /** 12410619Sandreas.hansson@arm.com * Remeber if the memory system is in timing mode 12510619Sandreas.hansson@arm.com */ 12610619Sandreas.hansson@arm.com bool isTimingMode; 12710619Sandreas.hansson@arm.com 12810619Sandreas.hansson@arm.com /** 1299243SN/A * Remember if we have to retry a request when available. 1309243SN/A */ 1319243SN/A bool retryRdReq; 1329243SN/A bool retryWrReq; 1339243SN/A 1349243SN/A /** 13510206Sandreas.hansson@arm.com * Bus state used to control the read/write switching and drive 13610206Sandreas.hansson@arm.com * the scheduling of the next request. 1379243SN/A */ 13810206Sandreas.hansson@arm.com enum BusState { 13910206Sandreas.hansson@arm.com READ = 0, 14010206Sandreas.hansson@arm.com READ_TO_WRITE, 14110206Sandreas.hansson@arm.com WRITE, 14210206Sandreas.hansson@arm.com WRITE_TO_READ 14310206Sandreas.hansson@arm.com }; 14410206Sandreas.hansson@arm.com 14510206Sandreas.hansson@arm.com BusState busState; 1469243SN/A 1479243SN/A /** 14810210Sandreas.hansson@arm.com * A basic class to track the bank state, i.e. what row is 14910210Sandreas.hansson@arm.com * currently open (if any), when is the bank free to accept a new 15010211Sandreas.hansson@arm.com * column (read/write) command, when can it be precharged, and 15110211Sandreas.hansson@arm.com * when can it be activated. 15210210Sandreas.hansson@arm.com * 15310210Sandreas.hansson@arm.com * The bank also keeps track of how many bytes have been accessed 15410210Sandreas.hansson@arm.com * in the open row since it was opened. 1559243SN/A */ 1569243SN/A class Bank 1579243SN/A { 1589243SN/A 1599243SN/A public: 1609243SN/A 16110207Sandreas.hansson@arm.com static const uint32_t NO_ROW = -1; 1629243SN/A 1639243SN/A uint32_t openRow; 16410246Sandreas.hansson@arm.com uint8_t bank; 16510394Swendy.elsasser@arm.com uint8_t bankgr; 1669243SN/A 16710211Sandreas.hansson@arm.com Tick colAllowedAt; 16810210Sandreas.hansson@arm.com Tick preAllowedAt; 1699969SN/A Tick actAllowedAt; 1709243SN/A 17110141SN/A uint32_t rowAccesses; 1729727SN/A uint32_t bytesAccessed; 1739727SN/A 1749727SN/A Bank() : 17510618SOmar.Naji@arm.com openRow(NO_ROW), bank(0), bankgr(0), 17610246Sandreas.hansson@arm.com colAllowedAt(0), preAllowedAt(0), actAllowedAt(0), 17710141SN/A rowAccesses(0), bytesAccessed(0) 1789243SN/A { } 1799243SN/A }; 1809243SN/A 18110618SOmar.Naji@arm.com 18210618SOmar.Naji@arm.com /** 18310618SOmar.Naji@arm.com * Rank class includes a vector of banks. Refresh and Power state 18410618SOmar.Naji@arm.com * machines are defined per rank. Events required to change the 18510618SOmar.Naji@arm.com * state of the refresh and power state machine are scheduled per 18610618SOmar.Naji@arm.com * rank. This class allows the implementation of rank-wise refresh 18710618SOmar.Naji@arm.com * and rank-wise power-down. 18810618SOmar.Naji@arm.com */ 18910618SOmar.Naji@arm.com class Rank : public EventManager 19010618SOmar.Naji@arm.com { 19110618SOmar.Naji@arm.com 19210618SOmar.Naji@arm.com private: 19310618SOmar.Naji@arm.com 19410618SOmar.Naji@arm.com /** 19510618SOmar.Naji@arm.com * The power state captures the different operational states of 19610618SOmar.Naji@arm.com * the DRAM and interacts with the bus read/write state machine, 19710618SOmar.Naji@arm.com * and the refresh state machine. In the idle state all banks are 19810618SOmar.Naji@arm.com * precharged. From there we either go to an auto refresh (as 19910618SOmar.Naji@arm.com * determined by the refresh state machine), or to a precharge 20010618SOmar.Naji@arm.com * power down mode. From idle the memory can also go to the active 20110618SOmar.Naji@arm.com * state (with one or more banks active), and in turn from there 20210618SOmar.Naji@arm.com * to active power down. At the moment we do not capture the deep 20310618SOmar.Naji@arm.com * power down and self-refresh state. 20410618SOmar.Naji@arm.com */ 20510618SOmar.Naji@arm.com enum PowerState { 20610618SOmar.Naji@arm.com PWR_IDLE = 0, 20710618SOmar.Naji@arm.com PWR_REF, 20810618SOmar.Naji@arm.com PWR_PRE_PDN, 20910618SOmar.Naji@arm.com PWR_ACT, 21010618SOmar.Naji@arm.com PWR_ACT_PDN 21110618SOmar.Naji@arm.com }; 21210618SOmar.Naji@arm.com 21310618SOmar.Naji@arm.com /** 21410618SOmar.Naji@arm.com * The refresh state is used to control the progress of the 21510618SOmar.Naji@arm.com * refresh scheduling. When normal operation is in progress the 21610618SOmar.Naji@arm.com * refresh state is idle. From there, it progresses to the refresh 21710618SOmar.Naji@arm.com * drain state once tREFI has passed. The refresh drain state 21810618SOmar.Naji@arm.com * captures the DRAM row active state, as it will stay there until 21910618SOmar.Naji@arm.com * all ongoing accesses complete. Thereafter all banks are 22010618SOmar.Naji@arm.com * precharged, and lastly, the DRAM is refreshed. 22110618SOmar.Naji@arm.com */ 22210618SOmar.Naji@arm.com enum RefreshState { 22310618SOmar.Naji@arm.com REF_IDLE = 0, 22410618SOmar.Naji@arm.com REF_DRAIN, 22510618SOmar.Naji@arm.com REF_PRE, 22610618SOmar.Naji@arm.com REF_RUN 22710618SOmar.Naji@arm.com }; 22810618SOmar.Naji@arm.com 22910618SOmar.Naji@arm.com /** 23010618SOmar.Naji@arm.com * A reference to the parent DRAMCtrl instance 23110618SOmar.Naji@arm.com */ 23210618SOmar.Naji@arm.com DRAMCtrl& memory; 23310618SOmar.Naji@arm.com 23410618SOmar.Naji@arm.com /** 23510618SOmar.Naji@arm.com * Since we are taking decisions out of order, we need to keep 23610618SOmar.Naji@arm.com * track of what power transition is happening at what time, such 23710618SOmar.Naji@arm.com * that we can go back in time and change history. For example, if 23810618SOmar.Naji@arm.com * we precharge all banks and schedule going to the idle state, we 23910618SOmar.Naji@arm.com * might at a later point decide to activate a bank before the 24010618SOmar.Naji@arm.com * transition to idle would have taken place. 24110618SOmar.Naji@arm.com */ 24210618SOmar.Naji@arm.com PowerState pwrStateTrans; 24310618SOmar.Naji@arm.com 24410618SOmar.Naji@arm.com /** 24510618SOmar.Naji@arm.com * Current power state. 24610618SOmar.Naji@arm.com */ 24710618SOmar.Naji@arm.com PowerState pwrState; 24810618SOmar.Naji@arm.com 24910618SOmar.Naji@arm.com /** 25010618SOmar.Naji@arm.com * Track when we transitioned to the current power state 25110618SOmar.Naji@arm.com */ 25210618SOmar.Naji@arm.com Tick pwrStateTick; 25310618SOmar.Naji@arm.com 25410618SOmar.Naji@arm.com /** 25510618SOmar.Naji@arm.com * current refresh state 25610618SOmar.Naji@arm.com */ 25710618SOmar.Naji@arm.com RefreshState refreshState; 25810618SOmar.Naji@arm.com 25910618SOmar.Naji@arm.com /** 26010618SOmar.Naji@arm.com * Keep track of when a refresh is due. 26110618SOmar.Naji@arm.com */ 26210618SOmar.Naji@arm.com Tick refreshDueAt; 26310618SOmar.Naji@arm.com 26410618SOmar.Naji@arm.com /* 26510618SOmar.Naji@arm.com * Command energies 26610618SOmar.Naji@arm.com */ 26710618SOmar.Naji@arm.com Stats::Scalar actEnergy; 26810618SOmar.Naji@arm.com Stats::Scalar preEnergy; 26910618SOmar.Naji@arm.com Stats::Scalar readEnergy; 27010618SOmar.Naji@arm.com Stats::Scalar writeEnergy; 27110618SOmar.Naji@arm.com Stats::Scalar refreshEnergy; 27210618SOmar.Naji@arm.com 27310618SOmar.Naji@arm.com /* 27410618SOmar.Naji@arm.com * Active Background Energy 27510618SOmar.Naji@arm.com */ 27610618SOmar.Naji@arm.com Stats::Scalar actBackEnergy; 27710618SOmar.Naji@arm.com 27810618SOmar.Naji@arm.com /* 27910618SOmar.Naji@arm.com * Precharge Background Energy 28010618SOmar.Naji@arm.com */ 28110618SOmar.Naji@arm.com Stats::Scalar preBackEnergy; 28210618SOmar.Naji@arm.com 28310618SOmar.Naji@arm.com Stats::Scalar totalEnergy; 28410618SOmar.Naji@arm.com Stats::Scalar averagePower; 28510618SOmar.Naji@arm.com 28610618SOmar.Naji@arm.com /** 28710618SOmar.Naji@arm.com * Track time spent in each power state. 28810618SOmar.Naji@arm.com */ 28910618SOmar.Naji@arm.com Stats::Vector pwrStateTime; 29010618SOmar.Naji@arm.com 29110618SOmar.Naji@arm.com /** 29210618SOmar.Naji@arm.com * Function to update Power Stats 29310618SOmar.Naji@arm.com */ 29410618SOmar.Naji@arm.com void updatePowerStats(); 29510618SOmar.Naji@arm.com 29610618SOmar.Naji@arm.com /** 29710618SOmar.Naji@arm.com * Schedule a power state transition in the future, and 29810618SOmar.Naji@arm.com * potentially override an already scheduled transition. 29910618SOmar.Naji@arm.com * 30010618SOmar.Naji@arm.com * @param pwr_state Power state to transition to 30110618SOmar.Naji@arm.com * @param tick Tick when transition should take place 30210618SOmar.Naji@arm.com */ 30310618SOmar.Naji@arm.com void schedulePowerEvent(PowerState pwr_state, Tick tick); 30410618SOmar.Naji@arm.com 30510618SOmar.Naji@arm.com public: 30610618SOmar.Naji@arm.com 30710618SOmar.Naji@arm.com /** 30810618SOmar.Naji@arm.com * Current Rank index 30910618SOmar.Naji@arm.com */ 31010618SOmar.Naji@arm.com uint8_t rank; 31110618SOmar.Naji@arm.com 31210618SOmar.Naji@arm.com /** 31310618SOmar.Naji@arm.com * One DRAMPower instance per rank 31410618SOmar.Naji@arm.com */ 31510618SOmar.Naji@arm.com DRAMPower power; 31610618SOmar.Naji@arm.com 31710618SOmar.Naji@arm.com /** 31810618SOmar.Naji@arm.com * Vector of Banks. Each rank is made of several devices which in 31910618SOmar.Naji@arm.com * term are made from several banks. 32010618SOmar.Naji@arm.com */ 32110618SOmar.Naji@arm.com std::vector<Bank> banks; 32210618SOmar.Naji@arm.com 32310618SOmar.Naji@arm.com /** 32410618SOmar.Naji@arm.com * To track number of banks which are currently active for 32510618SOmar.Naji@arm.com * this rank. 32610618SOmar.Naji@arm.com */ 32710618SOmar.Naji@arm.com unsigned int numBanksActive; 32810618SOmar.Naji@arm.com 32910618SOmar.Naji@arm.com /** List to keep track of activate ticks */ 33010618SOmar.Naji@arm.com std::deque<Tick> actTicks; 33110618SOmar.Naji@arm.com 33210618SOmar.Naji@arm.com Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p); 33310618SOmar.Naji@arm.com 33410618SOmar.Naji@arm.com const std::string name() const 33510618SOmar.Naji@arm.com { 33610618SOmar.Naji@arm.com return csprintf("%s_%d", memory.name(), rank); 33710618SOmar.Naji@arm.com } 33810618SOmar.Naji@arm.com 33910618SOmar.Naji@arm.com /** 34010618SOmar.Naji@arm.com * Kick off accounting for power and refresh states and 34110618SOmar.Naji@arm.com * schedule initial refresh. 34210618SOmar.Naji@arm.com * 34310618SOmar.Naji@arm.com * @param ref_tick Tick for first refresh 34410618SOmar.Naji@arm.com */ 34510618SOmar.Naji@arm.com void startup(Tick ref_tick); 34610618SOmar.Naji@arm.com 34710618SOmar.Naji@arm.com /** 34810619Sandreas.hansson@arm.com * Stop the refresh events. 34910619Sandreas.hansson@arm.com */ 35010619Sandreas.hansson@arm.com void suspend(); 35110619Sandreas.hansson@arm.com 35210619Sandreas.hansson@arm.com /** 35310618SOmar.Naji@arm.com * Check if the current rank is available for scheduling. 35410618SOmar.Naji@arm.com * 35510618SOmar.Naji@arm.com * @param Return true if the rank is idle from a refresh point of view 35610618SOmar.Naji@arm.com */ 35710618SOmar.Naji@arm.com bool isAvailable() const { return refreshState == REF_IDLE; } 35810618SOmar.Naji@arm.com 35910618SOmar.Naji@arm.com /** 36010618SOmar.Naji@arm.com * Let the rank check if it was waiting for requests to drain 36110618SOmar.Naji@arm.com * to allow it to transition states. 36210618SOmar.Naji@arm.com */ 36310618SOmar.Naji@arm.com void checkDrainDone(); 36410618SOmar.Naji@arm.com 36510618SOmar.Naji@arm.com /* 36610618SOmar.Naji@arm.com * Function to register Stats 36710618SOmar.Naji@arm.com */ 36810618SOmar.Naji@arm.com void regStats(); 36910618SOmar.Naji@arm.com 37010618SOmar.Naji@arm.com void processActivateEvent(); 37110618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processActivateEvent> 37210618SOmar.Naji@arm.com activateEvent; 37310618SOmar.Naji@arm.com 37410618SOmar.Naji@arm.com void processPrechargeEvent(); 37510618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processPrechargeEvent> 37610618SOmar.Naji@arm.com prechargeEvent; 37710618SOmar.Naji@arm.com 37810618SOmar.Naji@arm.com void processRefreshEvent(); 37910618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processRefreshEvent> 38010618SOmar.Naji@arm.com refreshEvent; 38110618SOmar.Naji@arm.com 38210618SOmar.Naji@arm.com void processPowerEvent(); 38310618SOmar.Naji@arm.com EventWrapper<Rank, &Rank::processPowerEvent> 38410618SOmar.Naji@arm.com powerEvent; 38510618SOmar.Naji@arm.com 38610618SOmar.Naji@arm.com }; 38710618SOmar.Naji@arm.com 3889243SN/A /** 3899831SN/A * A burst helper helps organize and manage a packet that is larger than 3909831SN/A * the DRAM burst size. A system packet that is larger than the burst size 3919831SN/A * is split into multiple DRAM packets and all those DRAM packets point to 3929831SN/A * a single burst helper such that we know when the whole packet is served. 3939831SN/A */ 3949831SN/A class BurstHelper { 3959831SN/A 3969831SN/A public: 3979831SN/A 3989831SN/A /** Number of DRAM bursts requred for a system packet **/ 3999831SN/A const unsigned int burstCount; 4009831SN/A 4019831SN/A /** Number of DRAM bursts serviced so far for a system packet **/ 4029831SN/A unsigned int burstsServiced; 4039831SN/A 4049831SN/A BurstHelper(unsigned int _burstCount) 4059831SN/A : burstCount(_burstCount), burstsServiced(0) 40610618SOmar.Naji@arm.com { } 4079831SN/A }; 4089831SN/A 4099831SN/A /** 4109243SN/A * A DRAM packet stores packets along with the timestamp of when 4119243SN/A * the packet entered the queue, and also the decoded address. 4129243SN/A */ 4139243SN/A class DRAMPacket { 4149243SN/A 4159243SN/A public: 4169243SN/A 4179243SN/A /** When did request enter the controller */ 4189243SN/A const Tick entryTime; 4199243SN/A 4209243SN/A /** When will request leave the controller */ 4219243SN/A Tick readyTime; 4229243SN/A 4239243SN/A /** This comes from the outside world */ 4249243SN/A const PacketPtr pkt; 4259243SN/A 4269966SN/A const bool isRead; 4279966SN/A 4289243SN/A /** Will be populated by address decoder */ 4299243SN/A const uint8_t rank; 4309967SN/A const uint8_t bank; 43110245Sandreas.hansson@arm.com const uint32_t row; 4329831SN/A 4339831SN/A /** 4349967SN/A * Bank id is calculated considering banks in all the ranks 4359967SN/A * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and 4369967SN/A * bankId = 8 --> rank1, bank0 4379967SN/A */ 4389967SN/A const uint16_t bankId; 4399967SN/A 4409967SN/A /** 4419831SN/A * The starting address of the DRAM packet. 4429831SN/A * This address could be unaligned to burst size boundaries. The 4439831SN/A * reason is to keep the address offset so we can accurately check 4449831SN/A * incoming read packets with packets in the write queue. 4459831SN/A */ 4469832SN/A Addr addr; 4479831SN/A 4489831SN/A /** 4499831SN/A * The size of this dram packet in bytes 4509831SN/A * It is always equal or smaller than DRAM burst size 4519831SN/A */ 4529832SN/A unsigned int size; 4539831SN/A 4549831SN/A /** 4559831SN/A * A pointer to the BurstHelper if this DRAMPacket is a split packet 4569831SN/A * If not a split packet (common case), this is set to NULL 4579831SN/A */ 4589831SN/A BurstHelper* burstHelper; 4599967SN/A Bank& bankRef; 46010618SOmar.Naji@arm.com Rank& rankRef; 4619243SN/A 4629967SN/A DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank, 46310245Sandreas.hansson@arm.com uint32_t _row, uint16_t bank_id, Addr _addr, 46410618SOmar.Naji@arm.com unsigned int _size, Bank& bank_ref, Rank& rank_ref) 4659243SN/A : entryTime(curTick()), readyTime(curTick()), 4669967SN/A pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row), 4679967SN/A bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL), 46810618SOmar.Naji@arm.com bankRef(bank_ref), rankRef(rank_ref) 4699243SN/A { } 4709243SN/A 4719243SN/A }; 4729243SN/A 4739243SN/A /** 4749243SN/A * Bunch of things requires to setup "events" in gem5 47510206Sandreas.hansson@arm.com * When event "respondEvent" occurs for example, the method 47610206Sandreas.hansson@arm.com * processRespondEvent is called; no parameters are allowed 4779243SN/A * in these methods 4789243SN/A */ 47910208Sandreas.hansson@arm.com void processNextReqEvent(); 48010208Sandreas.hansson@arm.com EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent; 48110208Sandreas.hansson@arm.com 4829243SN/A void processRespondEvent(); 48310146Sandreas.hansson@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent; 4849243SN/A 4859243SN/A /** 4869243SN/A * Check if the read queue has room for more entries 4879243SN/A * 4889831SN/A * @param pktCount The number of entries needed in the read queue 4899243SN/A * @return true if read queue is full, false otherwise 4909243SN/A */ 4919831SN/A bool readQueueFull(unsigned int pktCount) const; 4929243SN/A 4939243SN/A /** 4949243SN/A * Check if the write queue has room for more entries 4959243SN/A * 4969831SN/A * @param pktCount The number of entries needed in the write queue 4979243SN/A * @return true if write queue is full, false otherwise 4989243SN/A */ 4999831SN/A bool writeQueueFull(unsigned int pktCount) const; 5009243SN/A 5019243SN/A /** 5029243SN/A * When a new read comes in, first check if the write q has a 5039243SN/A * pending request to the same address.\ If not, decode the 5049831SN/A * address to populate rank/bank/row, create one or mutliple 5059831SN/A * "dram_pkt", and push them to the back of the read queue.\ 5069831SN/A * If this is the only 5079243SN/A * read request in the system, schedule an event to start 5089243SN/A * servicing it. 5099243SN/A * 5109243SN/A * @param pkt The request packet from the outside world 5119831SN/A * @param pktCount The number of DRAM bursts the pkt 5129831SN/A * translate to. If pkt size is larger then one full burst, 5139831SN/A * then pktCount is greater than one. 5149243SN/A */ 5159831SN/A void addToReadQueue(PacketPtr pkt, unsigned int pktCount); 5169243SN/A 5179243SN/A /** 5189243SN/A * Decode the incoming pkt, create a dram_pkt and push to the 5199243SN/A * back of the write queue. \If the write q length is more than 5209243SN/A * the threshold specified by the user, ie the queue is beginning 5219243SN/A * to get full, stop reads, and start draining writes. 5229243SN/A * 5239243SN/A * @param pkt The request packet from the outside world 5249831SN/A * @param pktCount The number of DRAM bursts the pkt 5259831SN/A * translate to. If pkt size is larger then one full burst, 5269831SN/A * then pktCount is greater than one. 5279243SN/A */ 5289831SN/A void addToWriteQueue(PacketPtr pkt, unsigned int pktCount); 5299243SN/A 5309243SN/A /** 5319243SN/A * Actually do the DRAM access - figure out the latency it 5329243SN/A * will take to service the req based on bank state, channel state etc 5339243SN/A * and then update those states to account for this request.\ Based 5349243SN/A * on this, update the packet's "readyTime" and move it to the 5359243SN/A * response q from where it will eventually go back to the outside 5369243SN/A * world. 5379243SN/A * 5389243SN/A * @param pkt The DRAM packet created from the outside world pkt 5399243SN/A */ 5409243SN/A void doDRAMAccess(DRAMPacket* dram_pkt); 5419243SN/A 5429243SN/A /** 5439243SN/A * When a packet reaches its "readyTime" in the response Q, 5449243SN/A * use the "access()" method in AbstractMemory to actually 5459243SN/A * create the response packet, and send it back to the outside 5469243SN/A * world requestor. 5479243SN/A * 5489243SN/A * @param pkt The packet from the outside world 5499726SN/A * @param static_latency Static latency to add before sending the packet 5509243SN/A */ 5519726SN/A void accessAndRespond(PacketPtr pkt, Tick static_latency); 5529243SN/A 5539243SN/A /** 5549243SN/A * Address decoder to figure out physical mapping onto ranks, 5559831SN/A * banks, and rows. This function is called multiple times on the same 5569831SN/A * system packet if the pakcet is larger than burst of the memory. The 5579831SN/A * dramPktAddr is used for the offset within the packet. 5589243SN/A * 5599243SN/A * @param pkt The packet from the outside world 5609831SN/A * @param dramPktAddr The starting address of the DRAM packet 5619831SN/A * @param size The size of the DRAM packet in bytes 5629966SN/A * @param isRead Is the request for a read or a write to DRAM 5639243SN/A * @return A DRAMPacket pointer with the decoded information 5649243SN/A */ 56510143SN/A DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size, 56610143SN/A bool isRead); 5679243SN/A 5689243SN/A /** 56910206Sandreas.hansson@arm.com * The memory schduler/arbiter - picks which request needs to 5709567SN/A * go next, based on the specified policy such as FCFS or FR-FCFS 57110206Sandreas.hansson@arm.com * and moves it to the head of the queue. 57210393Swendy.elsasser@arm.com * Prioritizes accesses to the same rank as previous burst unless 57310393Swendy.elsasser@arm.com * controller is switching command type. 57410393Swendy.elsasser@arm.com * 57510393Swendy.elsasser@arm.com * @param queue Queued requests to consider 57610393Swendy.elsasser@arm.com * @param switched_cmd_type Command type is changing 57710618SOmar.Naji@arm.com * @return true if a packet is scheduled to a rank which is available else 57810618SOmar.Naji@arm.com * false 5799243SN/A */ 58010618SOmar.Naji@arm.com bool chooseNext(std::deque<DRAMPacket*>& queue, bool switched_cmd_type); 5819243SN/A 5829243SN/A /** 5839974SN/A * For FR-FCFS policy reorder the read/write queue depending on row buffer 5849974SN/A * hits and earliest banks available in DRAM 58510393Swendy.elsasser@arm.com * Prioritizes accesses to the same rank as previous burst unless 58610393Swendy.elsasser@arm.com * controller is switching command type. 58710393Swendy.elsasser@arm.com * 58810393Swendy.elsasser@arm.com * @param queue Queued requests to consider 58910393Swendy.elsasser@arm.com * @param switched_cmd_type Command type is changing 59010618SOmar.Naji@arm.com * @return true if a packet is scheduled to a rank which is available else 59110618SOmar.Naji@arm.com * false 5929974SN/A */ 59310618SOmar.Naji@arm.com bool reorderQueue(std::deque<DRAMPacket*>& queue, bool switched_cmd_type); 5949974SN/A 5959974SN/A /** 59610211Sandreas.hansson@arm.com * Find which are the earliest banks ready to issue an activate 59710211Sandreas.hansson@arm.com * for the enqueued requests. Assumes maximum of 64 banks per DIMM 59810393Swendy.elsasser@arm.com * Also checks if the bank is already prepped. 5999967SN/A * 60010393Swendy.elsasser@arm.com * @param queue Queued requests to consider 60110393Swendy.elsasser@arm.com * @param switched_cmd_type Command type is changing 6029967SN/A * @return One-hot encoded mask of bank indices 6039967SN/A */ 60410393Swendy.elsasser@arm.com uint64_t minBankPrep(const std::deque<DRAMPacket*>& queue, 60510393Swendy.elsasser@arm.com bool switched_cmd_type) const; 6069488SN/A 6079488SN/A /** 6089488SN/A * Keep track of when row activations happen, in order to enforce 6099488SN/A * the maximum number of activations in the activation window. The 6109488SN/A * method updates the time that the banks become available based 6119488SN/A * on the current limits. 61210210Sandreas.hansson@arm.com * 61310618SOmar.Naji@arm.com * @param rank_ref Reference to the rank 61410618SOmar.Naji@arm.com * @param bank_ref Reference to the bank 61510210Sandreas.hansson@arm.com * @param act_tick Time when the activation takes place 61610210Sandreas.hansson@arm.com * @param row Index of the row 6179488SN/A */ 61810618SOmar.Naji@arm.com void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick, 61910618SOmar.Naji@arm.com uint32_t row); 62010207Sandreas.hansson@arm.com 62110207Sandreas.hansson@arm.com /** 62210207Sandreas.hansson@arm.com * Precharge a given bank and also update when the precharge is 62310207Sandreas.hansson@arm.com * done. This will also deal with any stats related to the 62410207Sandreas.hansson@arm.com * accesses to the open page. 62510207Sandreas.hansson@arm.com * 62610618SOmar.Naji@arm.com * @param rank_ref The rank to precharge 62710247Sandreas.hansson@arm.com * @param bank_ref The bank to precharge 62810211Sandreas.hansson@arm.com * @param pre_at Time when the precharge takes place 62910247Sandreas.hansson@arm.com * @param trace Is this an auto precharge then do not add to trace 63010207Sandreas.hansson@arm.com */ 63110618SOmar.Naji@arm.com void prechargeBank(Rank& rank_ref, Bank& bank_ref, 63210618SOmar.Naji@arm.com Tick pre_at, bool trace = true); 6339488SN/A 63410143SN/A /** 63510143SN/A * Used for debugging to observe the contents of the queues. 63610143SN/A */ 6379243SN/A void printQs() const; 6389243SN/A 6399243SN/A /** 6409243SN/A * The controller's main read and write queues 6419243SN/A */ 6429833SN/A std::deque<DRAMPacket*> readQueue; 6439833SN/A std::deque<DRAMPacket*> writeQueue; 6449243SN/A 6459243SN/A /** 6469243SN/A * Response queue where read packets wait after we're done working 6479567SN/A * with them, but it's not time to send the response yet. The 6489567SN/A * responses are stored seperately mostly to keep the code clean 6499567SN/A * and help with events scheduling. For all logical purposes such 6509567SN/A * as sizing the read queue, this and the main read queue need to 6519567SN/A * be added together. 6529243SN/A */ 6539833SN/A std::deque<DRAMPacket*> respQueue; 6549243SN/A 6559567SN/A /** 6569567SN/A * If we need to drain, keep the drain manager around until we're 6579567SN/A * done here. 6589243SN/A */ 6599342SN/A DrainManager *drainManager; 6609243SN/A 6619243SN/A /** 66210618SOmar.Naji@arm.com * Vector of ranks 6639243SN/A */ 66410618SOmar.Naji@arm.com std::vector<Rank*> ranks; 6659243SN/A 6669243SN/A /** 6679243SN/A * The following are basic design parameters of the memory 6689831SN/A * controller, and are initialized based on parameter values. 6699831SN/A * The rowsPerBank is determined based on the capacity, number of 6709831SN/A * ranks and banks, the burst size, and the row buffer size. 6719243SN/A */ 67210489SOmar.Naji@arm.com const uint32_t deviceSize; 6739831SN/A const uint32_t deviceBusWidth; 6749831SN/A const uint32_t burstLength; 6759831SN/A const uint32_t deviceRowBufferSize; 6769831SN/A const uint32_t devicesPerRank; 6779831SN/A const uint32_t burstSize; 6789831SN/A const uint32_t rowBufferSize; 67910140SN/A const uint32_t columnsPerRowBuffer; 68010286Sandreas.hansson@arm.com const uint32_t columnsPerStripe; 6819243SN/A const uint32_t ranksPerChannel; 68210394Swendy.elsasser@arm.com const uint32_t bankGroupsPerRank; 68310394Swendy.elsasser@arm.com const bool bankGroupArch; 6849243SN/A const uint32_t banksPerRank; 6859566SN/A const uint32_t channels; 6869243SN/A uint32_t rowsPerBank; 6879243SN/A const uint32_t readBufferSize; 6889243SN/A const uint32_t writeBufferSize; 68910140SN/A const uint32_t writeHighThreshold; 69010140SN/A const uint32_t writeLowThreshold; 69110140SN/A const uint32_t minWritesPerSwitch; 69210140SN/A uint32_t writesThisTime; 69310147Sandreas.hansson@arm.com uint32_t readsThisTime; 6949243SN/A 6959243SN/A /** 6969243SN/A * Basic memory timing parameters initialized based on parameter 6979243SN/A * values. 6989243SN/A */ 69910286Sandreas.hansson@arm.com const Tick M5_CLASS_VAR_USED tCK; 7009243SN/A const Tick tWTR; 70110206Sandreas.hansson@arm.com const Tick tRTW; 70210393Swendy.elsasser@arm.com const Tick tCS; 7039243SN/A const Tick tBURST; 70410394Swendy.elsasser@arm.com const Tick tCCD_L; 7059243SN/A const Tick tRCD; 7069243SN/A const Tick tCL; 7079243SN/A const Tick tRP; 7089963SN/A const Tick tRAS; 70910210Sandreas.hansson@arm.com const Tick tWR; 71010212Sandreas.hansson@arm.com const Tick tRTP; 7119243SN/A const Tick tRFC; 7129243SN/A const Tick tREFI; 7139971SN/A const Tick tRRD; 71410394Swendy.elsasser@arm.com const Tick tRRD_L; 7159488SN/A const Tick tXAW; 7169488SN/A const uint32_t activationLimit; 7179243SN/A 7189243SN/A /** 7199243SN/A * Memory controller configuration initialized based on parameter 7209243SN/A * values. 7219243SN/A */ 7229243SN/A Enums::MemSched memSchedPolicy; 7239243SN/A Enums::AddrMap addrMapping; 7249243SN/A Enums::PageManage pageMgmt; 7259243SN/A 7269243SN/A /** 72710141SN/A * Max column accesses (read and write) per row, before forefully 72810141SN/A * closing it. 72910141SN/A */ 73010141SN/A const uint32_t maxAccessesPerRow; 73110141SN/A 73210141SN/A /** 7339726SN/A * Pipeline latency of the controller frontend. The frontend 7349726SN/A * contribution is added to writes (that complete when they are in 7359726SN/A * the write buffer) and reads that are serviced the write buffer. 7369726SN/A */ 7379726SN/A const Tick frontendLatency; 7389726SN/A 7399726SN/A /** 7409726SN/A * Pipeline latency of the backend and PHY. Along with the 7419726SN/A * frontend contribution, this latency is added to reads serviced 7429726SN/A * by the DRAM. 7439726SN/A */ 7449726SN/A const Tick backendLatency; 7459726SN/A 7469726SN/A /** 7479243SN/A * Till when has the main data bus been spoken for already? 7489243SN/A */ 7499243SN/A Tick busBusyUntil; 7509243SN/A 7519243SN/A Tick prevArrival; 7529243SN/A 75310206Sandreas.hansson@arm.com /** 75410206Sandreas.hansson@arm.com * The soonest you have to start thinking about the next request 75510206Sandreas.hansson@arm.com * is the longest access time that can occur before 75610206Sandreas.hansson@arm.com * busBusyUntil. Assuming you need to precharge, open a new row, 75710206Sandreas.hansson@arm.com * and access, it is tRP + tRCD + tCL. 75810206Sandreas.hansson@arm.com */ 75910206Sandreas.hansson@arm.com Tick nextReqTime; 7609972SN/A 7619243SN/A // All statistics that the model needs to capture 7629243SN/A Stats::Scalar readReqs; 7639243SN/A Stats::Scalar writeReqs; 7649831SN/A Stats::Scalar readBursts; 7659831SN/A Stats::Scalar writeBursts; 7669975SN/A Stats::Scalar bytesReadDRAM; 7679975SN/A Stats::Scalar bytesReadWrQ; 7689243SN/A Stats::Scalar bytesWritten; 7699977SN/A Stats::Scalar bytesReadSys; 7709977SN/A Stats::Scalar bytesWrittenSys; 7719243SN/A Stats::Scalar servicedByWrQ; 7729977SN/A Stats::Scalar mergedWrBursts; 7739243SN/A Stats::Scalar neitherReadNorWrite; 7749977SN/A Stats::Vector perBankRdBursts; 7759977SN/A Stats::Vector perBankWrBursts; 7769243SN/A Stats::Scalar numRdRetry; 7779243SN/A Stats::Scalar numWrRetry; 7789243SN/A Stats::Scalar totGap; 7799243SN/A Stats::Vector readPktSize; 7809243SN/A Stats::Vector writePktSize; 7819243SN/A Stats::Vector rdQLenPdf; 7829243SN/A Stats::Vector wrQLenPdf; 7839727SN/A Stats::Histogram bytesPerActivate; 78410147Sandreas.hansson@arm.com Stats::Histogram rdPerTurnAround; 78510147Sandreas.hansson@arm.com Stats::Histogram wrPerTurnAround; 7869243SN/A 7879243SN/A // Latencies summed over all requests 7889243SN/A Stats::Scalar totQLat; 7899243SN/A Stats::Scalar totMemAccLat; 7909243SN/A Stats::Scalar totBusLat; 7919243SN/A 7929243SN/A // Average latencies per request 7939243SN/A Stats::Formula avgQLat; 7949243SN/A Stats::Formula avgBusLat; 7959243SN/A Stats::Formula avgMemAccLat; 7969243SN/A 7979243SN/A // Average bandwidth 7989243SN/A Stats::Formula avgRdBW; 7999243SN/A Stats::Formula avgWrBW; 8009977SN/A Stats::Formula avgRdBWSys; 8019977SN/A Stats::Formula avgWrBWSys; 8029243SN/A Stats::Formula peakBW; 8039243SN/A Stats::Formula busUtil; 8049975SN/A Stats::Formula busUtilRead; 8059975SN/A Stats::Formula busUtilWrite; 8069243SN/A 8079243SN/A // Average queue lengths 8089243SN/A Stats::Average avgRdQLen; 8099243SN/A Stats::Average avgWrQLen; 8109243SN/A 8119243SN/A // Row hit count and rate 8129243SN/A Stats::Scalar readRowHits; 8139243SN/A Stats::Scalar writeRowHits; 8149243SN/A Stats::Formula readRowHitRate; 8159243SN/A Stats::Formula writeRowHitRate; 8169243SN/A Stats::Formula avgGap; 8179243SN/A 8189975SN/A // DRAM Power Calculation 8199975SN/A Stats::Formula pageHitRate; 8209975SN/A 82110393Swendy.elsasser@arm.com // Holds the value of the rank of burst issued 82210393Swendy.elsasser@arm.com uint8_t activeRank; 82310393Swendy.elsasser@arm.com 82410432SOmar.Naji@arm.com // timestamp offset 82510432SOmar.Naji@arm.com uint64_t timeStampOffset; 82610432SOmar.Naji@arm.com 8279349SN/A /** @todo this is a temporary workaround until the 4-phase code is 8289349SN/A * committed. upstream caches needs this packet until true is returned, so 8299349SN/A * hold onto it for deletion until a subsequent call 8309349SN/A */ 8319349SN/A std::vector<PacketPtr> pendingDelete; 8329349SN/A 83310432SOmar.Naji@arm.com /** 83410618SOmar.Naji@arm.com * This function increments the energy when called. If stats are 83510618SOmar.Naji@arm.com * dumped periodically, note accumulated energy values will 83610618SOmar.Naji@arm.com * appear in the stats (even if the stats are reset). This is a 83710618SOmar.Naji@arm.com * result of the energy values coming from DRAMPower, and there 83810618SOmar.Naji@arm.com * is currently no support for resetting the state. 83910618SOmar.Naji@arm.com * 84010618SOmar.Naji@arm.com * @param rank Currrent rank 84110618SOmar.Naji@arm.com */ 84210618SOmar.Naji@arm.com void updatePowerStats(Rank& rank_ref); 84310432SOmar.Naji@arm.com 84410432SOmar.Naji@arm.com /** 84510432SOmar.Naji@arm.com * Function for sorting commands in the command list of DRAMPower. 84610432SOmar.Naji@arm.com * 84710432SOmar.Naji@arm.com * @param a Memory Command in command list of DRAMPower library 84810432SOmar.Naji@arm.com * @param next Memory Command in command list of DRAMPower 84910432SOmar.Naji@arm.com * @return true if timestamp of Command 1 < timestamp of Command 2 85010432SOmar.Naji@arm.com */ 85110432SOmar.Naji@arm.com static bool sortTime(const Data::MemCommand& m1, 85210432SOmar.Naji@arm.com const Data::MemCommand& m2) { 85310432SOmar.Naji@arm.com return m1.getTime() < m2.getTime(); 85410432SOmar.Naji@arm.com }; 85510432SOmar.Naji@arm.com 85610432SOmar.Naji@arm.com 8579243SN/A public: 8589243SN/A 8599243SN/A void regStats(); 8609243SN/A 86110146Sandreas.hansson@arm.com DRAMCtrl(const DRAMCtrlParams* p); 8629243SN/A 8639342SN/A unsigned int drain(DrainManager* dm); 8649243SN/A 8659294SN/A virtual BaseSlavePort& getSlavePort(const std::string& if_name, 8669294SN/A PortID idx = InvalidPortID); 8679243SN/A 86810619Sandreas.hansson@arm.com virtual void init() M5_ATTR_OVERRIDE; 86910619Sandreas.hansson@arm.com virtual void startup() M5_ATTR_OVERRIDE; 87010619Sandreas.hansson@arm.com virtual void drainResume() M5_ATTR_OVERRIDE; 8719243SN/A 8729243SN/A protected: 8739243SN/A 8749243SN/A Tick recvAtomic(PacketPtr pkt); 8759243SN/A void recvFunctional(PacketPtr pkt); 8769243SN/A bool recvTimingReq(PacketPtr pkt); 8779243SN/A 8789243SN/A}; 8799243SN/A 88010146Sandreas.hansson@arm.com#endif //__MEM_DRAM_CTRL_HH__ 881