dram_ctrl.hh revision 10287
19243SN/A/* 210206Sandreas.hansson@arm.com * Copyright (c) 2012-2014 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 439243SN/A */ 449243SN/A 459243SN/A/** 469243SN/A * @file 4710146Sandreas.hansson@arm.com * DRAMCtrl declaration 489243SN/A */ 499243SN/A 5010146Sandreas.hansson@arm.com#ifndef __MEM_DRAM_CTRL_HH__ 5110146Sandreas.hansson@arm.com#define __MEM_DRAM_CTRL_HH__ 529243SN/A 539488SN/A#include <deque> 549488SN/A 559243SN/A#include "base/statistics.hh" 569243SN/A#include "enums/AddrMap.hh" 579243SN/A#include "enums/MemSched.hh" 589243SN/A#include "enums/PageManage.hh" 599243SN/A#include "mem/abstract_mem.hh" 609243SN/A#include "mem/qport.hh" 6110146Sandreas.hansson@arm.com#include "params/DRAMCtrl.hh" 629243SN/A#include "sim/eventq.hh" 639243SN/A 649243SN/A/** 6510287Sandreas.hansson@arm.com * The DRAM controller is a single-channel memory controller capturing 6610287Sandreas.hansson@arm.com * the most important timing constraints associated with a 6710287Sandreas.hansson@arm.com * contemporary DRAM. For multi-channel memory systems, the controller 6810287Sandreas.hansson@arm.com * is combined with a crossbar model, with the channel address 6910287Sandreas.hansson@arm.com * interleaving taking part in the crossbar. 709243SN/A * 7110287Sandreas.hansson@arm.com * As a basic design principle, this controller 7210287Sandreas.hansson@arm.com * model is not cycle callable, but instead uses events to: 1) decide 7310287Sandreas.hansson@arm.com * when new decisions can be made, 2) when resources become available, 7410287Sandreas.hansson@arm.com * 3) when things are to be considered done, and 4) when to send 7510287Sandreas.hansson@arm.com * things back. Through these simple principles, the model delivers 7610287Sandreas.hansson@arm.com * high performance, and lots of flexibility, allowing users to 7710287Sandreas.hansson@arm.com * evaluate the system impact of a wide range of memory technologies, 7810287Sandreas.hansson@arm.com * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC. 7910287Sandreas.hansson@arm.com * 8010287Sandreas.hansson@arm.com * For more details, please see Hansson et al, "Simulating DRAM 8110287Sandreas.hansson@arm.com * controllers for future system architecture exploration", 8210287Sandreas.hansson@arm.com * Proc. ISPASS, 2014. If you use this model as part of your research 8310287Sandreas.hansson@arm.com * please cite the paper. 849243SN/A */ 8510146Sandreas.hansson@arm.comclass DRAMCtrl : public AbstractMemory 869243SN/A{ 879243SN/A 889243SN/A private: 899243SN/A 909243SN/A // For now, make use of a queued slave port to avoid dealing with 919243SN/A // flow control for the responses being sent back 929243SN/A class MemoryPort : public QueuedSlavePort 939243SN/A { 949243SN/A 959243SN/A SlavePacketQueue queue; 9610146Sandreas.hansson@arm.com DRAMCtrl& memory; 979243SN/A 989243SN/A public: 999243SN/A 10010146Sandreas.hansson@arm.com MemoryPort(const std::string& name, DRAMCtrl& _memory); 1019243SN/A 1029243SN/A protected: 1039243SN/A 1049243SN/A Tick recvAtomic(PacketPtr pkt); 1059243SN/A 1069243SN/A void recvFunctional(PacketPtr pkt); 1079243SN/A 1089243SN/A bool recvTimingReq(PacketPtr); 1099243SN/A 1109243SN/A virtual AddrRangeList getAddrRanges() const; 1119243SN/A 1129243SN/A }; 1139243SN/A 1149243SN/A /** 1159243SN/A * Our incoming port, for a multi-ported controller add a crossbar 1169243SN/A * in front of it 1179243SN/A */ 1189243SN/A MemoryPort port; 1199243SN/A 1209243SN/A /** 1219243SN/A * Remember if we have to retry a request when available. 1229243SN/A */ 1239243SN/A bool retryRdReq; 1249243SN/A bool retryWrReq; 1259243SN/A 1269243SN/A /** 12710206Sandreas.hansson@arm.com * Bus state used to control the read/write switching and drive 12810206Sandreas.hansson@arm.com * the scheduling of the next request. 1299243SN/A */ 13010206Sandreas.hansson@arm.com enum BusState { 13110206Sandreas.hansson@arm.com READ = 0, 13210206Sandreas.hansson@arm.com READ_TO_WRITE, 13310206Sandreas.hansson@arm.com WRITE, 13410206Sandreas.hansson@arm.com WRITE_TO_READ 13510206Sandreas.hansson@arm.com }; 13610206Sandreas.hansson@arm.com 13710206Sandreas.hansson@arm.com BusState busState; 1389243SN/A 1399488SN/A /** List to keep track of activate ticks */ 1409969SN/A std::vector<std::deque<Tick>> actTicks; 1419488SN/A 1429243SN/A /** 14310210Sandreas.hansson@arm.com * A basic class to track the bank state, i.e. what row is 14410210Sandreas.hansson@arm.com * currently open (if any), when is the bank free to accept a new 14510211Sandreas.hansson@arm.com * column (read/write) command, when can it be precharged, and 14610211Sandreas.hansson@arm.com * when can it be activated. 14710210Sandreas.hansson@arm.com * 14810210Sandreas.hansson@arm.com * The bank also keeps track of how many bytes have been accessed 14910210Sandreas.hansson@arm.com * in the open row since it was opened. 1509243SN/A */ 1519243SN/A class Bank 1529243SN/A { 1539243SN/A 1549243SN/A public: 1559243SN/A 15610207Sandreas.hansson@arm.com static const uint32_t NO_ROW = -1; 1579243SN/A 1589243SN/A uint32_t openRow; 15910246Sandreas.hansson@arm.com uint8_t rank; 16010246Sandreas.hansson@arm.com uint8_t bank; 1619243SN/A 16210211Sandreas.hansson@arm.com Tick colAllowedAt; 16310210Sandreas.hansson@arm.com Tick preAllowedAt; 1649969SN/A Tick actAllowedAt; 1659243SN/A 16610141SN/A uint32_t rowAccesses; 1679727SN/A uint32_t bytesAccessed; 1689727SN/A 1699727SN/A Bank() : 17010246Sandreas.hansson@arm.com openRow(NO_ROW), rank(0), bank(0), 17110246Sandreas.hansson@arm.com colAllowedAt(0), preAllowedAt(0), actAllowedAt(0), 17210141SN/A rowAccesses(0), bytesAccessed(0) 1739243SN/A { } 1749243SN/A }; 1759243SN/A 1769243SN/A /** 1779831SN/A * A burst helper helps organize and manage a packet that is larger than 1789831SN/A * the DRAM burst size. A system packet that is larger than the burst size 1799831SN/A * is split into multiple DRAM packets and all those DRAM packets point to 1809831SN/A * a single burst helper such that we know when the whole packet is served. 1819831SN/A */ 1829831SN/A class BurstHelper { 1839831SN/A 1849831SN/A public: 1859831SN/A 1869831SN/A /** Number of DRAM bursts requred for a system packet **/ 1879831SN/A const unsigned int burstCount; 1889831SN/A 1899831SN/A /** Number of DRAM bursts serviced so far for a system packet **/ 1909831SN/A unsigned int burstsServiced; 1919831SN/A 1929831SN/A BurstHelper(unsigned int _burstCount) 1939831SN/A : burstCount(_burstCount), burstsServiced(0) 1949831SN/A { } 1959831SN/A }; 1969831SN/A 1979831SN/A /** 1989243SN/A * A DRAM packet stores packets along with the timestamp of when 1999243SN/A * the packet entered the queue, and also the decoded address. 2009243SN/A */ 2019243SN/A class DRAMPacket { 2029243SN/A 2039243SN/A public: 2049243SN/A 2059243SN/A /** When did request enter the controller */ 2069243SN/A const Tick entryTime; 2079243SN/A 2089243SN/A /** When will request leave the controller */ 2099243SN/A Tick readyTime; 2109243SN/A 2119243SN/A /** This comes from the outside world */ 2129243SN/A const PacketPtr pkt; 2139243SN/A 2149966SN/A const bool isRead; 2159966SN/A 2169243SN/A /** Will be populated by address decoder */ 2179243SN/A const uint8_t rank; 2189967SN/A const uint8_t bank; 21910245Sandreas.hansson@arm.com const uint32_t row; 2209831SN/A 2219831SN/A /** 2229967SN/A * Bank id is calculated considering banks in all the ranks 2239967SN/A * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and 2249967SN/A * bankId = 8 --> rank1, bank0 2259967SN/A */ 2269967SN/A const uint16_t bankId; 2279967SN/A 2289967SN/A /** 2299831SN/A * The starting address of the DRAM packet. 2309831SN/A * This address could be unaligned to burst size boundaries. The 2319831SN/A * reason is to keep the address offset so we can accurately check 2329831SN/A * incoming read packets with packets in the write queue. 2339831SN/A */ 2349832SN/A Addr addr; 2359831SN/A 2369831SN/A /** 2379831SN/A * The size of this dram packet in bytes 2389831SN/A * It is always equal or smaller than DRAM burst size 2399831SN/A */ 2409832SN/A unsigned int size; 2419831SN/A 2429831SN/A /** 2439831SN/A * A pointer to the BurstHelper if this DRAMPacket is a split packet 2449831SN/A * If not a split packet (common case), this is set to NULL 2459831SN/A */ 2469831SN/A BurstHelper* burstHelper; 2479967SN/A Bank& bankRef; 2489243SN/A 2499967SN/A DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank, 25010245Sandreas.hansson@arm.com uint32_t _row, uint16_t bank_id, Addr _addr, 2519967SN/A unsigned int _size, Bank& bank_ref) 2529243SN/A : entryTime(curTick()), readyTime(curTick()), 2539967SN/A pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row), 2549967SN/A bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL), 2559967SN/A bankRef(bank_ref) 2569243SN/A { } 2579243SN/A 2589243SN/A }; 2599243SN/A 2609243SN/A /** 2619243SN/A * Bunch of things requires to setup "events" in gem5 26210206Sandreas.hansson@arm.com * When event "respondEvent" occurs for example, the method 26310206Sandreas.hansson@arm.com * processRespondEvent is called; no parameters are allowed 2649243SN/A * in these methods 2659243SN/A */ 26610208Sandreas.hansson@arm.com void processNextReqEvent(); 26710208Sandreas.hansson@arm.com EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent; 26810208Sandreas.hansson@arm.com 2699243SN/A void processRespondEvent(); 27010146Sandreas.hansson@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent; 2719243SN/A 27210208Sandreas.hansson@arm.com void processActivateEvent(); 27310208Sandreas.hansson@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processActivateEvent> activateEvent; 27410208Sandreas.hansson@arm.com 27510208Sandreas.hansson@arm.com void processPrechargeEvent(); 27610208Sandreas.hansson@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processPrechargeEvent> prechargeEvent; 27710208Sandreas.hansson@arm.com 2789243SN/A void processRefreshEvent(); 27910146Sandreas.hansson@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processRefreshEvent> refreshEvent; 2809243SN/A 28110208Sandreas.hansson@arm.com void processPowerEvent(); 28210208Sandreas.hansson@arm.com EventWrapper<DRAMCtrl,&DRAMCtrl::processPowerEvent> powerEvent; 2839243SN/A 2849243SN/A /** 2859243SN/A * Check if the read queue has room for more entries 2869243SN/A * 2879831SN/A * @param pktCount The number of entries needed in the read queue 2889243SN/A * @return true if read queue is full, false otherwise 2899243SN/A */ 2909831SN/A bool readQueueFull(unsigned int pktCount) const; 2919243SN/A 2929243SN/A /** 2939243SN/A * Check if the write queue has room for more entries 2949243SN/A * 2959831SN/A * @param pktCount The number of entries needed in the write queue 2969243SN/A * @return true if write queue is full, false otherwise 2979243SN/A */ 2989831SN/A bool writeQueueFull(unsigned int pktCount) const; 2999243SN/A 3009243SN/A /** 3019243SN/A * When a new read comes in, first check if the write q has a 3029243SN/A * pending request to the same address.\ If not, decode the 3039831SN/A * address to populate rank/bank/row, create one or mutliple 3049831SN/A * "dram_pkt", and push them to the back of the read queue.\ 3059831SN/A * If this is the only 3069243SN/A * read request in the system, schedule an event to start 3079243SN/A * servicing it. 3089243SN/A * 3099243SN/A * @param pkt The request packet from the outside world 3109831SN/A * @param pktCount The number of DRAM bursts the pkt 3119831SN/A * translate to. If pkt size is larger then one full burst, 3129831SN/A * then pktCount is greater than one. 3139243SN/A */ 3149831SN/A void addToReadQueue(PacketPtr pkt, unsigned int pktCount); 3159243SN/A 3169243SN/A /** 3179243SN/A * Decode the incoming pkt, create a dram_pkt and push to the 3189243SN/A * back of the write queue. \If the write q length is more than 3199243SN/A * the threshold specified by the user, ie the queue is beginning 3209243SN/A * to get full, stop reads, and start draining writes. 3219243SN/A * 3229243SN/A * @param pkt The request packet from the outside world 3239831SN/A * @param pktCount The number of DRAM bursts the pkt 3249831SN/A * translate to. If pkt size is larger then one full burst, 3259831SN/A * then pktCount is greater than one. 3269243SN/A */ 3279831SN/A void addToWriteQueue(PacketPtr pkt, unsigned int pktCount); 3289243SN/A 3299243SN/A /** 3309243SN/A * Actually do the DRAM access - figure out the latency it 3319243SN/A * will take to service the req based on bank state, channel state etc 3329243SN/A * and then update those states to account for this request.\ Based 3339243SN/A * on this, update the packet's "readyTime" and move it to the 3349243SN/A * response q from where it will eventually go back to the outside 3359243SN/A * world. 3369243SN/A * 3379243SN/A * @param pkt The DRAM packet created from the outside world pkt 3389243SN/A */ 3399243SN/A void doDRAMAccess(DRAMPacket* dram_pkt); 3409243SN/A 3419243SN/A /** 3429243SN/A * When a packet reaches its "readyTime" in the response Q, 3439243SN/A * use the "access()" method in AbstractMemory to actually 3449243SN/A * create the response packet, and send it back to the outside 3459243SN/A * world requestor. 3469243SN/A * 3479243SN/A * @param pkt The packet from the outside world 3489726SN/A * @param static_latency Static latency to add before sending the packet 3499243SN/A */ 3509726SN/A void accessAndRespond(PacketPtr pkt, Tick static_latency); 3519243SN/A 3529243SN/A /** 3539243SN/A * Address decoder to figure out physical mapping onto ranks, 3549831SN/A * banks, and rows. This function is called multiple times on the same 3559831SN/A * system packet if the pakcet is larger than burst of the memory. The 3569831SN/A * dramPktAddr is used for the offset within the packet. 3579243SN/A * 3589243SN/A * @param pkt The packet from the outside world 3599831SN/A * @param dramPktAddr The starting address of the DRAM packet 3609831SN/A * @param size The size of the DRAM packet in bytes 3619966SN/A * @param isRead Is the request for a read or a write to DRAM 3629243SN/A * @return A DRAMPacket pointer with the decoded information 3639243SN/A */ 36410143SN/A DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size, 36510143SN/A bool isRead); 3669243SN/A 3679243SN/A /** 36810206Sandreas.hansson@arm.com * The memory schduler/arbiter - picks which request needs to 3699567SN/A * go next, based on the specified policy such as FCFS or FR-FCFS 37010206Sandreas.hansson@arm.com * and moves it to the head of the queue. 3719243SN/A */ 37210206Sandreas.hansson@arm.com void chooseNext(std::deque<DRAMPacket*>& queue); 3739243SN/A 3749243SN/A /** 3759974SN/A * For FR-FCFS policy reorder the read/write queue depending on row buffer 3769974SN/A * hits and earliest banks available in DRAM 3779974SN/A */ 3789974SN/A void reorderQueue(std::deque<DRAMPacket*>& queue); 3799974SN/A 3809974SN/A /** 38110211Sandreas.hansson@arm.com * Find which are the earliest banks ready to issue an activate 38210211Sandreas.hansson@arm.com * for the enqueued requests. Assumes maximum of 64 banks per DIMM 3839967SN/A * 3849967SN/A * @param Queued requests to consider 3859967SN/A * @return One-hot encoded mask of bank indices 3869967SN/A */ 38710211Sandreas.hansson@arm.com uint64_t minBankActAt(const std::deque<DRAMPacket*>& queue) const; 3889488SN/A 3899488SN/A /** 3909488SN/A * Keep track of when row activations happen, in order to enforce 3919488SN/A * the maximum number of activations in the activation window. The 3929488SN/A * method updates the time that the banks become available based 3939488SN/A * on the current limits. 39410210Sandreas.hansson@arm.com * 39510246Sandreas.hansson@arm.com * @param bank Reference to the bank 39610210Sandreas.hansson@arm.com * @param act_tick Time when the activation takes place 39710210Sandreas.hansson@arm.com * @param row Index of the row 3989488SN/A */ 39910246Sandreas.hansson@arm.com void activateBank(Bank& bank, Tick act_tick, uint32_t row); 40010207Sandreas.hansson@arm.com 40110207Sandreas.hansson@arm.com /** 40210207Sandreas.hansson@arm.com * Precharge a given bank and also update when the precharge is 40310207Sandreas.hansson@arm.com * done. This will also deal with any stats related to the 40410207Sandreas.hansson@arm.com * accesses to the open page. 40510207Sandreas.hansson@arm.com * 40610247Sandreas.hansson@arm.com * @param bank_ref The bank to precharge 40710211Sandreas.hansson@arm.com * @param pre_at Time when the precharge takes place 40810247Sandreas.hansson@arm.com * @param trace Is this an auto precharge then do not add to trace 40910207Sandreas.hansson@arm.com */ 41010247Sandreas.hansson@arm.com void prechargeBank(Bank& bank_ref, Tick pre_at, bool trace = true); 4119488SN/A 41210143SN/A /** 41310143SN/A * Used for debugging to observe the contents of the queues. 41410143SN/A */ 4159243SN/A void printQs() const; 4169243SN/A 4179243SN/A /** 4189243SN/A * The controller's main read and write queues 4199243SN/A */ 4209833SN/A std::deque<DRAMPacket*> readQueue; 4219833SN/A std::deque<DRAMPacket*> writeQueue; 4229243SN/A 4239243SN/A /** 4249243SN/A * Response queue where read packets wait after we're done working 4259567SN/A * with them, but it's not time to send the response yet. The 4269567SN/A * responses are stored seperately mostly to keep the code clean 4279567SN/A * and help with events scheduling. For all logical purposes such 4289567SN/A * as sizing the read queue, this and the main read queue need to 4299567SN/A * be added together. 4309243SN/A */ 4319833SN/A std::deque<DRAMPacket*> respQueue; 4329243SN/A 4339567SN/A /** 4349567SN/A * If we need to drain, keep the drain manager around until we're 4359567SN/A * done here. 4369243SN/A */ 4379342SN/A DrainManager *drainManager; 4389243SN/A 4399243SN/A /** 4409243SN/A * Multi-dimensional vector of banks, first dimension is ranks, 4419243SN/A * second is bank 4429243SN/A */ 4439243SN/A std::vector<std::vector<Bank> > banks; 4449243SN/A 4459243SN/A /** 4469243SN/A * The following are basic design parameters of the memory 4479831SN/A * controller, and are initialized based on parameter values. 4489831SN/A * The rowsPerBank is determined based on the capacity, number of 4499831SN/A * ranks and banks, the burst size, and the row buffer size. 4509243SN/A */ 4519831SN/A const uint32_t deviceBusWidth; 4529831SN/A const uint32_t burstLength; 4539831SN/A const uint32_t deviceRowBufferSize; 4549831SN/A const uint32_t devicesPerRank; 4559831SN/A const uint32_t burstSize; 4569831SN/A const uint32_t rowBufferSize; 45710140SN/A const uint32_t columnsPerRowBuffer; 45810286Sandreas.hansson@arm.com const uint32_t columnsPerStripe; 4599243SN/A const uint32_t ranksPerChannel; 4609243SN/A const uint32_t banksPerRank; 4619566SN/A const uint32_t channels; 4629243SN/A uint32_t rowsPerBank; 4639243SN/A const uint32_t readBufferSize; 4649243SN/A const uint32_t writeBufferSize; 46510140SN/A const uint32_t writeHighThreshold; 46610140SN/A const uint32_t writeLowThreshold; 46710140SN/A const uint32_t minWritesPerSwitch; 46810140SN/A uint32_t writesThisTime; 46910147Sandreas.hansson@arm.com uint32_t readsThisTime; 4709243SN/A 4719243SN/A /** 4729243SN/A * Basic memory timing parameters initialized based on parameter 4739243SN/A * values. 4749243SN/A */ 47510286Sandreas.hansson@arm.com const Tick M5_CLASS_VAR_USED tCK; 4769243SN/A const Tick tWTR; 47710206Sandreas.hansson@arm.com const Tick tRTW; 4789243SN/A const Tick tBURST; 4799243SN/A const Tick tRCD; 4809243SN/A const Tick tCL; 4819243SN/A const Tick tRP; 4829963SN/A const Tick tRAS; 48310210Sandreas.hansson@arm.com const Tick tWR; 48410212Sandreas.hansson@arm.com const Tick tRTP; 4859243SN/A const Tick tRFC; 4869243SN/A const Tick tREFI; 4879971SN/A const Tick tRRD; 4889488SN/A const Tick tXAW; 4899488SN/A const uint32_t activationLimit; 4909243SN/A 4919243SN/A /** 4929243SN/A * Memory controller configuration initialized based on parameter 4939243SN/A * values. 4949243SN/A */ 4959243SN/A Enums::MemSched memSchedPolicy; 4969243SN/A Enums::AddrMap addrMapping; 4979243SN/A Enums::PageManage pageMgmt; 4989243SN/A 4999243SN/A /** 50010141SN/A * Max column accesses (read and write) per row, before forefully 50110141SN/A * closing it. 50210141SN/A */ 50310141SN/A const uint32_t maxAccessesPerRow; 50410141SN/A 50510141SN/A /** 5069726SN/A * Pipeline latency of the controller frontend. The frontend 5079726SN/A * contribution is added to writes (that complete when they are in 5089726SN/A * the write buffer) and reads that are serviced the write buffer. 5099726SN/A */ 5109726SN/A const Tick frontendLatency; 5119726SN/A 5129726SN/A /** 5139726SN/A * Pipeline latency of the backend and PHY. Along with the 5149726SN/A * frontend contribution, this latency is added to reads serviced 5159726SN/A * by the DRAM. 5169726SN/A */ 5179726SN/A const Tick backendLatency; 5189726SN/A 5199726SN/A /** 5209243SN/A * Till when has the main data bus been spoken for already? 5219243SN/A */ 5229243SN/A Tick busBusyUntil; 5239243SN/A 52410207Sandreas.hansson@arm.com /** 52510207Sandreas.hansson@arm.com * Keep track of when a refresh is due. 52610207Sandreas.hansson@arm.com */ 52710207Sandreas.hansson@arm.com Tick refreshDueAt; 52810207Sandreas.hansson@arm.com 52910207Sandreas.hansson@arm.com /** 53010207Sandreas.hansson@arm.com * The refresh state is used to control the progress of the 53110207Sandreas.hansson@arm.com * refresh scheduling. When normal operation is in progress the 53210207Sandreas.hansson@arm.com * refresh state is idle. From there, it progresses to the refresh 53310207Sandreas.hansson@arm.com * drain state once tREFI has passed. The refresh drain state 53410207Sandreas.hansson@arm.com * captures the DRAM row active state, as it will stay there until 53510207Sandreas.hansson@arm.com * all ongoing accesses complete. Thereafter all banks are 53610207Sandreas.hansson@arm.com * precharged, and lastly, the DRAM is refreshed. 53710207Sandreas.hansson@arm.com */ 53810207Sandreas.hansson@arm.com enum RefreshState { 53910207Sandreas.hansson@arm.com REF_IDLE = 0, 54010207Sandreas.hansson@arm.com REF_DRAIN, 54110207Sandreas.hansson@arm.com REF_PRE, 54210207Sandreas.hansson@arm.com REF_RUN 54310207Sandreas.hansson@arm.com }; 54410207Sandreas.hansson@arm.com 54510207Sandreas.hansson@arm.com RefreshState refreshState; 54610207Sandreas.hansson@arm.com 54710208Sandreas.hansson@arm.com /** 54810208Sandreas.hansson@arm.com * The power state captures the different operational states of 54910208Sandreas.hansson@arm.com * the DRAM and interacts with the bus read/write state machine, 55010208Sandreas.hansson@arm.com * and the refresh state machine. In the idle state all banks are 55110208Sandreas.hansson@arm.com * precharged. From there we either go to an auto refresh (as 55210208Sandreas.hansson@arm.com * determined by the refresh state machine), or to a precharge 55310208Sandreas.hansson@arm.com * power down mode. From idle the memory can also go to the active 55410208Sandreas.hansson@arm.com * state (with one or more banks active), and in turn from there 55510208Sandreas.hansson@arm.com * to active power down. At the moment we do not capture the deep 55610208Sandreas.hansson@arm.com * power down and self-refresh state. 55710208Sandreas.hansson@arm.com */ 55810208Sandreas.hansson@arm.com enum PowerState { 55910208Sandreas.hansson@arm.com PWR_IDLE = 0, 56010208Sandreas.hansson@arm.com PWR_REF, 56110208Sandreas.hansson@arm.com PWR_PRE_PDN, 56210208Sandreas.hansson@arm.com PWR_ACT, 56310208Sandreas.hansson@arm.com PWR_ACT_PDN 56410208Sandreas.hansson@arm.com }; 56510208Sandreas.hansson@arm.com 56610208Sandreas.hansson@arm.com /** 56710208Sandreas.hansson@arm.com * Since we are taking decisions out of order, we need to keep 56810208Sandreas.hansson@arm.com * track of what power transition is happening at what time, such 56910208Sandreas.hansson@arm.com * that we can go back in time and change history. For example, if 57010208Sandreas.hansson@arm.com * we precharge all banks and schedule going to the idle state, we 57110208Sandreas.hansson@arm.com * might at a later point decide to activate a bank before the 57210208Sandreas.hansson@arm.com * transition to idle would have taken place. 57310208Sandreas.hansson@arm.com */ 57410208Sandreas.hansson@arm.com PowerState pwrStateTrans; 57510208Sandreas.hansson@arm.com 57610208Sandreas.hansson@arm.com /** 57710208Sandreas.hansson@arm.com * Current power state. 57810208Sandreas.hansson@arm.com */ 57910208Sandreas.hansson@arm.com PowerState pwrState; 58010208Sandreas.hansson@arm.com 58110208Sandreas.hansson@arm.com /** 58210208Sandreas.hansson@arm.com * Schedule a power state transition in the future, and 58310208Sandreas.hansson@arm.com * potentially override an already scheduled transition. 58410208Sandreas.hansson@arm.com * 58510208Sandreas.hansson@arm.com * @param pwr_state Power state to transition to 58610208Sandreas.hansson@arm.com * @param tick Tick when transition should take place 58710208Sandreas.hansson@arm.com */ 58810208Sandreas.hansson@arm.com void schedulePowerEvent(PowerState pwr_state, Tick tick); 58910208Sandreas.hansson@arm.com 5909243SN/A Tick prevArrival; 5919243SN/A 59210206Sandreas.hansson@arm.com /** 59310206Sandreas.hansson@arm.com * The soonest you have to start thinking about the next request 59410206Sandreas.hansson@arm.com * is the longest access time that can occur before 59510206Sandreas.hansson@arm.com * busBusyUntil. Assuming you need to precharge, open a new row, 59610206Sandreas.hansson@arm.com * and access, it is tRP + tRCD + tCL. 59710206Sandreas.hansson@arm.com */ 59810206Sandreas.hansson@arm.com Tick nextReqTime; 5999972SN/A 6009243SN/A // All statistics that the model needs to capture 6019243SN/A Stats::Scalar readReqs; 6029243SN/A Stats::Scalar writeReqs; 6039831SN/A Stats::Scalar readBursts; 6049831SN/A Stats::Scalar writeBursts; 6059975SN/A Stats::Scalar bytesReadDRAM; 6069975SN/A Stats::Scalar bytesReadWrQ; 6079243SN/A Stats::Scalar bytesWritten; 6089977SN/A Stats::Scalar bytesReadSys; 6099977SN/A Stats::Scalar bytesWrittenSys; 6109243SN/A Stats::Scalar servicedByWrQ; 6119977SN/A Stats::Scalar mergedWrBursts; 6129243SN/A Stats::Scalar neitherReadNorWrite; 6139977SN/A Stats::Vector perBankRdBursts; 6149977SN/A Stats::Vector perBankWrBursts; 6159243SN/A Stats::Scalar numRdRetry; 6169243SN/A Stats::Scalar numWrRetry; 6179243SN/A Stats::Scalar totGap; 6189243SN/A Stats::Vector readPktSize; 6199243SN/A Stats::Vector writePktSize; 6209243SN/A Stats::Vector rdQLenPdf; 6219243SN/A Stats::Vector wrQLenPdf; 6229727SN/A Stats::Histogram bytesPerActivate; 62310147Sandreas.hansson@arm.com Stats::Histogram rdPerTurnAround; 62410147Sandreas.hansson@arm.com Stats::Histogram wrPerTurnAround; 6259243SN/A 6269243SN/A // Latencies summed over all requests 6279243SN/A Stats::Scalar totQLat; 6289243SN/A Stats::Scalar totMemAccLat; 6299243SN/A Stats::Scalar totBusLat; 6309243SN/A 6319243SN/A // Average latencies per request 6329243SN/A Stats::Formula avgQLat; 6339243SN/A Stats::Formula avgBusLat; 6349243SN/A Stats::Formula avgMemAccLat; 6359243SN/A 6369243SN/A // Average bandwidth 6379243SN/A Stats::Formula avgRdBW; 6389243SN/A Stats::Formula avgWrBW; 6399977SN/A Stats::Formula avgRdBWSys; 6409977SN/A Stats::Formula avgWrBWSys; 6419243SN/A Stats::Formula peakBW; 6429243SN/A Stats::Formula busUtil; 6439975SN/A Stats::Formula busUtilRead; 6449975SN/A Stats::Formula busUtilWrite; 6459243SN/A 6469243SN/A // Average queue lengths 6479243SN/A Stats::Average avgRdQLen; 6489243SN/A Stats::Average avgWrQLen; 6499243SN/A 6509243SN/A // Row hit count and rate 6519243SN/A Stats::Scalar readRowHits; 6529243SN/A Stats::Scalar writeRowHits; 6539243SN/A Stats::Formula readRowHitRate; 6549243SN/A Stats::Formula writeRowHitRate; 6559243SN/A Stats::Formula avgGap; 6569243SN/A 6579975SN/A // DRAM Power Calculation 6589975SN/A Stats::Formula pageHitRate; 65910208Sandreas.hansson@arm.com Stats::Vector pwrStateTime; 6609975SN/A 66110208Sandreas.hansson@arm.com // Track when we transitioned to the current power state 66210208Sandreas.hansson@arm.com Tick pwrStateTick; 66310207Sandreas.hansson@arm.com 6649975SN/A // To track number of banks which are currently active 6659975SN/A unsigned int numBanksActive; 6669975SN/A 6679349SN/A /** @todo this is a temporary workaround until the 4-phase code is 6689349SN/A * committed. upstream caches needs this packet until true is returned, so 6699349SN/A * hold onto it for deletion until a subsequent call 6709349SN/A */ 6719349SN/A std::vector<PacketPtr> pendingDelete; 6729349SN/A 6739243SN/A public: 6749243SN/A 6759243SN/A void regStats(); 6769243SN/A 67710146Sandreas.hansson@arm.com DRAMCtrl(const DRAMCtrlParams* p); 6789243SN/A 6799342SN/A unsigned int drain(DrainManager* dm); 6809243SN/A 6819294SN/A virtual BaseSlavePort& getSlavePort(const std::string& if_name, 6829294SN/A PortID idx = InvalidPortID); 6839243SN/A 6849243SN/A virtual void init(); 6859243SN/A virtual void startup(); 6869243SN/A 6879243SN/A protected: 6889243SN/A 6899243SN/A Tick recvAtomic(PacketPtr pkt); 6909243SN/A void recvFunctional(PacketPtr pkt); 6919243SN/A bool recvTimingReq(PacketPtr pkt); 6929243SN/A 6939243SN/A}; 6949243SN/A 69510146Sandreas.hansson@arm.com#endif //__MEM_DRAM_CTRL_HH__ 696