dram_ctrl.hh revision 10207
19243SN/A/* 210206Sandreas.hansson@arm.com * Copyright (c) 2012-2014 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 439243SN/A */ 449243SN/A 459243SN/A/** 469243SN/A * @file 4710146Sandreas.hansson@arm.com * DRAMCtrl declaration 489243SN/A */ 499243SN/A 5010146Sandreas.hansson@arm.com#ifndef __MEM_DRAM_CTRL_HH__ 5110146Sandreas.hansson@arm.com#define __MEM_DRAM_CTRL_HH__ 529243SN/A 539488SN/A#include <deque> 549488SN/A 559243SN/A#include "base/statistics.hh" 569243SN/A#include "enums/AddrMap.hh" 579243SN/A#include "enums/MemSched.hh" 589243SN/A#include "enums/PageManage.hh" 599243SN/A#include "mem/abstract_mem.hh" 609243SN/A#include "mem/qport.hh" 6110146Sandreas.hansson@arm.com#include "params/DRAMCtrl.hh" 629243SN/A#include "sim/eventq.hh" 639243SN/A 649243SN/A/** 6510146Sandreas.hansson@arm.com * The DRAM controller is a basic single-channel memory controller 6610146Sandreas.hansson@arm.com * aiming to mimic a high-level DRAM controller and the most important 6710146Sandreas.hansson@arm.com * timing constraints associated with the DRAM. The focus is really on 689243SN/A * modelling the impact on the system rather than the DRAM itself, 699243SN/A * hence the focus is on the controller model and not on the 709243SN/A * memory. By adhering to the correct timing constraints, ultimately 719243SN/A * there is no need for a memory model in addition to the controller 729243SN/A * model. 739243SN/A * 749243SN/A * As a basic design principle, this controller is not cycle callable, 759243SN/A * but instead uses events to decide when new decisions can be made, 769243SN/A * when resources become available, when things are to be considered 779243SN/A * done, and when to send things back. Through these simple 789243SN/A * principles, we achieve a performant model that is not 799243SN/A * cycle-accurate, but enables us to evaluate the system impact of a 809243SN/A * wide range of memory technologies, and also collect statistics 819243SN/A * about the use of the memory. 829243SN/A */ 8310146Sandreas.hansson@arm.comclass DRAMCtrl : public AbstractMemory 849243SN/A{ 859243SN/A 869243SN/A private: 879243SN/A 889243SN/A // For now, make use of a queued slave port to avoid dealing with 899243SN/A // flow control for the responses being sent back 909243SN/A class MemoryPort : public QueuedSlavePort 919243SN/A { 929243SN/A 939243SN/A SlavePacketQueue queue; 9410146Sandreas.hansson@arm.com DRAMCtrl& memory; 959243SN/A 969243SN/A public: 979243SN/A 9810146Sandreas.hansson@arm.com MemoryPort(const std::string& name, DRAMCtrl& _memory); 999243SN/A 1009243SN/A protected: 1019243SN/A 1029243SN/A Tick recvAtomic(PacketPtr pkt); 1039243SN/A 1049243SN/A void recvFunctional(PacketPtr pkt); 1059243SN/A 1069243SN/A bool recvTimingReq(PacketPtr); 1079243SN/A 1089243SN/A virtual AddrRangeList getAddrRanges() const; 1099243SN/A 1109243SN/A }; 1119243SN/A 1129243SN/A /** 1139243SN/A * Our incoming port, for a multi-ported controller add a crossbar 1149243SN/A * in front of it 1159243SN/A */ 1169243SN/A MemoryPort port; 1179243SN/A 1189243SN/A /** 1199243SN/A * Remember if we have to retry a request when available. 1209243SN/A */ 1219243SN/A bool retryRdReq; 1229243SN/A bool retryWrReq; 1239243SN/A 1249243SN/A /** 1259243SN/A * Remember that a row buffer hit occured 1269243SN/A */ 1279243SN/A bool rowHitFlag; 1289243SN/A 1299243SN/A /** 13010206Sandreas.hansson@arm.com * Bus state used to control the read/write switching and drive 13110206Sandreas.hansson@arm.com * the scheduling of the next request. 1329243SN/A */ 13310206Sandreas.hansson@arm.com enum BusState { 13410206Sandreas.hansson@arm.com READ = 0, 13510206Sandreas.hansson@arm.com READ_TO_WRITE, 13610206Sandreas.hansson@arm.com WRITE, 13710206Sandreas.hansson@arm.com WRITE_TO_READ 13810206Sandreas.hansson@arm.com }; 13910206Sandreas.hansson@arm.com 14010206Sandreas.hansson@arm.com BusState busState; 1419243SN/A 1429488SN/A /** List to keep track of activate ticks */ 1439969SN/A std::vector<std::deque<Tick>> actTicks; 1449488SN/A 1459243SN/A /** 1469727SN/A * A basic class to track the bank state indirectly via times 1479727SN/A * "freeAt" and "tRASDoneAt" and what page is currently open. The 1489727SN/A * bank also keeps track of how many bytes have been accessed in 1499727SN/A * the open row since it was opened. 1509243SN/A */ 1519243SN/A class Bank 1529243SN/A { 1539243SN/A 1549243SN/A public: 1559243SN/A 15610207Sandreas.hansson@arm.com static const uint32_t NO_ROW = -1; 1579243SN/A 1589243SN/A uint32_t openRow; 1599243SN/A 1609243SN/A Tick freeAt; 1619243SN/A Tick tRASDoneAt; 1629969SN/A Tick actAllowedAt; 1639243SN/A 16410141SN/A uint32_t rowAccesses; 1659727SN/A uint32_t bytesAccessed; 1669727SN/A 1679727SN/A Bank() : 16810207Sandreas.hansson@arm.com openRow(NO_ROW), freeAt(0), tRASDoneAt(0), actAllowedAt(0), 16910141SN/A rowAccesses(0), bytesAccessed(0) 1709243SN/A { } 1719243SN/A }; 1729243SN/A 1739243SN/A /** 1749831SN/A * A burst helper helps organize and manage a packet that is larger than 1759831SN/A * the DRAM burst size. A system packet that is larger than the burst size 1769831SN/A * is split into multiple DRAM packets and all those DRAM packets point to 1779831SN/A * a single burst helper such that we know when the whole packet is served. 1789831SN/A */ 1799831SN/A class BurstHelper { 1809831SN/A 1819831SN/A public: 1829831SN/A 1839831SN/A /** Number of DRAM bursts requred for a system packet **/ 1849831SN/A const unsigned int burstCount; 1859831SN/A 1869831SN/A /** Number of DRAM bursts serviced so far for a system packet **/ 1879831SN/A unsigned int burstsServiced; 1889831SN/A 1899831SN/A BurstHelper(unsigned int _burstCount) 1909831SN/A : burstCount(_burstCount), burstsServiced(0) 1919831SN/A { } 1929831SN/A }; 1939831SN/A 1949831SN/A /** 1959243SN/A * A DRAM packet stores packets along with the timestamp of when 1969243SN/A * the packet entered the queue, and also the decoded address. 1979243SN/A */ 1989243SN/A class DRAMPacket { 1999243SN/A 2009243SN/A public: 2019243SN/A 2029243SN/A /** When did request enter the controller */ 2039243SN/A const Tick entryTime; 2049243SN/A 2059243SN/A /** When will request leave the controller */ 2069243SN/A Tick readyTime; 2079243SN/A 2089243SN/A /** This comes from the outside world */ 2099243SN/A const PacketPtr pkt; 2109243SN/A 2119966SN/A const bool isRead; 2129966SN/A 2139243SN/A /** Will be populated by address decoder */ 2149243SN/A const uint8_t rank; 2159967SN/A const uint8_t bank; 2169243SN/A const uint16_t row; 2179831SN/A 2189831SN/A /** 2199967SN/A * Bank id is calculated considering banks in all the ranks 2209967SN/A * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and 2219967SN/A * bankId = 8 --> rank1, bank0 2229967SN/A */ 2239967SN/A const uint16_t bankId; 2249967SN/A 2259967SN/A /** 2269831SN/A * The starting address of the DRAM packet. 2279831SN/A * This address could be unaligned to burst size boundaries. The 2289831SN/A * reason is to keep the address offset so we can accurately check 2299831SN/A * incoming read packets with packets in the write queue. 2309831SN/A */ 2319832SN/A Addr addr; 2329831SN/A 2339831SN/A /** 2349831SN/A * The size of this dram packet in bytes 2359831SN/A * It is always equal or smaller than DRAM burst size 2369831SN/A */ 2379832SN/A unsigned int size; 2389831SN/A 2399831SN/A /** 2409831SN/A * A pointer to the BurstHelper if this DRAMPacket is a split packet 2419831SN/A * If not a split packet (common case), this is set to NULL 2429831SN/A */ 2439831SN/A BurstHelper* burstHelper; 2449967SN/A Bank& bankRef; 2459243SN/A 2469967SN/A DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank, 2479967SN/A uint16_t _row, uint16_t bank_id, Addr _addr, 2489967SN/A unsigned int _size, Bank& bank_ref) 2499243SN/A : entryTime(curTick()), readyTime(curTick()), 2509967SN/A pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row), 2519967SN/A bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL), 2529967SN/A bankRef(bank_ref) 2539243SN/A { } 2549243SN/A 2559243SN/A }; 2569243SN/A 2579243SN/A /** 2589243SN/A * Bunch of things requires to setup "events" in gem5 25910206Sandreas.hansson@arm.com * When event "respondEvent" occurs for example, the method 26010206Sandreas.hansson@arm.com * processRespondEvent is called; no parameters are allowed 2619243SN/A * in these methods 2629243SN/A */ 2639243SN/A void processRespondEvent(); 26410146Sandreas.hansson@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent; 2659243SN/A 2669243SN/A void processRefreshEvent(); 26710146Sandreas.hansson@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processRefreshEvent> refreshEvent; 2689243SN/A 2699243SN/A void processNextReqEvent(); 27010146Sandreas.hansson@arm.com EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent; 2719243SN/A 2729243SN/A 2739243SN/A /** 2749243SN/A * Check if the read queue has room for more entries 2759243SN/A * 2769831SN/A * @param pktCount The number of entries needed in the read queue 2779243SN/A * @return true if read queue is full, false otherwise 2789243SN/A */ 2799831SN/A bool readQueueFull(unsigned int pktCount) const; 2809243SN/A 2819243SN/A /** 2829243SN/A * Check if the write queue has room for more entries 2839243SN/A * 2849831SN/A * @param pktCount The number of entries needed in the write queue 2859243SN/A * @return true if write queue is full, false otherwise 2869243SN/A */ 2879831SN/A bool writeQueueFull(unsigned int pktCount) const; 2889243SN/A 2899243SN/A /** 2909243SN/A * When a new read comes in, first check if the write q has a 2919243SN/A * pending request to the same address.\ If not, decode the 2929831SN/A * address to populate rank/bank/row, create one or mutliple 2939831SN/A * "dram_pkt", and push them to the back of the read queue.\ 2949831SN/A * If this is the only 2959243SN/A * read request in the system, schedule an event to start 2969243SN/A * servicing it. 2979243SN/A * 2989243SN/A * @param pkt The request packet from the outside world 2999831SN/A * @param pktCount The number of DRAM bursts the pkt 3009831SN/A * translate to. If pkt size is larger then one full burst, 3019831SN/A * then pktCount is greater than one. 3029243SN/A */ 3039831SN/A void addToReadQueue(PacketPtr pkt, unsigned int pktCount); 3049243SN/A 3059243SN/A /** 3069243SN/A * Decode the incoming pkt, create a dram_pkt and push to the 3079243SN/A * back of the write queue. \If the write q length is more than 3089243SN/A * the threshold specified by the user, ie the queue is beginning 3099243SN/A * to get full, stop reads, and start draining writes. 3109243SN/A * 3119243SN/A * @param pkt The request packet from the outside world 3129831SN/A * @param pktCount The number of DRAM bursts the pkt 3139831SN/A * translate to. If pkt size is larger then one full burst, 3149831SN/A * then pktCount is greater than one. 3159243SN/A */ 3169831SN/A void addToWriteQueue(PacketPtr pkt, unsigned int pktCount); 3179243SN/A 3189243SN/A /** 3199243SN/A * Actually do the DRAM access - figure out the latency it 3209243SN/A * will take to service the req based on bank state, channel state etc 3219243SN/A * and then update those states to account for this request.\ Based 3229243SN/A * on this, update the packet's "readyTime" and move it to the 3239243SN/A * response q from where it will eventually go back to the outside 3249243SN/A * world. 3259243SN/A * 3269243SN/A * @param pkt The DRAM packet created from the outside world pkt 3279243SN/A */ 3289243SN/A void doDRAMAccess(DRAMPacket* dram_pkt); 3299243SN/A 3309243SN/A /** 3319243SN/A * When a packet reaches its "readyTime" in the response Q, 3329243SN/A * use the "access()" method in AbstractMemory to actually 3339243SN/A * create the response packet, and send it back to the outside 3349243SN/A * world requestor. 3359243SN/A * 3369243SN/A * @param pkt The packet from the outside world 3379726SN/A * @param static_latency Static latency to add before sending the packet 3389243SN/A */ 3399726SN/A void accessAndRespond(PacketPtr pkt, Tick static_latency); 3409243SN/A 3419243SN/A /** 3429243SN/A * Address decoder to figure out physical mapping onto ranks, 3439831SN/A * banks, and rows. This function is called multiple times on the same 3449831SN/A * system packet if the pakcet is larger than burst of the memory. The 3459831SN/A * dramPktAddr is used for the offset within the packet. 3469243SN/A * 3479243SN/A * @param pkt The packet from the outside world 3489831SN/A * @param dramPktAddr The starting address of the DRAM packet 3499831SN/A * @param size The size of the DRAM packet in bytes 3509966SN/A * @param isRead Is the request for a read or a write to DRAM 3519243SN/A * @return A DRAMPacket pointer with the decoded information 3529243SN/A */ 35310143SN/A DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size, 35410143SN/A bool isRead); 3559243SN/A 3569243SN/A /** 35710206Sandreas.hansson@arm.com * The memory schduler/arbiter - picks which request needs to 3589567SN/A * go next, based on the specified policy such as FCFS or FR-FCFS 35910206Sandreas.hansson@arm.com * and moves it to the head of the queue. 3609243SN/A */ 36110206Sandreas.hansson@arm.com void chooseNext(std::deque<DRAMPacket*>& queue); 3629243SN/A 3639243SN/A /** 3649243SN/A *Looks at the state of the banks, channels, row buffer hits etc 3659243SN/A * to estimate how long a request will take to complete. 3669243SN/A * 3679243SN/A * @param dram_pkt The request for which we want to estimate latency 3689243SN/A * @param inTime The tick at which you want to probe the memory 3699243SN/A * 3709243SN/A * @return A pair of ticks, one indicating how many ticks *after* 3719243SN/A * inTime the request require, and the other indicating how 3729243SN/A * much of that was just the bank access time, ignoring the 3739243SN/A * ticks spent simply waiting for resources to become free 3749243SN/A */ 3759243SN/A std::pair<Tick, Tick> estimateLatency(DRAMPacket* dram_pkt, Tick inTime); 3769243SN/A 3779243SN/A /** 3789243SN/A * Move the request at the head of the read queue to the response 3799243SN/A * queue, sorting by readyTime.\ If it is the only packet in the 3809243SN/A * response queue, schedule a respond event to send it back to the 3819243SN/A * outside world 3829243SN/A */ 3839243SN/A void moveToRespQ(); 3849243SN/A 3859243SN/A /** 3869974SN/A * For FR-FCFS policy reorder the read/write queue depending on row buffer 3879974SN/A * hits and earliest banks available in DRAM 3889974SN/A */ 3899974SN/A void reorderQueue(std::deque<DRAMPacket*>& queue); 3909974SN/A 3919974SN/A /** 3929967SN/A * Find which are the earliest available banks for the enqueued 3939967SN/A * requests. Assumes maximum of 64 banks per DIMM 3949967SN/A * 3959967SN/A * @param Queued requests to consider 3969967SN/A * @return One-hot encoded mask of bank indices 3979967SN/A */ 3989967SN/A uint64_t minBankFreeAt(const std::deque<DRAMPacket*>& queue) const; 3999488SN/A 4009488SN/A /** 4019488SN/A * Keep track of when row activations happen, in order to enforce 4029488SN/A * the maximum number of activations in the activation window. The 4039488SN/A * method updates the time that the banks become available based 4049488SN/A * on the current limits. 4059488SN/A */ 40610207Sandreas.hansson@arm.com void recordActivate(Tick act_tick, uint8_t rank, uint8_t bank, 40710207Sandreas.hansson@arm.com uint16_t row); 40810207Sandreas.hansson@arm.com 40910207Sandreas.hansson@arm.com /** 41010207Sandreas.hansson@arm.com * Precharge a given bank and also update when the precharge is 41110207Sandreas.hansson@arm.com * done. This will also deal with any stats related to the 41210207Sandreas.hansson@arm.com * accesses to the open page. 41310207Sandreas.hansson@arm.com * 41410207Sandreas.hansson@arm.com * @param bank The bank to precharge 41510207Sandreas.hansson@arm.com * @param free_at Time when the precharge is done 41610207Sandreas.hansson@arm.com */ 41710207Sandreas.hansson@arm.com void prechargeBank(Bank& bank, Tick free_at); 4189488SN/A 4199243SN/A void printParams() const; 42010143SN/A 42110143SN/A /** 42210143SN/A * Used for debugging to observe the contents of the queues. 42310143SN/A */ 4249243SN/A void printQs() const; 4259243SN/A 4269243SN/A /** 4279243SN/A * The controller's main read and write queues 4289243SN/A */ 4299833SN/A std::deque<DRAMPacket*> readQueue; 4309833SN/A std::deque<DRAMPacket*> writeQueue; 4319243SN/A 4329243SN/A /** 4339243SN/A * Response queue where read packets wait after we're done working 4349567SN/A * with them, but it's not time to send the response yet. The 4359567SN/A * responses are stored seperately mostly to keep the code clean 4369567SN/A * and help with events scheduling. For all logical purposes such 4379567SN/A * as sizing the read queue, this and the main read queue need to 4389567SN/A * be added together. 4399243SN/A */ 4409833SN/A std::deque<DRAMPacket*> respQueue; 4419243SN/A 4429567SN/A /** 4439567SN/A * If we need to drain, keep the drain manager around until we're 4449567SN/A * done here. 4459243SN/A */ 4469342SN/A DrainManager *drainManager; 4479243SN/A 4489243SN/A /** 4499243SN/A * Multi-dimensional vector of banks, first dimension is ranks, 4509243SN/A * second is bank 4519243SN/A */ 4529243SN/A std::vector<std::vector<Bank> > banks; 4539243SN/A 4549243SN/A /** 4559243SN/A * The following are basic design parameters of the memory 4569831SN/A * controller, and are initialized based on parameter values. 4579831SN/A * The rowsPerBank is determined based on the capacity, number of 4589831SN/A * ranks and banks, the burst size, and the row buffer size. 4599243SN/A */ 4609831SN/A const uint32_t deviceBusWidth; 4619831SN/A const uint32_t burstLength; 4629831SN/A const uint32_t deviceRowBufferSize; 4639831SN/A const uint32_t devicesPerRank; 4649831SN/A const uint32_t burstSize; 4659831SN/A const uint32_t rowBufferSize; 46610140SN/A const uint32_t columnsPerRowBuffer; 4679243SN/A const uint32_t ranksPerChannel; 4689243SN/A const uint32_t banksPerRank; 4699566SN/A const uint32_t channels; 4709243SN/A uint32_t rowsPerBank; 4719243SN/A const uint32_t readBufferSize; 4729243SN/A const uint32_t writeBufferSize; 47310140SN/A const uint32_t writeHighThreshold; 47410140SN/A const uint32_t writeLowThreshold; 47510140SN/A const uint32_t minWritesPerSwitch; 47610140SN/A uint32_t writesThisTime; 47710147Sandreas.hansson@arm.com uint32_t readsThisTime; 4789243SN/A 4799243SN/A /** 4809243SN/A * Basic memory timing parameters initialized based on parameter 4819243SN/A * values. 4829243SN/A */ 4839243SN/A const Tick tWTR; 48410206Sandreas.hansson@arm.com const Tick tRTW; 4859243SN/A const Tick tBURST; 4869243SN/A const Tick tRCD; 4879243SN/A const Tick tCL; 4889243SN/A const Tick tRP; 4899963SN/A const Tick tRAS; 4909243SN/A const Tick tRFC; 4919243SN/A const Tick tREFI; 4929971SN/A const Tick tRRD; 4939488SN/A const Tick tXAW; 4949488SN/A const uint32_t activationLimit; 4959243SN/A 4969243SN/A /** 4979243SN/A * Memory controller configuration initialized based on parameter 4989243SN/A * values. 4999243SN/A */ 5009243SN/A Enums::MemSched memSchedPolicy; 5019243SN/A Enums::AddrMap addrMapping; 5029243SN/A Enums::PageManage pageMgmt; 5039243SN/A 5049243SN/A /** 50510141SN/A * Max column accesses (read and write) per row, before forefully 50610141SN/A * closing it. 50710141SN/A */ 50810141SN/A const uint32_t maxAccessesPerRow; 50910141SN/A 51010141SN/A /** 5119726SN/A * Pipeline latency of the controller frontend. The frontend 5129726SN/A * contribution is added to writes (that complete when they are in 5139726SN/A * the write buffer) and reads that are serviced the write buffer. 5149726SN/A */ 5159726SN/A const Tick frontendLatency; 5169726SN/A 5179726SN/A /** 5189726SN/A * Pipeline latency of the backend and PHY. Along with the 5199726SN/A * frontend contribution, this latency is added to reads serviced 5209726SN/A * by the DRAM. 5219726SN/A */ 5229726SN/A const Tick backendLatency; 5239726SN/A 5249726SN/A /** 5259243SN/A * Till when has the main data bus been spoken for already? 5269243SN/A */ 5279243SN/A Tick busBusyUntil; 5289243SN/A 52910207Sandreas.hansson@arm.com /** 53010207Sandreas.hansson@arm.com * Keep track of when a refresh is due. 53110207Sandreas.hansson@arm.com */ 53210207Sandreas.hansson@arm.com Tick refreshDueAt; 53310207Sandreas.hansson@arm.com 53410207Sandreas.hansson@arm.com /** 53510207Sandreas.hansson@arm.com * The refresh state is used to control the progress of the 53610207Sandreas.hansson@arm.com * refresh scheduling. When normal operation is in progress the 53710207Sandreas.hansson@arm.com * refresh state is idle. From there, it progresses to the refresh 53810207Sandreas.hansson@arm.com * drain state once tREFI has passed. The refresh drain state 53910207Sandreas.hansson@arm.com * captures the DRAM row active state, as it will stay there until 54010207Sandreas.hansson@arm.com * all ongoing accesses complete. Thereafter all banks are 54110207Sandreas.hansson@arm.com * precharged, and lastly, the DRAM is refreshed. 54210207Sandreas.hansson@arm.com */ 54310207Sandreas.hansson@arm.com enum RefreshState { 54410207Sandreas.hansson@arm.com REF_IDLE = 0, 54510207Sandreas.hansson@arm.com REF_DRAIN, 54610207Sandreas.hansson@arm.com REF_PRE, 54710207Sandreas.hansson@arm.com REF_RUN 54810207Sandreas.hansson@arm.com }; 54910207Sandreas.hansson@arm.com 55010207Sandreas.hansson@arm.com RefreshState refreshState; 55110207Sandreas.hansson@arm.com 5529243SN/A Tick prevArrival; 5539243SN/A 55410206Sandreas.hansson@arm.com /** 55510206Sandreas.hansson@arm.com * The soonest you have to start thinking about the next request 55610206Sandreas.hansson@arm.com * is the longest access time that can occur before 55710206Sandreas.hansson@arm.com * busBusyUntil. Assuming you need to precharge, open a new row, 55810206Sandreas.hansson@arm.com * and access, it is tRP + tRCD + tCL. 55910206Sandreas.hansson@arm.com */ 56010206Sandreas.hansson@arm.com Tick nextReqTime; 5619972SN/A 5629243SN/A // All statistics that the model needs to capture 5639243SN/A Stats::Scalar readReqs; 5649243SN/A Stats::Scalar writeReqs; 5659831SN/A Stats::Scalar readBursts; 5669831SN/A Stats::Scalar writeBursts; 5679975SN/A Stats::Scalar bytesReadDRAM; 5689975SN/A Stats::Scalar bytesReadWrQ; 5699243SN/A Stats::Scalar bytesWritten; 5709977SN/A Stats::Scalar bytesReadSys; 5719977SN/A Stats::Scalar bytesWrittenSys; 5729243SN/A Stats::Scalar servicedByWrQ; 5739977SN/A Stats::Scalar mergedWrBursts; 5749243SN/A Stats::Scalar neitherReadNorWrite; 5759977SN/A Stats::Vector perBankRdBursts; 5769977SN/A Stats::Vector perBankWrBursts; 5779243SN/A Stats::Scalar numRdRetry; 5789243SN/A Stats::Scalar numWrRetry; 5799243SN/A Stats::Scalar totGap; 5809243SN/A Stats::Vector readPktSize; 5819243SN/A Stats::Vector writePktSize; 5829243SN/A Stats::Vector rdQLenPdf; 5839243SN/A Stats::Vector wrQLenPdf; 5849727SN/A Stats::Histogram bytesPerActivate; 58510147Sandreas.hansson@arm.com Stats::Histogram rdPerTurnAround; 58610147Sandreas.hansson@arm.com Stats::Histogram wrPerTurnAround; 5879243SN/A 5889243SN/A // Latencies summed over all requests 5899243SN/A Stats::Scalar totQLat; 5909243SN/A Stats::Scalar totMemAccLat; 5919243SN/A Stats::Scalar totBusLat; 5929243SN/A Stats::Scalar totBankLat; 5939243SN/A 5949243SN/A // Average latencies per request 5959243SN/A Stats::Formula avgQLat; 5969243SN/A Stats::Formula avgBankLat; 5979243SN/A Stats::Formula avgBusLat; 5989243SN/A Stats::Formula avgMemAccLat; 5999243SN/A 6009243SN/A // Average bandwidth 6019243SN/A Stats::Formula avgRdBW; 6029243SN/A Stats::Formula avgWrBW; 6039977SN/A Stats::Formula avgRdBWSys; 6049977SN/A Stats::Formula avgWrBWSys; 6059243SN/A Stats::Formula peakBW; 6069243SN/A Stats::Formula busUtil; 6079975SN/A Stats::Formula busUtilRead; 6089975SN/A Stats::Formula busUtilWrite; 6099243SN/A 6109243SN/A // Average queue lengths 6119243SN/A Stats::Average avgRdQLen; 6129243SN/A Stats::Average avgWrQLen; 6139243SN/A 6149243SN/A // Row hit count and rate 6159243SN/A Stats::Scalar readRowHits; 6169243SN/A Stats::Scalar writeRowHits; 6179243SN/A Stats::Formula readRowHitRate; 6189243SN/A Stats::Formula writeRowHitRate; 6199243SN/A Stats::Formula avgGap; 6209243SN/A 6219975SN/A // DRAM Power Calculation 6229975SN/A Stats::Formula pageHitRate; 6239975SN/A Stats::Formula prechargeAllPercent; 6249975SN/A Stats::Scalar prechargeAllTime; 6259975SN/A 62610207Sandreas.hansson@arm.com // To track number of cycles the DRAM is idle, i.e. all the banks 62710207Sandreas.hansson@arm.com // are precharged 62810207Sandreas.hansson@arm.com Tick idleStartTick; 62910207Sandreas.hansson@arm.com 6309975SN/A // To track number of banks which are currently active 6319975SN/A unsigned int numBanksActive; 6329975SN/A 6339349SN/A /** @todo this is a temporary workaround until the 4-phase code is 6349349SN/A * committed. upstream caches needs this packet until true is returned, so 6359349SN/A * hold onto it for deletion until a subsequent call 6369349SN/A */ 6379349SN/A std::vector<PacketPtr> pendingDelete; 6389349SN/A 6399243SN/A public: 6409243SN/A 6419243SN/A void regStats(); 6429243SN/A 64310146Sandreas.hansson@arm.com DRAMCtrl(const DRAMCtrlParams* p); 6449243SN/A 6459342SN/A unsigned int drain(DrainManager* dm); 6469243SN/A 6479294SN/A virtual BaseSlavePort& getSlavePort(const std::string& if_name, 6489294SN/A PortID idx = InvalidPortID); 6499243SN/A 6509243SN/A virtual void init(); 6519243SN/A virtual void startup(); 6529243SN/A 6539243SN/A protected: 6549243SN/A 6559243SN/A Tick recvAtomic(PacketPtr pkt); 6569243SN/A void recvFunctional(PacketPtr pkt); 6579243SN/A bool recvTimingReq(PacketPtr pkt); 6589243SN/A 6599243SN/A}; 6609243SN/A 66110146Sandreas.hansson@arm.com#endif //__MEM_DRAM_CTRL_HH__ 662