dram_ctrl.hh revision 10147
19243SN/A/* 29243SN/A * Copyright (c) 2012 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 439243SN/A */ 449243SN/A 459243SN/A/** 469243SN/A * @file 4710146Sandreas.hansson@arm.com * DRAMCtrl declaration 489243SN/A */ 499243SN/A 5010146Sandreas.hansson@arm.com#ifndef __MEM_DRAM_CTRL_HH__ 5110146Sandreas.hansson@arm.com#define __MEM_DRAM_CTRL_HH__ 529243SN/A 539488SN/A#include <deque> 549488SN/A 559243SN/A#include "base/statistics.hh" 569243SN/A#include "enums/AddrMap.hh" 579243SN/A#include "enums/MemSched.hh" 589243SN/A#include "enums/PageManage.hh" 599243SN/A#include "mem/abstract_mem.hh" 609243SN/A#include "mem/qport.hh" 6110146Sandreas.hansson@arm.com#include "params/DRAMCtrl.hh" 629243SN/A#include "sim/eventq.hh" 639243SN/A 649243SN/A/** 6510146Sandreas.hansson@arm.com * The DRAM controller is a basic single-channel memory controller 6610146Sandreas.hansson@arm.com * aiming to mimic a high-level DRAM controller and the most important 6710146Sandreas.hansson@arm.com * timing constraints associated with the DRAM. The focus is really on 689243SN/A * modelling the impact on the system rather than the DRAM itself, 699243SN/A * hence the focus is on the controller model and not on the 709243SN/A * memory. By adhering to the correct timing constraints, ultimately 719243SN/A * there is no need for a memory model in addition to the controller 729243SN/A * model. 739243SN/A * 749243SN/A * As a basic design principle, this controller is not cycle callable, 759243SN/A * but instead uses events to decide when new decisions can be made, 769243SN/A * when resources become available, when things are to be considered 779243SN/A * done, and when to send things back. Through these simple 789243SN/A * principles, we achieve a performant model that is not 799243SN/A * cycle-accurate, but enables us to evaluate the system impact of a 809243SN/A * wide range of memory technologies, and also collect statistics 819243SN/A * about the use of the memory. 829243SN/A */ 8310146Sandreas.hansson@arm.comclass DRAMCtrl : public AbstractMemory 849243SN/A{ 859243SN/A 869243SN/A private: 879243SN/A 889243SN/A // For now, make use of a queued slave port to avoid dealing with 899243SN/A // flow control for the responses being sent back 909243SN/A class MemoryPort : public QueuedSlavePort 919243SN/A { 929243SN/A 939243SN/A SlavePacketQueue queue; 9410146Sandreas.hansson@arm.com DRAMCtrl& memory; 959243SN/A 969243SN/A public: 979243SN/A 9810146Sandreas.hansson@arm.com MemoryPort(const std::string& name, DRAMCtrl& _memory); 999243SN/A 1009243SN/A protected: 1019243SN/A 1029243SN/A Tick recvAtomic(PacketPtr pkt); 1039243SN/A 1049243SN/A void recvFunctional(PacketPtr pkt); 1059243SN/A 1069243SN/A bool recvTimingReq(PacketPtr); 1079243SN/A 1089243SN/A virtual AddrRangeList getAddrRanges() const; 1099243SN/A 1109243SN/A }; 1119243SN/A 1129243SN/A /** 1139243SN/A * Our incoming port, for a multi-ported controller add a crossbar 1149243SN/A * in front of it 1159243SN/A */ 1169243SN/A MemoryPort port; 1179243SN/A 1189243SN/A /** 1199243SN/A * Remember if we have to retry a request when available. 1209243SN/A */ 1219243SN/A bool retryRdReq; 1229243SN/A bool retryWrReq; 1239243SN/A 1249243SN/A /** 1259243SN/A * Remember that a row buffer hit occured 1269243SN/A */ 1279243SN/A bool rowHitFlag; 1289243SN/A 1299243SN/A /** 1309243SN/A * Use this flag to shutoff reads, i.e. do not schedule any reads 1319243SN/A * beyond those already done so that we can turn the bus around 1329243SN/A * and do a few writes, or refresh, or whatever 1339243SN/A */ 1349243SN/A bool stopReads; 1359243SN/A 1369488SN/A /** List to keep track of activate ticks */ 1379969SN/A std::vector<std::deque<Tick>> actTicks; 1389488SN/A 1399243SN/A /** 1409727SN/A * A basic class to track the bank state indirectly via times 1419727SN/A * "freeAt" and "tRASDoneAt" and what page is currently open. The 1429727SN/A * bank also keeps track of how many bytes have been accessed in 1439727SN/A * the open row since it was opened. 1449243SN/A */ 1459243SN/A class Bank 1469243SN/A { 1479243SN/A 1489243SN/A public: 1499243SN/A 1509243SN/A static const uint32_t INVALID_ROW = -1; 1519243SN/A 1529243SN/A uint32_t openRow; 1539243SN/A 1549243SN/A Tick freeAt; 1559243SN/A Tick tRASDoneAt; 1569969SN/A Tick actAllowedAt; 1579243SN/A 15810141SN/A uint32_t rowAccesses; 1599727SN/A uint32_t bytesAccessed; 1609727SN/A 1619727SN/A Bank() : 1629969SN/A openRow(INVALID_ROW), freeAt(0), tRASDoneAt(0), actAllowedAt(0), 16310141SN/A rowAccesses(0), bytesAccessed(0) 1649243SN/A { } 1659243SN/A }; 1669243SN/A 1679243SN/A /** 1689831SN/A * A burst helper helps organize and manage a packet that is larger than 1699831SN/A * the DRAM burst size. A system packet that is larger than the burst size 1709831SN/A * is split into multiple DRAM packets and all those DRAM packets point to 1719831SN/A * a single burst helper such that we know when the whole packet is served. 1729831SN/A */ 1739831SN/A class BurstHelper { 1749831SN/A 1759831SN/A public: 1769831SN/A 1779831SN/A /** Number of DRAM bursts requred for a system packet **/ 1789831SN/A const unsigned int burstCount; 1799831SN/A 1809831SN/A /** Number of DRAM bursts serviced so far for a system packet **/ 1819831SN/A unsigned int burstsServiced; 1829831SN/A 1839831SN/A BurstHelper(unsigned int _burstCount) 1849831SN/A : burstCount(_burstCount), burstsServiced(0) 1859831SN/A { } 1869831SN/A }; 1879831SN/A 1889831SN/A /** 1899243SN/A * A DRAM packet stores packets along with the timestamp of when 1909243SN/A * the packet entered the queue, and also the decoded address. 1919243SN/A */ 1929243SN/A class DRAMPacket { 1939243SN/A 1949243SN/A public: 1959243SN/A 1969243SN/A /** When did request enter the controller */ 1979243SN/A const Tick entryTime; 1989243SN/A 1999243SN/A /** When will request leave the controller */ 2009243SN/A Tick readyTime; 2019243SN/A 2029243SN/A /** This comes from the outside world */ 2039243SN/A const PacketPtr pkt; 2049243SN/A 2059966SN/A const bool isRead; 2069966SN/A 2079243SN/A /** Will be populated by address decoder */ 2089243SN/A const uint8_t rank; 2099967SN/A const uint8_t bank; 2109243SN/A const uint16_t row; 2119831SN/A 2129831SN/A /** 2139967SN/A * Bank id is calculated considering banks in all the ranks 2149967SN/A * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and 2159967SN/A * bankId = 8 --> rank1, bank0 2169967SN/A */ 2179967SN/A const uint16_t bankId; 2189967SN/A 2199967SN/A /** 2209831SN/A * The starting address of the DRAM packet. 2219831SN/A * This address could be unaligned to burst size boundaries. The 2229831SN/A * reason is to keep the address offset so we can accurately check 2239831SN/A * incoming read packets with packets in the write queue. 2249831SN/A */ 2259832SN/A Addr addr; 2269831SN/A 2279831SN/A /** 2289831SN/A * The size of this dram packet in bytes 2299831SN/A * It is always equal or smaller than DRAM burst size 2309831SN/A */ 2319832SN/A unsigned int size; 2329831SN/A 2339831SN/A /** 2349831SN/A * A pointer to the BurstHelper if this DRAMPacket is a split packet 2359831SN/A * If not a split packet (common case), this is set to NULL 2369831SN/A */ 2379831SN/A BurstHelper* burstHelper; 2389967SN/A Bank& bankRef; 2399243SN/A 2409967SN/A DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank, 2419967SN/A uint16_t _row, uint16_t bank_id, Addr _addr, 2429967SN/A unsigned int _size, Bank& bank_ref) 2439243SN/A : entryTime(curTick()), readyTime(curTick()), 2449967SN/A pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row), 2459967SN/A bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL), 2469967SN/A bankRef(bank_ref) 2479243SN/A { } 2489243SN/A 2499243SN/A }; 2509243SN/A 2519243SN/A /** 2529243SN/A * Bunch of things requires to setup "events" in gem5 2539243SN/A * When event "writeEvent" occurs for example, the method 2549243SN/A * processWriteEvent is called; no parameters are allowed 2559243SN/A * in these methods 2569243SN/A */ 2579243SN/A void processWriteEvent(); 25810146Sandreas.hansson@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processWriteEvent> writeEvent; 2599243SN/A 2609243SN/A void processRespondEvent(); 26110146Sandreas.hansson@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent; 2629243SN/A 2639243SN/A void processRefreshEvent(); 26410146Sandreas.hansson@arm.com EventWrapper<DRAMCtrl, &DRAMCtrl::processRefreshEvent> refreshEvent; 2659243SN/A 2669243SN/A void processNextReqEvent(); 26710146Sandreas.hansson@arm.com EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent; 2689243SN/A 2699243SN/A 2709243SN/A /** 2719243SN/A * Check if the read queue has room for more entries 2729243SN/A * 2739831SN/A * @param pktCount The number of entries needed in the read queue 2749243SN/A * @return true if read queue is full, false otherwise 2759243SN/A */ 2769831SN/A bool readQueueFull(unsigned int pktCount) const; 2779243SN/A 2789243SN/A /** 2799243SN/A * Check if the write queue has room for more entries 2809243SN/A * 2819831SN/A * @param pktCount The number of entries needed in the write queue 2829243SN/A * @return true if write queue is full, false otherwise 2839243SN/A */ 2849831SN/A bool writeQueueFull(unsigned int pktCount) const; 2859243SN/A 2869243SN/A /** 2879243SN/A * When a new read comes in, first check if the write q has a 2889243SN/A * pending request to the same address.\ If not, decode the 2899831SN/A * address to populate rank/bank/row, create one or mutliple 2909831SN/A * "dram_pkt", and push them to the back of the read queue.\ 2919831SN/A * If this is the only 2929243SN/A * read request in the system, schedule an event to start 2939243SN/A * servicing it. 2949243SN/A * 2959243SN/A * @param pkt The request packet from the outside world 2969831SN/A * @param pktCount The number of DRAM bursts the pkt 2979831SN/A * translate to. If pkt size is larger then one full burst, 2989831SN/A * then pktCount is greater than one. 2999243SN/A */ 3009831SN/A void addToReadQueue(PacketPtr pkt, unsigned int pktCount); 3019243SN/A 3029243SN/A /** 3039243SN/A * Decode the incoming pkt, create a dram_pkt and push to the 3049243SN/A * back of the write queue. \If the write q length is more than 3059243SN/A * the threshold specified by the user, ie the queue is beginning 3069243SN/A * to get full, stop reads, and start draining writes. 3079243SN/A * 3089243SN/A * @param pkt The request packet from the outside world 3099831SN/A * @param pktCount The number of DRAM bursts the pkt 3109831SN/A * translate to. If pkt size is larger then one full burst, 3119831SN/A * then pktCount is greater than one. 3129243SN/A */ 3139831SN/A void addToWriteQueue(PacketPtr pkt, unsigned int pktCount); 3149243SN/A 3159243SN/A /** 3169243SN/A * Actually do the DRAM access - figure out the latency it 3179243SN/A * will take to service the req based on bank state, channel state etc 3189243SN/A * and then update those states to account for this request.\ Based 3199243SN/A * on this, update the packet's "readyTime" and move it to the 3209243SN/A * response q from where it will eventually go back to the outside 3219243SN/A * world. 3229243SN/A * 3239243SN/A * @param pkt The DRAM packet created from the outside world pkt 3249243SN/A */ 3259243SN/A void doDRAMAccess(DRAMPacket* dram_pkt); 3269243SN/A 3279243SN/A /** 3289243SN/A * Check when the channel is free to turnaround, add turnaround 3299243SN/A * delay and schedule a whole bunch of writes. 3309243SN/A */ 3319243SN/A void triggerWrites(); 3329243SN/A 3339243SN/A /** 3349243SN/A * When a packet reaches its "readyTime" in the response Q, 3359243SN/A * use the "access()" method in AbstractMemory to actually 3369243SN/A * create the response packet, and send it back to the outside 3379243SN/A * world requestor. 3389243SN/A * 3399243SN/A * @param pkt The packet from the outside world 3409726SN/A * @param static_latency Static latency to add before sending the packet 3419243SN/A */ 3429726SN/A void accessAndRespond(PacketPtr pkt, Tick static_latency); 3439243SN/A 3449243SN/A /** 3459243SN/A * Address decoder to figure out physical mapping onto ranks, 3469831SN/A * banks, and rows. This function is called multiple times on the same 3479831SN/A * system packet if the pakcet is larger than burst of the memory. The 3489831SN/A * dramPktAddr is used for the offset within the packet. 3499243SN/A * 3509243SN/A * @param pkt The packet from the outside world 3519831SN/A * @param dramPktAddr The starting address of the DRAM packet 3529831SN/A * @param size The size of the DRAM packet in bytes 3539966SN/A * @param isRead Is the request for a read or a write to DRAM 3549243SN/A * @return A DRAMPacket pointer with the decoded information 3559243SN/A */ 35610143SN/A DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size, 35710143SN/A bool isRead); 3589243SN/A 3599243SN/A /** 3609567SN/A * The memory schduler/arbiter - picks which read request needs to 3619567SN/A * go next, based on the specified policy such as FCFS or FR-FCFS 3629567SN/A * and moves it to the head of the read queue. 3639243SN/A * 3649567SN/A * @return True if a request was chosen and false if queue is empty 3659243SN/A */ 3669567SN/A bool chooseNextRead(); 3679243SN/A 3689243SN/A /** 3699243SN/A * Calls chooseNextReq() to pick the right request, then calls 3709243SN/A * doDRAMAccess on that request in order to actually service 3719243SN/A * that request 3729243SN/A */ 3739243SN/A void scheduleNextReq(); 3749243SN/A 3759243SN/A /** 3769243SN/A *Looks at the state of the banks, channels, row buffer hits etc 3779243SN/A * to estimate how long a request will take to complete. 3789243SN/A * 3799243SN/A * @param dram_pkt The request for which we want to estimate latency 3809243SN/A * @param inTime The tick at which you want to probe the memory 3819243SN/A * 3829243SN/A * @return A pair of ticks, one indicating how many ticks *after* 3839243SN/A * inTime the request require, and the other indicating how 3849243SN/A * much of that was just the bank access time, ignoring the 3859243SN/A * ticks spent simply waiting for resources to become free 3869243SN/A */ 3879243SN/A std::pair<Tick, Tick> estimateLatency(DRAMPacket* dram_pkt, Tick inTime); 3889243SN/A 3899243SN/A /** 3909243SN/A * Move the request at the head of the read queue to the response 3919243SN/A * queue, sorting by readyTime.\ If it is the only packet in the 3929243SN/A * response queue, schedule a respond event to send it back to the 3939243SN/A * outside world 3949243SN/A */ 3959243SN/A void moveToRespQ(); 3969243SN/A 3979243SN/A /** 3989567SN/A * Scheduling policy within the write queue 3999243SN/A */ 4009243SN/A void chooseNextWrite(); 4019243SN/A 4029243SN/A /** 4039974SN/A * For FR-FCFS policy reorder the read/write queue depending on row buffer 4049974SN/A * hits and earliest banks available in DRAM 4059974SN/A */ 4069974SN/A void reorderQueue(std::deque<DRAMPacket*>& queue); 4079974SN/A 4089974SN/A /** 4099243SN/A * Looking at all banks, determine the moment in time when they 4109243SN/A * are all free. 4119243SN/A * 4129243SN/A * @return The tick when all banks are free 4139243SN/A */ 4149243SN/A Tick maxBankFreeAt() const; 4159243SN/A 4169967SN/A /** 4179967SN/A * Find which are the earliest available banks for the enqueued 4189967SN/A * requests. Assumes maximum of 64 banks per DIMM 4199967SN/A * 4209967SN/A * @param Queued requests to consider 4219967SN/A * @return One-hot encoded mask of bank indices 4229967SN/A */ 4239967SN/A uint64_t minBankFreeAt(const std::deque<DRAMPacket*>& queue) const; 4249488SN/A 4259488SN/A /** 4269488SN/A * Keep track of when row activations happen, in order to enforce 4279488SN/A * the maximum number of activations in the activation window. The 4289488SN/A * method updates the time that the banks become available based 4299488SN/A * on the current limits. 4309488SN/A */ 4319971SN/A void recordActivate(Tick act_tick, uint8_t rank, uint8_t bank); 4329488SN/A 4339243SN/A void printParams() const; 43410143SN/A 43510143SN/A /** 43610143SN/A * Used for debugging to observe the contents of the queues. 43710143SN/A */ 4389243SN/A void printQs() const; 4399243SN/A 4409243SN/A /** 4419243SN/A * The controller's main read and write queues 4429243SN/A */ 4439833SN/A std::deque<DRAMPacket*> readQueue; 4449833SN/A std::deque<DRAMPacket*> writeQueue; 4459243SN/A 4469243SN/A /** 4479243SN/A * Response queue where read packets wait after we're done working 4489567SN/A * with them, but it's not time to send the response yet. The 4499567SN/A * responses are stored seperately mostly to keep the code clean 4509567SN/A * and help with events scheduling. For all logical purposes such 4519567SN/A * as sizing the read queue, this and the main read queue need to 4529567SN/A * be added together. 4539243SN/A */ 4549833SN/A std::deque<DRAMPacket*> respQueue; 4559243SN/A 4569567SN/A /** 4579567SN/A * If we need to drain, keep the drain manager around until we're 4589567SN/A * done here. 4599243SN/A */ 4609342SN/A DrainManager *drainManager; 4619243SN/A 4629243SN/A /** 4639243SN/A * Multi-dimensional vector of banks, first dimension is ranks, 4649243SN/A * second is bank 4659243SN/A */ 4669243SN/A std::vector<std::vector<Bank> > banks; 4679243SN/A 4689243SN/A /** 4699243SN/A * The following are basic design parameters of the memory 4709831SN/A * controller, and are initialized based on parameter values. 4719831SN/A * The rowsPerBank is determined based on the capacity, number of 4729831SN/A * ranks and banks, the burst size, and the row buffer size. 4739243SN/A */ 4749831SN/A const uint32_t deviceBusWidth; 4759831SN/A const uint32_t burstLength; 4769831SN/A const uint32_t deviceRowBufferSize; 4779831SN/A const uint32_t devicesPerRank; 4789831SN/A const uint32_t burstSize; 4799831SN/A const uint32_t rowBufferSize; 48010140SN/A const uint32_t columnsPerRowBuffer; 4819243SN/A const uint32_t ranksPerChannel; 4829243SN/A const uint32_t banksPerRank; 4839566SN/A const uint32_t channels; 4849243SN/A uint32_t rowsPerBank; 4859243SN/A const uint32_t readBufferSize; 4869243SN/A const uint32_t writeBufferSize; 48710140SN/A const uint32_t writeHighThreshold; 48810140SN/A const uint32_t writeLowThreshold; 48910140SN/A const uint32_t minWritesPerSwitch; 49010140SN/A uint32_t writesThisTime; 49110147Sandreas.hansson@arm.com uint32_t readsThisTime; 4929243SN/A 4939243SN/A /** 4949243SN/A * Basic memory timing parameters initialized based on parameter 4959243SN/A * values. 4969243SN/A */ 4979243SN/A const Tick tWTR; 4989243SN/A const Tick tBURST; 4999243SN/A const Tick tRCD; 5009243SN/A const Tick tCL; 5019243SN/A const Tick tRP; 5029963SN/A const Tick tRAS; 5039243SN/A const Tick tRFC; 5049243SN/A const Tick tREFI; 5059971SN/A const Tick tRRD; 5069488SN/A const Tick tXAW; 5079488SN/A const uint32_t activationLimit; 5089243SN/A 5099243SN/A /** 5109243SN/A * Memory controller configuration initialized based on parameter 5119243SN/A * values. 5129243SN/A */ 5139243SN/A Enums::MemSched memSchedPolicy; 5149243SN/A Enums::AddrMap addrMapping; 5159243SN/A Enums::PageManage pageMgmt; 5169243SN/A 5179243SN/A /** 51810141SN/A * Max column accesses (read and write) per row, before forefully 51910141SN/A * closing it. 52010141SN/A */ 52110141SN/A const uint32_t maxAccessesPerRow; 52210141SN/A 52310141SN/A /** 5249726SN/A * Pipeline latency of the controller frontend. The frontend 5259726SN/A * contribution is added to writes (that complete when they are in 5269726SN/A * the write buffer) and reads that are serviced the write buffer. 5279726SN/A */ 5289726SN/A const Tick frontendLatency; 5299726SN/A 5309726SN/A /** 5319726SN/A * Pipeline latency of the backend and PHY. Along with the 5329726SN/A * frontend contribution, this latency is added to reads serviced 5339726SN/A * by the DRAM. 5349726SN/A */ 5359726SN/A const Tick backendLatency; 5369726SN/A 5379726SN/A /** 5389243SN/A * Till when has the main data bus been spoken for already? 5399243SN/A */ 5409243SN/A Tick busBusyUntil; 5419243SN/A 5429243SN/A Tick prevArrival; 5439243SN/A 5449972SN/A // The absolute soonest you have to start thinking about the 5459972SN/A // next request is the longest access time that can occur before 5469972SN/A // busBusyUntil. Assuming you need to precharge, 5479972SN/A // open a new row, and access, it is tRP + tRCD + tCL 5489972SN/A Tick newTime; 5499972SN/A 5509243SN/A // All statistics that the model needs to capture 5519243SN/A Stats::Scalar readReqs; 5529243SN/A Stats::Scalar writeReqs; 5539831SN/A Stats::Scalar readBursts; 5549831SN/A Stats::Scalar writeBursts; 5559975SN/A Stats::Scalar bytesReadDRAM; 5569975SN/A Stats::Scalar bytesReadWrQ; 5579243SN/A Stats::Scalar bytesWritten; 5589977SN/A Stats::Scalar bytesReadSys; 5599977SN/A Stats::Scalar bytesWrittenSys; 5609243SN/A Stats::Scalar servicedByWrQ; 5619977SN/A Stats::Scalar mergedWrBursts; 5629243SN/A Stats::Scalar neitherReadNorWrite; 5639977SN/A Stats::Vector perBankRdBursts; 5649977SN/A Stats::Vector perBankWrBursts; 5659243SN/A Stats::Scalar numRdRetry; 5669243SN/A Stats::Scalar numWrRetry; 5679243SN/A Stats::Scalar totGap; 5689243SN/A Stats::Vector readPktSize; 5699243SN/A Stats::Vector writePktSize; 5709243SN/A Stats::Vector rdQLenPdf; 5719243SN/A Stats::Vector wrQLenPdf; 5729727SN/A Stats::Histogram bytesPerActivate; 57310147Sandreas.hansson@arm.com Stats::Histogram rdPerTurnAround; 57410147Sandreas.hansson@arm.com Stats::Histogram wrPerTurnAround; 5759243SN/A 5769243SN/A // Latencies summed over all requests 5779243SN/A Stats::Scalar totQLat; 5789243SN/A Stats::Scalar totMemAccLat; 5799243SN/A Stats::Scalar totBusLat; 5809243SN/A Stats::Scalar totBankLat; 5819243SN/A 5829243SN/A // Average latencies per request 5839243SN/A Stats::Formula avgQLat; 5849243SN/A Stats::Formula avgBankLat; 5859243SN/A Stats::Formula avgBusLat; 5869243SN/A Stats::Formula avgMemAccLat; 5879243SN/A 5889243SN/A // Average bandwidth 5899243SN/A Stats::Formula avgRdBW; 5909243SN/A Stats::Formula avgWrBW; 5919977SN/A Stats::Formula avgRdBWSys; 5929977SN/A Stats::Formula avgWrBWSys; 5939243SN/A Stats::Formula peakBW; 5949243SN/A Stats::Formula busUtil; 5959975SN/A Stats::Formula busUtilRead; 5969975SN/A Stats::Formula busUtilWrite; 5979243SN/A 5989243SN/A // Average queue lengths 5999243SN/A Stats::Average avgRdQLen; 6009243SN/A Stats::Average avgWrQLen; 6019243SN/A 6029243SN/A // Row hit count and rate 6039243SN/A Stats::Scalar readRowHits; 6049243SN/A Stats::Scalar writeRowHits; 6059243SN/A Stats::Formula readRowHitRate; 6069243SN/A Stats::Formula writeRowHitRate; 6079243SN/A Stats::Formula avgGap; 6089243SN/A 6099975SN/A // DRAM Power Calculation 6109975SN/A Stats::Formula pageHitRate; 6119975SN/A Stats::Formula prechargeAllPercent; 6129975SN/A Stats::Scalar prechargeAllTime; 6139975SN/A 6149975SN/A // To track number of cycles all the banks are precharged 6159975SN/A Tick startTickPrechargeAll; 6169975SN/A // To track number of banks which are currently active 6179975SN/A unsigned int numBanksActive; 6189975SN/A 6199349SN/A /** @todo this is a temporary workaround until the 4-phase code is 6209349SN/A * committed. upstream caches needs this packet until true is returned, so 6219349SN/A * hold onto it for deletion until a subsequent call 6229349SN/A */ 6239349SN/A std::vector<PacketPtr> pendingDelete; 6249349SN/A 6259243SN/A public: 6269243SN/A 6279243SN/A void regStats(); 6289243SN/A 62910146Sandreas.hansson@arm.com DRAMCtrl(const DRAMCtrlParams* p); 6309243SN/A 6319342SN/A unsigned int drain(DrainManager* dm); 6329243SN/A 6339294SN/A virtual BaseSlavePort& getSlavePort(const std::string& if_name, 6349294SN/A PortID idx = InvalidPortID); 6359243SN/A 6369243SN/A virtual void init(); 6379243SN/A virtual void startup(); 6389243SN/A 6399243SN/A protected: 6409243SN/A 6419243SN/A Tick recvAtomic(PacketPtr pkt); 6429243SN/A void recvFunctional(PacketPtr pkt); 6439243SN/A bool recvTimingReq(PacketPtr pkt); 6449243SN/A 6459243SN/A}; 6469243SN/A 64710146Sandreas.hansson@arm.com#endif //__MEM_DRAM_CTRL_HH__ 648