dram_ctrl.cc revision 10211
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2013 Amin Farmahini-Farahani
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Andreas Hansson
41 *          Ani Udipi
42 *          Neha Agarwal
43 */
44
45#include "base/bitfield.hh"
46#include "base/trace.hh"
47#include "debug/DRAM.hh"
48#include "debug/DRAMState.hh"
49#include "debug/Drain.hh"
50#include "mem/dram_ctrl.hh"
51#include "sim/system.hh"
52
53using namespace std;
54
55DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
56    AbstractMemory(p),
57    port(name() + ".port", *this),
58    retryRdReq(false), retryWrReq(false),
59    busState(READ),
60    nextReqEvent(this), respondEvent(this), activateEvent(this),
61    prechargeEvent(this), refreshEvent(this), powerEvent(this),
62    drainManager(NULL),
63    deviceBusWidth(p->device_bus_width), burstLength(p->burst_length),
64    deviceRowBufferSize(p->device_rowbuffer_size),
65    devicesPerRank(p->devices_per_rank),
66    burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8),
67    rowBufferSize(devicesPerRank * deviceRowBufferSize),
68    columnsPerRowBuffer(rowBufferSize / burstSize),
69    ranksPerChannel(p->ranks_per_channel),
70    banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0),
71    readBufferSize(p->read_buffer_size),
72    writeBufferSize(p->write_buffer_size),
73    writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0),
74    writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0),
75    minWritesPerSwitch(p->min_writes_per_switch),
76    writesThisTime(0), readsThisTime(0),
77    tWTR(p->tWTR), tRTW(p->tRTW), tBURST(p->tBURST),
78    tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), tWR(p->tWR),
79    tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD),
80    tXAW(p->tXAW), activationLimit(p->activation_limit),
81    memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping),
82    pageMgmt(p->page_policy),
83    maxAccessesPerRow(p->max_accesses_per_row),
84    frontendLatency(p->static_frontend_latency),
85    backendLatency(p->static_backend_latency),
86    busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE),
87    pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), prevArrival(0),
88    nextReqTime(0), pwrStateTick(0), numBanksActive(0)
89{
90    // create the bank states based on the dimensions of the ranks and
91    // banks
92    banks.resize(ranksPerChannel);
93    actTicks.resize(ranksPerChannel);
94    for (size_t c = 0; c < ranksPerChannel; ++c) {
95        banks[c].resize(banksPerRank);
96        actTicks[c].resize(activationLimit, 0);
97    }
98
99    // perform a basic check of the write thresholds
100    if (p->write_low_thresh_perc >= p->write_high_thresh_perc)
101        fatal("Write buffer low threshold %d must be smaller than the "
102              "high threshold %d\n", p->write_low_thresh_perc,
103              p->write_high_thresh_perc);
104
105    // determine the rows per bank by looking at the total capacity
106    uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size());
107
108    DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity,
109            AbstractMemory::size());
110
111    DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n",
112            rowBufferSize, columnsPerRowBuffer);
113
114    rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel);
115
116    if (range.interleaved()) {
117        if (channels != range.stripes())
118            fatal("%s has %d interleaved address stripes but %d channel(s)\n",
119                  name(), range.stripes(), channels);
120
121        if (addrMapping == Enums::RoRaBaChCo) {
122            if (rowBufferSize != range.granularity()) {
123                fatal("Interleaving of %s doesn't match RoRaBaChCo "
124                      "address map\n", name());
125            }
126        } else if (addrMapping == Enums::RoRaBaCoCh) {
127            if (system()->cacheLineSize() != range.granularity()) {
128                fatal("Interleaving of %s doesn't match RoRaBaCoCh "
129                      "address map\n", name());
130            }
131        } else if (addrMapping == Enums::RoCoRaBaCh) {
132            if (system()->cacheLineSize() != range.granularity())
133                fatal("Interleaving of %s doesn't match RoCoRaBaCh "
134                      "address map\n", name());
135        }
136    }
137
138    // some basic sanity checks
139    if (tREFI <= tRP || tREFI <= tRFC) {
140        fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n",
141              tREFI, tRP, tRFC);
142    }
143}
144
145void
146DRAMCtrl::init()
147{
148    if (!port.isConnected()) {
149        fatal("DRAMCtrl %s is unconnected!\n", name());
150    } else {
151        port.sendRangeChange();
152    }
153}
154
155void
156DRAMCtrl::startup()
157{
158    // update the start tick for the precharge accounting to the
159    // current tick
160    pwrStateTick = curTick();
161
162    // shift the bus busy time sufficiently far ahead that we never
163    // have to worry about negative values when computing the time for
164    // the next request, this will add an insignificant bubble at the
165    // start of simulation
166    busBusyUntil = curTick() + tRP + tRCD + tCL;
167
168    // print the configuration of the controller
169    printParams();
170
171    // kick off the refresh, and give ourselves enough time to
172    // precharge
173    schedule(refreshEvent, curTick() + tREFI - tRP);
174}
175
176Tick
177DRAMCtrl::recvAtomic(PacketPtr pkt)
178{
179    DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr());
180
181    // do the actual memory access and turn the packet into a response
182    access(pkt);
183
184    Tick latency = 0;
185    if (!pkt->memInhibitAsserted() && pkt->hasData()) {
186        // this value is not supposed to be accurate, just enough to
187        // keep things going, mimic a closed page
188        latency = tRP + tRCD + tCL;
189    }
190    return latency;
191}
192
193bool
194DRAMCtrl::readQueueFull(unsigned int neededEntries) const
195{
196    DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n",
197            readBufferSize, readQueue.size() + respQueue.size(),
198            neededEntries);
199
200    return
201        (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize;
202}
203
204bool
205DRAMCtrl::writeQueueFull(unsigned int neededEntries) const
206{
207    DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n",
208            writeBufferSize, writeQueue.size(), neededEntries);
209    return (writeQueue.size() + neededEntries) > writeBufferSize;
210}
211
212DRAMCtrl::DRAMPacket*
213DRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size,
214                       bool isRead)
215{
216    // decode the address based on the address mapping scheme, with
217    // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and
218    // channel, respectively
219    uint8_t rank;
220    uint8_t bank;
221    uint16_t row;
222
223    // truncate the address to the access granularity
224    Addr addr = dramPktAddr / burstSize;
225
226    // we have removed the lowest order address bits that denote the
227    // position within the column
228    if (addrMapping == Enums::RoRaBaChCo) {
229        // the lowest order bits denote the column to ensure that
230        // sequential cache lines occupy the same row
231        addr = addr / columnsPerRowBuffer;
232
233        // take out the channel part of the address
234        addr = addr / channels;
235
236        // after the channel bits, get the bank bits to interleave
237        // over the banks
238        bank = addr % banksPerRank;
239        addr = addr / banksPerRank;
240
241        // after the bank, we get the rank bits which thus interleaves
242        // over the ranks
243        rank = addr % ranksPerChannel;
244        addr = addr / ranksPerChannel;
245
246        // lastly, get the row bits
247        row = addr % rowsPerBank;
248        addr = addr / rowsPerBank;
249    } else if (addrMapping == Enums::RoRaBaCoCh) {
250        // take out the channel part of the address
251        addr = addr / channels;
252
253        // next, the column
254        addr = addr / columnsPerRowBuffer;
255
256        // after the column bits, we get the bank bits to interleave
257        // over the banks
258        bank = addr % banksPerRank;
259        addr = addr / banksPerRank;
260
261        // after the bank, we get the rank bits which thus interleaves
262        // over the ranks
263        rank = addr % ranksPerChannel;
264        addr = addr / ranksPerChannel;
265
266        // lastly, get the row bits
267        row = addr % rowsPerBank;
268        addr = addr / rowsPerBank;
269    } else if (addrMapping == Enums::RoCoRaBaCh) {
270        // optimise for closed page mode and utilise maximum
271        // parallelism of the DRAM (at the cost of power)
272
273        // take out the channel part of the address, not that this has
274        // to match with how accesses are interleaved between the
275        // controllers in the address mapping
276        addr = addr / channels;
277
278        // start with the bank bits, as this provides the maximum
279        // opportunity for parallelism between requests
280        bank = addr % banksPerRank;
281        addr = addr / banksPerRank;
282
283        // next get the rank bits
284        rank = addr % ranksPerChannel;
285        addr = addr / ranksPerChannel;
286
287        // next the column bits which we do not need to keep track of
288        // and simply skip past
289        addr = addr / columnsPerRowBuffer;
290
291        // lastly, get the row bits
292        row = addr % rowsPerBank;
293        addr = addr / rowsPerBank;
294    } else
295        panic("Unknown address mapping policy chosen!");
296
297    assert(rank < ranksPerChannel);
298    assert(bank < banksPerRank);
299    assert(row < rowsPerBank);
300
301    DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n",
302            dramPktAddr, rank, bank, row);
303
304    // create the corresponding DRAM packet with the entry time and
305    // ready time set to the current tick, the latter will be updated
306    // later
307    uint16_t bank_id = banksPerRank * rank + bank;
308    return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr,
309                          size, banks[rank][bank]);
310}
311
312void
313DRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount)
314{
315    // only add to the read queue here. whenever the request is
316    // eventually done, set the readyTime, and call schedule()
317    assert(!pkt->isWrite());
318
319    assert(pktCount != 0);
320
321    // if the request size is larger than burst size, the pkt is split into
322    // multiple DRAM packets
323    // Note if the pkt starting address is not aligened to burst size, the
324    // address of first DRAM packet is kept unaliged. Subsequent DRAM packets
325    // are aligned to burst size boundaries. This is to ensure we accurately
326    // check read packets against packets in write queue.
327    Addr addr = pkt->getAddr();
328    unsigned pktsServicedByWrQ = 0;
329    BurstHelper* burst_helper = NULL;
330    for (int cnt = 0; cnt < pktCount; ++cnt) {
331        unsigned size = std::min((addr | (burstSize - 1)) + 1,
332                        pkt->getAddr() + pkt->getSize()) - addr;
333        readPktSize[ceilLog2(size)]++;
334        readBursts++;
335
336        // First check write buffer to see if the data is already at
337        // the controller
338        bool foundInWrQ = false;
339        for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) {
340            // check if the read is subsumed in the write entry we are
341            // looking at
342            if ((*i)->addr <= addr &&
343                (addr + size) <= ((*i)->addr + (*i)->size)) {
344                foundInWrQ = true;
345                servicedByWrQ++;
346                pktsServicedByWrQ++;
347                DPRINTF(DRAM, "Read to addr %lld with size %d serviced by "
348                        "write queue\n", addr, size);
349                bytesReadWrQ += burstSize;
350                break;
351            }
352        }
353
354        // If not found in the write q, make a DRAM packet and
355        // push it onto the read queue
356        if (!foundInWrQ) {
357
358            // Make the burst helper for split packets
359            if (pktCount > 1 && burst_helper == NULL) {
360                DPRINTF(DRAM, "Read to addr %lld translates to %d "
361                        "dram requests\n", pkt->getAddr(), pktCount);
362                burst_helper = new BurstHelper(pktCount);
363            }
364
365            DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true);
366            dram_pkt->burstHelper = burst_helper;
367
368            assert(!readQueueFull(1));
369            rdQLenPdf[readQueue.size() + respQueue.size()]++;
370
371            DPRINTF(DRAM, "Adding to read queue\n");
372
373            readQueue.push_back(dram_pkt);
374
375            // Update stats
376            avgRdQLen = readQueue.size() + respQueue.size();
377        }
378
379        // Starting address of next dram pkt (aligend to burstSize boundary)
380        addr = (addr | (burstSize - 1)) + 1;
381    }
382
383    // If all packets are serviced by write queue, we send the repsonse back
384    if (pktsServicedByWrQ == pktCount) {
385        accessAndRespond(pkt, frontendLatency);
386        return;
387    }
388
389    // Update how many split packets are serviced by write queue
390    if (burst_helper != NULL)
391        burst_helper->burstsServiced = pktsServicedByWrQ;
392
393    // If we are not already scheduled to get a request out of the
394    // queue, do so now
395    if (!nextReqEvent.scheduled()) {
396        DPRINTF(DRAM, "Request scheduled immediately\n");
397        schedule(nextReqEvent, curTick());
398    }
399}
400
401void
402DRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
403{
404    // only add to the write queue here. whenever the request is
405    // eventually done, set the readyTime, and call schedule()
406    assert(pkt->isWrite());
407
408    // if the request size is larger than burst size, the pkt is split into
409    // multiple DRAM packets
410    Addr addr = pkt->getAddr();
411    for (int cnt = 0; cnt < pktCount; ++cnt) {
412        unsigned size = std::min((addr | (burstSize - 1)) + 1,
413                        pkt->getAddr() + pkt->getSize()) - addr;
414        writePktSize[ceilLog2(size)]++;
415        writeBursts++;
416
417        // see if we can merge with an existing item in the write
418        // queue and keep track of whether we have merged or not so we
419        // can stop at that point and also avoid enqueueing a new
420        // request
421        bool merged = false;
422        auto w = writeQueue.begin();
423
424        while(!merged && w != writeQueue.end()) {
425            // either of the two could be first, if they are the same
426            // it does not matter which way we go
427            if ((*w)->addr >= addr) {
428                // the existing one starts after the new one, figure
429                // out where the new one ends with respect to the
430                // existing one
431                if ((addr + size) >= ((*w)->addr + (*w)->size)) {
432                    // check if the existing one is completely
433                    // subsumed in the new one
434                    DPRINTF(DRAM, "Merging write covering existing burst\n");
435                    merged = true;
436                    // update both the address and the size
437                    (*w)->addr = addr;
438                    (*w)->size = size;
439                } else if ((addr + size) >= (*w)->addr &&
440                           ((*w)->addr + (*w)->size - addr) <= burstSize) {
441                    // the new one is just before or partially
442                    // overlapping with the existing one, and together
443                    // they fit within a burst
444                    DPRINTF(DRAM, "Merging write before existing burst\n");
445                    merged = true;
446                    // the existing queue item needs to be adjusted with
447                    // respect to both address and size
448                    (*w)->size = (*w)->addr + (*w)->size - addr;
449                    (*w)->addr = addr;
450                }
451            } else {
452                // the new one starts after the current one, figure
453                // out where the existing one ends with respect to the
454                // new one
455                if (((*w)->addr + (*w)->size) >= (addr + size)) {
456                    // check if the new one is completely subsumed in the
457                    // existing one
458                    DPRINTF(DRAM, "Merging write into existing burst\n");
459                    merged = true;
460                    // no adjustments necessary
461                } else if (((*w)->addr + (*w)->size) >= addr &&
462                           (addr + size - (*w)->addr) <= burstSize) {
463                    // the existing one is just before or partially
464                    // overlapping with the new one, and together
465                    // they fit within a burst
466                    DPRINTF(DRAM, "Merging write after existing burst\n");
467                    merged = true;
468                    // the address is right, and only the size has
469                    // to be adjusted
470                    (*w)->size = addr + size - (*w)->addr;
471                }
472            }
473            ++w;
474        }
475
476        // if the item was not merged we need to create a new write
477        // and enqueue it
478        if (!merged) {
479            DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false);
480
481            assert(writeQueue.size() < writeBufferSize);
482            wrQLenPdf[writeQueue.size()]++;
483
484            DPRINTF(DRAM, "Adding to write queue\n");
485
486            writeQueue.push_back(dram_pkt);
487
488            // Update stats
489            avgWrQLen = writeQueue.size();
490        } else {
491            // keep track of the fact that this burst effectively
492            // disappeared as it was merged with an existing one
493            mergedWrBursts++;
494        }
495
496        // Starting address of next dram pkt (aligend to burstSize boundary)
497        addr = (addr | (burstSize - 1)) + 1;
498    }
499
500    // we do not wait for the writes to be send to the actual memory,
501    // but instead take responsibility for the consistency here and
502    // snoop the write queue for any upcoming reads
503    // @todo, if a pkt size is larger than burst size, we might need a
504    // different front end latency
505    accessAndRespond(pkt, frontendLatency);
506
507    // If we are not already scheduled to get a request out of the
508    // queue, do so now
509    if (!nextReqEvent.scheduled()) {
510        DPRINTF(DRAM, "Request scheduled immediately\n");
511        schedule(nextReqEvent, curTick());
512    }
513}
514
515void
516DRAMCtrl::printParams() const
517{
518    // Sanity check print of important parameters
519    DPRINTF(DRAM,
520            "Memory controller %s physical organization\n"      \
521            "Number of devices per rank   %d\n"                 \
522            "Device bus width (in bits)   %d\n"                 \
523            "DRAM data bus burst (bytes)  %d\n"                 \
524            "Row buffer size (bytes)      %d\n"                 \
525            "Columns per row buffer       %d\n"                 \
526            "Rows    per bank             %d\n"                 \
527            "Banks   per rank             %d\n"                 \
528            "Ranks   per channel          %d\n"                 \
529            "Total mem capacity (bytes)   %u\n",
530            name(), devicesPerRank, deviceBusWidth, burstSize, rowBufferSize,
531            columnsPerRowBuffer, rowsPerBank, banksPerRank, ranksPerChannel,
532            rowBufferSize * rowsPerBank * banksPerRank * ranksPerChannel);
533
534    string scheduler =  memSchedPolicy == Enums::fcfs ? "FCFS" : "FR-FCFS";
535    string address_mapping = addrMapping == Enums::RoRaBaChCo ? "RoRaBaChCo" :
536        (addrMapping == Enums::RoRaBaCoCh ? "RoRaBaCoCh" : "RoCoRaBaCh");
537    string page_policy = pageMgmt == Enums::open ? "OPEN" :
538        (pageMgmt == Enums::open_adaptive ? "OPEN (adaptive)" :
539        (pageMgmt == Enums::close_adaptive ? "CLOSE (adaptive)" : "CLOSE"));
540
541    DPRINTF(DRAM,
542            "Memory controller %s characteristics\n"    \
543            "Read buffer size     %d\n"                 \
544            "Write buffer size    %d\n"                 \
545            "Write high thresh    %d\n"                 \
546            "Write low thresh     %d\n"                 \
547            "Scheduler            %s\n"                 \
548            "Address mapping      %s\n"                 \
549            "Page policy          %s\n",
550            name(), readBufferSize, writeBufferSize, writeHighThreshold,
551            writeLowThreshold, scheduler, address_mapping, page_policy);
552
553    DPRINTF(DRAM, "Memory controller %s timing specs\n" \
554            "tRCD      %d ticks\n"                        \
555            "tCL       %d ticks\n"                        \
556            "tRP       %d ticks\n"                        \
557            "tBURST    %d ticks\n"                        \
558            "tRFC      %d ticks\n"                        \
559            "tREFI     %d ticks\n"                        \
560            "tWTR      %d ticks\n"                        \
561            "tRTW      %d ticks\n"                        \
562            "tWR       %d ticks\n"                        \
563            "tXAW (%d) %d ticks\n",
564            name(), tRCD, tCL, tRP, tBURST, tRFC, tREFI, tWTR,
565            tRTW, tWR, activationLimit, tXAW);
566}
567
568void
569DRAMCtrl::printQs() const {
570    DPRINTF(DRAM, "===READ QUEUE===\n\n");
571    for (auto i = readQueue.begin() ;  i != readQueue.end() ; ++i) {
572        DPRINTF(DRAM, "Read %lu\n", (*i)->addr);
573    }
574    DPRINTF(DRAM, "\n===RESP QUEUE===\n\n");
575    for (auto i = respQueue.begin() ;  i != respQueue.end() ; ++i) {
576        DPRINTF(DRAM, "Response %lu\n", (*i)->addr);
577    }
578    DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n");
579    for (auto i = writeQueue.begin() ;  i != writeQueue.end() ; ++i) {
580        DPRINTF(DRAM, "Write %lu\n", (*i)->addr);
581    }
582}
583
584bool
585DRAMCtrl::recvTimingReq(PacketPtr pkt)
586{
587    /// @todo temporary hack to deal with memory corruption issues until
588    /// 4-phase transactions are complete
589    for (int x = 0; x < pendingDelete.size(); x++)
590        delete pendingDelete[x];
591    pendingDelete.clear();
592
593    // This is where we enter from the outside world
594    DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n",
595            pkt->cmdString(), pkt->getAddr(), pkt->getSize());
596
597    // simply drop inhibited packets for now
598    if (pkt->memInhibitAsserted()) {
599        DPRINTF(DRAM, "Inhibited packet -- Dropping it now\n");
600        pendingDelete.push_back(pkt);
601        return true;
602    }
603
604    // Calc avg gap between requests
605    if (prevArrival != 0) {
606        totGap += curTick() - prevArrival;
607    }
608    prevArrival = curTick();
609
610
611    // Find out how many dram packets a pkt translates to
612    // If the burst size is equal or larger than the pkt size, then a pkt
613    // translates to only one dram packet. Otherwise, a pkt translates to
614    // multiple dram packets
615    unsigned size = pkt->getSize();
616    unsigned offset = pkt->getAddr() & (burstSize - 1);
617    unsigned int dram_pkt_count = divCeil(offset + size, burstSize);
618
619    // check local buffers and do not accept if full
620    if (pkt->isRead()) {
621        assert(size != 0);
622        if (readQueueFull(dram_pkt_count)) {
623            DPRINTF(DRAM, "Read queue full, not accepting\n");
624            // remember that we have to retry this port
625            retryRdReq = true;
626            numRdRetry++;
627            return false;
628        } else {
629            addToReadQueue(pkt, dram_pkt_count);
630            readReqs++;
631            bytesReadSys += size;
632        }
633    } else if (pkt->isWrite()) {
634        assert(size != 0);
635        if (writeQueueFull(dram_pkt_count)) {
636            DPRINTF(DRAM, "Write queue full, not accepting\n");
637            // remember that we have to retry this port
638            retryWrReq = true;
639            numWrRetry++;
640            return false;
641        } else {
642            addToWriteQueue(pkt, dram_pkt_count);
643            writeReqs++;
644            bytesWrittenSys += size;
645        }
646    } else {
647        DPRINTF(DRAM,"Neither read nor write, ignore timing\n");
648        neitherReadNorWrite++;
649        accessAndRespond(pkt, 1);
650    }
651
652    return true;
653}
654
655void
656DRAMCtrl::processRespondEvent()
657{
658    DPRINTF(DRAM,
659            "processRespondEvent(): Some req has reached its readyTime\n");
660
661    DRAMPacket* dram_pkt = respQueue.front();
662
663    if (dram_pkt->burstHelper) {
664        // it is a split packet
665        dram_pkt->burstHelper->burstsServiced++;
666        if (dram_pkt->burstHelper->burstsServiced ==
667            dram_pkt->burstHelper->burstCount) {
668            // we have now serviced all children packets of a system packet
669            // so we can now respond to the requester
670            // @todo we probably want to have a different front end and back
671            // end latency for split packets
672            accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency);
673            delete dram_pkt->burstHelper;
674            dram_pkt->burstHelper = NULL;
675        }
676    } else {
677        // it is not a split packet
678        accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency);
679    }
680
681    delete respQueue.front();
682    respQueue.pop_front();
683
684    if (!respQueue.empty()) {
685        assert(respQueue.front()->readyTime >= curTick());
686        assert(!respondEvent.scheduled());
687        schedule(respondEvent, respQueue.front()->readyTime);
688    } else {
689        // if there is nothing left in any queue, signal a drain
690        if (writeQueue.empty() && readQueue.empty() &&
691            drainManager) {
692            drainManager->signalDrainDone();
693            drainManager = NULL;
694        }
695    }
696
697    // We have made a location in the queue available at this point,
698    // so if there is a read that was forced to wait, retry now
699    if (retryRdReq) {
700        retryRdReq = false;
701        port.sendRetry();
702    }
703}
704
705void
706DRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue)
707{
708    // This method does the arbitration between requests. The chosen
709    // packet is simply moved to the head of the queue. The other
710    // methods know that this is the place to look. For example, with
711    // FCFS, this method does nothing
712    assert(!queue.empty());
713
714    if (queue.size() == 1) {
715        DPRINTF(DRAM, "Single request, nothing to do\n");
716        return;
717    }
718
719    if (memSchedPolicy == Enums::fcfs) {
720        // Do nothing, since the correct request is already head
721    } else if (memSchedPolicy == Enums::frfcfs) {
722        reorderQueue(queue);
723    } else
724        panic("No scheduling policy chosen\n");
725}
726
727void
728DRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue)
729{
730    // Only determine this when needed
731    uint64_t earliest_banks = 0;
732
733    // Search for row hits first, if no row hit is found then schedule the
734    // packet to one of the earliest banks available
735    bool found_earliest_pkt = false;
736    auto selected_pkt_it = queue.begin();
737
738    for (auto i = queue.begin(); i != queue.end() ; ++i) {
739        DRAMPacket* dram_pkt = *i;
740        const Bank& bank = dram_pkt->bankRef;
741        // Check if it is a row hit
742        if (bank.openRow == dram_pkt->row) {
743            // FCFS within the hits
744            DPRINTF(DRAM, "Row buffer hit\n");
745            selected_pkt_it = i;
746            break;
747        } else if (!found_earliest_pkt) {
748            // No row hit, go for first ready
749            if (earliest_banks == 0)
750                earliest_banks = minBankActAt(queue);
751
752            // simplistic approximation of when the bank can issue an
753            // activate, this is calculated in minBankActAt and could
754            // be cached
755            Tick act_at = bank.openRow == Bank::NO_ROW ?
756                bank.actAllowedAt :
757                std::max(bank.preAllowedAt, curTick()) + tRP;
758
759            // Bank is ready or is the first available bank
760            if (act_at <= curTick() ||
761                bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) {
762                // Remember the packet to be scheduled to one of the earliest
763                // banks available, FCFS amongst the earliest banks
764                selected_pkt_it = i;
765                found_earliest_pkt = true;
766            }
767        }
768    }
769
770    DRAMPacket* selected_pkt = *selected_pkt_it;
771    queue.erase(selected_pkt_it);
772    queue.push_front(selected_pkt);
773}
774
775void
776DRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency)
777{
778    DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr());
779
780    bool needsResponse = pkt->needsResponse();
781    // do the actual memory access which also turns the packet into a
782    // response
783    access(pkt);
784
785    // turn packet around to go back to requester if response expected
786    if (needsResponse) {
787        // access already turned the packet into a response
788        assert(pkt->isResponse());
789
790        // @todo someone should pay for this
791        pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
792
793        // queue the packet in the response queue to be sent out after
794        // the static latency has passed
795        port.schedTimingResp(pkt, curTick() + static_latency);
796    } else {
797        // @todo the packet is going to be deleted, and the DRAMPacket
798        // is still having a pointer to it
799        pendingDelete.push_back(pkt);
800    }
801
802    DPRINTF(DRAM, "Done\n");
803
804    return;
805}
806
807void
808DRAMCtrl::activateBank(Tick act_tick, uint8_t rank, uint8_t bank,
809                       uint16_t row, Bank& bank_ref)
810{
811    assert(0 <= rank && rank < ranksPerChannel);
812    assert(actTicks[rank].size() == activationLimit);
813
814    DPRINTF(DRAM, "Activate at tick %d\n", act_tick);
815
816    // update the open row
817    assert(bank_ref.openRow == Bank::NO_ROW);
818    bank_ref.openRow = row;
819
820    // start counting anew, this covers both the case when we
821    // auto-precharged, and when this access is forced to
822    // precharge
823    bank_ref.bytesAccessed = 0;
824    bank_ref.rowAccesses = 0;
825
826    ++numBanksActive;
827    assert(numBanksActive <= banksPerRank * ranksPerChannel);
828
829    DPRINTF(DRAM, "Activate bank at tick %lld, now got %d active\n",
830            act_tick, numBanksActive);
831
832    // The next access has to respect tRAS for this bank
833    bank_ref.preAllowedAt = act_tick + tRAS;
834
835    // Respect the row-to-column command delay
836    bank_ref.colAllowedAt = act_tick + tRCD;
837
838    // start by enforcing tRRD
839    for(int i = 0; i < banksPerRank; i++) {
840        // next activate to any bank in this rank must not happen
841        // before tRRD
842        banks[rank][i].actAllowedAt = std::max(act_tick + tRRD,
843                                               banks[rank][i].actAllowedAt);
844    }
845
846    // next, we deal with tXAW, if the activation limit is disabled
847    // then we are done
848    if (actTicks[rank].empty())
849        return;
850
851    // sanity check
852    if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) {
853        panic("Got %d activates in window %d (%llu - %llu) which is smaller "
854              "than %llu\n", activationLimit, act_tick - actTicks[rank].back(),
855              act_tick, actTicks[rank].back(), tXAW);
856    }
857
858    // shift the times used for the book keeping, the last element
859    // (highest index) is the oldest one and hence the lowest value
860    actTicks[rank].pop_back();
861
862    // record an new activation (in the future)
863    actTicks[rank].push_front(act_tick);
864
865    // cannot activate more than X times in time window tXAW, push the
866    // next one (the X + 1'st activate) to be tXAW away from the
867    // oldest in our window of X
868    if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) {
869        DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate no earlier "
870                "than %llu\n", activationLimit, actTicks[rank].back() + tXAW);
871            for(int j = 0; j < banksPerRank; j++)
872                // next activate must not happen before end of window
873                banks[rank][j].actAllowedAt =
874                    std::max(actTicks[rank].back() + tXAW,
875                             banks[rank][j].actAllowedAt);
876    }
877
878    // at the point when this activate takes place, make sure we
879    // transition to the active power state
880    if (!activateEvent.scheduled())
881        schedule(activateEvent, act_tick);
882    else if (activateEvent.when() > act_tick)
883        // move it sooner in time
884        reschedule(activateEvent, act_tick);
885}
886
887void
888DRAMCtrl::processActivateEvent()
889{
890    // we should transition to the active state as soon as any bank is active
891    if (pwrState != PWR_ACT)
892        // note that at this point numBanksActive could be back at
893        // zero again due to a precharge scheduled in the future
894        schedulePowerEvent(PWR_ACT, curTick());
895}
896
897void
898DRAMCtrl::prechargeBank(Bank& bank, Tick pre_at)
899{
900    // make sure the bank has an open row
901    assert(bank.openRow != Bank::NO_ROW);
902
903    // sample the bytes per activate here since we are closing
904    // the page
905    bytesPerActivate.sample(bank.bytesAccessed);
906
907    bank.openRow = Bank::NO_ROW;
908
909    Tick pre_done_at = pre_at + tRP;
910
911    bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at);
912
913    assert(numBanksActive != 0);
914    --numBanksActive;
915
916    DPRINTF(DRAM, "Precharging bank at tick %lld, now got %d active\n",
917            pre_at, numBanksActive);
918
919    // if we look at the current number of active banks we might be
920    // tempted to think the DRAM is now idle, however this can be
921    // undone by an activate that is scheduled to happen before we
922    // would have reached the idle state, so schedule an event and
923    // rather check once we actually make it to the point in time when
924    // the (last) precharge takes place
925    if (!prechargeEvent.scheduled())
926        schedule(prechargeEvent, pre_done_at);
927    else if (prechargeEvent.when() < pre_done_at)
928        reschedule(prechargeEvent, pre_done_at);
929}
930
931void
932DRAMCtrl::processPrechargeEvent()
933{
934    // if we reached zero, then special conditions apply as we track
935    // if all banks are precharged for the power models
936    if (numBanksActive == 0) {
937        // we should transition to the idle state when the last bank
938        // is precharged
939        schedulePowerEvent(PWR_IDLE, curTick());
940    }
941}
942
943void
944DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt)
945{
946    DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
947            dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row);
948
949    // get the bank
950    Bank& bank = dram_pkt->bankRef;
951
952    // for the state we need to track if it is a row hit or not
953    bool row_hit = true;
954
955    // respect any constraints on the command (e.g. tRCD or tCCD)
956    Tick cmd_at = std::max(bank.colAllowedAt, curTick());
957
958    // Determine the access latency and update the bank state
959    if (bank.openRow == dram_pkt->row) {
960        // nothing to do
961    } else {
962        row_hit = false;
963
964        // If there is a page open, precharge it.
965        if (bank.openRow != Bank::NO_ROW) {
966            prechargeBank(bank, std::max(bank.preAllowedAt, curTick()));
967        }
968
969        // next we need to account for the delay in activating the
970        // page
971        Tick act_tick = std::max(bank.actAllowedAt, curTick());
972
973        // Record the activation and deal with all the global timing
974        // constraints caused be a new activation (tRRD and tXAW)
975        activateBank(act_tick, dram_pkt->rank, dram_pkt->bank,
976                     dram_pkt->row, bank);
977
978        // issue the command as early as possible
979        cmd_at = bank.colAllowedAt;
980    }
981
982    // we need to wait until the bus is available before we can issue
983    // the command
984    cmd_at = std::max(cmd_at, busBusyUntil - tCL);
985
986    // update the packet ready time
987    dram_pkt->readyTime = cmd_at + tCL + tBURST;
988
989    // only one burst can use the bus at any one point in time
990    assert(dram_pkt->readyTime - busBusyUntil >= tBURST);
991
992    // not strictly necessary, but update the time for the next
993    // read/write (add a max with tCCD here)
994    bank.colAllowedAt = cmd_at + tBURST;
995
996    // If this is a write, we also need to respect the write
997    // recovery time before a precharge
998    if (!dram_pkt->isRead) {
999        bank.preAllowedAt = std::max(bank.preAllowedAt,
1000                                     dram_pkt->readyTime + tWR);
1001    }
1002
1003    // increment the bytes accessed and the accesses per row
1004    bank.bytesAccessed += burstSize;
1005    ++bank.rowAccesses;
1006
1007    // if we reached the max, then issue with an auto-precharge
1008    bool auto_precharge = pageMgmt == Enums::close ||
1009        bank.rowAccesses == maxAccessesPerRow;
1010
1011    // if we did not hit the limit, we might still want to
1012    // auto-precharge
1013    if (!auto_precharge &&
1014        (pageMgmt == Enums::open_adaptive ||
1015         pageMgmt == Enums::close_adaptive)) {
1016        // a twist on the open and close page policies:
1017        // 1) open_adaptive page policy does not blindly keep the
1018        // page open, but close it if there are no row hits, and there
1019        // are bank conflicts in the queue
1020        // 2) close_adaptive page policy does not blindly close the
1021        // page, but closes it only if there are no row hits in the queue.
1022        // In this case, only force an auto precharge when there
1023        // are no same page hits in the queue
1024        bool got_more_hits = false;
1025        bool got_bank_conflict = false;
1026
1027        // either look at the read queue or write queue
1028        const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue :
1029            writeQueue;
1030        auto p = queue.begin();
1031        // make sure we are not considering the packet that we are
1032        // currently dealing with (which is the head of the queue)
1033        ++p;
1034
1035        // keep on looking until we have found required condition or
1036        // reached the end
1037        while (!(got_more_hits &&
1038                 (got_bank_conflict || pageMgmt == Enums::close_adaptive)) &&
1039               p != queue.end()) {
1040            bool same_rank_bank = (dram_pkt->rank == (*p)->rank) &&
1041                (dram_pkt->bank == (*p)->bank);
1042            bool same_row = dram_pkt->row == (*p)->row;
1043            got_more_hits |= same_rank_bank && same_row;
1044            got_bank_conflict |= same_rank_bank && !same_row;
1045            ++p;
1046        }
1047
1048        // auto pre-charge when either
1049        // 1) open_adaptive policy, we have not got any more hits, and
1050        //    have a bank conflict
1051        // 2) close_adaptive policy and we have not got any more hits
1052        auto_precharge = !got_more_hits &&
1053            (got_bank_conflict || pageMgmt == Enums::close_adaptive);
1054    }
1055
1056    // if this access should use auto-precharge, then we are
1057    // closing the row
1058    if (auto_precharge) {
1059        prechargeBank(bank, std::max(curTick(), bank.preAllowedAt));
1060
1061        DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId);
1062    }
1063
1064    // Update bus state
1065    busBusyUntil = dram_pkt->readyTime;
1066
1067    DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n",
1068            dram_pkt->addr, dram_pkt->readyTime, busBusyUntil);
1069
1070    // Update the minimum timing between the requests, this is a
1071    // conservative estimate of when we have to schedule the next
1072    // request to not introduce any unecessary bubbles. In most cases
1073    // we will wake up sooner than we have to.
1074    nextReqTime = busBusyUntil - (tRP + tRCD + tCL);
1075
1076    // Update the stats and schedule the next request
1077    if (dram_pkt->isRead) {
1078        ++readsThisTime;
1079        if (row_hit)
1080            readRowHits++;
1081        bytesReadDRAM += burstSize;
1082        perBankRdBursts[dram_pkt->bankId]++;
1083
1084        // Update latency stats
1085        totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime;
1086        totBusLat += tBURST;
1087        totQLat += cmd_at - dram_pkt->entryTime;
1088    } else {
1089        ++writesThisTime;
1090        if (row_hit)
1091            writeRowHits++;
1092        bytesWritten += burstSize;
1093        perBankWrBursts[dram_pkt->bankId]++;
1094    }
1095}
1096
1097void
1098DRAMCtrl::moveToRespQ()
1099{
1100    // Remove from read queue
1101    DRAMPacket* dram_pkt = readQueue.front();
1102    readQueue.pop_front();
1103
1104    // sanity check
1105    assert(dram_pkt->size <= burstSize);
1106
1107    // Insert into response queue sorted by readyTime
1108    // It will be sent back to the requestor at its
1109    // readyTime
1110    if (respQueue.empty()) {
1111        respQueue.push_front(dram_pkt);
1112        assert(!respondEvent.scheduled());
1113        assert(dram_pkt->readyTime >= curTick());
1114        schedule(respondEvent, dram_pkt->readyTime);
1115    } else {
1116        bool done = false;
1117        auto i = respQueue.begin();
1118        while (!done && i != respQueue.end()) {
1119            if ((*i)->readyTime > dram_pkt->readyTime) {
1120                respQueue.insert(i, dram_pkt);
1121                done = true;
1122            }
1123            ++i;
1124        }
1125
1126        if (!done)
1127            respQueue.push_back(dram_pkt);
1128
1129        assert(respondEvent.scheduled());
1130
1131        if (respQueue.front()->readyTime < respondEvent.when()) {
1132            assert(respQueue.front()->readyTime >= curTick());
1133            reschedule(respondEvent, respQueue.front()->readyTime);
1134        }
1135    }
1136}
1137
1138void
1139DRAMCtrl::processNextReqEvent()
1140{
1141    if (busState == READ_TO_WRITE) {
1142        DPRINTF(DRAM, "Switching to writes after %d reads with %d reads "
1143                "waiting\n", readsThisTime, readQueue.size());
1144
1145        // sample and reset the read-related stats as we are now
1146        // transitioning to writes, and all reads are done
1147        rdPerTurnAround.sample(readsThisTime);
1148        readsThisTime = 0;
1149
1150        // now proceed to do the actual writes
1151        busState = WRITE;
1152    } else if (busState == WRITE_TO_READ) {
1153        DPRINTF(DRAM, "Switching to reads after %d writes with %d writes "
1154                "waiting\n", writesThisTime, writeQueue.size());
1155
1156        wrPerTurnAround.sample(writesThisTime);
1157        writesThisTime = 0;
1158
1159        busState = READ;
1160    }
1161
1162    if (refreshState != REF_IDLE) {
1163        // if a refresh waiting for this event loop to finish, then hand
1164        // over now, and do not schedule a new nextReqEvent
1165        if (refreshState == REF_DRAIN) {
1166            DPRINTF(DRAM, "Refresh drain done, now precharging\n");
1167
1168            refreshState = REF_PRE;
1169
1170            // hand control back to the refresh event loop
1171            schedule(refreshEvent, curTick());
1172        }
1173
1174        // let the refresh finish before issuing any further requests
1175        return;
1176    }
1177
1178    // when we get here it is either a read or a write
1179    if (busState == READ) {
1180
1181        // track if we should switch or not
1182        bool switch_to_writes = false;
1183
1184        if (readQueue.empty()) {
1185            // In the case there is no read request to go next,
1186            // trigger writes if we have passed the low threshold (or
1187            // if we are draining)
1188            if (!writeQueue.empty() &&
1189                (drainManager || writeQueue.size() > writeLowThreshold)) {
1190
1191                switch_to_writes = true;
1192            } else {
1193                // check if we are drained
1194                if (respQueue.empty () && drainManager) {
1195                    drainManager->signalDrainDone();
1196                    drainManager = NULL;
1197                }
1198
1199                // nothing to do, not even any point in scheduling an
1200                // event for the next request
1201                return;
1202            }
1203        } else {
1204            // Figure out which read request goes next, and move it to the
1205            // front of the read queue
1206            chooseNext(readQueue);
1207
1208            doDRAMAccess(readQueue.front());
1209
1210            // At this point we're done dealing with the request
1211            // It will be moved to a separate response queue with a
1212            // correct readyTime, and eventually be sent back at that
1213            // time
1214            moveToRespQ();
1215
1216            // we have so many writes that we have to transition
1217            if (writeQueue.size() > writeHighThreshold) {
1218                switch_to_writes = true;
1219            }
1220        }
1221
1222        // switching to writes, either because the read queue is empty
1223        // and the writes have passed the low threshold (or we are
1224        // draining), or because the writes hit the hight threshold
1225        if (switch_to_writes) {
1226            // transition to writing
1227            busState = READ_TO_WRITE;
1228
1229            // add a bubble to the data bus, as defined by the
1230            // tRTW parameter
1231            busBusyUntil += tRTW;
1232
1233            // update the minimum timing between the requests,
1234            // this shifts us back in time far enough to do any
1235            // bank preparation
1236            nextReqTime = busBusyUntil - (tRP + tRCD + tCL);
1237        }
1238    } else {
1239        chooseNext(writeQueue);
1240        DRAMPacket* dram_pkt = writeQueue.front();
1241        // sanity check
1242        assert(dram_pkt->size <= burstSize);
1243        doDRAMAccess(dram_pkt);
1244
1245        writeQueue.pop_front();
1246        delete dram_pkt;
1247
1248        // If we emptied the write queue, or got sufficiently below the
1249        // threshold (using the minWritesPerSwitch as the hysteresis) and
1250        // are not draining, or we have reads waiting and have done enough
1251        // writes, then switch to reads.
1252        if (writeQueue.empty() ||
1253            (writeQueue.size() + minWritesPerSwitch < writeLowThreshold &&
1254             !drainManager) ||
1255            (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) {
1256            // turn the bus back around for reads again
1257            busState = WRITE_TO_READ;
1258
1259            // note that the we switch back to reads also in the idle
1260            // case, which eventually will check for any draining and
1261            // also pause any further scheduling if there is really
1262            // nothing to do
1263
1264            // here we get a bit creative and shift the bus busy time not
1265            // just the tWTR, but also a CAS latency to capture the fact
1266            // that we are allowed to prepare a new bank, but not issue a
1267            // read command until after tWTR, in essence we capture a
1268            // bubble on the data bus that is tWTR + tCL
1269            busBusyUntil += tWTR + tCL;
1270
1271            // update the minimum timing between the requests, this shifts
1272            // us back in time far enough to do any bank preparation
1273            nextReqTime = busBusyUntil - (tRP + tRCD + tCL);
1274        }
1275    }
1276
1277    schedule(nextReqEvent, std::max(nextReqTime, curTick()));
1278
1279    // If there is space available and we have writes waiting then let
1280    // them retry. This is done here to ensure that the retry does not
1281    // cause a nextReqEvent to be scheduled before we do so as part of
1282    // the next request processing
1283    if (retryWrReq && writeQueue.size() < writeBufferSize) {
1284        retryWrReq = false;
1285        port.sendRetry();
1286    }
1287}
1288
1289uint64_t
1290DRAMCtrl::minBankActAt(const deque<DRAMPacket*>& queue) const
1291{
1292    uint64_t bank_mask = 0;
1293    Tick min_act_at = MaxTick;
1294
1295    // deterimne if we have queued transactions targetting a
1296    // bank in question
1297    vector<bool> got_waiting(ranksPerChannel * banksPerRank, false);
1298    for (auto p = queue.begin(); p != queue.end(); ++p) {
1299        got_waiting[(*p)->bankId] = true;
1300    }
1301
1302    for (int i = 0; i < ranksPerChannel; i++) {
1303        for (int j = 0; j < banksPerRank; j++) {
1304            uint8_t bank_id = i * banksPerRank + j;
1305
1306            // if we have waiting requests for the bank, and it is
1307            // amongst the first available, update the mask
1308            if (got_waiting[bank_id]) {
1309                // simplistic approximation of when the bank can issue
1310                // an activate, ignoring any rank-to-rank switching
1311                // cost
1312                Tick act_at = banks[i][j].openRow == Bank::NO_ROW ?
1313                    banks[i][j].actAllowedAt :
1314                    std::max(banks[i][j].preAllowedAt, curTick()) + tRP;
1315
1316                if (act_at <= min_act_at) {
1317                    // reset bank mask if new minimum is found
1318                    if (act_at < min_act_at)
1319                        bank_mask = 0;
1320                    // set the bit corresponding to the available bank
1321                    replaceBits(bank_mask, bank_id, bank_id, 1);
1322                    min_act_at = act_at;
1323                }
1324            }
1325        }
1326    }
1327
1328    return bank_mask;
1329}
1330
1331void
1332DRAMCtrl::processRefreshEvent()
1333{
1334    // when first preparing the refresh, remember when it was due
1335    if (refreshState == REF_IDLE) {
1336        // remember when the refresh is due
1337        refreshDueAt = curTick();
1338
1339        // proceed to drain
1340        refreshState = REF_DRAIN;
1341
1342        DPRINTF(DRAM, "Refresh due\n");
1343    }
1344
1345    // let any scheduled read or write go ahead, after which it will
1346    // hand control back to this event loop
1347    if (refreshState == REF_DRAIN) {
1348        if (nextReqEvent.scheduled()) {
1349            // hand control over to the request loop until it is
1350            // evaluated next
1351            DPRINTF(DRAM, "Refresh awaiting draining\n");
1352
1353            return;
1354        } else {
1355            refreshState = REF_PRE;
1356        }
1357    }
1358
1359    // at this point, ensure that all banks are precharged
1360    if (refreshState == REF_PRE) {
1361        // precharge any active bank if we are not already in the idle
1362        // state
1363        if (pwrState != PWR_IDLE) {
1364            DPRINTF(DRAM, "Precharging all\n");
1365            for (int i = 0; i < ranksPerChannel; i++) {
1366                for (int j = 0; j < banksPerRank; j++) {
1367                    if (banks[i][j].openRow != Bank::NO_ROW) {
1368                        // respect both causality and any existing bank
1369                        // constraints
1370                        Tick pre_at = std::max(banks[i][j].preAllowedAt,
1371                                                curTick());
1372
1373                        prechargeBank(banks[i][j], pre_at);
1374                    }
1375                }
1376            }
1377        } else {
1378            DPRINTF(DRAM, "All banks already precharged, starting refresh\n");
1379
1380            // go ahead and kick the power state machine into gear if
1381            // we are already idle
1382            schedulePowerEvent(PWR_REF, curTick());
1383        }
1384
1385        refreshState = REF_RUN;
1386        assert(numBanksActive == 0);
1387
1388        // wait for all banks to be precharged, at which point the
1389        // power state machine will transition to the idle state, and
1390        // automatically move to a refresh, at that point it will also
1391        // call this method to get the refresh event loop going again
1392        return;
1393    }
1394
1395    // last but not least we perform the actual refresh
1396    if (refreshState == REF_RUN) {
1397        // should never get here with any banks active
1398        assert(numBanksActive == 0);
1399        assert(pwrState == PWR_REF);
1400
1401        Tick ref_done_at = curTick() + tRFC;
1402
1403        for (int i = 0; i < ranksPerChannel; i++) {
1404            for (int j = 0; j < banksPerRank; j++) {
1405                banks[i][j].actAllowedAt = ref_done_at;
1406            }
1407        }
1408
1409        // make sure we did not wait so long that we cannot make up
1410        // for it
1411        if (refreshDueAt + tREFI < ref_done_at) {
1412            fatal("Refresh was delayed so long we cannot catch up\n");
1413        }
1414
1415        // compensate for the delay in actually performing the refresh
1416        // when scheduling the next one
1417        schedule(refreshEvent, refreshDueAt + tREFI - tRP);
1418
1419        assert(!powerEvent.scheduled());
1420
1421        // move to the idle power state once the refresh is done, this
1422        // will also move the refresh state machine to the refresh
1423        // idle state
1424        schedulePowerEvent(PWR_IDLE, ref_done_at);
1425
1426        DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n",
1427                ref_done_at, refreshDueAt + tREFI);
1428    }
1429}
1430
1431void
1432DRAMCtrl::schedulePowerEvent(PowerState pwr_state, Tick tick)
1433{
1434    // respect causality
1435    assert(tick >= curTick());
1436
1437    if (!powerEvent.scheduled()) {
1438        DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n",
1439                tick, pwr_state);
1440
1441        // insert the new transition
1442        pwrStateTrans = pwr_state;
1443
1444        schedule(powerEvent, tick);
1445    } else {
1446        panic("Scheduled power event at %llu to state %d, "
1447              "with scheduled event at %llu to %d\n", tick, pwr_state,
1448              powerEvent.when(), pwrStateTrans);
1449    }
1450}
1451
1452void
1453DRAMCtrl::processPowerEvent()
1454{
1455    // remember where we were, and for how long
1456    Tick duration = curTick() - pwrStateTick;
1457    PowerState prev_state = pwrState;
1458
1459    // update the accounting
1460    pwrStateTime[prev_state] += duration;
1461
1462    pwrState = pwrStateTrans;
1463    pwrStateTick = curTick();
1464
1465    if (pwrState == PWR_IDLE) {
1466        DPRINTF(DRAMState, "All banks precharged\n");
1467
1468        // if we were refreshing, make sure we start scheduling requests again
1469        if (prev_state == PWR_REF) {
1470            DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration);
1471            assert(pwrState == PWR_IDLE);
1472
1473            // kick things into action again
1474            refreshState = REF_IDLE;
1475            assert(!nextReqEvent.scheduled());
1476            schedule(nextReqEvent, curTick());
1477        } else {
1478            assert(prev_state == PWR_ACT);
1479
1480            // if we have a pending refresh, and are now moving to
1481            // the idle state, direclty transition to a refresh
1482            if (refreshState == REF_RUN) {
1483                // there should be nothing waiting at this point
1484                assert(!powerEvent.scheduled());
1485
1486                // update the state in zero time and proceed below
1487                pwrState = PWR_REF;
1488            }
1489        }
1490    }
1491
1492    // we transition to the refresh state, let the refresh state
1493    // machine know of this state update and let it deal with the
1494    // scheduling of the next power state transition as well as the
1495    // following refresh
1496    if (pwrState == PWR_REF) {
1497        DPRINTF(DRAMState, "Refreshing\n");
1498        // kick the refresh event loop into action again, and that
1499        // in turn will schedule a transition to the idle power
1500        // state once the refresh is done
1501        assert(refreshState == REF_RUN);
1502        processRefreshEvent();
1503    }
1504}
1505
1506void
1507DRAMCtrl::regStats()
1508{
1509    using namespace Stats;
1510
1511    AbstractMemory::regStats();
1512
1513    readReqs
1514        .name(name() + ".readReqs")
1515        .desc("Number of read requests accepted");
1516
1517    writeReqs
1518        .name(name() + ".writeReqs")
1519        .desc("Number of write requests accepted");
1520
1521    readBursts
1522        .name(name() + ".readBursts")
1523        .desc("Number of DRAM read bursts, "
1524              "including those serviced by the write queue");
1525
1526    writeBursts
1527        .name(name() + ".writeBursts")
1528        .desc("Number of DRAM write bursts, "
1529              "including those merged in the write queue");
1530
1531    servicedByWrQ
1532        .name(name() + ".servicedByWrQ")
1533        .desc("Number of DRAM read bursts serviced by the write queue");
1534
1535    mergedWrBursts
1536        .name(name() + ".mergedWrBursts")
1537        .desc("Number of DRAM write bursts merged with an existing one");
1538
1539    neitherReadNorWrite
1540        .name(name() + ".neitherReadNorWriteReqs")
1541        .desc("Number of requests that are neither read nor write");
1542
1543    perBankRdBursts
1544        .init(banksPerRank * ranksPerChannel)
1545        .name(name() + ".perBankRdBursts")
1546        .desc("Per bank write bursts");
1547
1548    perBankWrBursts
1549        .init(banksPerRank * ranksPerChannel)
1550        .name(name() + ".perBankWrBursts")
1551        .desc("Per bank write bursts");
1552
1553    avgRdQLen
1554        .name(name() + ".avgRdQLen")
1555        .desc("Average read queue length when enqueuing")
1556        .precision(2);
1557
1558    avgWrQLen
1559        .name(name() + ".avgWrQLen")
1560        .desc("Average write queue length when enqueuing")
1561        .precision(2);
1562
1563    totQLat
1564        .name(name() + ".totQLat")
1565        .desc("Total ticks spent queuing");
1566
1567    totBusLat
1568        .name(name() + ".totBusLat")
1569        .desc("Total ticks spent in databus transfers");
1570
1571    totMemAccLat
1572        .name(name() + ".totMemAccLat")
1573        .desc("Total ticks spent from burst creation until serviced "
1574              "by the DRAM");
1575
1576    avgQLat
1577        .name(name() + ".avgQLat")
1578        .desc("Average queueing delay per DRAM burst")
1579        .precision(2);
1580
1581    avgQLat = totQLat / (readBursts - servicedByWrQ);
1582
1583    avgBusLat
1584        .name(name() + ".avgBusLat")
1585        .desc("Average bus latency per DRAM burst")
1586        .precision(2);
1587
1588    avgBusLat = totBusLat / (readBursts - servicedByWrQ);
1589
1590    avgMemAccLat
1591        .name(name() + ".avgMemAccLat")
1592        .desc("Average memory access latency per DRAM burst")
1593        .precision(2);
1594
1595    avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ);
1596
1597    numRdRetry
1598        .name(name() + ".numRdRetry")
1599        .desc("Number of times read queue was full causing retry");
1600
1601    numWrRetry
1602        .name(name() + ".numWrRetry")
1603        .desc("Number of times write queue was full causing retry");
1604
1605    readRowHits
1606        .name(name() + ".readRowHits")
1607        .desc("Number of row buffer hits during reads");
1608
1609    writeRowHits
1610        .name(name() + ".writeRowHits")
1611        .desc("Number of row buffer hits during writes");
1612
1613    readRowHitRate
1614        .name(name() + ".readRowHitRate")
1615        .desc("Row buffer hit rate for reads")
1616        .precision(2);
1617
1618    readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100;
1619
1620    writeRowHitRate
1621        .name(name() + ".writeRowHitRate")
1622        .desc("Row buffer hit rate for writes")
1623        .precision(2);
1624
1625    writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100;
1626
1627    readPktSize
1628        .init(ceilLog2(burstSize) + 1)
1629        .name(name() + ".readPktSize")
1630        .desc("Read request sizes (log2)");
1631
1632     writePktSize
1633        .init(ceilLog2(burstSize) + 1)
1634        .name(name() + ".writePktSize")
1635        .desc("Write request sizes (log2)");
1636
1637     rdQLenPdf
1638        .init(readBufferSize)
1639        .name(name() + ".rdQLenPdf")
1640        .desc("What read queue length does an incoming req see");
1641
1642     wrQLenPdf
1643        .init(writeBufferSize)
1644        .name(name() + ".wrQLenPdf")
1645        .desc("What write queue length does an incoming req see");
1646
1647     bytesPerActivate
1648         .init(maxAccessesPerRow)
1649         .name(name() + ".bytesPerActivate")
1650         .desc("Bytes accessed per row activation")
1651         .flags(nozero);
1652
1653     rdPerTurnAround
1654         .init(readBufferSize)
1655         .name(name() + ".rdPerTurnAround")
1656         .desc("Reads before turning the bus around for writes")
1657         .flags(nozero);
1658
1659     wrPerTurnAround
1660         .init(writeBufferSize)
1661         .name(name() + ".wrPerTurnAround")
1662         .desc("Writes before turning the bus around for reads")
1663         .flags(nozero);
1664
1665    bytesReadDRAM
1666        .name(name() + ".bytesReadDRAM")
1667        .desc("Total number of bytes read from DRAM");
1668
1669    bytesReadWrQ
1670        .name(name() + ".bytesReadWrQ")
1671        .desc("Total number of bytes read from write queue");
1672
1673    bytesWritten
1674        .name(name() + ".bytesWritten")
1675        .desc("Total number of bytes written to DRAM");
1676
1677    bytesReadSys
1678        .name(name() + ".bytesReadSys")
1679        .desc("Total read bytes from the system interface side");
1680
1681    bytesWrittenSys
1682        .name(name() + ".bytesWrittenSys")
1683        .desc("Total written bytes from the system interface side");
1684
1685    avgRdBW
1686        .name(name() + ".avgRdBW")
1687        .desc("Average DRAM read bandwidth in MiByte/s")
1688        .precision(2);
1689
1690    avgRdBW = (bytesReadDRAM / 1000000) / simSeconds;
1691
1692    avgWrBW
1693        .name(name() + ".avgWrBW")
1694        .desc("Average achieved write bandwidth in MiByte/s")
1695        .precision(2);
1696
1697    avgWrBW = (bytesWritten / 1000000) / simSeconds;
1698
1699    avgRdBWSys
1700        .name(name() + ".avgRdBWSys")
1701        .desc("Average system read bandwidth in MiByte/s")
1702        .precision(2);
1703
1704    avgRdBWSys = (bytesReadSys / 1000000) / simSeconds;
1705
1706    avgWrBWSys
1707        .name(name() + ".avgWrBWSys")
1708        .desc("Average system write bandwidth in MiByte/s")
1709        .precision(2);
1710
1711    avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds;
1712
1713    peakBW
1714        .name(name() + ".peakBW")
1715        .desc("Theoretical peak bandwidth in MiByte/s")
1716        .precision(2);
1717
1718    peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000;
1719
1720    busUtil
1721        .name(name() + ".busUtil")
1722        .desc("Data bus utilization in percentage")
1723        .precision(2);
1724
1725    busUtil = (avgRdBW + avgWrBW) / peakBW * 100;
1726
1727    totGap
1728        .name(name() + ".totGap")
1729        .desc("Total gap between requests");
1730
1731    avgGap
1732        .name(name() + ".avgGap")
1733        .desc("Average gap between requests")
1734        .precision(2);
1735
1736    avgGap = totGap / (readReqs + writeReqs);
1737
1738    // Stats for DRAM Power calculation based on Micron datasheet
1739    busUtilRead
1740        .name(name() + ".busUtilRead")
1741        .desc("Data bus utilization in percentage for reads")
1742        .precision(2);
1743
1744    busUtilRead = avgRdBW / peakBW * 100;
1745
1746    busUtilWrite
1747        .name(name() + ".busUtilWrite")
1748        .desc("Data bus utilization in percentage for writes")
1749        .precision(2);
1750
1751    busUtilWrite = avgWrBW / peakBW * 100;
1752
1753    pageHitRate
1754        .name(name() + ".pageHitRate")
1755        .desc("Row buffer hit rate, read and write combined")
1756        .precision(2);
1757
1758    pageHitRate = (writeRowHits + readRowHits) /
1759        (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100;
1760
1761    pwrStateTime
1762        .init(5)
1763        .name(name() + ".memoryStateTime")
1764        .desc("Time in different power states");
1765    pwrStateTime.subname(0, "IDLE");
1766    pwrStateTime.subname(1, "REF");
1767    pwrStateTime.subname(2, "PRE_PDN");
1768    pwrStateTime.subname(3, "ACT");
1769    pwrStateTime.subname(4, "ACT_PDN");
1770}
1771
1772void
1773DRAMCtrl::recvFunctional(PacketPtr pkt)
1774{
1775    // rely on the abstract memory
1776    functionalAccess(pkt);
1777}
1778
1779BaseSlavePort&
1780DRAMCtrl::getSlavePort(const string &if_name, PortID idx)
1781{
1782    if (if_name != "port") {
1783        return MemObject::getSlavePort(if_name, idx);
1784    } else {
1785        return port;
1786    }
1787}
1788
1789unsigned int
1790DRAMCtrl::drain(DrainManager *dm)
1791{
1792    unsigned int count = port.drain(dm);
1793
1794    // if there is anything in any of our internal queues, keep track
1795    // of that as well
1796    if (!(writeQueue.empty() && readQueue.empty() &&
1797          respQueue.empty())) {
1798        DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d,"
1799                " resp: %d\n", writeQueue.size(), readQueue.size(),
1800                respQueue.size());
1801        ++count;
1802        drainManager = dm;
1803
1804        // the only part that is not drained automatically over time
1805        // is the write queue, thus kick things into action if needed
1806        if (!writeQueue.empty() && !nextReqEvent.scheduled()) {
1807            schedule(nextReqEvent, curTick());
1808        }
1809    }
1810
1811    if (count)
1812        setDrainState(Drainable::Draining);
1813    else
1814        setDrainState(Drainable::Drained);
1815    return count;
1816}
1817
1818DRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory)
1819    : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this),
1820      memory(_memory)
1821{ }
1822
1823AddrRangeList
1824DRAMCtrl::MemoryPort::getAddrRanges() const
1825{
1826    AddrRangeList ranges;
1827    ranges.push_back(memory.getAddrRange());
1828    return ranges;
1829}
1830
1831void
1832DRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt)
1833{
1834    pkt->pushLabel(memory.name());
1835
1836    if (!queue.checkFunctional(pkt)) {
1837        // Default implementation of SimpleTimingPort::recvFunctional()
1838        // calls recvAtomic() and throws away the latency; we can save a
1839        // little here by just not calculating the latency.
1840        memory.recvFunctional(pkt);
1841    }
1842
1843    pkt->popLabel();
1844}
1845
1846Tick
1847DRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt)
1848{
1849    return memory.recvAtomic(pkt);
1850}
1851
1852bool
1853DRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt)
1854{
1855    // pass it to the memory controller
1856    return memory.recvTimingReq(pkt);
1857}
1858
1859DRAMCtrl*
1860DRAMCtrlParams::create()
1861{
1862    return new DRAMCtrl(this);
1863}
1864