dram_ctrl.cc revision 9965
1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2013 Amin Farmahini-Farahani 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Andreas Hansson 41 * Ani Udipi 42 */ 43 44#include "base/trace.hh" 45#include "debug/Drain.hh" 46#include "debug/DRAM.hh" 47#include "debug/DRAMWR.hh" 48#include "mem/simple_dram.hh" 49#include "sim/system.hh" 50 51using namespace std; 52 53SimpleDRAM::SimpleDRAM(const SimpleDRAMParams* p) : 54 AbstractMemory(p), 55 port(name() + ".port", *this), 56 retryRdReq(false), retryWrReq(false), 57 rowHitFlag(false), stopReads(false), actTicks(p->activation_limit, 0), 58 writeEvent(this), respondEvent(this), 59 refreshEvent(this), nextReqEvent(this), drainManager(NULL), 60 deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 61 deviceRowBufferSize(p->device_rowbuffer_size), 62 devicesPerRank(p->devices_per_rank), 63 burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 64 rowBufferSize(devicesPerRank * deviceRowBufferSize), 65 ranksPerChannel(p->ranks_per_channel), 66 banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 67 readBufferSize(p->read_buffer_size), 68 writeBufferSize(p->write_buffer_size), 69 writeThresholdPerc(p->write_thresh_perc), 70 tWTR(p->tWTR), tBURST(p->tBURST), 71 tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), 72 tRFC(p->tRFC), tREFI(p->tREFI), 73 tXAW(p->tXAW), activationLimit(p->activation_limit), 74 memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 75 pageMgmt(p->page_policy), 76 frontendLatency(p->static_frontend_latency), 77 backendLatency(p->static_backend_latency), 78 busBusyUntil(0), writeStartTime(0), 79 prevArrival(0), numReqs(0) 80{ 81 // create the bank states based on the dimensions of the ranks and 82 // banks 83 banks.resize(ranksPerChannel); 84 for (size_t c = 0; c < ranksPerChannel; ++c) { 85 banks[c].resize(banksPerRank); 86 } 87 88 // round the write threshold percent to a whole number of entries 89 // in the buffer 90 writeThreshold = writeBufferSize * writeThresholdPerc / 100.0; 91} 92 93void 94SimpleDRAM::init() 95{ 96 if (!port.isConnected()) { 97 fatal("SimpleDRAM %s is unconnected!\n", name()); 98 } else { 99 port.sendRangeChange(); 100 } 101 102 // we could deal with plenty options here, but for now do a quick 103 // sanity check 104 DPRINTF(DRAM, "Burst size %d bytes\n", burstSize); 105 106 // determine the rows per bank by looking at the total capacity 107 uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 108 109 DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 110 AbstractMemory::size()); 111 112 columnsPerRowBuffer = rowBufferSize / burstSize; 113 114 DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 115 rowBufferSize, columnsPerRowBuffer); 116 117 rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 118 119 if (range.interleaved()) { 120 if (channels != range.stripes()) 121 panic("%s has %d interleaved address stripes but %d channel(s)\n", 122 name(), range.stripes(), channels); 123 124 if (addrMapping == Enums::RaBaChCo) { 125 if (rowBufferSize != range.granularity()) { 126 panic("Interleaving of %s doesn't match RaBaChCo address map\n", 127 name()); 128 } 129 } else if (addrMapping == Enums::RaBaCoCh) { 130 if (burstSize != range.granularity()) { 131 panic("Interleaving of %s doesn't match RaBaCoCh address map\n", 132 name()); 133 } 134 } else if (addrMapping == Enums::CoRaBaCh) { 135 if (burstSize != range.granularity()) 136 panic("Interleaving of %s doesn't match CoRaBaCh address map\n", 137 name()); 138 } 139 } 140} 141 142void 143SimpleDRAM::startup() 144{ 145 // print the configuration of the controller 146 printParams(); 147 148 // kick off the refresh 149 schedule(refreshEvent, curTick() + tREFI); 150} 151 152Tick 153SimpleDRAM::recvAtomic(PacketPtr pkt) 154{ 155 DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 156 157 // do the actual memory access and turn the packet into a response 158 access(pkt); 159 160 Tick latency = 0; 161 if (!pkt->memInhibitAsserted() && pkt->hasData()) { 162 // this value is not supposed to be accurate, just enough to 163 // keep things going, mimic a closed page 164 latency = tRP + tRCD + tCL; 165 } 166 return latency; 167} 168 169bool 170SimpleDRAM::readQueueFull(unsigned int neededEntries) const 171{ 172 DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 173 readBufferSize, readQueue.size() + respQueue.size(), 174 neededEntries); 175 176 return 177 (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 178} 179 180bool 181SimpleDRAM::writeQueueFull(unsigned int neededEntries) const 182{ 183 DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 184 writeBufferSize, writeQueue.size(), neededEntries); 185 return (writeQueue.size() + neededEntries) > writeBufferSize; 186} 187 188SimpleDRAM::DRAMPacket* 189SimpleDRAM::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size) 190{ 191 // decode the address based on the address mapping scheme, with 192 // Ra, Co, Ba and Ch denoting rank, column, bank and channel, 193 // respectively 194 uint8_t rank; 195 uint16_t bank; 196 uint16_t row; 197 198 // truncate the address to the access granularity 199 Addr addr = dramPktAddr / burstSize; 200 201 // we have removed the lowest order address bits that denote the 202 // position within the column 203 if (addrMapping == Enums::RaBaChCo) { 204 // the lowest order bits denote the column to ensure that 205 // sequential cache lines occupy the same row 206 addr = addr / columnsPerRowBuffer; 207 208 // take out the channel part of the address 209 addr = addr / channels; 210 211 // after the channel bits, get the bank bits to interleave 212 // over the banks 213 bank = addr % banksPerRank; 214 addr = addr / banksPerRank; 215 216 // after the bank, we get the rank bits which thus interleaves 217 // over the ranks 218 rank = addr % ranksPerChannel; 219 addr = addr / ranksPerChannel; 220 221 // lastly, get the row bits 222 row = addr % rowsPerBank; 223 addr = addr / rowsPerBank; 224 } else if (addrMapping == Enums::RaBaCoCh) { 225 // take out the channel part of the address 226 addr = addr / channels; 227 228 // next, the column 229 addr = addr / columnsPerRowBuffer; 230 231 // after the column bits, we get the bank bits to interleave 232 // over the banks 233 bank = addr % banksPerRank; 234 addr = addr / banksPerRank; 235 236 // after the bank, we get the rank bits which thus interleaves 237 // over the ranks 238 rank = addr % ranksPerChannel; 239 addr = addr / ranksPerChannel; 240 241 // lastly, get the row bits 242 row = addr % rowsPerBank; 243 addr = addr / rowsPerBank; 244 } else if (addrMapping == Enums::CoRaBaCh) { 245 // optimise for closed page mode and utilise maximum 246 // parallelism of the DRAM (at the cost of power) 247 248 // take out the channel part of the address, not that this has 249 // to match with how accesses are interleaved between the 250 // controllers in the address mapping 251 addr = addr / channels; 252 253 // start with the bank bits, as this provides the maximum 254 // opportunity for parallelism between requests 255 bank = addr % banksPerRank; 256 addr = addr / banksPerRank; 257 258 // next get the rank bits 259 rank = addr % ranksPerChannel; 260 addr = addr / ranksPerChannel; 261 262 // next the column bits which we do not need to keep track of 263 // and simply skip past 264 addr = addr / columnsPerRowBuffer; 265 266 // lastly, get the row bits 267 row = addr % rowsPerBank; 268 addr = addr / rowsPerBank; 269 } else 270 panic("Unknown address mapping policy chosen!"); 271 272 assert(rank < ranksPerChannel); 273 assert(bank < banksPerRank); 274 assert(row < rowsPerBank); 275 276 DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 277 dramPktAddr, rank, bank, row); 278 279 // create the corresponding DRAM packet with the entry time and 280 // ready time set to the current tick, the latter will be updated 281 // later 282 return new DRAMPacket(pkt, rank, bank, row, dramPktAddr, size, 283 banks[rank][bank]); 284} 285 286void 287SimpleDRAM::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 288{ 289 // only add to the read queue here. whenever the request is 290 // eventually done, set the readyTime, and call schedule() 291 assert(!pkt->isWrite()); 292 293 assert(pktCount != 0); 294 295 // if the request size is larger than burst size, the pkt is split into 296 // multiple DRAM packets 297 // Note if the pkt starting address is not aligened to burst size, the 298 // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 299 // are aligned to burst size boundaries. This is to ensure we accurately 300 // check read packets against packets in write queue. 301 Addr addr = pkt->getAddr(); 302 unsigned pktsServicedByWrQ = 0; 303 BurstHelper* burst_helper = NULL; 304 for (int cnt = 0; cnt < pktCount; ++cnt) { 305 unsigned size = std::min((addr | (burstSize - 1)) + 1, 306 pkt->getAddr() + pkt->getSize()) - addr; 307 readPktSize[ceilLog2(size)]++; 308 readBursts++; 309 310 // First check write buffer to see if the data is already at 311 // the controller 312 bool foundInWrQ = false; 313 for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) { 314 // check if the read is subsumed in the write entry we are 315 // looking at 316 if ((*i)->addr <= addr && 317 (addr + size) <= ((*i)->addr + (*i)->size)) { 318 foundInWrQ = true; 319 servicedByWrQ++; 320 pktsServicedByWrQ++; 321 DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 322 "write queue\n", addr, size); 323 bytesRead += burstSize; 324 bytesConsumedRd += size; 325 break; 326 } 327 } 328 329 // If not found in the write q, make a DRAM packet and 330 // push it onto the read queue 331 if (!foundInWrQ) { 332 333 // Make the burst helper for split packets 334 if (pktCount > 1 && burst_helper == NULL) { 335 DPRINTF(DRAM, "Read to addr %lld translates to %d " 336 "dram requests\n", pkt->getAddr(), pktCount); 337 burst_helper = new BurstHelper(pktCount); 338 } 339 340 DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size); 341 dram_pkt->burstHelper = burst_helper; 342 343 assert(!readQueueFull(1)); 344 rdQLenPdf[readQueue.size() + respQueue.size()]++; 345 346 DPRINTF(DRAM, "Adding to read queue\n"); 347 348 readQueue.push_back(dram_pkt); 349 350 // Update stats 351 uint32_t bank_id = banksPerRank * dram_pkt->rank + dram_pkt->bank; 352 assert(bank_id < ranksPerChannel * banksPerRank); 353 perBankRdReqs[bank_id]++; 354 355 avgRdQLen = readQueue.size() + respQueue.size(); 356 } 357 358 // Starting address of next dram pkt (aligend to burstSize boundary) 359 addr = (addr | (burstSize - 1)) + 1; 360 } 361 362 // If all packets are serviced by write queue, we send the repsonse back 363 if (pktsServicedByWrQ == pktCount) { 364 accessAndRespond(pkt, frontendLatency); 365 return; 366 } 367 368 // Update how many split packets are serviced by write queue 369 if (burst_helper != NULL) 370 burst_helper->burstsServiced = pktsServicedByWrQ; 371 372 // If we are not already scheduled to get the read request out of 373 // the queue, do so now 374 if (!nextReqEvent.scheduled() && !stopReads) { 375 DPRINTF(DRAM, "Request scheduled immediately\n"); 376 schedule(nextReqEvent, curTick()); 377 } 378} 379 380void 381SimpleDRAM::processWriteEvent() 382{ 383 assert(!writeQueue.empty()); 384 uint32_t numWritesThisTime = 0; 385 Tick actTick; 386 387 DPRINTF(DRAMWR, "Beginning DRAM Writes\n"); 388 Tick temp1 M5_VAR_USED = std::max(curTick(), busBusyUntil); 389 Tick temp2 M5_VAR_USED = std::max(curTick(), maxBankFreeAt()); 390 391 // @todo: are there any dangers with the untimed while loop? 392 while (!writeQueue.empty()) { 393 if (numWritesThisTime > writeThreshold) { 394 DPRINTF(DRAMWR, "Hit write threshold %d\n", writeThreshold); 395 break; 396 } 397 398 chooseNextWrite(); 399 DRAMPacket* dram_pkt = writeQueue.front(); 400 401 // sanity check 402 assert(dram_pkt->size <= burstSize); 403 404 // What's the earliest the request can be put on the bus 405 Tick schedTime = std::max(curTick(), busBusyUntil); 406 407 DPRINTF(DRAMWR, "Asking for latency estimate at %lld\n", 408 schedTime + tBURST); 409 410 pair<Tick, Tick> lat = estimateLatency(dram_pkt, schedTime + tBURST); 411 Tick accessLat = lat.second; 412 413 // look at the rowHitFlag set by estimateLatency 414 if (rowHitFlag) 415 writeRowHits++; 416 417 Bank& bank = dram_pkt->bank_ref; 418 419 if (pageMgmt == Enums::open) { 420 bank.openRow = dram_pkt->row; 421 bank.freeAt = schedTime + tBURST + std::max(accessLat, tCL); 422 busBusyUntil = bank.freeAt - tCL; 423 bank.bytesAccessed += burstSize; 424 425 if (!rowHitFlag) { 426 actTick = bank.freeAt - tCL - tRCD;//new row opened 427 bank.tRASDoneAt = actTick + tRAS; 428 recordActivate(actTick); 429 busBusyUntil = actTick; 430 431 // sample the number of bytes accessed and reset it as 432 // we are now closing this row 433 bytesPerActivate.sample(bank.bytesAccessed); 434 bank.bytesAccessed = 0; 435 } 436 } else if (pageMgmt == Enums::close) { 437 // All ticks waiting for a bank (if required) are included 438 // in accessLat 439 actTick = schedTime + tBURST + accessLat - tCL - tRCD; 440 recordActivate(actTick); 441 442 // If the DRAM has a very quick tRAS, bank can be made free 443 // after consecutive tCL,tRCD,tRP times. In general, however, 444 // an additional wait is required to respect tRAS. 445 bank.freeAt = std::max(actTick + tRAS + tRP, 446 actTick + tCL + tRCD + tRP); 447 448 //assuming that DRAM first gets write data, then activates 449 busBusyUntil = actTick; 450 DPRINTF(DRAMWR, "processWriteEvent::bank.freeAt for " 451 "banks_id %d is %lld\n", 452 dram_pkt->rank * banksPerRank + dram_pkt->bank, 453 bank.freeAt); 454 bytesPerActivate.sample(burstSize); 455 } else 456 panic("Unknown page management policy chosen\n"); 457 458 DPRINTF(DRAMWR, "Done writing to address %lld\n", dram_pkt->addr); 459 460 DPRINTF(DRAMWR, "schedtime is %lld, tBURST is %lld, " 461 "busbusyuntil is %lld\n", 462 schedTime, tBURST, busBusyUntil); 463 464 writeQueue.pop_front(); 465 delete dram_pkt; 466 467 numWritesThisTime++; 468 } 469 470 DPRINTF(DRAMWR, "Completed %d writes, bus busy for %lld ticks,"\ 471 "banks busy for %lld ticks\n", numWritesThisTime, 472 busBusyUntil - temp1, maxBankFreeAt() - temp2); 473 474 // Update stats 475 avgWrQLen = writeQueue.size(); 476 477 // turn the bus back around for reads again 478 busBusyUntil += tWTR; 479 stopReads = false; 480 481 if (retryWrReq) { 482 retryWrReq = false; 483 port.sendRetry(); 484 } 485 486 // if there is nothing left in any queue, signal a drain 487 if (writeQueue.empty() && readQueue.empty() && 488 respQueue.empty () && drainManager) { 489 drainManager->signalDrainDone(); 490 drainManager = NULL; 491 } 492 493 // Once you're done emptying the write queue, check if there's 494 // anything in the read queue, and call schedule if required. The 495 // retry above could already have caused it to be scheduled, so 496 // first check 497 if (!nextReqEvent.scheduled()) 498 schedule(nextReqEvent, busBusyUntil); 499} 500 501void 502SimpleDRAM::triggerWrites() 503{ 504 DPRINTF(DRAM, "Writes triggered at %lld\n", curTick()); 505 // Flag variable to stop any more read scheduling 506 stopReads = true; 507 508 writeStartTime = std::max(busBusyUntil, curTick()) + tWTR; 509 510 DPRINTF(DRAM, "Writes scheduled at %lld\n", writeStartTime); 511 512 assert(writeStartTime >= curTick()); 513 assert(!writeEvent.scheduled()); 514 schedule(writeEvent, writeStartTime); 515} 516 517void 518SimpleDRAM::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 519{ 520 // only add to the write queue here. whenever the request is 521 // eventually done, set the readyTime, and call schedule() 522 assert(pkt->isWrite()); 523 524 // if the request size is larger than burst size, the pkt is split into 525 // multiple DRAM packets 526 Addr addr = pkt->getAddr(); 527 for (int cnt = 0; cnt < pktCount; ++cnt) { 528 unsigned size = std::min((addr | (burstSize - 1)) + 1, 529 pkt->getAddr() + pkt->getSize()) - addr; 530 writePktSize[ceilLog2(size)]++; 531 writeBursts++; 532 533 // see if we can merge with an existing item in the write 534 // queue and keep track of whether we have merged or not so we 535 // can stop at that point and also avoid enqueueing a new 536 // request 537 bool merged = false; 538 auto w = writeQueue.begin(); 539 540 while(!merged && w != writeQueue.end()) { 541 // either of the two could be first, if they are the same 542 // it does not matter which way we go 543 if ((*w)->addr >= addr) { 544 // the existing one starts after the new one, figure 545 // out where the new one ends with respect to the 546 // existing one 547 if ((addr + size) >= ((*w)->addr + (*w)->size)) { 548 // check if the existing one is completely 549 // subsumed in the new one 550 DPRINTF(DRAM, "Merging write covering existing burst\n"); 551 merged = true; 552 // update both the address and the size 553 (*w)->addr = addr; 554 (*w)->size = size; 555 } else if ((addr + size) >= (*w)->addr && 556 ((*w)->addr + (*w)->size - addr) <= burstSize) { 557 // the new one is just before or partially 558 // overlapping with the existing one, and together 559 // they fit within a burst 560 DPRINTF(DRAM, "Merging write before existing burst\n"); 561 merged = true; 562 // the existing queue item needs to be adjusted with 563 // respect to both address and size 564 (*w)->addr = addr; 565 (*w)->size = (*w)->addr + (*w)->size - addr; 566 } 567 } else { 568 // the new one starts after the current one, figure 569 // out where the existing one ends with respect to the 570 // new one 571 if (((*w)->addr + (*w)->size) >= (addr + size)) { 572 // check if the new one is completely subsumed in the 573 // existing one 574 DPRINTF(DRAM, "Merging write into existing burst\n"); 575 merged = true; 576 // no adjustments necessary 577 } else if (((*w)->addr + (*w)->size) >= addr && 578 (addr + size - (*w)->addr) <= burstSize) { 579 // the existing one is just before or partially 580 // overlapping with the new one, and together 581 // they fit within a burst 582 DPRINTF(DRAM, "Merging write after existing burst\n"); 583 merged = true; 584 // the address is right, and only the size has 585 // to be adjusted 586 (*w)->size = addr + size - (*w)->addr; 587 } 588 } 589 ++w; 590 } 591 592 // if the item was not merged we need to create a new write 593 // and enqueue it 594 if (!merged) { 595 DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size); 596 597 assert(writeQueue.size() < writeBufferSize); 598 wrQLenPdf[writeQueue.size()]++; 599 600 DPRINTF(DRAM, "Adding to write queue\n"); 601 602 writeQueue.push_back(dram_pkt); 603 604 // Update stats 605 uint32_t bank_id = banksPerRank * dram_pkt->rank + dram_pkt->bank; 606 assert(bank_id < ranksPerChannel * banksPerRank); 607 perBankWrReqs[bank_id]++; 608 609 avgWrQLen = writeQueue.size(); 610 } 611 612 bytesConsumedWr += size; 613 bytesWritten += burstSize; 614 615 // Starting address of next dram pkt (aligend to burstSize boundary) 616 addr = (addr | (burstSize - 1)) + 1; 617 } 618 619 // we do not wait for the writes to be send to the actual memory, 620 // but instead take responsibility for the consistency here and 621 // snoop the write queue for any upcoming reads 622 // @todo, if a pkt size is larger than burst size, we might need a 623 // different front end latency 624 accessAndRespond(pkt, frontendLatency); 625 626 // If your write buffer is starting to fill up, drain it! 627 if (writeQueue.size() > writeThreshold && !stopReads){ 628 triggerWrites(); 629 } 630} 631 632void 633SimpleDRAM::printParams() const 634{ 635 // Sanity check print of important parameters 636 DPRINTF(DRAM, 637 "Memory controller %s physical organization\n" \ 638 "Number of devices per rank %d\n" \ 639 "Device bus width (in bits) %d\n" \ 640 "DRAM data bus burst %d\n" \ 641 "Row buffer size %d\n" \ 642 "Columns per row buffer %d\n" \ 643 "Rows per bank %d\n" \ 644 "Banks per rank %d\n" \ 645 "Ranks per channel %d\n" \ 646 "Total mem capacity %u\n", 647 name(), devicesPerRank, deviceBusWidth, burstSize, rowBufferSize, 648 columnsPerRowBuffer, rowsPerBank, banksPerRank, ranksPerChannel, 649 rowBufferSize * rowsPerBank * banksPerRank * ranksPerChannel); 650 651 string scheduler = memSchedPolicy == Enums::fcfs ? "FCFS" : "FR-FCFS"; 652 string address_mapping = addrMapping == Enums::RaBaChCo ? "RaBaChCo" : 653 (addrMapping == Enums::RaBaCoCh ? "RaBaCoCh" : "CoRaBaCh"); 654 string page_policy = pageMgmt == Enums::open ? "OPEN" : "CLOSE"; 655 656 DPRINTF(DRAM, 657 "Memory controller %s characteristics\n" \ 658 "Read buffer size %d\n" \ 659 "Write buffer size %d\n" \ 660 "Write buffer thresh %d\n" \ 661 "Scheduler %s\n" \ 662 "Address mapping %s\n" \ 663 "Page policy %s\n", 664 name(), readBufferSize, writeBufferSize, writeThreshold, 665 scheduler, address_mapping, page_policy); 666 667 DPRINTF(DRAM, "Memory controller %s timing specs\n" \ 668 "tRCD %d ticks\n" \ 669 "tCL %d ticks\n" \ 670 "tRP %d ticks\n" \ 671 "tBURST %d ticks\n" \ 672 "tRFC %d ticks\n" \ 673 "tREFI %d ticks\n" \ 674 "tWTR %d ticks\n" \ 675 "tXAW (%d) %d ticks\n", 676 name(), tRCD, tCL, tRP, tBURST, tRFC, tREFI, tWTR, 677 activationLimit, tXAW); 678} 679 680void 681SimpleDRAM::printQs() const { 682 DPRINTF(DRAM, "===READ QUEUE===\n\n"); 683 for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 684 DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 685 } 686 DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 687 for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 688 DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 689 } 690 DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 691 for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 692 DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 693 } 694} 695 696bool 697SimpleDRAM::recvTimingReq(PacketPtr pkt) 698{ 699 /// @todo temporary hack to deal with memory corruption issues until 700 /// 4-phase transactions are complete 701 for (int x = 0; x < pendingDelete.size(); x++) 702 delete pendingDelete[x]; 703 pendingDelete.clear(); 704 705 // This is where we enter from the outside world 706 DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 707 pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 708 709 // simply drop inhibited packets for now 710 if (pkt->memInhibitAsserted()) { 711 DPRINTF(DRAM,"Inhibited packet -- Dropping it now\n"); 712 pendingDelete.push_back(pkt); 713 return true; 714 } 715 716 // Every million accesses, print the state of the queues 717 if (numReqs % 1000000 == 0) 718 printQs(); 719 720 // Calc avg gap between requests 721 if (prevArrival != 0) { 722 totGap += curTick() - prevArrival; 723 } 724 prevArrival = curTick(); 725 726 727 // Find out how many dram packets a pkt translates to 728 // If the burst size is equal or larger than the pkt size, then a pkt 729 // translates to only one dram packet. Otherwise, a pkt translates to 730 // multiple dram packets 731 unsigned size = pkt->getSize(); 732 unsigned offset = pkt->getAddr() & (burstSize - 1); 733 unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 734 735 // check local buffers and do not accept if full 736 if (pkt->isRead()) { 737 assert(size != 0); 738 if (readQueueFull(dram_pkt_count)) { 739 DPRINTF(DRAM, "Read queue full, not accepting\n"); 740 // remember that we have to retry this port 741 retryRdReq = true; 742 numRdRetry++; 743 return false; 744 } else { 745 addToReadQueue(pkt, dram_pkt_count); 746 readReqs++; 747 numReqs++; 748 } 749 } else if (pkt->isWrite()) { 750 assert(size != 0); 751 if (writeQueueFull(dram_pkt_count)) { 752 DPRINTF(DRAM, "Write queue full, not accepting\n"); 753 // remember that we have to retry this port 754 retryWrReq = true; 755 numWrRetry++; 756 return false; 757 } else { 758 addToWriteQueue(pkt, dram_pkt_count); 759 writeReqs++; 760 numReqs++; 761 } 762 } else { 763 DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 764 neitherReadNorWrite++; 765 accessAndRespond(pkt, 1); 766 } 767 768 retryRdReq = false; 769 retryWrReq = false; 770 return true; 771} 772 773void 774SimpleDRAM::processRespondEvent() 775{ 776 DPRINTF(DRAM, 777 "processRespondEvent(): Some req has reached its readyTime\n"); 778 779 DRAMPacket* dram_pkt = respQueue.front(); 780 781 // Actually responds to the requestor 782 bytesConsumedRd += dram_pkt->size; 783 bytesRead += burstSize; 784 if (dram_pkt->burstHelper) { 785 // it is a split packet 786 dram_pkt->burstHelper->burstsServiced++; 787 if (dram_pkt->burstHelper->burstsServiced == 788 dram_pkt->burstHelper->burstCount) { 789 // we have now serviced all children packets of a system packet 790 // so we can now respond to the requester 791 // @todo we probably want to have a different front end and back 792 // end latency for split packets 793 accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 794 delete dram_pkt->burstHelper; 795 dram_pkt->burstHelper = NULL; 796 } 797 } else { 798 // it is not a split packet 799 accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 800 } 801 802 delete respQueue.front(); 803 respQueue.pop_front(); 804 805 // Update stats 806 avgRdQLen = readQueue.size() + respQueue.size(); 807 808 if (!respQueue.empty()) { 809 assert(respQueue.front()->readyTime >= curTick()); 810 assert(!respondEvent.scheduled()); 811 schedule(respondEvent, respQueue.front()->readyTime); 812 } else { 813 // if there is nothing left in any queue, signal a drain 814 if (writeQueue.empty() && readQueue.empty() && 815 drainManager) { 816 drainManager->signalDrainDone(); 817 drainManager = NULL; 818 } 819 } 820 821 // We have made a location in the queue available at this point, 822 // so if there is a read that was forced to wait, retry now 823 if (retryRdReq) { 824 retryRdReq = false; 825 port.sendRetry(); 826 } 827} 828 829void 830SimpleDRAM::chooseNextWrite() 831{ 832 // This method does the arbitration between write requests. The 833 // chosen packet is simply moved to the head of the write 834 // queue. The other methods know that this is the place to 835 // look. For example, with FCFS, this method does nothing 836 assert(!writeQueue.empty()); 837 838 if (writeQueue.size() == 1) { 839 DPRINTF(DRAMWR, "Single write request, nothing to do\n"); 840 return; 841 } 842 843 if (memSchedPolicy == Enums::fcfs) { 844 // Do nothing, since the correct request is already head 845 } else if (memSchedPolicy == Enums::frfcfs) { 846 auto i = writeQueue.begin(); 847 bool foundRowHit = false; 848 while (!foundRowHit && i != writeQueue.end()) { 849 DRAMPacket* dram_pkt = *i; 850 const Bank& bank = dram_pkt->bank_ref; 851 if (bank.openRow == dram_pkt->row) { //FR part 852 DPRINTF(DRAMWR, "Write row buffer hit\n"); 853 writeQueue.erase(i); 854 writeQueue.push_front(dram_pkt); 855 foundRowHit = true; 856 } else { //FCFS part 857 ; 858 } 859 ++i; 860 } 861 } else 862 panic("No scheduling policy chosen\n"); 863 864 DPRINTF(DRAMWR, "Selected next write request\n"); 865} 866 867bool 868SimpleDRAM::chooseNextRead() 869{ 870 // This method does the arbitration between read requests. The 871 // chosen packet is simply moved to the head of the queue. The 872 // other methods know that this is the place to look. For example, 873 // with FCFS, this method does nothing 874 if (readQueue.empty()) { 875 DPRINTF(DRAM, "No read request to select\n"); 876 return false; 877 } 878 879 // If there is only one request then there is nothing left to do 880 if (readQueue.size() == 1) 881 return true; 882 883 if (memSchedPolicy == Enums::fcfs) { 884 // Do nothing, since the request to serve is already the first 885 // one in the read queue 886 } else if (memSchedPolicy == Enums::frfcfs) { 887 for (auto i = readQueue.begin(); i != readQueue.end() ; ++i) { 888 DRAMPacket* dram_pkt = *i; 889 const Bank& bank = dram_pkt->bank_ref; 890 // Check if it is a row hit 891 if (bank.openRow == dram_pkt->row) { //FR part 892 DPRINTF(DRAM, "Row buffer hit\n"); 893 readQueue.erase(i); 894 readQueue.push_front(dram_pkt); 895 break; 896 } else { //FCFS part 897 ; 898 } 899 } 900 } else 901 panic("No scheduling policy chosen!\n"); 902 903 DPRINTF(DRAM, "Selected next read request\n"); 904 return true; 905} 906 907void 908SimpleDRAM::accessAndRespond(PacketPtr pkt, Tick static_latency) 909{ 910 DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 911 912 bool needsResponse = pkt->needsResponse(); 913 // do the actual memory access which also turns the packet into a 914 // response 915 access(pkt); 916 917 // turn packet around to go back to requester if response expected 918 if (needsResponse) { 919 // access already turned the packet into a response 920 assert(pkt->isResponse()); 921 922 // @todo someone should pay for this 923 pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; 924 925 // queue the packet in the response queue to be sent out after 926 // the static latency has passed 927 port.schedTimingResp(pkt, curTick() + static_latency); 928 } else { 929 // @todo the packet is going to be deleted, and the DRAMPacket 930 // is still having a pointer to it 931 pendingDelete.push_back(pkt); 932 } 933 934 DPRINTF(DRAM, "Done\n"); 935 936 return; 937} 938 939pair<Tick, Tick> 940SimpleDRAM::estimateLatency(DRAMPacket* dram_pkt, Tick inTime) 941{ 942 // If a request reaches a bank at tick 'inTime', how much time 943 // *after* that does it take to finish the request, depending 944 // on bank status and page open policy. Note that this method 945 // considers only the time taken for the actual read or write 946 // to complete, NOT any additional time thereafter for tRAS or 947 // tRP. 948 Tick accLat = 0; 949 Tick bankLat = 0; 950 rowHitFlag = false; 951 952 const Bank& bank = dram_pkt->bank_ref; 953 if (pageMgmt == Enums::open) { // open-page policy 954 if (bank.openRow == dram_pkt->row) { 955 // When we have a row-buffer hit, 956 // we don't care about tRAS having expired or not, 957 // but do care about bank being free for access 958 rowHitFlag = true; 959 960 // When a series of requests arrive to the same row, 961 // DDR systems are capable of streaming data continuously 962 // at maximum bandwidth (subject to tCCD). Here, we approximate 963 // this condition, and assume that if whenever a bank is already 964 // busy and a new request comes in, it can be completed with no 965 // penalty beyond waiting for the existing read to complete. 966 if (bank.freeAt > inTime) { 967 accLat += bank.freeAt - inTime; 968 bankLat += tBURST; 969 } else { 970 // CAS latency only 971 accLat += tCL; 972 bankLat += tCL; 973 } 974 975 } else { 976 // Row-buffer miss, need to close existing row 977 // once tRAS has expired, then open the new one, 978 // then add cas latency. 979 Tick freeTime = std::max(bank.tRASDoneAt, bank.freeAt); 980 981 if (freeTime > inTime) 982 accLat += freeTime - inTime; 983 984 accLat += tRP + tRCD + tCL; 985 bankLat += tRP + tRCD + tCL; 986 } 987 } else if (pageMgmt == Enums::close) { 988 // With a close page policy, no notion of 989 // bank.tRASDoneAt 990 if (bank.freeAt > inTime) 991 accLat += bank.freeAt - inTime; 992 993 // page already closed, simply open the row, and 994 // add cas latency 995 accLat += tRCD + tCL; 996 bankLat += tRCD + tCL; 997 } else 998 panic("No page management policy chosen\n"); 999 1000 DPRINTF(DRAM, "Returning < %lld, %lld > from estimateLatency()\n", 1001 bankLat, accLat); 1002 1003 return make_pair(bankLat, accLat); 1004} 1005 1006void 1007SimpleDRAM::processNextReqEvent() 1008{ 1009 scheduleNextReq(); 1010} 1011 1012void 1013SimpleDRAM::recordActivate(Tick act_tick) 1014{ 1015 assert(actTicks.size() == activationLimit); 1016 1017 DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 1018 1019 // if the activation limit is disabled then we are done 1020 if (actTicks.empty()) 1021 return; 1022 1023 // sanity check 1024 if (actTicks.back() && (act_tick - actTicks.back()) < tXAW) { 1025 // @todo For now, stick with a warning 1026 warn("Got %d activates in window %d (%d - %d) which is smaller " 1027 "than %d\n", activationLimit, act_tick - actTicks.back(), 1028 act_tick, actTicks.back(), tXAW); 1029 } 1030 1031 // shift the times used for the book keeping, the last element 1032 // (highest index) is the oldest one and hence the lowest value 1033 actTicks.pop_back(); 1034 1035 // record an new activation (in the future) 1036 actTicks.push_front(act_tick); 1037 1038 // cannot activate more than X times in time window tXAW, push the 1039 // next one (the X + 1'st activate) to be tXAW away from the 1040 // oldest in our window of X 1041 if (actTicks.back() && (act_tick - actTicks.back()) < tXAW) { 1042 DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate no earlier " 1043 "than %d\n", activationLimit, actTicks.back() + tXAW); 1044 for(int i = 0; i < ranksPerChannel; i++) 1045 for(int j = 0; j < banksPerRank; j++) 1046 // next activate must not happen before end of window 1047 banks[i][j].freeAt = std::max(banks[i][j].freeAt, 1048 actTicks.back() + tXAW); 1049 } 1050} 1051 1052void 1053SimpleDRAM::doDRAMAccess(DRAMPacket* dram_pkt) 1054{ 1055 1056 DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 1057 dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 1058 1059 // estimate the bank and access latency 1060 pair<Tick, Tick> lat = estimateLatency(dram_pkt, curTick()); 1061 Tick bankLat = lat.first; 1062 Tick accessLat = lat.second; 1063 Tick actTick; 1064 1065 // This request was woken up at this time based on a prior call 1066 // to estimateLatency(). However, between then and now, both the 1067 // accessLatency and/or busBusyUntil may have changed. We need 1068 // to correct for that. 1069 1070 Tick addDelay = (curTick() + accessLat < busBusyUntil) ? 1071 busBusyUntil - (curTick() + accessLat) : 0; 1072 1073 Bank& bank = dram_pkt->bank_ref; 1074 1075 // Update bank state 1076 if (pageMgmt == Enums::open) { 1077 bank.openRow = dram_pkt->row; 1078 bank.freeAt = curTick() + addDelay + accessLat; 1079 bank.bytesAccessed += burstSize; 1080 1081 // If you activated a new row do to this access, the next access 1082 // will have to respect tRAS for this bank. 1083 if (!rowHitFlag) { 1084 // any waiting for banks account for in freeAt 1085 actTick = bank.freeAt - tCL - tRCD; 1086 bank.tRASDoneAt = actTick + tRAS; 1087 recordActivate(actTick); 1088 1089 // sample the number of bytes accessed and reset it as 1090 // we are now closing this row 1091 bytesPerActivate.sample(bank.bytesAccessed); 1092 bank.bytesAccessed = 0; 1093 } 1094 } else if (pageMgmt == Enums::close) { 1095 actTick = curTick() + addDelay + accessLat - tRCD - tCL; 1096 recordActivate(actTick); 1097 1098 // If the DRAM has a very quick tRAS, bank can be made free 1099 // after consecutive tCL,tRCD,tRP times. In general, however, 1100 // an additional wait is required to respect tRAS. 1101 bank.freeAt = std::max(actTick + tRAS + tRP, 1102 actTick + tRCD + tCL + tRP); 1103 1104 DPRINTF(DRAM,"doDRAMAccess::bank.freeAt is %lld\n",bank.freeAt); 1105 bytesPerActivate.sample(burstSize); 1106 } else 1107 panic("No page management policy chosen\n"); 1108 1109 // Update request parameters 1110 dram_pkt->readyTime = curTick() + addDelay + accessLat + tBURST; 1111 1112 1113 DPRINTF(DRAM, "Req %lld: curtick is %lld accessLat is %d " \ 1114 "readytime is %lld busbusyuntil is %lld. " \ 1115 "Scheduling at readyTime\n", dram_pkt->addr, 1116 curTick(), accessLat, dram_pkt->readyTime, busBusyUntil); 1117 1118 // Make sure requests are not overlapping on the databus 1119 assert (dram_pkt->readyTime - busBusyUntil >= tBURST); 1120 1121 // Update bus state 1122 busBusyUntil = dram_pkt->readyTime; 1123 1124 DPRINTF(DRAM,"Access time is %lld\n", 1125 dram_pkt->readyTime - dram_pkt->entryTime); 1126 1127 // Update stats 1128 totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 1129 totBankLat += bankLat; 1130 totBusLat += tBURST; 1131 totQLat += dram_pkt->readyTime - dram_pkt->entryTime - bankLat - tBURST; 1132 1133 if (rowHitFlag) 1134 readRowHits++; 1135 1136 // At this point we're done dealing with the request 1137 // It will be moved to a separate response queue with a 1138 // correct readyTime, and eventually be sent back at that 1139 //time 1140 moveToRespQ(); 1141 1142 // The absolute soonest you have to start thinking about the 1143 // next request is the longest access time that can occur before 1144 // busBusyUntil. Assuming you need to precharge, 1145 // open a new row, and access, it is tRP + tRCD + tCL 1146 1147 Tick newTime = (busBusyUntil > tRP + tRCD + tCL ) ? 1148 std::max(busBusyUntil - (tRP + tRCD + tCL) , curTick()) : 1149 curTick(); 1150 1151 if (!nextReqEvent.scheduled() && !stopReads){ 1152 schedule(nextReqEvent, newTime); 1153 } else { 1154 if (newTime < nextReqEvent.when()) 1155 reschedule(nextReqEvent, newTime); 1156 } 1157 1158 1159} 1160 1161void 1162SimpleDRAM::moveToRespQ() 1163{ 1164 // Remove from read queue 1165 DRAMPacket* dram_pkt = readQueue.front(); 1166 readQueue.pop_front(); 1167 1168 // sanity check 1169 assert(dram_pkt->size <= burstSize); 1170 1171 // Insert into response queue sorted by readyTime 1172 // It will be sent back to the requestor at its 1173 // readyTime 1174 if (respQueue.empty()) { 1175 respQueue.push_front(dram_pkt); 1176 assert(!respondEvent.scheduled()); 1177 assert(dram_pkt->readyTime >= curTick()); 1178 schedule(respondEvent, dram_pkt->readyTime); 1179 } else { 1180 bool done = false; 1181 auto i = respQueue.begin(); 1182 while (!done && i != respQueue.end()) { 1183 if ((*i)->readyTime > dram_pkt->readyTime) { 1184 respQueue.insert(i, dram_pkt); 1185 done = true; 1186 } 1187 ++i; 1188 } 1189 1190 if (!done) 1191 respQueue.push_back(dram_pkt); 1192 1193 assert(respondEvent.scheduled()); 1194 1195 if (respQueue.front()->readyTime < respondEvent.when()) { 1196 assert(respQueue.front()->readyTime >= curTick()); 1197 reschedule(respondEvent, respQueue.front()->readyTime); 1198 } 1199 } 1200} 1201 1202void 1203SimpleDRAM::scheduleNextReq() 1204{ 1205 DPRINTF(DRAM, "Reached scheduleNextReq()\n"); 1206 1207 // Figure out which read request goes next, and move it to the 1208 // front of the read queue 1209 if (!chooseNextRead()) { 1210 // In the case there is no read request to go next, see if we 1211 // are asked to drain, and if so trigger writes, this also 1212 // ensures that if we hit the write limit we will do this 1213 // multiple times until we are completely drained 1214 if (drainManager && !writeQueue.empty() && !writeEvent.scheduled()) 1215 triggerWrites(); 1216 } else { 1217 doDRAMAccess(readQueue.front()); 1218 } 1219} 1220 1221Tick 1222SimpleDRAM::maxBankFreeAt() const 1223{ 1224 Tick banksFree = 0; 1225 1226 for(int i = 0; i < ranksPerChannel; i++) 1227 for(int j = 0; j < banksPerRank; j++) 1228 banksFree = std::max(banks[i][j].freeAt, banksFree); 1229 1230 return banksFree; 1231} 1232 1233void 1234SimpleDRAM::processRefreshEvent() 1235{ 1236 DPRINTF(DRAM, "Refreshing at tick %ld\n", curTick()); 1237 1238 Tick banksFree = std::max(curTick(), maxBankFreeAt()) + tRFC; 1239 1240 for(int i = 0; i < ranksPerChannel; i++) 1241 for(int j = 0; j < banksPerRank; j++) 1242 banks[i][j].freeAt = banksFree; 1243 1244 schedule(refreshEvent, curTick() + tREFI); 1245} 1246 1247void 1248SimpleDRAM::regStats() 1249{ 1250 using namespace Stats; 1251 1252 AbstractMemory::regStats(); 1253 1254 readReqs 1255 .name(name() + ".readReqs") 1256 .desc("Total number of read requests accepted by DRAM controller"); 1257 1258 writeReqs 1259 .name(name() + ".writeReqs") 1260 .desc("Total number of write requests accepted by DRAM controller"); 1261 1262 readBursts 1263 .name(name() + ".readBursts") 1264 .desc("Total number of DRAM read bursts. " 1265 "Each DRAM read request translates to either one or multiple " 1266 "DRAM read bursts"); 1267 1268 writeBursts 1269 .name(name() + ".writeBursts") 1270 .desc("Total number of DRAM write bursts. " 1271 "Each DRAM write request translates to either one or multiple " 1272 "DRAM write bursts"); 1273 1274 servicedByWrQ 1275 .name(name() + ".servicedByWrQ") 1276 .desc("Number of DRAM read bursts serviced by write Q"); 1277 1278 neitherReadNorWrite 1279 .name(name() + ".neitherReadNorWrite") 1280 .desc("Reqs where no action is needed"); 1281 1282 perBankRdReqs 1283 .init(banksPerRank * ranksPerChannel) 1284 .name(name() + ".perBankRdReqs") 1285 .desc("Track reads on a per bank basis"); 1286 1287 perBankWrReqs 1288 .init(banksPerRank * ranksPerChannel) 1289 .name(name() + ".perBankWrReqs") 1290 .desc("Track writes on a per bank basis"); 1291 1292 avgRdQLen 1293 .name(name() + ".avgRdQLen") 1294 .desc("Average read queue length over time") 1295 .precision(2); 1296 1297 avgWrQLen 1298 .name(name() + ".avgWrQLen") 1299 .desc("Average write queue length over time") 1300 .precision(2); 1301 1302 totQLat 1303 .name(name() + ".totQLat") 1304 .desc("Total cycles spent in queuing delays"); 1305 1306 totBankLat 1307 .name(name() + ".totBankLat") 1308 .desc("Total cycles spent in bank access"); 1309 1310 totBusLat 1311 .name(name() + ".totBusLat") 1312 .desc("Total cycles spent in databus access"); 1313 1314 totMemAccLat 1315 .name(name() + ".totMemAccLat") 1316 .desc("Sum of mem lat for all requests"); 1317 1318 avgQLat 1319 .name(name() + ".avgQLat") 1320 .desc("Average queueing delay per request") 1321 .precision(2); 1322 1323 avgQLat = totQLat / (readBursts - servicedByWrQ); 1324 1325 avgBankLat 1326 .name(name() + ".avgBankLat") 1327 .desc("Average bank access latency per request") 1328 .precision(2); 1329 1330 avgBankLat = totBankLat / (readBursts - servicedByWrQ); 1331 1332 avgBusLat 1333 .name(name() + ".avgBusLat") 1334 .desc("Average bus latency per request") 1335 .precision(2); 1336 1337 avgBusLat = totBusLat / (readBursts - servicedByWrQ); 1338 1339 avgMemAccLat 1340 .name(name() + ".avgMemAccLat") 1341 .desc("Average memory access latency") 1342 .precision(2); 1343 1344 avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 1345 1346 numRdRetry 1347 .name(name() + ".numRdRetry") 1348 .desc("Number of times rd buffer was full causing retry"); 1349 1350 numWrRetry 1351 .name(name() + ".numWrRetry") 1352 .desc("Number of times wr buffer was full causing retry"); 1353 1354 readRowHits 1355 .name(name() + ".readRowHits") 1356 .desc("Number of row buffer hits during reads"); 1357 1358 writeRowHits 1359 .name(name() + ".writeRowHits") 1360 .desc("Number of row buffer hits during writes"); 1361 1362 readRowHitRate 1363 .name(name() + ".readRowHitRate") 1364 .desc("Row buffer hit rate for reads") 1365 .precision(2); 1366 1367 readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 1368 1369 writeRowHitRate 1370 .name(name() + ".writeRowHitRate") 1371 .desc("Row buffer hit rate for writes") 1372 .precision(2); 1373 1374 writeRowHitRate = (writeRowHits / writeBursts) * 100; 1375 1376 readPktSize 1377 .init(ceilLog2(burstSize) + 1) 1378 .name(name() + ".readPktSize") 1379 .desc("Categorize read packet sizes"); 1380 1381 writePktSize 1382 .init(ceilLog2(burstSize) + 1) 1383 .name(name() + ".writePktSize") 1384 .desc("Categorize write packet sizes"); 1385 1386 rdQLenPdf 1387 .init(readBufferSize) 1388 .name(name() + ".rdQLenPdf") 1389 .desc("What read queue length does an incoming req see"); 1390 1391 wrQLenPdf 1392 .init(writeBufferSize) 1393 .name(name() + ".wrQLenPdf") 1394 .desc("What write queue length does an incoming req see"); 1395 1396 bytesPerActivate 1397 .init(rowBufferSize) 1398 .name(name() + ".bytesPerActivate") 1399 .desc("Bytes accessed per row activation") 1400 .flags(nozero); 1401 1402 bytesRead 1403 .name(name() + ".bytesRead") 1404 .desc("Total number of bytes read from memory"); 1405 1406 bytesWritten 1407 .name(name() + ".bytesWritten") 1408 .desc("Total number of bytes written to memory"); 1409 1410 bytesConsumedRd 1411 .name(name() + ".bytesConsumedRd") 1412 .desc("bytesRead derated as per pkt->getSize()"); 1413 1414 bytesConsumedWr 1415 .name(name() + ".bytesConsumedWr") 1416 .desc("bytesWritten derated as per pkt->getSize()"); 1417 1418 avgRdBW 1419 .name(name() + ".avgRdBW") 1420 .desc("Average achieved read bandwidth in MB/s") 1421 .precision(2); 1422 1423 avgRdBW = (bytesRead / 1000000) / simSeconds; 1424 1425 avgWrBW 1426 .name(name() + ".avgWrBW") 1427 .desc("Average achieved write bandwidth in MB/s") 1428 .precision(2); 1429 1430 avgWrBW = (bytesWritten / 1000000) / simSeconds; 1431 1432 avgConsumedRdBW 1433 .name(name() + ".avgConsumedRdBW") 1434 .desc("Average consumed read bandwidth in MB/s") 1435 .precision(2); 1436 1437 avgConsumedRdBW = (bytesConsumedRd / 1000000) / simSeconds; 1438 1439 avgConsumedWrBW 1440 .name(name() + ".avgConsumedWrBW") 1441 .desc("Average consumed write bandwidth in MB/s") 1442 .precision(2); 1443 1444 avgConsumedWrBW = (bytesConsumedWr / 1000000) / simSeconds; 1445 1446 peakBW 1447 .name(name() + ".peakBW") 1448 .desc("Theoretical peak bandwidth in MB/s") 1449 .precision(2); 1450 1451 peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 1452 1453 busUtil 1454 .name(name() + ".busUtil") 1455 .desc("Data bus utilization in percentage") 1456 .precision(2); 1457 1458 busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 1459 1460 totGap 1461 .name(name() + ".totGap") 1462 .desc("Total gap between requests"); 1463 1464 avgGap 1465 .name(name() + ".avgGap") 1466 .desc("Average gap between requests") 1467 .precision(2); 1468 1469 avgGap = totGap / (readReqs + writeReqs); 1470} 1471 1472void 1473SimpleDRAM::recvFunctional(PacketPtr pkt) 1474{ 1475 // rely on the abstract memory 1476 functionalAccess(pkt); 1477} 1478 1479BaseSlavePort& 1480SimpleDRAM::getSlavePort(const string &if_name, PortID idx) 1481{ 1482 if (if_name != "port") { 1483 return MemObject::getSlavePort(if_name, idx); 1484 } else { 1485 return port; 1486 } 1487} 1488 1489unsigned int 1490SimpleDRAM::drain(DrainManager *dm) 1491{ 1492 unsigned int count = port.drain(dm); 1493 1494 // if there is anything in any of our internal queues, keep track 1495 // of that as well 1496 if (!(writeQueue.empty() && readQueue.empty() && 1497 respQueue.empty())) { 1498 DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 1499 " resp: %d\n", writeQueue.size(), readQueue.size(), 1500 respQueue.size()); 1501 ++count; 1502 drainManager = dm; 1503 // the only part that is not drained automatically over time 1504 // is the write queue, thus trigger writes if there are any 1505 // waiting and no reads waiting, otherwise wait until the 1506 // reads are done 1507 if (readQueue.empty() && !writeQueue.empty() && 1508 !writeEvent.scheduled()) 1509 triggerWrites(); 1510 } 1511 1512 if (count) 1513 setDrainState(Drainable::Draining); 1514 else 1515 setDrainState(Drainable::Drained); 1516 return count; 1517} 1518 1519SimpleDRAM::MemoryPort::MemoryPort(const std::string& name, SimpleDRAM& _memory) 1520 : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 1521 memory(_memory) 1522{ } 1523 1524AddrRangeList 1525SimpleDRAM::MemoryPort::getAddrRanges() const 1526{ 1527 AddrRangeList ranges; 1528 ranges.push_back(memory.getAddrRange()); 1529 return ranges; 1530} 1531 1532void 1533SimpleDRAM::MemoryPort::recvFunctional(PacketPtr pkt) 1534{ 1535 pkt->pushLabel(memory.name()); 1536 1537 if (!queue.checkFunctional(pkt)) { 1538 // Default implementation of SimpleTimingPort::recvFunctional() 1539 // calls recvAtomic() and throws away the latency; we can save a 1540 // little here by just not calculating the latency. 1541 memory.recvFunctional(pkt); 1542 } 1543 1544 pkt->popLabel(); 1545} 1546 1547Tick 1548SimpleDRAM::MemoryPort::recvAtomic(PacketPtr pkt) 1549{ 1550 return memory.recvAtomic(pkt); 1551} 1552 1553bool 1554SimpleDRAM::MemoryPort::recvTimingReq(PacketPtr pkt) 1555{ 1556 // pass it to the memory controller 1557 return memory.recvTimingReq(pkt); 1558} 1559 1560SimpleDRAM* 1561SimpleDRAMParams::create() 1562{ 1563 return new SimpleDRAM(this); 1564} 1565