dram_ctrl.cc revision 9549
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andreas Hansson 38 * Ani Udipi 39 */ 40 41#include "base/trace.hh" 42#include "debug/Drain.hh" 43#include "debug/DRAM.hh" 44#include "debug/DRAMWR.hh" 45#include "mem/simple_dram.hh" 46#include "sim/stat_control.hh" 47 48using namespace std; 49 50SimpleDRAM::SimpleDRAM(const SimpleDRAMParams* p) : 51 AbstractMemory(p), 52 port(name() + ".port", *this), 53 retryRdReq(false), retryWrReq(false), 54 rowHitFlag(false), stopReads(false), actTicks(p->activation_limit, 0), 55 writeEvent(this), respondEvent(this), 56 refreshEvent(this), nextReqEvent(this), drainManager(NULL), 57 bytesPerCacheLine(0), 58 linesPerRowBuffer(p->lines_per_rowbuffer), 59 ranksPerChannel(p->ranks_per_channel), 60 banksPerRank(p->banks_per_rank), rowsPerBank(0), 61 readBufferSize(p->read_buffer_size), 62 writeBufferSize(p->write_buffer_size), 63 writeThresholdPerc(p->write_thresh_perc), 64 tWTR(p->tWTR), tBURST(p->tBURST), 65 tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), 66 tRFC(p->tRFC), tREFI(p->tREFI), 67 tXAW(p->tXAW), activationLimit(p->activation_limit), 68 memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 69 pageMgmt(p->page_policy), 70 busBusyUntil(0), prevdramaccess(0), writeStartTime(0), 71 prevArrival(0), numReqs(0) 72{ 73 // create the bank states based on the dimensions of the ranks and 74 // banks 75 banks.resize(ranksPerChannel); 76 for (size_t c = 0; c < ranksPerChannel; ++c) { 77 banks[c].resize(banksPerRank); 78 } 79 80 // round the write threshold percent to a whole number of entries 81 // in the buffer 82 writeThreshold = writeBufferSize * writeThresholdPerc / 100.0; 83} 84 85void 86SimpleDRAM::init() 87{ 88 if (!port.isConnected()) { 89 fatal("SimpleDRAM %s is unconnected!\n", name()); 90 } else { 91 port.sendRangeChange(); 92 } 93 94 // get the cache line size from the connected port 95 bytesPerCacheLine = port.peerBlockSize(); 96 97 // we could deal with plenty options here, but for now do a quick 98 // sanity check 99 if (bytesPerCacheLine != 64 && bytesPerCacheLine != 32) 100 panic("Unexpected cache line size %d", bytesPerCacheLine); 101 102 // determine the rows per bank by looking at the total capacity 103 uint64_t capacity = AbstractMemory::size(); 104 uint64_t i = 1; 105 while (i < 64 && capacity > ((1 << i))) { 106 ++i; 107 } 108 109 // rounded up to nearest power of two 110 DPRINTF(DRAM, "i is %lld\n", i); 111 capacity = 1 << i; 112 113 DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 114 AbstractMemory::size()); 115 rowsPerBank = capacity / (bytesPerCacheLine * linesPerRowBuffer * 116 banksPerRank * ranksPerChannel); 117 118} 119 120void 121SimpleDRAM::startup() 122{ 123 // print the configuration of the controller 124 printParams(); 125 126 // kick off the refresh 127 schedule(&refreshEvent, curTick() + tREFI); 128} 129 130 131Tick 132SimpleDRAM::recvAtomic(PacketPtr pkt) 133{ 134 DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 135 136 // do the actual memory access and turn the packet into a response 137 access(pkt); 138 139 Tick latency = 0; 140 if (!pkt->memInhibitAsserted() && pkt->hasData()) { 141 // this value is not supposed to be accurate, just enough to 142 // keep things going, mimic a closed page 143 latency = tRP + tRCD + tCL; 144 } 145 return latency; 146} 147 148bool 149SimpleDRAM::readQueueFull() const 150{ 151 DPRINTF(DRAM, "Read queue limit %d current size %d\n", 152 readBufferSize, dramReadQueue.size() + dramRespQueue.size()); 153 154 return (dramReadQueue.size() + dramRespQueue.size()) == readBufferSize; 155} 156 157bool 158SimpleDRAM::writeQueueFull() const 159{ 160 DPRINTF(DRAM, "Write queue limit %d current size %d\n", 161 writeBufferSize, dramWriteQueue.size()); 162 return dramWriteQueue.size() == writeBufferSize; 163} 164 165 166SimpleDRAM::DRAMPacket* 167SimpleDRAM::decodeAddr(PacketPtr pkt) 168{ 169 // decode the address based on the address mapping scheme 170 // 171 // with R, C, B and K denoting rank, column, bank and rank, 172 // respectively, and going from MSB to LSB, the two schemes are 173 // RKBC (openmap) and RCKB (closedmap) 174 uint8_t rank; 175 uint16_t bank; 176 uint16_t row; 177 178 Addr addr = pkt->getAddr(); 179 Addr temp = addr; 180 181 // truncate the address to the access granularity 182 addr = addr / bytesPerCacheLine; 183 184 // we have removed the lowest order address bits that denote the 185 // position within the cache line, proceed and select the 186 // appropriate bits for bank, rank and row (no column address is 187 // needed) 188 if (addrMapping == Enums::openmap) { 189 // the lowest order bits denote the column to ensure that 190 // sequential cache lines occupy the same row 191 addr = addr / linesPerRowBuffer; 192 193 // after the column bits, we get the bank bits to interleave 194 // over the banks 195 bank = addr % banksPerRank; 196 addr = addr / banksPerRank; 197 198 // after the bank, we get the rank bits which thus interleaves 199 // over the ranks 200 rank = addr % ranksPerChannel; 201 addr = addr / ranksPerChannel; 202 203 // lastly, get the row bits 204 row = addr % rowsPerBank; 205 addr = addr / rowsPerBank; 206 } else if (addrMapping == Enums::closemap) { 207 // optimise for closed page mode and utilise maximum 208 // parallelism of the DRAM (at the cost of power) 209 210 // start with the bank bits, as this provides the maximum 211 // opportunity for parallelism between requests 212 bank = addr % banksPerRank; 213 addr = addr / banksPerRank; 214 215 // next get the rank bits 216 rank = addr % ranksPerChannel; 217 addr = addr / ranksPerChannel; 218 219 // next the column bits which we do not need to keep track of 220 // and simply skip past 221 addr = addr / linesPerRowBuffer; 222 223 // lastly, get the row bits 224 row = addr % rowsPerBank; 225 addr = addr / rowsPerBank; 226 } else 227 panic("Unknown address mapping policy chosen!"); 228 229 assert(rank < ranksPerChannel); 230 assert(bank < banksPerRank); 231 assert(row < rowsPerBank); 232 233 DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 234 temp, rank, bank, row); 235 236 // create the corresponding DRAM packet with the entry time and 237 // ready time set to the current tick, they will be updated later 238 DRAMPacket* dram_pkt = new DRAMPacket(pkt, rank, bank, row, temp, 239 banks[rank][bank]); 240 241 return dram_pkt; 242} 243 244void 245SimpleDRAM::addToReadQueue(PacketPtr pkt) 246{ 247 // only add to the read queue here. whenever the request is 248 // eventually done, set the readyTime, and call schedule() 249 assert(!pkt->isWrite()); 250 251 // First check write buffer to see if the data is already at 252 // the controller 253 std::list<DRAMPacket*>::const_iterator i; 254 Addr addr = pkt->getAddr(); 255 256 // @todo: add size check 257 for (i = dramWriteQueue.begin(); i != dramWriteQueue.end(); ++i) { 258 if ((*i)->addr == addr){ 259 servicedByWrQ++; 260 DPRINTF(DRAM,"Serviced by write Q\n"); 261 bytesRead += bytesPerCacheLine; 262 bytesConsumedRd += pkt->getSize(); 263 accessAndRespond(pkt); 264 return; 265 } 266 } 267 268 DRAMPacket* dram_pkt = decodeAddr(pkt); 269 270 assert(dramReadQueue.size() + dramRespQueue.size() < readBufferSize); 271 rdQLenPdf[dramReadQueue.size() + dramRespQueue.size()]++; 272 273 DPRINTF(DRAM, "Adding to read queue\n"); 274 275 dramReadQueue.push_back(dram_pkt); 276 277 // Update stats 278 uint32_t bank_id = banksPerRank * dram_pkt->rank + dram_pkt->bank; 279 assert(bank_id < ranksPerChannel * banksPerRank); 280 perBankRdReqs[bank_id]++; 281 282 avgRdQLen = dramReadQueue.size() + dramRespQueue.size(); 283 284 // Special case where no arbitration is required between requests 285 if (!nextReqEvent.scheduled() && !stopReads) { 286 DPRINTF(DRAM, "Request %lld - need to schedule immediately"); 287 schedule(&nextReqEvent, curTick() + 1); 288 } 289} 290 291void 292SimpleDRAM::processWriteEvent() 293{ 294 assert(!dramWriteQueue.empty()); 295 uint32_t numWritesThisTime = 0; 296 297 DPRINTF(DRAMWR, "Beginning DRAM Writes\n"); 298 Tick temp1 M5_VAR_USED = std::max(curTick(), busBusyUntil); 299 Tick temp2 M5_VAR_USED = std::max(curTick(), maxBankFreeAt()); 300 301 // @todo: are there any dangers with the untimed while loop? 302 while (!dramWriteQueue.empty()) { 303 if (numWritesThisTime > writeThreshold) 304 break; 305 306 chooseNextWrite(); 307 DRAMPacket* dram_pkt = dramWriteQueue.front(); 308 // What's the earlier the request can be put on the bus 309 Tick schedTime = std::max(curTick(), busBusyUntil); 310 311 DPRINTF(DRAMWR, "Asking for latency estimate at %lld\n", 312 schedTime + tBURST); 313 314 pair<Tick, Tick> lat = estimateLatency(dram_pkt, schedTime + tBURST); 315 Tick accessLat = lat.second; 316 317 // look at the rowHitFlag set by estimateLatency 318 319 // @todo: Race condition here where another packet gives rise 320 // to another call to estimateLatency in the meanwhile? 321 if (rowHitFlag) 322 writeRowHits++; 323 324 Bank& bank = dram_pkt->bank_ref; 325 326 if (pageMgmt == Enums::open) { 327 bank.openRow = dram_pkt->row; 328 bank.freeAt = schedTime + tBURST + std::max(accessLat, tCL); 329 busBusyUntil = bank.freeAt - tCL; 330 331 if (!rowHitFlag) { 332 bank.tRASDoneAt = bank.freeAt + tRP; 333 recordActivate(bank.freeAt - tCL - tRCD); 334 busBusyUntil = bank.freeAt - tCL - tRCD; 335 } 336 } else if (pageMgmt == Enums::close) { 337 bank.freeAt = schedTime + tBURST + accessLat + tRP + tRP; 338 // Work backwards from bank.freeAt to determine activate time 339 recordActivate(bank.freeAt - tRP - tRP - tCL - tRCD); 340 busBusyUntil = bank.freeAt - tRP - tRP - tCL - tRCD; 341 DPRINTF(DRAMWR, "processWriteEvent::bank.freeAt for " 342 "banks_id %d is %lld\n", 343 dram_pkt->rank * banksPerRank + dram_pkt->bank, 344 bank.freeAt); 345 } else 346 panic("Unknown page management policy chosen\n"); 347 348 DPRINTF(DRAMWR,"Done writing to address %lld\n",dram_pkt->addr); 349 350 DPRINTF(DRAMWR,"schedtime is %lld, tBURST is %lld, " 351 "busbusyuntil is %lld\n", 352 schedTime, tBURST, busBusyUntil); 353 354 dramWriteQueue.pop_front(); 355 delete dram_pkt; 356 357 numWritesThisTime++; 358 } 359 360 DPRINTF(DRAMWR, "Completed %d writes, bus busy for %lld ticks,"\ 361 "banks busy for %lld ticks\n", numWritesThisTime, 362 busBusyUntil - temp1, maxBankFreeAt() - temp2); 363 364 // Update stats 365 avgWrQLen = dramWriteQueue.size(); 366 367 // turn the bus back around for reads again 368 busBusyUntil += tWTR; 369 stopReads = false; 370 371 if (retryWrReq) { 372 retryWrReq = false; 373 port.sendRetry(); 374 } 375 376 // if there is nothing left in any queue, signal a drain 377 if (dramWriteQueue.empty() && dramReadQueue.empty() && 378 dramRespQueue.empty () && drainManager) { 379 drainManager->signalDrainDone(); 380 drainManager = NULL; 381 } 382 383 // Once you're done emptying the write queue, check if there's 384 // anything in the read queue, and call schedule if required 385 schedule(&nextReqEvent, busBusyUntil); 386} 387 388void 389SimpleDRAM::triggerWrites() 390{ 391 DPRINTF(DRAM, "Writes triggered at %lld\n", curTick()); 392 // Flag variable to stop any more read scheduling 393 stopReads = true; 394 395 writeStartTime = std::max(busBusyUntil, curTick()) + tWTR; 396 397 DPRINTF(DRAM, "Writes scheduled at %lld\n", writeStartTime); 398 399 assert(writeStartTime >= curTick()); 400 assert(!writeEvent.scheduled()); 401 schedule(&writeEvent, writeStartTime); 402} 403 404void 405SimpleDRAM::addToWriteQueue(PacketPtr pkt) 406{ 407 // only add to the write queue here. whenever the request is 408 // eventually done, set the readyTime, and call schedule() 409 assert(pkt->isWrite()); 410 411 DRAMPacket* dram_pkt = decodeAddr(pkt); 412 413 assert(dramWriteQueue.size() < writeBufferSize); 414 wrQLenPdf[dramWriteQueue.size()]++; 415 416 DPRINTF(DRAM, "Adding to write queue\n"); 417 418 dramWriteQueue.push_back(dram_pkt); 419 420 // Update stats 421 uint32_t bank_id = banksPerRank * dram_pkt->rank + dram_pkt->bank; 422 assert(bank_id < ranksPerChannel * banksPerRank); 423 perBankWrReqs[bank_id]++; 424 425 avgWrQLen = dramWriteQueue.size(); 426 427 // we do not wait for the writes to be send to the actual memory, 428 // but instead take responsibility for the consistency here and 429 // snoop the write queue for any upcoming reads 430 431 bytesConsumedWr += pkt->getSize(); 432 bytesWritten += bytesPerCacheLine; 433 accessAndRespond(pkt); 434 435 // If your write buffer is starting to fill up, drain it! 436 if (dramWriteQueue.size() > writeThreshold && !stopReads){ 437 triggerWrites(); 438 } 439} 440 441void 442SimpleDRAM::printParams() const 443{ 444 // Sanity check print of important parameters 445 DPRINTF(DRAM, 446 "Memory controller %s physical organization\n" \ 447 "Bytes per cacheline %d\n" \ 448 "Lines per row buffer %d\n" \ 449 "Rows per bank %d\n" \ 450 "Banks per rank %d\n" \ 451 "Ranks per channel %d\n" \ 452 "Total mem capacity %u\n", 453 name(), bytesPerCacheLine ,linesPerRowBuffer, rowsPerBank, 454 banksPerRank, ranksPerChannel, bytesPerCacheLine * 455 linesPerRowBuffer * rowsPerBank * banksPerRank * ranksPerChannel); 456 457 string scheduler = memSchedPolicy == Enums::fcfs ? "FCFS" : "FR-FCFS"; 458 string address_mapping = addrMapping == Enums::openmap ? "OPENMAP" : 459 "CLOSEMAP"; 460 string page_policy = pageMgmt == Enums::open ? "OPEN" : "CLOSE"; 461 462 DPRINTF(DRAM, 463 "Memory controller %s characteristics\n" \ 464 "Read buffer size %d\n" \ 465 "Write buffer size %d\n" \ 466 "Write buffer thresh %d\n" \ 467 "Scheduler %s\n" \ 468 "Address mapping %s\n" \ 469 "Page policy %s\n", 470 name(), readBufferSize, writeBufferSize, writeThreshold, 471 scheduler, address_mapping, page_policy); 472 473 DPRINTF(DRAM, "Memory controller %s timing specs\n" \ 474 "tRCD %d ticks\n" \ 475 "tCL %d ticks\n" \ 476 "tRP %d ticks\n" \ 477 "tBURST %d ticks\n" \ 478 "tRFC %d ticks\n" \ 479 "tREFI %d ticks\n" \ 480 "tWTR %d ticks\n", 481 name(), tRCD, tCL, tRP, tBURST, tRFC, tREFI, tWTR); 482} 483 484void 485SimpleDRAM::printQs() const { 486 487 list<DRAMPacket*>::const_iterator i; 488 489 DPRINTF(DRAM, "===READ QUEUE===\n\n"); 490 for (i = dramReadQueue.begin() ; i != dramReadQueue.end() ; ++i) { 491 DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 492 } 493 DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 494 for (i = dramRespQueue.begin() ; i != dramRespQueue.end() ; ++i) { 495 DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 496 } 497 DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 498 for (i = dramWriteQueue.begin() ; i != dramWriteQueue.end() ; ++i) { 499 DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 500 } 501} 502 503bool 504SimpleDRAM::recvTimingReq(PacketPtr pkt) 505{ 506 /// @todo temporary hack to deal with memory corruption issues until 507 /// 4-phase transactions are complete 508 for (int x = 0; x < pendingDelete.size(); x++) 509 delete pendingDelete[x]; 510 pendingDelete.clear(); 511 512 513 // This is where we enter from the outside world 514 DPRINTF(DRAM, "Inside recvTimingReq: request %s addr %lld size %d\n", 515 pkt->cmdString(),pkt->getAddr(), pkt->getSize()); 516 517 int index; 518 519 if (pkt->getSize() == bytesPerCacheLine) 520 cpuReqs++; 521 522 if (numReqs % 1000000 == 0) 523 printQs(); 524 525 // Calc avg gap between requests 526 if (prevArrival != 0) { 527 totGap += curTick() - prevArrival; 528 } 529 prevArrival = curTick(); 530 531 // simply drop inhibited packets for now 532 if (pkt->memInhibitAsserted()) { 533 DPRINTF(DRAM,"Inhibited packet -- Dropping it now\n"); 534 pendingDelete.push_back(pkt); 535 return true; 536 } 537 538 unsigned size = pkt->getSize(); 539 if (size > bytesPerCacheLine) 540 panic("Request size %d is greater than cache line size %d", 541 size, bytesPerCacheLine); 542 543 if (size == 0) 544 index = log2(bytesPerCacheLine) + 1; 545 else 546 index = log2(size); 547 548 if (size != 0 && (1 << index) != size) 549 index = log2(bytesPerCacheLine) + 2; 550 551 // @todo: Do we really want to do all this before the packet is 552 // actually accepted? 553 554 /* Index 0 - Size 1 byte 555 Index 1 - Size 2 bytes 556 Index 2 - Size 4 bytes 557 . 558 . 559 Index 6 - Size 64 bytes 560 Index 7 - Size 0 bytes 561 Index 8 - Non-power-of-2 size */ 562 563 if (pkt->isRead()) 564 readPktSize[index]++; 565 else if (pkt->isWrite()) 566 writePktSize[index]++; 567 else 568 neitherPktSize[index]++; 569 570 // check local buffers and do not accept if full 571 if (pkt->isRead()) { 572 if (readQueueFull()) { 573 DPRINTF(DRAM,"Read queue full, not accepting\n"); 574 // remember that we have to retry this port 575 retryRdReq = true; 576 numRdRetry++; 577 return false; 578 } else { 579 addToReadQueue(pkt); 580 readReqs++; 581 numReqs++; 582 } 583 } else if (pkt->isWrite()) { 584 if (writeQueueFull()) { 585 DPRINTF(DRAM,"Write queue full, not accepting\n"); 586 // remember that we have to retry this port 587 retryWrReq = true; 588 numWrRetry++; 589 return false; 590 } else { 591 addToWriteQueue(pkt); 592 writeReqs++; 593 numReqs++; 594 } 595 } else { 596 DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 597 neitherReadNorWrite++; 598 accessAndRespond(pkt); 599 } 600 601 602 retryRdReq = false; 603 retryWrReq = false; 604 return true; 605} 606 607void 608SimpleDRAM::processRespondEvent() 609{ 610 DPRINTF(DRAM, 611 "processRespondEvent(): Some req has reached its readyTime\n"); 612 613 PacketPtr pkt = dramRespQueue.front()->pkt; 614 615 // Actually responds to the requestor 616 bytesConsumedRd += pkt->getSize(); 617 bytesRead += bytesPerCacheLine; 618 accessAndRespond(pkt); 619 620 DRAMPacket* dram_pkt = dramRespQueue.front(); 621 dramRespQueue.pop_front(); 622 delete dram_pkt; 623 624 // Update stats 625 avgRdQLen = dramReadQueue.size() + dramRespQueue.size(); 626 627 if (!dramRespQueue.empty()){ 628 assert(dramRespQueue.front()->readyTime >= curTick()); 629 assert(!respondEvent.scheduled()); 630 schedule(&respondEvent, dramRespQueue.front()->readyTime); 631 } else { 632 // if there is nothing left in any queue, signal a drain 633 if (dramWriteQueue.empty() && dramReadQueue.empty() && 634 drainManager) { 635 drainManager->signalDrainDone(); 636 drainManager = NULL; 637 } 638 } 639} 640 641void 642SimpleDRAM::chooseNextWrite() 643{ 644 // This method does the arbitration between requests. The chosen 645 // packet is simply moved to the head of the queue. The other 646 // methods know that this is the place to look. For example, with 647 // FCFS, this method does nothing 648 assert(!dramWriteQueue.empty()); 649 650 if (dramWriteQueue.size() == 1) { 651 DPRINTF(DRAMWR, "chooseNextWrite(): Single element, nothing to do\n"); 652 return; 653 } 654 655 if (memSchedPolicy == Enums::fcfs) { 656 657 // Do nothing, since the correct request is already head 658 659 } else if (memSchedPolicy == Enums::frfcfs) { 660 661 list<DRAMPacket*>::iterator i = dramWriteQueue.begin(); 662 bool foundRowHit = false; 663 while (!foundRowHit && i != dramWriteQueue.end()) { 664 DRAMPacket* dram_pkt = *i; 665 const Bank& bank = dram_pkt->bank_ref; 666 if (bank.openRow == dram_pkt->row) { //FR part 667 DPRINTF(DRAMWR,"Row buffer hit\n"); 668 dramWriteQueue.erase(i); 669 dramWriteQueue.push_front(dram_pkt); 670 foundRowHit = true; 671 } else { //FCFS part 672 ; 673 } 674 ++i; 675 } 676 677 } else 678 panic("No scheduling policy chosen\n"); 679 680 DPRINTF(DRAMWR, "chooseNextWrite(): Something chosen\n"); 681} 682 683bool 684SimpleDRAM::chooseNextReq() 685{ 686 // This method does the arbitration between requests. 687 // The chosen packet is simply moved to the head of the 688 // queue. The other methods know that this is the place 689 // to look. For example, with FCFS, this method does nothing 690 list<DRAMPacket*>::iterator i; 691 DRAMPacket* dram_pkt; 692 693 if (dramReadQueue.empty()){ 694 DPRINTF(DRAM, "chooseNextReq(): Returning False\n"); 695 return false; 696 } 697 698 if (dramReadQueue.size() == 1) 699 return true; 700 701 if (memSchedPolicy == Enums::fcfs) { 702 703 // Do nothing, since the correct request is already head 704 705 } else if (memSchedPolicy == Enums::frfcfs) { 706 707 for (i = dramReadQueue.begin() ; i != dramReadQueue.end() ; ++i) { 708 dram_pkt = *i; 709 const Bank& bank = dram_pkt->bank_ref; 710 if (bank.openRow == dram_pkt->row) { //FR part 711 DPRINTF(DRAM, "Row buffer hit\n"); 712 dramReadQueue.erase(i); 713 dramReadQueue.push_front(dram_pkt); 714 break; 715 } else { //FCFS part 716 ; 717 } 718 719 } 720 721 } else 722 panic("No scheduling policy chosen!\n"); 723 724 725 DPRINTF(DRAM,"chooseNextReq(): Chosen something, returning True\n"); 726 return true; 727} 728 729void 730SimpleDRAM::accessAndRespond(PacketPtr pkt) 731{ 732 DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 733 734 bool needsResponse = pkt->needsResponse(); 735 // do the actual memory access which also turns the packet into a 736 // response 737 access(pkt); 738 739 // turn packet around to go back to requester if response expected 740 if (needsResponse) { 741 // access already turned the packet into a response 742 assert(pkt->isResponse()); 743 744 // @todo someone should pay for this 745 pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; 746 747 // queue the packet in the response queue to be sent out the 748 // next tick 749 port.schedTimingResp(pkt, curTick() + 1); 750 } else { 751 } 752 753 DPRINTF(DRAM, "Done\n"); 754 755 return; 756} 757 758pair<Tick, Tick> 759SimpleDRAM::estimateLatency(DRAMPacket* dram_pkt, Tick inTime) 760{ 761 // If a request reaches a bank at tick 'inTime', how much time 762 // *after* that does it take to finish the request, depending 763 // on bank status and page open policy. Note that this method 764 // considers only the time taken for the actual read or write 765 // to complete, NOT any additional time thereafter for tRAS or 766 // tRP. 767 Tick accLat = 0; 768 Tick bankLat = 0; 769 rowHitFlag = false; 770 771 const Bank& bank = dram_pkt->bank_ref; 772 if (pageMgmt == Enums::open) { // open-page policy 773 if (bank.openRow == dram_pkt->row) { 774 // When we have a row-buffer hit, 775 // we don't care about tRAS having expired or not, 776 // but do care about bank being free for access 777 rowHitFlag = true; 778 779 if (bank.freeAt < inTime) { 780 // CAS latency only 781 accLat += tCL; 782 bankLat += tCL; 783 } else { 784 accLat += 0; 785 bankLat += 0; 786 } 787 788 } else { 789 // Row-buffer miss, need to close existing row 790 // once tRAS has expired, then open the new one, 791 // then add cas latency. 792 Tick freeTime = std::max(bank.tRASDoneAt, bank.freeAt); 793 794 if (freeTime > inTime) 795 accLat += freeTime - inTime; 796 797 accLat += tRP + tRCD + tCL; 798 bankLat += tRP + tRCD + tCL; 799 } 800 } else if (pageMgmt == Enums::close) { 801 802 // With a close page policy, no notion of 803 // bank.tRASDoneAt 804 if (bank.freeAt > inTime) 805 accLat += bank.freeAt - inTime; 806 807 // page already closed, simply open the row, and 808 // add cas latency 809 accLat += tRCD + tCL; 810 bankLat += tRCD + tCL; 811 } else 812 panic("No page management policy chosen\n"); 813 814 DPRINTF(DRAM, "Returning < %lld, %lld > from estimateLatency()\n", 815 bankLat, accLat); 816 817 return make_pair(bankLat, accLat); 818} 819 820void 821SimpleDRAM::processNextReqEvent() 822{ 823 scheduleNextReq(); 824} 825 826void 827SimpleDRAM::recordActivate(Tick act_tick) 828{ 829 assert(actTicks.size() == activationLimit); 830 831 DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 832 833 // sanity check 834 if (actTicks.back() && (act_tick - actTicks.back()) < tXAW) { 835 panic("Got %d activates in window %d (%d - %d) which is smaller " 836 "than %d\n", activationLimit, act_tick - actTicks.back(), 837 act_tick, actTicks.back(), tXAW); 838 } 839 840 // shift the times used for the book keeping, the last element 841 // (highest index) is the oldest one and hence the lowest value 842 actTicks.pop_back(); 843 844 // record an new activation (in the future) 845 actTicks.push_front(act_tick); 846 847 // cannot activate more than X times in time window tXAW, push the 848 // next one (the X + 1'st activate) to be tXAW away from the 849 // oldest in our window of X 850 if (actTicks.back() && (act_tick - actTicks.back()) < tXAW) { 851 DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate no earlier " 852 "than %d\n", activationLimit, actTicks.back() + tXAW); 853 for(int i = 0; i < ranksPerChannel; i++) 854 for(int j = 0; j < banksPerRank; j++) 855 // next activate must not happen before end of window 856 banks[i][j].freeAt = std::max(banks[i][j].freeAt, 857 actTicks.back() + tXAW); 858 } 859} 860 861void 862SimpleDRAM::doDRAMAccess(DRAMPacket* dram_pkt) 863{ 864 865 DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 866 dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 867 868 assert(curTick() >= prevdramaccess); 869 prevdramaccess = curTick(); 870 871 // estimate the bank and access latency 872 pair<Tick, Tick> lat = estimateLatency(dram_pkt, curTick()); 873 Tick bankLat = lat.first; 874 Tick accessLat = lat.second; 875 876 // This request was woken up at this time based on a prior call 877 // to estimateLatency(). However, between then and now, both the 878 // accessLatency and/or busBusyUntil may have changed. We need 879 // to correct for that. 880 881 Tick addDelay = (curTick() + accessLat < busBusyUntil) ? 882 busBusyUntil - (curTick() + accessLat) : 0; 883 884 Bank& bank = dram_pkt->bank_ref; 885 886 // Update bank state 887 if (pageMgmt == Enums::open) { 888 bank.openRow = dram_pkt->row; 889 bank.freeAt = curTick() + addDelay + accessLat; 890 // If you activated a new row do to this access, the next access 891 // will have to respect tRAS for this bank. Assume tRAS ~= 3 * tRP. 892 // Also need to account for t_XAW 893 if (!rowHitFlag) { 894 bank.tRASDoneAt = bank.freeAt + tRP; 895 recordActivate(bank.freeAt - tCL - tRCD); //since this is open page, 896 //no tRP by default 897 } 898 } else if (pageMgmt == Enums::close) { // accounting for tRAS also 899 // assuming that tRAS ~= 3 * tRP, and tRC ~= 4 * tRP, as is common 900 // (refer Jacob/Ng/Wang and Micron datasheets) 901 bank.freeAt = curTick() + addDelay + accessLat + tRP + tRP; 902 recordActivate(bank.freeAt - tRP - tRP - tCL - tRCD); //essentially (freeAt - tRC) 903 DPRINTF(DRAM,"doDRAMAccess::bank.freeAt is %lld\n",bank.freeAt); 904 } else 905 panic("No page management policy chosen\n"); 906 907 // Update request parameters 908 dram_pkt->readyTime = curTick() + addDelay + accessLat + tBURST; 909 910 911 DPRINTF(DRAM, "Req %lld: curtick is %lld accessLat is %d " \ 912 "readytime is %lld busbusyuntil is %lld. " \ 913 "Scheduling at readyTime\n", dram_pkt->addr, 914 curTick(), accessLat, dram_pkt->readyTime, busBusyUntil); 915 916 // Make sure requests are not overlapping on the databus 917 assert (dram_pkt->readyTime - busBusyUntil >= tBURST); 918 919 // Update bus state 920 busBusyUntil = dram_pkt->readyTime; 921 922 DPRINTF(DRAM,"Access time is %lld\n", 923 dram_pkt->readyTime - dram_pkt->entryTime); 924 925 // Update stats 926 totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 927 totBankLat += bankLat; 928 totBusLat += tBURST; 929 totQLat += dram_pkt->readyTime - dram_pkt->entryTime - bankLat - tBURST; 930 931 if (rowHitFlag) 932 readRowHits++; 933 934 // At this point we're done dealing with the request 935 // It will be moved to a separate response queue with a 936 // correct readyTime, and eventually be sent back at that 937 //time 938 moveToRespQ(); 939 940 // The absolute soonest you have to start thinking about the 941 // next request is the longest access time that can occur before 942 // busBusyUntil. Assuming you need to meet tRAS, then precharge, 943 // open a new row, and access, it is ~4*tRCD. 944 945 946 Tick newTime = (busBusyUntil > 4 * tRCD) ? 947 std::max(busBusyUntil - 4 * tRCD, curTick()) : 948 curTick(); 949 950 if (!nextReqEvent.scheduled() && !stopReads){ 951 schedule(&nextReqEvent, newTime); 952 } else { 953 if (newTime < nextReqEvent.when()) 954 reschedule(&nextReqEvent, newTime); 955 } 956 957 958} 959 960void 961SimpleDRAM::moveToRespQ() 962{ 963 // Remove from read queue 964 DRAMPacket* dram_pkt = dramReadQueue.front(); 965 dramReadQueue.pop_front(); 966 967 // Insert into response queue sorted by readyTime 968 // It will be sent back to the requestor at its 969 // readyTime 970 if (dramRespQueue.empty()) { 971 dramRespQueue.push_front(dram_pkt); 972 assert(!respondEvent.scheduled()); 973 assert(dram_pkt->readyTime >= curTick()); 974 schedule(&respondEvent, dram_pkt->readyTime); 975 } else { 976 bool done = false; 977 std::list<DRAMPacket*>::iterator i = dramRespQueue.begin(); 978 while (!done && i != dramRespQueue.end()) { 979 if ((*i)->readyTime > dram_pkt->readyTime) { 980 dramRespQueue.insert(i, dram_pkt); 981 done = true; 982 } 983 ++i; 984 } 985 986 if (!done) 987 dramRespQueue.push_back(dram_pkt); 988 989 assert(respondEvent.scheduled()); 990 991 if (dramRespQueue.front()->readyTime < respondEvent.when()) { 992 assert(dramRespQueue.front()->readyTime >= curTick()); 993 reschedule(&respondEvent, dramRespQueue.front()->readyTime); 994 } 995 } 996 997 if (retryRdReq) { 998 retryRdReq = false; 999 port.sendRetry(); 1000 } 1001} 1002 1003void 1004SimpleDRAM::scheduleNextReq() 1005{ 1006 DPRINTF(DRAM, "Reached scheduleNextReq()\n"); 1007 1008 // Figure out which request goes next, and move it to front() 1009 if (!chooseNextReq()) { 1010 // In the case there is no read request to go next, see if we 1011 // are asked to drain, and if so trigger writes, this also 1012 // ensures that if we hit the write limit we will do this 1013 // multiple times until we are completely drained 1014 if (drainManager && !dramWriteQueue.empty() && !writeEvent.scheduled()) 1015 triggerWrites(); 1016 } else { 1017 doDRAMAccess(dramReadQueue.front()); 1018 } 1019} 1020 1021Tick 1022SimpleDRAM::maxBankFreeAt() const 1023{ 1024 Tick banksFree = 0; 1025 1026 for(int i = 0; i < ranksPerChannel; i++) 1027 for(int j = 0; j < banksPerRank; j++) 1028 banksFree = std::max(banks[i][j].freeAt, banksFree); 1029 1030 return banksFree; 1031} 1032 1033void 1034SimpleDRAM::processRefreshEvent() 1035{ 1036 DPRINTF(DRAM, "Refreshing at tick %ld\n", curTick()); 1037 1038 Tick banksFree = std::max(curTick(), maxBankFreeAt()) + tRFC; 1039 1040 for(int i = 0; i < ranksPerChannel; i++) 1041 for(int j = 0; j < banksPerRank; j++) 1042 banks[i][j].freeAt = banksFree; 1043 1044 schedule(&refreshEvent, curTick() + tREFI); 1045} 1046 1047void 1048SimpleDRAM::regStats() 1049{ 1050 using namespace Stats; 1051 1052 AbstractMemory::regStats(); 1053 1054 readReqs 1055 .name(name() + ".readReqs") 1056 .desc("Total number of read requests seen"); 1057 1058 writeReqs 1059 .name(name() + ".writeReqs") 1060 .desc("Total number of write requests seen"); 1061 1062 servicedByWrQ 1063 .name(name() + ".servicedByWrQ") 1064 .desc("Number of read reqs serviced by write Q"); 1065 1066 cpuReqs 1067 .name(name() + ".cpureqs") 1068 .desc("Reqs generatd by CPU via cache - shady"); 1069 1070 neitherReadNorWrite 1071 .name(name() + ".neitherReadNorWrite") 1072 .desc("Reqs where no action is needed"); 1073 1074 perBankRdReqs 1075 .init(banksPerRank * ranksPerChannel) 1076 .name(name() + ".perBankRdReqs") 1077 .desc("Track reads on a per bank basis"); 1078 1079 perBankWrReqs 1080 .init(banksPerRank * ranksPerChannel) 1081 .name(name() + ".perBankWrReqs") 1082 .desc("Track writes on a per bank basis"); 1083 1084 avgRdQLen 1085 .name(name() + ".avgRdQLen") 1086 .desc("Average read queue length over time") 1087 .precision(2); 1088 1089 avgWrQLen 1090 .name(name() + ".avgWrQLen") 1091 .desc("Average write queue length over time") 1092 .precision(2); 1093 1094 totQLat 1095 .name(name() + ".totQLat") 1096 .desc("Total cycles spent in queuing delays"); 1097 1098 totBankLat 1099 .name(name() + ".totBankLat") 1100 .desc("Total cycles spent in bank access"); 1101 1102 totBusLat 1103 .name(name() + ".totBusLat") 1104 .desc("Total cycles spent in databus access"); 1105 1106 totMemAccLat 1107 .name(name() + ".totMemAccLat") 1108 .desc("Sum of mem lat for all requests"); 1109 1110 avgQLat 1111 .name(name() + ".avgQLat") 1112 .desc("Average queueing delay per request") 1113 .precision(2); 1114 1115 avgQLat = totQLat / (readReqs - servicedByWrQ); 1116 1117 avgBankLat 1118 .name(name() + ".avgBankLat") 1119 .desc("Average bank access latency per request") 1120 .precision(2); 1121 1122 avgBankLat = totBankLat / (readReqs - servicedByWrQ); 1123 1124 avgBusLat 1125 .name(name() + ".avgBusLat") 1126 .desc("Average bus latency per request") 1127 .precision(2); 1128 1129 avgBusLat = totBusLat / (readReqs - servicedByWrQ); 1130 1131 avgMemAccLat 1132 .name(name() + ".avgMemAccLat") 1133 .desc("Average memory access latency") 1134 .precision(2); 1135 1136 avgMemAccLat = totMemAccLat / (readReqs - servicedByWrQ); 1137 1138 numRdRetry 1139 .name(name() + ".numRdRetry") 1140 .desc("Number of times rd buffer was full causing retry"); 1141 1142 numWrRetry 1143 .name(name() + ".numWrRetry") 1144 .desc("Number of times wr buffer was full causing retry"); 1145 1146 readRowHits 1147 .name(name() + ".readRowHits") 1148 .desc("Number of row buffer hits during reads"); 1149 1150 writeRowHits 1151 .name(name() + ".writeRowHits") 1152 .desc("Number of row buffer hits during writes"); 1153 1154 readRowHitRate 1155 .name(name() + ".readRowHitRate") 1156 .desc("Row buffer hit rate for reads") 1157 .precision(2); 1158 1159 readRowHitRate = (readRowHits / (readReqs - servicedByWrQ)) * 100; 1160 1161 writeRowHitRate 1162 .name(name() + ".writeRowHitRate") 1163 .desc("Row buffer hit rate for writes") 1164 .precision(2); 1165 1166 writeRowHitRate = (writeRowHits / writeReqs) * 100; 1167 1168 readPktSize 1169 .init(log2(bytesPerCacheLine)+3) 1170 .name(name() + ".readPktSize") 1171 .desc("Categorize read packet sizes"); 1172 1173 writePktSize 1174 .init(log2(bytesPerCacheLine)+3) 1175 .name(name() + ".writePktSize") 1176 .desc("categorize write packet sizes"); 1177 1178 neitherPktSize 1179 .init(log2(bytesPerCacheLine)+3) 1180 .name(name() + ".neitherpktsize") 1181 .desc("categorize neither packet sizes"); 1182 1183 rdQLenPdf 1184 .init(readBufferSize + 1) 1185 .name(name() + ".rdQLenPdf") 1186 .desc("What read queue length does an incoming req see"); 1187 1188 wrQLenPdf 1189 .init(writeBufferSize + 1) 1190 .name(name() + ".wrQLenPdf") 1191 .desc("What write queue length does an incoming req see"); 1192 1193 1194 bytesRead 1195 .name(name() + ".bytesRead") 1196 .desc("Total number of bytes read from memory"); 1197 1198 bytesWritten 1199 .name(name() + ".bytesWritten") 1200 .desc("Total number of bytes written to memory"); 1201 1202 bytesConsumedRd 1203 .name(name() + ".bytesConsumedRd") 1204 .desc("bytesRead derated as per pkt->getSize()"); 1205 1206 bytesConsumedWr 1207 .name(name() + ".bytesConsumedWr") 1208 .desc("bytesWritten derated as per pkt->getSize()"); 1209 1210 avgRdBW 1211 .name(name() + ".avgRdBW") 1212 .desc("Average achieved read bandwidth in MB/s") 1213 .precision(2); 1214 1215 avgRdBW = (bytesRead / 1000000) / simSeconds; 1216 1217 avgWrBW 1218 .name(name() + ".avgWrBW") 1219 .desc("Average achieved write bandwidth in MB/s") 1220 .precision(2); 1221 1222 avgWrBW = (bytesWritten / 1000000) / simSeconds; 1223 1224 avgConsumedRdBW 1225 .name(name() + ".avgConsumedRdBW") 1226 .desc("Average consumed read bandwidth in MB/s") 1227 .precision(2); 1228 1229 avgConsumedRdBW = (bytesConsumedRd / 1000000) / simSeconds; 1230 1231 avgConsumedWrBW 1232 .name(name() + ".avgConsumedWrBW") 1233 .desc("Average consumed write bandwidth in MB/s") 1234 .precision(2); 1235 1236 avgConsumedWrBW = (bytesConsumedWr / 1000000) / simSeconds; 1237 1238 peakBW 1239 .name(name() + ".peakBW") 1240 .desc("Theoretical peak bandwidth in MB/s") 1241 .precision(2); 1242 1243 peakBW = (SimClock::Frequency / tBURST) * bytesPerCacheLine / 1000000; 1244 1245 busUtil 1246 .name(name() + ".busUtil") 1247 .desc("Data bus utilization in percentage") 1248 .precision(2); 1249 1250 busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 1251 1252 totGap 1253 .name(name() + ".totGap") 1254 .desc("Total gap between requests"); 1255 1256 avgGap 1257 .name(name() + ".avgGap") 1258 .desc("Average gap between requests") 1259 .precision(2); 1260 1261 avgGap = totGap / (readReqs + writeReqs); 1262} 1263 1264void 1265SimpleDRAM::recvFunctional(PacketPtr pkt) 1266{ 1267 // rely on the abstract memory 1268 functionalAccess(pkt); 1269} 1270 1271BaseSlavePort& 1272SimpleDRAM::getSlavePort(const string &if_name, PortID idx) 1273{ 1274 if (if_name != "port") { 1275 return MemObject::getSlavePort(if_name, idx); 1276 } else { 1277 return port; 1278 } 1279} 1280 1281unsigned int 1282SimpleDRAM::drain(DrainManager *dm) 1283{ 1284 unsigned int count = port.drain(dm); 1285 1286 // if there is anything in any of our internal queues, keep track 1287 // of that as well 1288 if (!(dramWriteQueue.empty() && dramReadQueue.empty() && 1289 dramRespQueue.empty())) { 1290 DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 1291 " resp: %d\n", dramWriteQueue.size(), dramReadQueue.size(), 1292 dramRespQueue.size()); 1293 ++count; 1294 drainManager = dm; 1295 // the only part that is not drained automatically over time 1296 // is the write queue, thus trigger writes if there are any 1297 // waiting and no reads waiting, otherwise wait until the 1298 // reads are done 1299 if (dramReadQueue.empty() && !dramWriteQueue.empty() && 1300 !writeEvent.scheduled()) 1301 triggerWrites(); 1302 } 1303 1304 if (count) 1305 setDrainState(Drainable::Draining); 1306 else 1307 setDrainState(Drainable::Drained); 1308 return count; 1309} 1310 1311SimpleDRAM::MemoryPort::MemoryPort(const std::string& name, SimpleDRAM& _memory) 1312 : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 1313 memory(_memory) 1314{ } 1315 1316AddrRangeList 1317SimpleDRAM::MemoryPort::getAddrRanges() const 1318{ 1319 AddrRangeList ranges; 1320 ranges.push_back(memory.getAddrRange()); 1321 return ranges; 1322} 1323 1324void 1325SimpleDRAM::MemoryPort::recvFunctional(PacketPtr pkt) 1326{ 1327 pkt->pushLabel(memory.name()); 1328 1329 if (!queue.checkFunctional(pkt)) { 1330 // Default implementation of SimpleTimingPort::recvFunctional() 1331 // calls recvAtomic() and throws away the latency; we can save a 1332 // little here by just not calculating the latency. 1333 memory.recvFunctional(pkt); 1334 } 1335 1336 pkt->popLabel(); 1337} 1338 1339Tick 1340SimpleDRAM::MemoryPort::recvAtomic(PacketPtr pkt) 1341{ 1342 return memory.recvAtomic(pkt); 1343} 1344 1345bool 1346SimpleDRAM::MemoryPort::recvTimingReq(PacketPtr pkt) 1347{ 1348 // pass it to the memory controller 1349 return memory.recvTimingReq(pkt); 1350} 1351 1352SimpleDRAM* 1353SimpleDRAMParams::create() 1354{ 1355 return new SimpleDRAM(this); 1356} 1357