dram_ctrl.cc revision 9352
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andreas Hansson 38 * Ani Udipi 39 */ 40 41#include "debug/Drain.hh" 42#include "debug/DRAM.hh" 43#include "debug/DRAMWR.hh" 44#include "mem/simple_dram.hh" 45#include "sim/stat_control.hh" 46 47using namespace std; 48 49SimpleDRAM::SimpleDRAM(const SimpleDRAMParams* p) : 50 AbstractMemory(p), 51 port(name() + ".port", *this), 52 retryRdReq(false), retryWrReq(false), 53 rowHitFlag(false), stopReads(false), 54 writeEvent(this), respondEvent(this), 55 refreshEvent(this), nextReqEvent(this), drainManager(NULL), 56 bytesPerCacheLine(0), 57 linesPerRowBuffer(p->lines_per_rowbuffer), 58 ranksPerChannel(p->ranks_per_channel), 59 banksPerRank(p->banks_per_rank), rowsPerBank(0), 60 readBufferSize(p->read_buffer_size), 61 writeBufferSize(p->write_buffer_size), 62 writeThresholdPerc(p->write_thresh_perc), 63 tWTR(p->tWTR), tBURST(p->tBURST), 64 tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), 65 tRFC(p->tRFC), tREFI(p->tREFI), 66 memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 67 pageMgmt(p->page_policy), 68 busBusyUntil(0), prevdramaccess(0), writeStartTime(0), 69 prevArrival(0), numReqs(0) 70{ 71 // create the bank states based on the dimensions of the ranks and 72 // banks 73 banks.resize(ranksPerChannel); 74 for (size_t c = 0; c < ranksPerChannel; ++c) { 75 banks[c].resize(banksPerRank); 76 } 77 78 // round the write threshold percent to a whole number of entries 79 // in the buffer 80 writeThreshold = writeBufferSize * writeThresholdPerc / 100.0; 81} 82 83void 84SimpleDRAM::init() 85{ 86 if (!port.isConnected()) { 87 fatal("SimpleDRAM %s is unconnected!\n", name()); 88 } else { 89 port.sendRangeChange(); 90 } 91 92 // get the cache line size from the connected port 93 bytesPerCacheLine = port.peerBlockSize(); 94 95 // we could deal with plenty options here, but for now do a quick 96 // sanity check 97 if (bytesPerCacheLine != 64 && bytesPerCacheLine != 32) 98 panic("Unexpected cache line size %d", bytesPerCacheLine); 99 100 // determine the rows per bank by looking at the total capacity 101 uint64_t capacity = AbstractMemory::size(); 102 uint64_t i = 1; 103 while (i < 64 && capacity > ((1 << i))) { 104 ++i; 105 } 106 107 // rounded up to nearest power of two 108 DPRINTF(DRAM, "i is %lld\n", i); 109 capacity = 1 << i; 110 111 DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 112 AbstractMemory::size()); 113 rowsPerBank = capacity / (bytesPerCacheLine * linesPerRowBuffer * 114 banksPerRank * ranksPerChannel); 115 116} 117 118void 119SimpleDRAM::startup() 120{ 121 // print the configuration of the controller 122 printParams(); 123 124 // kick off the refresh 125 schedule(&refreshEvent, curTick() + tREFI); 126} 127 128 129Tick 130SimpleDRAM::recvAtomic(PacketPtr pkt) 131{ 132 DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 133 134 // do the actual memory access and turn the packet into a response 135 access(pkt); 136 137 Tick latency = 0; 138 if (!pkt->memInhibitAsserted() && pkt->hasData()) { 139 // this value is not supposed to be accurate, just enough to 140 // keep things going, mimic a closed page 141 latency = tRP + tRCD + tCL; 142 } 143 return latency; 144} 145 146bool 147SimpleDRAM::readQueueFull() const 148{ 149 DPRINTF(DRAM, "Read queue limit %d current size %d\n", 150 readBufferSize, dramReadQueue.size() + dramRespQueue.size()); 151 152 return (dramReadQueue.size() + dramRespQueue.size()) == readBufferSize; 153} 154 155bool 156SimpleDRAM::writeQueueFull() const 157{ 158 DPRINTF(DRAM, "Write queue limit %d current size %d\n", 159 writeBufferSize, dramWriteQueue.size()); 160 return dramWriteQueue.size() == writeBufferSize; 161} 162 163 164SimpleDRAM::DRAMPacket* 165SimpleDRAM::decodeAddr(PacketPtr pkt) 166{ 167 uint8_t rank; 168 uint16_t bank; 169 uint16_t row; 170 171 Addr addr = pkt->getAddr(); 172 Addr temp = addr; 173 174 // truncate the address to the access granularity 175 addr = addr / bytesPerCacheLine; 176 177 if (addrMapping == Enums::openmap) { 178 addr = addr / linesPerRowBuffer; 179 180 bank = addr % banksPerRank; 181 addr = addr / banksPerRank; 182 183 rank = addr % ranksPerChannel; 184 addr = addr / ranksPerChannel; 185 186 row = addr % rowsPerBank; 187 addr = addr / rowsPerBank; 188 } else if (addrMapping == Enums::closemap) { 189 bank = addr % banksPerRank; 190 addr = addr / banksPerRank; 191 192 rank = addr % ranksPerChannel; 193 addr = addr / ranksPerChannel; 194 195 addr = addr / linesPerRowBuffer; 196 197 row = addr % rowsPerBank; 198 addr = addr / rowsPerBank; 199 } else 200 panic("Unknown address mapping policy chosen!"); 201 202 assert(rank < ranksPerChannel); 203 assert(bank < banksPerRank); 204 assert(row < rowsPerBank); 205 206 DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 207 temp, rank, bank, row); 208 209 // create the corresponding DRAM packet with the entry time and 210 // ready time set to the current tick, they will be updated later 211 DRAMPacket* dram_pkt = new DRAMPacket(pkt, rank, bank, row, temp, 212 banks[rank][bank]); 213 214 return dram_pkt; 215} 216 217void 218SimpleDRAM::addToReadQueue(PacketPtr pkt) 219{ 220 // only add to the read queue here. whenever the request is 221 // eventually done, set the readyTime, and call schedule() 222 assert(!pkt->isWrite()); 223 224 // First check write buffer to see if the data is already at 225 // the controller 226 std::list<DRAMPacket*>::const_iterator i; 227 Addr addr = pkt->getAddr(); 228 229 // @todo: add size check 230 for (i = dramWriteQueue.begin(); i != dramWriteQueue.end(); ++i) { 231 if ((*i)->addr == addr){ 232 servicedByWrQ++; 233 DPRINTF(DRAM,"Serviced by write Q\n"); 234 bytesRead += bytesPerCacheLine; 235 bytesConsumedRd += pkt->getSize(); 236 accessAndRespond(pkt); 237 return; 238 } 239 } 240 241 DRAMPacket* dram_pkt = decodeAddr(pkt); 242 243 assert(dramReadQueue.size() + dramRespQueue.size() < readBufferSize); 244 rdQLenPdf[dramReadQueue.size() + dramRespQueue.size()]++; 245 246 DPRINTF(DRAM, "Adding to read queue\n"); 247 248 dramReadQueue.push_back(dram_pkt); 249 250 // Update stats 251 uint32_t bank_id = banksPerRank * dram_pkt->rank + dram_pkt->bank; 252 assert(bank_id < ranksPerChannel * banksPerRank); 253 perBankRdReqs[bank_id]++; 254 255 avgRdQLen = dramReadQueue.size() + dramRespQueue.size(); 256 257 // Special case where no arbitration is required between requests 258 if (!nextReqEvent.scheduled() && !stopReads) { 259 DPRINTF(DRAM, "Request %lld - need to schedule immediately"); 260 schedule(&nextReqEvent, curTick() + 1); 261 } 262} 263 264void 265SimpleDRAM::processWriteEvent() 266{ 267 assert(!dramWriteQueue.empty()); 268 uint32_t numWritesThisTime = 0; 269 270 DPRINTF(DRAMWR, "Beginning DRAM Writes\n"); 271 Tick temp1 M5_VAR_USED = std::max(curTick(), busBusyUntil); 272 Tick temp2 M5_VAR_USED = std::max(curTick(), maxBankFreeAt()); 273 274 // @todo: are there any dangers with the untimed while loop? 275 while (!dramWriteQueue.empty()) { 276 if (numWritesThisTime > writeThreshold) 277 break; 278 279 chooseNextWrite(); 280 DRAMPacket* dram_pkt = dramWriteQueue.front(); 281 // What's the earlier the request can be put on the bus 282 Tick schedTime = std::max(curTick(), busBusyUntil); 283 284 DPRINTF(DRAMWR, "Asking for latency estimate at %lld\n", 285 schedTime + tBURST); 286 287 pair<Tick, Tick> lat = estimateLatency(dram_pkt, schedTime + tBURST); 288 Tick accessLat = lat.second; 289 290 // look at the rowHitFlag set by estimateLatency 291 292 // @todo: Race condition here where another packet gives rise 293 // to another call to estimateLatency in the meanwhile? 294 if (rowHitFlag) 295 writeRowHits++; 296 297 Bank& bank = dram_pkt->bank_ref; 298 299 if (pageMgmt == Enums::open) { 300 bank.openRow = dram_pkt->row; 301 bank.freeAt = schedTime + tBURST + accessLat; 302 303 if (!rowHitFlag) 304 bank.tRASDoneAt = bank.freeAt + tRP; 305 306 } else if (pageMgmt == Enums::close) { 307 bank.freeAt = schedTime + tBURST + accessLat + tRP + tRP; 308 DPRINTF(DRAMWR, "processWriteEvent::bank.freeAt for " 309 "banks_id %d is %lld\n", 310 dram_pkt->rank * banksPerRank + dram_pkt->bank, 311 bank.freeAt); 312 } else 313 panic("Unknown page management policy chosen\n"); 314 315 // @todo: As of now, write goes on the databus asap, maybe 316 // be held up at bank. May want to change it to delay the 317 // schedTime itself. 318 busBusyUntil = schedTime + tBURST; 319 DPRINTF(DRAMWR,"Done writing to address %lld\n",dram_pkt->addr); 320 321 322 DPRINTF(DRAMWR,"schedtime is %lld, tBURST is %lld, " 323 "busbusyuntil is %lld\n", 324 schedTime, tBURST, busBusyUntil); 325 326 dramWriteQueue.pop_front(); 327 delete dram_pkt; 328 329 numWritesThisTime++; 330 } 331 332 DPRINTF(DRAMWR, "Completed %d writes, bus busy for %lld ticks,"\ 333 "banks busy for %lld ticks\n", numWritesThisTime, 334 busBusyUntil - temp1, maxBankFreeAt() - temp2); 335 336 // Update stats 337 avgWrQLen = dramWriteQueue.size(); 338 339 // turn the bus back around for reads again 340 busBusyUntil += tWTR; 341 stopReads = false; 342 343 if (retryWrReq) { 344 retryWrReq = false; 345 port.sendRetry(); 346 } 347 348 // if there is nothing left in any queue, signal a drain 349 if (dramWriteQueue.empty() && dramReadQueue.empty() && 350 dramRespQueue.empty () && drainManager) { 351 drainManager->signalDrainDone(); 352 drainManager = NULL; 353 } 354 355 // Once you're done emptying the write queue, check if there's 356 // anything in the read queue, and call schedule if required 357 schedule(&nextReqEvent, busBusyUntil); 358} 359 360void 361SimpleDRAM::triggerWrites() 362{ 363 DPRINTF(DRAM, "Writes triggered at %lld\n", curTick()); 364 // Flag variable to stop any more read scheduling 365 stopReads = true; 366 367 writeStartTime = std::max(busBusyUntil, curTick()) + tWTR; 368 369 DPRINTF(DRAM, "Writes scheduled at %lld\n", writeStartTime); 370 371 assert(writeStartTime >= curTick()); 372 assert(!writeEvent.scheduled()); 373 schedule(&writeEvent, writeStartTime); 374} 375 376void 377SimpleDRAM::addToWriteQueue(PacketPtr pkt) 378{ 379 // only add to the write queue here. whenever the request is 380 // eventually done, set the readyTime, and call schedule() 381 assert(pkt->isWrite()); 382 383 DRAMPacket* dram_pkt = decodeAddr(pkt); 384 385 assert(dramWriteQueue.size() < writeBufferSize); 386 wrQLenPdf[dramWriteQueue.size()]++; 387 388 DPRINTF(DRAM, "Adding to write queue\n"); 389 390 dramWriteQueue.push_back(dram_pkt); 391 392 // Update stats 393 uint32_t bank_id = banksPerRank * dram_pkt->rank + dram_pkt->bank; 394 assert(bank_id < ranksPerChannel * banksPerRank); 395 perBankWrReqs[bank_id]++; 396 397 avgWrQLen = dramWriteQueue.size(); 398 399 // we do not wait for the writes to be send to the actual memory, 400 // but instead take responsibility for the consistency here and 401 // snoop the write queue for any upcoming reads 402 403 bytesConsumedWr += pkt->getSize(); 404 bytesWritten += bytesPerCacheLine; 405 accessAndRespond(pkt); 406 407 // If your write buffer is starting to fill up, drain it! 408 if (dramWriteQueue.size() > writeThreshold && !stopReads){ 409 triggerWrites(); 410 } 411} 412 413void 414SimpleDRAM::printParams() const 415{ 416 // Sanity check print of important parameters 417 DPRINTF(DRAM, 418 "Memory controller %s physical organization\n" \ 419 "Bytes per cacheline %d\n" \ 420 "Lines per row buffer %d\n" \ 421 "Rows per bank %d\n" \ 422 "Banks per rank %d\n" \ 423 "Ranks per channel %d\n" \ 424 "Total mem capacity %u\n", 425 name(), bytesPerCacheLine ,linesPerRowBuffer, rowsPerBank, 426 banksPerRank, ranksPerChannel, bytesPerCacheLine * 427 linesPerRowBuffer * rowsPerBank * banksPerRank * ranksPerChannel); 428 429 string scheduler = memSchedPolicy == Enums::fcfs ? "FCFS" : "FR-FCFS"; 430 string address_mapping = addrMapping == Enums::openmap ? "OPENMAP" : 431 "CLOSEMAP"; 432 string page_policy = pageMgmt == Enums::open ? "OPEN" : "CLOSE"; 433 434 DPRINTF(DRAM, 435 "Memory controller %s characteristics\n" \ 436 "Read buffer size %d\n" \ 437 "Write buffer size %d\n" \ 438 "Write buffer thresh %d\n" \ 439 "Scheduler %s\n" \ 440 "Address mapping %s\n" \ 441 "Page policy %s\n", 442 name(), readBufferSize, writeBufferSize, writeThreshold, 443 scheduler, address_mapping, page_policy); 444 445 DPRINTF(DRAM, "Memory controller %s timing specs\n" \ 446 "tRCD %d ticks\n" \ 447 "tCL %d ticks\n" \ 448 "tRP %d ticks\n" \ 449 "tBURST %d ticks\n" \ 450 "tRFC %d ticks\n" \ 451 "tREFI %d ticks\n" \ 452 "tWTR %d ticks\n", 453 name(), tRCD, tCL, tRP, tBURST, tRFC, tREFI, tWTR); 454} 455 456void 457SimpleDRAM::printQs() const { 458 459 list<DRAMPacket*>::const_iterator i; 460 461 DPRINTF(DRAM, "===READ QUEUE===\n\n"); 462 for (i = dramReadQueue.begin() ; i != dramReadQueue.end() ; ++i) { 463 DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 464 } 465 DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 466 for (i = dramRespQueue.begin() ; i != dramRespQueue.end() ; ++i) { 467 DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 468 } 469 DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 470 for (i = dramWriteQueue.begin() ; i != dramWriteQueue.end() ; ++i) { 471 DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 472 } 473} 474 475bool 476SimpleDRAM::recvTimingReq(PacketPtr pkt) 477{ 478 /// @todo temporary hack to deal with memory corruption issues until 479 /// 4-phase transactions are complete 480 for (int x = 0; x < pendingDelete.size(); x++) 481 delete pendingDelete[x]; 482 pendingDelete.clear(); 483 484 485 // This is where we enter from the outside world 486 DPRINTF(DRAM, "Inside recvTimingReq: request %s addr %lld size %d\n", 487 pkt->cmdString(),pkt->getAddr(), pkt->getSize()); 488 489 int index; 490 491 if (pkt->getSize() == bytesPerCacheLine) 492 cpuReqs++; 493 494 if (numReqs % 1000000 == 0) 495 printQs(); 496 497 // Calc avg gap between requests 498 if (prevArrival != 0) { 499 totGap += curTick() - prevArrival; 500 } 501 prevArrival = curTick(); 502 503 // simply drop inhibited packets for now 504 if (pkt->memInhibitAsserted()) { 505 DPRINTF(DRAM,"Inhibited packet -- Dropping it now\n"); 506 pendingDelete.push_back(pkt); 507 return true; 508 } 509 510 unsigned size = pkt->getSize(); 511 if (size > bytesPerCacheLine) 512 panic("Request size %d is greater than cache line size %d", 513 size, bytesPerCacheLine); 514 515 if (size == 0) 516 index = log2(bytesPerCacheLine) + 1; 517 else 518 index = log2(size); 519 520 if (size != 0 && (1 << index) != size) 521 index = log2(bytesPerCacheLine) + 2; 522 523 // @todo: Do we really want to do all this before the packet is 524 // actually accepted? 525 526 /* Index 0 - Size 1 byte 527 Index 1 - Size 2 bytes 528 Index 2 - Size 4 bytes 529 . 530 . 531 Index 6 - Size 64 bytes 532 Index 7 - Size 0 bytes 533 Index 8 - Non-power-of-2 size */ 534 535 if (pkt->isRead()) 536 readPktSize[index]++; 537 else if (pkt->isWrite()) 538 writePktSize[index]++; 539 else 540 neitherPktSize[index]++; 541 542 // check local buffers and do not accept if full 543 if (pkt->isRead()) { 544 if (readQueueFull()) { 545 DPRINTF(DRAM,"Read queue full, not accepting\n"); 546 // remember that we have to retry this port 547 retryRdReq = true; 548 numRdRetry++; 549 return false; 550 } else { 551 addToReadQueue(pkt); 552 readReqs++; 553 numReqs++; 554 } 555 } else if (pkt->isWrite()) { 556 if (writeQueueFull()) { 557 DPRINTF(DRAM,"Write queue full, not accepting\n"); 558 // remember that we have to retry this port 559 retryWrReq = true; 560 numWrRetry++; 561 return false; 562 } else { 563 addToWriteQueue(pkt); 564 writeReqs++; 565 numReqs++; 566 } 567 } else { 568 DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 569 neitherReadNorWrite++; 570 accessAndRespond(pkt); 571 } 572 573 574 retryRdReq = false; 575 retryWrReq = false; 576 return true; 577} 578 579void 580SimpleDRAM::processRespondEvent() 581{ 582 DPRINTF(DRAM, 583 "processRespondEvent(): Some req has reached its readyTime\n"); 584 585 PacketPtr pkt = dramRespQueue.front()->pkt; 586 587 // Actually responds to the requestor 588 bytesConsumedRd += pkt->getSize(); 589 bytesRead += bytesPerCacheLine; 590 accessAndRespond(pkt); 591 592 DRAMPacket* dram_pkt = dramRespQueue.front(); 593 dramRespQueue.pop_front(); 594 delete dram_pkt; 595 596 // Update stats 597 avgRdQLen = dramReadQueue.size() + dramRespQueue.size(); 598 599 if (!dramRespQueue.empty()){ 600 assert(dramRespQueue.front()->readyTime >= curTick()); 601 assert(!respondEvent.scheduled()); 602 schedule(&respondEvent, dramRespQueue.front()->readyTime); 603 } else { 604 // if there is nothing left in any queue, signal a drain 605 if (dramWriteQueue.empty() && dramReadQueue.empty() && 606 drainManager) { 607 drainManager->signalDrainDone(); 608 drainManager = NULL; 609 } 610 } 611} 612 613void 614SimpleDRAM::chooseNextWrite() 615{ 616 // This method does the arbitration between requests. The chosen 617 // packet is simply moved to the head of the queue. The other 618 // methods know that this is the place to look. For example, with 619 // FCFS, this method does nothing 620 assert(!dramWriteQueue.empty()); 621 622 if (dramWriteQueue.size() == 1) { 623 DPRINTF(DRAMWR, "chooseNextWrite(): Single element, nothing to do\n"); 624 return; 625 } 626 627 if (memSchedPolicy == Enums::fcfs) { 628 629 // Do nothing, since the correct request is already head 630 631 } else if (memSchedPolicy == Enums::frfcfs) { 632 633 list<DRAMPacket*>::iterator i = dramWriteQueue.begin(); 634 bool foundRowHit = false; 635 while (!foundRowHit && i != dramWriteQueue.end()) { 636 DRAMPacket* dram_pkt = *i; 637 const Bank& bank = dram_pkt->bank_ref; 638 if (bank.openRow == dram_pkt->row) { //FR part 639 DPRINTF(DRAMWR,"Row buffer hit\n"); 640 dramWriteQueue.erase(i); 641 dramWriteQueue.push_front(dram_pkt); 642 foundRowHit = true; 643 } else { //FCFS part 644 ; 645 } 646 ++i; 647 } 648 649 } else 650 panic("No scheduling policy chosen\n"); 651 652 DPRINTF(DRAMWR, "chooseNextWrite(): Something chosen\n"); 653} 654 655bool 656SimpleDRAM::chooseNextReq() 657{ 658 // This method does the arbitration between requests. 659 // The chosen packet is simply moved to the head of the 660 // queue. The other methods know that this is the place 661 // to look. For example, with FCFS, this method does nothing 662 list<DRAMPacket*>::iterator i; 663 DRAMPacket* dram_pkt; 664 665 if (dramReadQueue.empty()){ 666 DPRINTF(DRAM, "chooseNextReq(): Returning False\n"); 667 return false; 668 } 669 670 if (dramReadQueue.size() == 1) 671 return true; 672 673 if (memSchedPolicy == Enums::fcfs) { 674 675 // Do nothing, since the correct request is already head 676 677 } else if (memSchedPolicy == Enums::frfcfs) { 678 679 for (i = dramReadQueue.begin() ; i != dramReadQueue.end() ; ++i) { 680 dram_pkt = *i; 681 const Bank& bank = dram_pkt->bank_ref; 682 if (bank.openRow == dram_pkt->row) { //FR part 683 DPRINTF(DRAM, "Row buffer hit\n"); 684 dramReadQueue.erase(i); 685 dramReadQueue.push_front(dram_pkt); 686 break; 687 } else { //FCFS part 688 ; 689 } 690 691 } 692 693 } else 694 panic("No scheduling policy chosen!\n"); 695 696 697 DPRINTF(DRAM,"chooseNextReq(): Chosen something, returning True\n"); 698 return true; 699} 700 701void 702SimpleDRAM::accessAndRespond(PacketPtr pkt) 703{ 704 DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 705 706 bool needsResponse = pkt->needsResponse(); 707 // do the actual memory access which also turns the packet into a 708 // response 709 access(pkt); 710 711 // turn packet around to go back to requester if response expected 712 if (needsResponse) { 713 // access already turned the packet into a response 714 assert(pkt->isResponse()); 715 716 // queue the packet in the response queue to be sent out the 717 // next tick 718 port.schedTimingResp(pkt, curTick() + 1); 719 } else { 720 } 721 722 DPRINTF(DRAM, "Done\n"); 723 724 return; 725} 726 727pair<Tick, Tick> 728SimpleDRAM::estimateLatency(DRAMPacket* dram_pkt, Tick inTime) 729{ 730 // If a request reaches a bank at tick 'inTime', how much time 731 // *after* that does it take to finish the request, depending 732 // on bank status and page open policy. Note that this method 733 // considers only the time taken for the actual read or write 734 // to complete, NOT any additional time thereafter for tRAS or 735 // tRP. 736 Tick accLat = 0; 737 Tick bankLat = 0; 738 rowHitFlag = false; 739 740 const Bank& bank = dram_pkt->bank_ref; 741 if (pageMgmt == Enums::open) { // open-page policy 742 if (bank.openRow == dram_pkt->row) { 743 // When we have a row-buffer hit, 744 // we don't care about tRAS having expired or not, 745 // but do care about bank being free for access 746 rowHitFlag = true; 747 748 if (bank.freeAt < inTime) { 749 // CAS latency only 750 accLat += tCL; 751 bankLat += tCL; 752 } else { 753 accLat += 0; 754 bankLat += 0; 755 } 756 757 } else { 758 // Row-buffer miss, need to close existing row 759 // once tRAS has expired, then open the new one, 760 // then add cas latency. 761 Tick freeTime = std::max(bank.tRASDoneAt, bank.freeAt); 762 763 if (freeTime > inTime) 764 accLat += freeTime - inTime; 765 766 accLat += tRP + tRCD + tCL; 767 bankLat += tRP + tRCD + tCL; 768 } 769 } else if (pageMgmt == Enums::close) { 770 771 // With a close page policy, no notion of 772 // bank.tRASDoneAt 773 if (bank.freeAt > inTime) 774 accLat += bank.freeAt - inTime; 775 776 // page already closed, simply open the row, and 777 // add cas latency 778 accLat += tRCD + tCL; 779 bankLat += tRCD + tCL; 780 } else 781 panic("No page management policy chosen\n"); 782 783 DPRINTF(DRAM, "Returning %lld from estimateLatency()\n",accLat); 784 785 return make_pair(bankLat, accLat); 786} 787 788void 789SimpleDRAM::processNextReqEvent() 790{ 791 scheduleNextReq(); 792} 793 794void 795SimpleDRAM::doDRAMAccess(DRAMPacket* dram_pkt) 796{ 797 798 DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 799 dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 800 801 assert(curTick() >= prevdramaccess); 802 prevdramaccess = curTick(); 803 804 // estimate the bank and access latency 805 pair<Tick, Tick> lat = estimateLatency(dram_pkt, curTick()); 806 Tick bankLat = lat.first; 807 Tick accessLat = lat.second; 808 809 // This request was woken up at this time based on a prior call 810 // to estimateLatency(). However, between then and now, both the 811 // accessLatency and/or busBusyUntil may have changed. We need 812 // to correct for that. 813 814 Tick addDelay = (curTick() + accessLat < busBusyUntil) ? 815 busBusyUntil - (curTick() + accessLat) : 0; 816 817 Bank& bank = dram_pkt->bank_ref; 818 819 // Update bank state 820 if (pageMgmt == Enums::open) { 821 bank.openRow = dram_pkt->row; 822 bank.freeAt = curTick() + addDelay + accessLat; 823 // If you activated a new row do to this access, the next access 824 // will have to respect tRAS for this bank. Assume tRAS ~= 3 * tRP 825 if (!rowHitFlag) 826 bank.tRASDoneAt = bank.freeAt + tRP; 827 828 } else if (pageMgmt == Enums::close) { // accounting for tRAS also 829 // assuming that tRAS ~= 3 * tRP, and tRAS ~= 4 * tRP, as is common 830 // (refer Jacob/Ng/Wang and Micron datasheets) 831 bank.freeAt = curTick() + addDelay + accessLat + tRP + tRP; 832 DPRINTF(DRAM,"doDRAMAccess::bank.freeAt is %lld\n",bank.freeAt); 833 } else 834 panic("No page management policy chosen\n"); 835 836 // Update request parameters 837 dram_pkt->readyTime = curTick() + addDelay + accessLat + tBURST; 838 839 840 DPRINTF(DRAM, "Req %lld: curtick is %lld accessLat is %d " \ 841 "readytime is %lld busbusyuntil is %lld. " \ 842 "Scheduling at readyTime\n", dram_pkt->addr, 843 curTick(), accessLat, dram_pkt->readyTime, busBusyUntil); 844 845 // Make sure requests are not overlapping on the databus 846 assert (dram_pkt->readyTime - busBusyUntil >= tBURST); 847 848 // Update bus state 849 busBusyUntil = dram_pkt->readyTime; 850 851 DPRINTF(DRAM,"Access time is %lld\n", 852 dram_pkt->readyTime - dram_pkt->entryTime); 853 854 // Update stats 855 totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 856 totBankLat += bankLat; 857 totBusLat += tBURST; 858 totQLat += dram_pkt->readyTime - dram_pkt->entryTime - bankLat - tBURST; 859 860 if (rowHitFlag) 861 readRowHits++; 862 863 // At this point we're done dealing with the request 864 // It will be moved to a separate response queue with a 865 // correct readyTime, and eventually be sent back at that 866 //time 867 moveToRespQ(); 868 869 // The absolute soonest you have to start thinking about the 870 // next request is the longest access time that can occur before 871 // busBusyUntil. Assuming you need to meet tRAS, then precharge, 872 // open a new row, and access, it is ~4*tRCD. 873 874 875 Tick newTime = (busBusyUntil > 4 * tRCD) ? 876 std::max(busBusyUntil - 4 * tRCD, curTick()) : 877 curTick(); 878 879 if (!nextReqEvent.scheduled() && !stopReads){ 880 schedule(&nextReqEvent, newTime); 881 } else { 882 if (newTime < nextReqEvent.when()) 883 reschedule(&nextReqEvent, newTime); 884 } 885 886 887} 888 889void 890SimpleDRAM::moveToRespQ() 891{ 892 // Remove from read queue 893 DRAMPacket* dram_pkt = dramReadQueue.front(); 894 dramReadQueue.pop_front(); 895 896 // Insert into response queue sorted by readyTime 897 // It will be sent back to the requestor at its 898 // readyTime 899 if (dramRespQueue.empty()) { 900 dramRespQueue.push_front(dram_pkt); 901 assert(!respondEvent.scheduled()); 902 assert(dram_pkt->readyTime >= curTick()); 903 schedule(&respondEvent, dram_pkt->readyTime); 904 } else { 905 bool done = false; 906 std::list<DRAMPacket*>::iterator i = dramRespQueue.begin(); 907 while (!done && i != dramRespQueue.end()) { 908 if ((*i)->readyTime > dram_pkt->readyTime) { 909 dramRespQueue.insert(i, dram_pkt); 910 done = true; 911 } 912 ++i; 913 } 914 915 if (!done) 916 dramRespQueue.push_back(dram_pkt); 917 918 assert(respondEvent.scheduled()); 919 920 if (dramRespQueue.front()->readyTime < respondEvent.when()) { 921 assert(dramRespQueue.front()->readyTime >= curTick()); 922 reschedule(&respondEvent, dramRespQueue.front()->readyTime); 923 } 924 } 925 926 if (retryRdReq) { 927 retryRdReq = false; 928 port.sendRetry(); 929 } 930} 931 932void 933SimpleDRAM::scheduleNextReq() 934{ 935 DPRINTF(DRAM, "Reached scheduleNextReq()\n"); 936 937 // Figure out which request goes next, and move it to front() 938 if (!chooseNextReq()) { 939 // In the case there is no read request to go next, see if we 940 // are asked to drain, and if so trigger writes, this also 941 // ensures that if we hit the write limit we will do this 942 // multiple times until we are completely drained 943 if (drainManager && !dramWriteQueue.empty() && !writeEvent.scheduled()) 944 triggerWrites(); 945 } else { 946 doDRAMAccess(dramReadQueue.front()); 947 } 948} 949 950Tick 951SimpleDRAM::maxBankFreeAt() const 952{ 953 Tick banksFree = 0; 954 955 for(int i = 0; i < ranksPerChannel; i++) 956 for(int j = 0; j < banksPerRank; j++) 957 banksFree = std::max(banks[i][j].freeAt, banksFree); 958 959 return banksFree; 960} 961 962void 963SimpleDRAM::processRefreshEvent() 964{ 965 DPRINTF(DRAM, "Refreshing at tick %ld\n", curTick()); 966 967 Tick banksFree = std::max(curTick(), maxBankFreeAt()) + tRFC; 968 969 for(int i = 0; i < ranksPerChannel; i++) 970 for(int j = 0; j < banksPerRank; j++) 971 banks[i][j].freeAt = banksFree; 972 973 schedule(&refreshEvent, curTick() + tREFI); 974} 975 976void 977SimpleDRAM::regStats() 978{ 979 using namespace Stats; 980 981 AbstractMemory::regStats(); 982 983 readReqs 984 .name(name() + ".readReqs") 985 .desc("Total number of read requests seen"); 986 987 writeReqs 988 .name(name() + ".writeReqs") 989 .desc("Total number of write requests seen"); 990 991 servicedByWrQ 992 .name(name() + ".servicedByWrQ") 993 .desc("Number of read reqs serviced by write Q"); 994 995 cpuReqs 996 .name(name() + ".cpureqs") 997 .desc("Reqs generatd by CPU via cache - shady"); 998 999 neitherReadNorWrite 1000 .name(name() + ".neitherReadNorWrite") 1001 .desc("Reqs where no action is needed"); 1002 1003 perBankRdReqs 1004 .init(banksPerRank * ranksPerChannel) 1005 .name(name() + ".perBankRdReqs") 1006 .desc("Track reads on a per bank basis"); 1007 1008 perBankWrReqs 1009 .init(banksPerRank * ranksPerChannel) 1010 .name(name() + ".perBankWrReqs") 1011 .desc("Track writes on a per bank basis"); 1012 1013 avgRdQLen 1014 .name(name() + ".avgRdQLen") 1015 .desc("Average read queue length over time") 1016 .precision(2); 1017 1018 avgWrQLen 1019 .name(name() + ".avgWrQLen") 1020 .desc("Average write queue length over time") 1021 .precision(2); 1022 1023 totQLat 1024 .name(name() + ".totQLat") 1025 .desc("Total cycles spent in queuing delays"); 1026 1027 totBankLat 1028 .name(name() + ".totBankLat") 1029 .desc("Total cycles spent in bank access"); 1030 1031 totBusLat 1032 .name(name() + ".totBusLat") 1033 .desc("Total cycles spent in databus access"); 1034 1035 totMemAccLat 1036 .name(name() + ".totMemAccLat") 1037 .desc("Sum of mem lat for all requests"); 1038 1039 avgQLat 1040 .name(name() + ".avgQLat") 1041 .desc("Average queueing delay per request") 1042 .precision(2); 1043 1044 avgQLat = totQLat / (readReqs - servicedByWrQ); 1045 1046 avgBankLat 1047 .name(name() + ".avgBankLat") 1048 .desc("Average bank access latency per request") 1049 .precision(2); 1050 1051 avgBankLat = totBankLat / (readReqs - servicedByWrQ); 1052 1053 avgBusLat 1054 .name(name() + ".avgBusLat") 1055 .desc("Average bus latency per request") 1056 .precision(2); 1057 1058 avgBusLat = totBusLat / (readReqs - servicedByWrQ); 1059 1060 avgMemAccLat 1061 .name(name() + ".avgMemAccLat") 1062 .desc("Average memory access latency") 1063 .precision(2); 1064 1065 avgMemAccLat = totMemAccLat / (readReqs - servicedByWrQ); 1066 1067 numRdRetry 1068 .name(name() + ".numRdRetry") 1069 .desc("Number of times rd buffer was full causing retry"); 1070 1071 numWrRetry 1072 .name(name() + ".numWrRetry") 1073 .desc("Number of times wr buffer was full causing retry"); 1074 1075 readRowHits 1076 .name(name() + ".readRowHits") 1077 .desc("Number of row buffer hits during reads"); 1078 1079 writeRowHits 1080 .name(name() + ".writeRowHits") 1081 .desc("Number of row buffer hits during writes"); 1082 1083 readRowHitRate 1084 .name(name() + ".readRowHitRate") 1085 .desc("Row buffer hit rate for reads") 1086 .precision(2); 1087 1088 readRowHitRate = (readRowHits / (readReqs - servicedByWrQ)) * 100; 1089 1090 writeRowHitRate 1091 .name(name() + ".writeRowHitRate") 1092 .desc("Row buffer hit rate for writes") 1093 .precision(2); 1094 1095 writeRowHitRate = (writeRowHits / writeReqs) * 100; 1096 1097 readPktSize 1098 .init(log2(bytesPerCacheLine)+3) 1099 .name(name() + ".readPktSize") 1100 .desc("Categorize read packet sizes"); 1101 1102 writePktSize 1103 .init(log2(bytesPerCacheLine)+3) 1104 .name(name() + ".writePktSize") 1105 .desc("categorize write packet sizes"); 1106 1107 neitherPktSize 1108 .init(log2(bytesPerCacheLine)+3) 1109 .name(name() + ".neitherpktsize") 1110 .desc("categorize neither packet sizes"); 1111 1112 rdQLenPdf 1113 .init(readBufferSize + 1) 1114 .name(name() + ".rdQLenPdf") 1115 .desc("What read queue length does an incoming req see"); 1116 1117 wrQLenPdf 1118 .init(writeBufferSize + 1) 1119 .name(name() + ".wrQLenPdf") 1120 .desc("What write queue length does an incoming req see"); 1121 1122 1123 bytesRead 1124 .name(name() + ".bytesRead") 1125 .desc("Total number of bytes read from memory"); 1126 1127 bytesWritten 1128 .name(name() + ".bytesWritten") 1129 .desc("Total number of bytes written to memory"); 1130 1131 bytesConsumedRd 1132 .name(name() + ".bytesConsumedRd") 1133 .desc("bytesRead derated as per pkt->getSize()"); 1134 1135 bytesConsumedWr 1136 .name(name() + ".bytesConsumedWr") 1137 .desc("bytesWritten derated as per pkt->getSize()"); 1138 1139 avgRdBW 1140 .name(name() + ".avgRdBW") 1141 .desc("Average achieved read bandwidth in MB/s") 1142 .precision(2); 1143 1144 avgRdBW = (bytesRead / 1000000) / simSeconds; 1145 1146 avgWrBW 1147 .name(name() + ".avgWrBW") 1148 .desc("Average achieved write bandwidth in MB/s") 1149 .precision(2); 1150 1151 avgWrBW = (bytesWritten / 1000000) / simSeconds; 1152 1153 avgConsumedRdBW 1154 .name(name() + ".avgConsumedRdBW") 1155 .desc("Average consumed read bandwidth in MB/s") 1156 .precision(2); 1157 1158 avgConsumedRdBW = (bytesConsumedRd / 1000000) / simSeconds; 1159 1160 avgConsumedWrBW 1161 .name(name() + ".avgConsumedWrBW") 1162 .desc("Average consumed write bandwidth in MB/s") 1163 .precision(2); 1164 1165 avgConsumedWrBW = (bytesConsumedWr / 1000000) / simSeconds; 1166 1167 peakBW 1168 .name(name() + ".peakBW") 1169 .desc("Theoretical peak bandwidth in MB/s") 1170 .precision(2); 1171 1172 peakBW = (SimClock::Frequency / tBURST) * bytesPerCacheLine / 1000000; 1173 1174 busUtil 1175 .name(name() + ".busUtil") 1176 .desc("Data bus utilization in percentage") 1177 .precision(2); 1178 1179 busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 1180 1181 totGap 1182 .name(name() + ".totGap") 1183 .desc("Total gap between requests"); 1184 1185 avgGap 1186 .name(name() + ".avgGap") 1187 .desc("Average gap between requests") 1188 .precision(2); 1189 1190 avgGap = totGap / (readReqs + writeReqs); 1191} 1192 1193void 1194SimpleDRAM::recvFunctional(PacketPtr pkt) 1195{ 1196 // rely on the abstract memory 1197 functionalAccess(pkt); 1198} 1199 1200BaseSlavePort& 1201SimpleDRAM::getSlavePort(const string &if_name, PortID idx) 1202{ 1203 if (if_name != "port") { 1204 return MemObject::getSlavePort(if_name, idx); 1205 } else { 1206 return port; 1207 } 1208} 1209 1210unsigned int 1211SimpleDRAM::drain(DrainManager *dm) 1212{ 1213 unsigned int count = port.drain(dm); 1214 1215 // if there is anything in any of our internal queues, keep track 1216 // of that as well 1217 if (!(dramWriteQueue.empty() && dramReadQueue.empty() && 1218 dramRespQueue.empty())) { 1219 DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 1220 " resp: %d\n", dramWriteQueue.size(), dramReadQueue.size(), 1221 dramRespQueue.size()); 1222 ++count; 1223 drainManager = dm; 1224 // the only part that is not drained automatically over time 1225 // is the write queue, thus trigger writes if there are any 1226 // waiting and no reads waiting, otherwise wait until the 1227 // reads are done 1228 if (dramReadQueue.empty() && !dramWriteQueue.empty() && 1229 !writeEvent.scheduled()) 1230 triggerWrites(); 1231 } 1232 1233 if (count) 1234 setDrainState(Drainable::Draining); 1235 else 1236 setDrainState(Drainable::Drained); 1237 return count; 1238} 1239 1240SimpleDRAM::MemoryPort::MemoryPort(const std::string& name, SimpleDRAM& _memory) 1241 : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 1242 memory(_memory) 1243{ } 1244 1245AddrRangeList 1246SimpleDRAM::MemoryPort::getAddrRanges() const 1247{ 1248 AddrRangeList ranges; 1249 ranges.push_back(memory.getAddrRange()); 1250 return ranges; 1251} 1252 1253void 1254SimpleDRAM::MemoryPort::recvFunctional(PacketPtr pkt) 1255{ 1256 pkt->pushLabel(memory.name()); 1257 1258 if (!queue.checkFunctional(pkt)) { 1259 // Default implementation of SimpleTimingPort::recvFunctional() 1260 // calls recvAtomic() and throws away the latency; we can save a 1261 // little here by just not calculating the latency. 1262 memory.recvFunctional(pkt); 1263 } 1264 1265 pkt->popLabel(); 1266} 1267 1268Tick 1269SimpleDRAM::MemoryPort::recvAtomic(PacketPtr pkt) 1270{ 1271 return memory.recvAtomic(pkt); 1272} 1273 1274bool 1275SimpleDRAM::MemoryPort::recvTimingReq(PacketPtr pkt) 1276{ 1277 // pass it to the memory controller 1278 return memory.recvTimingReq(pkt); 1279} 1280 1281SimpleDRAM* 1282SimpleDRAMParams::create() 1283{ 1284 return new SimpleDRAM(this); 1285} 1286