dram_ctrl.cc revision 13857
19243SN/A/* 212706Swendy.elsasser@arm.com * Copyright (c) 2010-2018 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 4310618SOmar.Naji@arm.com * Omar Naji 4411678Swendy.elsasser@arm.com * Wendy Elsasser 4512266Sradhika.jagtap@arm.com * Radhika Jagtap 469243SN/A */ 479243SN/A 4811793Sbrandon.potter@amd.com#include "mem/dram_ctrl.hh" 4911793Sbrandon.potter@amd.com 5010146Sandreas.hansson@arm.com#include "base/bitfield.hh" 519356SN/A#include "base/trace.hh" 5210146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 5310247Sandreas.hansson@arm.com#include "debug/DRAMPower.hh" 5410208Sandreas.hansson@arm.com#include "debug/DRAMState.hh" 559352SN/A#include "debug/Drain.hh" 5612969SMatteo.Andreozzi@arm.com#include "debug/QOS.hh" 579814SN/A#include "sim/system.hh" 589243SN/A 599243SN/Ausing namespace std; 6010432SOmar.Naji@arm.comusing namespace Data; 619243SN/A 6210146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 6312969SMatteo.Andreozzi@arm.com QoS::MemCtrl(p), 6410619Sandreas.hansson@arm.com port(name() + ".port", *this), isTimingMode(false), 659243SN/A retryRdReq(false), retryWrReq(false), 6612084Sspwilson2@wisc.edu nextReqEvent([this]{ processNextReqEvent(); }, name()), 6712084Sspwilson2@wisc.edu respondEvent([this]{ processRespondEvent(); }, name()), 6810489SOmar.Naji@arm.com deviceSize(p->device_size), 699831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 709831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 719831SN/A devicesPerRank(p->devices_per_rank), 729831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 739831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 7410140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 7510646Sandreas.hansson@arm.com columnsPerStripe(range.interleaved() ? range.granularity() / burstSize : 1), 769243SN/A ranksPerChannel(p->ranks_per_channel), 7710394Swendy.elsasser@arm.com bankGroupsPerRank(p->bank_groups_per_rank), 7810394Swendy.elsasser@arm.com bankGroupArch(p->bank_groups_per_rank > 0), 799566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 809243SN/A readBufferSize(p->read_buffer_size), 819243SN/A writeBufferSize(p->write_buffer_size), 8210140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 8310140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 8410147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 8510147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 8612706Swendy.elsasser@arm.com tCK(p->tCK), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST), 8712706Swendy.elsasser@arm.com tCCD_L_WR(p->tCCD_L_WR), 8810394Swendy.elsasser@arm.com tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), 8910394Swendy.elsasser@arm.com tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 9011673SOmar.Naji@arm.com tRRD_L(p->tRRD_L), tXAW(p->tXAW), tXP(p->tXP), tXS(p->tXS), 9112706Swendy.elsasser@arm.com activationLimit(p->activation_limit), rankToRankDly(tCS + tBURST), 9212706Swendy.elsasser@arm.com wrToRdDly(tCL + tBURST + p->tWTR), rdToWrDly(tRTW + tBURST), 939243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 949243SN/A pageMgmt(p->page_policy), 9510141SN/A maxAccessesPerRow(p->max_accesses_per_row), 969726SN/A frontendLatency(p->static_frontend_latency), 979726SN/A backendLatency(p->static_backend_latency), 9812706Swendy.elsasser@arm.com nextBurstAt(0), prevArrival(0), 9912266Sradhika.jagtap@arm.com nextReqTime(0), activeRank(0), timeStampOffset(0), 10012266Sradhika.jagtap@arm.com lastStatsResetTick(0) 1019243SN/A{ 10210620Sandreas.hansson@arm.com // sanity check the ranks since we rely on bit slicing for the 10310620Sandreas.hansson@arm.com // address decoding 10410620Sandreas.hansson@arm.com fatal_if(!isPowerOf2(ranksPerChannel), "DRAM rank count of %d is not " 10510620Sandreas.hansson@arm.com "allowed, must be a power of two\n", ranksPerChannel); 10610620Sandreas.hansson@arm.com 10710889Sandreas.hansson@arm.com fatal_if(!isPowerOf2(burstSize), "DRAM burst size %d is not allowed, " 10810889Sandreas.hansson@arm.com "must be a power of two\n", burstSize); 10912969SMatteo.Andreozzi@arm.com readQueue.resize(p->qos_priorities); 11012969SMatteo.Andreozzi@arm.com writeQueue.resize(p->qos_priorities); 11112969SMatteo.Andreozzi@arm.com 11210889Sandreas.hansson@arm.com 11310618SOmar.Naji@arm.com for (int i = 0; i < ranksPerChannel; i++) { 11412081Sspwilson2@wisc.edu Rank* rank = new Rank(*this, p, i); 11510618SOmar.Naji@arm.com ranks.push_back(rank); 11610246Sandreas.hansson@arm.com } 11710246Sandreas.hansson@arm.com 11810140SN/A // perform a basic check of the write thresholds 11910140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 12010140SN/A fatal("Write buffer low threshold %d must be smaller than the " 12110140SN/A "high threshold %d\n", p->write_low_thresh_perc, 12210140SN/A p->write_high_thresh_perc); 1239243SN/A 1249243SN/A // determine the rows per bank by looking at the total capacity 1259567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1269243SN/A 12710489SOmar.Naji@arm.com // determine the dram actual capacity from the DRAM config in Mbytes 12810489SOmar.Naji@arm.com uint64_t deviceCapacity = deviceSize / (1024 * 1024) * devicesPerRank * 12910489SOmar.Naji@arm.com ranksPerChannel; 13010489SOmar.Naji@arm.com 13110489SOmar.Naji@arm.com // if actual DRAM size does not match memory capacity in system warn! 13210489SOmar.Naji@arm.com if (deviceCapacity != capacity / (1024 * 1024)) 13310489SOmar.Naji@arm.com warn("DRAM device capacity (%d Mbytes) does not match the " 13410489SOmar.Naji@arm.com "address range assigned (%d Mbytes)\n", deviceCapacity, 13510489SOmar.Naji@arm.com capacity / (1024 * 1024)); 13610489SOmar.Naji@arm.com 1379243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1389243SN/A AbstractMemory::size()); 1399831SN/A 1409831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1419831SN/A rowBufferSize, columnsPerRowBuffer); 1429831SN/A 1439831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1449243SN/A 14510207Sandreas.hansson@arm.com // some basic sanity checks 14610207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 14710207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 14810207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 14910207Sandreas.hansson@arm.com } 15010394Swendy.elsasser@arm.com 15110394Swendy.elsasser@arm.com // basic bank group architecture checks -> 15210394Swendy.elsasser@arm.com if (bankGroupArch) { 15310394Swendy.elsasser@arm.com // must have at least one bank per bank group 15410394Swendy.elsasser@arm.com if (bankGroupsPerRank > banksPerRank) { 15510394Swendy.elsasser@arm.com fatal("banks per rank (%d) must be equal to or larger than " 15610394Swendy.elsasser@arm.com "banks groups per rank (%d)\n", 15710394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 15810394Swendy.elsasser@arm.com } 15910394Swendy.elsasser@arm.com // must have same number of banks in each bank group 16010394Swendy.elsasser@arm.com if ((banksPerRank % bankGroupsPerRank) != 0) { 16110394Swendy.elsasser@arm.com fatal("Banks per rank (%d) must be evenly divisible by bank groups " 16210394Swendy.elsasser@arm.com "per rank (%d) for equal banks per bank group\n", 16310394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 16410394Swendy.elsasser@arm.com } 16510394Swendy.elsasser@arm.com // tCCD_L should be greater than minimal, back-to-back burst delay 16610394Swendy.elsasser@arm.com if (tCCD_L <= tBURST) { 16710394Swendy.elsasser@arm.com fatal("tCCD_L (%d) should be larger than tBURST (%d) when " 16810394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 16910394Swendy.elsasser@arm.com tCCD_L, tBURST, bankGroupsPerRank); 17010394Swendy.elsasser@arm.com } 17112706Swendy.elsasser@arm.com // tCCD_L_WR should be greater than minimal, back-to-back burst delay 17212706Swendy.elsasser@arm.com if (tCCD_L_WR <= tBURST) { 17312706Swendy.elsasser@arm.com fatal("tCCD_L_WR (%d) should be larger than tBURST (%d) when " 17412706Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 17512706Swendy.elsasser@arm.com tCCD_L_WR, tBURST, bankGroupsPerRank); 17612706Swendy.elsasser@arm.com } 17710394Swendy.elsasser@arm.com // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay 17810561SOmar.Naji@arm.com // some datasheets might specify it equal to tRRD 17910561SOmar.Naji@arm.com if (tRRD_L < tRRD) { 18010394Swendy.elsasser@arm.com fatal("tRRD_L (%d) should be larger than tRRD (%d) when " 18110394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 18210394Swendy.elsasser@arm.com tRRD_L, tRRD, bankGroupsPerRank); 18310394Swendy.elsasser@arm.com } 18410394Swendy.elsasser@arm.com } 18510394Swendy.elsasser@arm.com 1869243SN/A} 1879243SN/A 1889243SN/Avoid 18910146Sandreas.hansson@arm.comDRAMCtrl::init() 19010140SN/A{ 19112969SMatteo.Andreozzi@arm.com MemCtrl::init(); 19210466Sandreas.hansson@arm.com 19310466Sandreas.hansson@arm.com if (!port.isConnected()) { 19410146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 19510140SN/A } else { 19610140SN/A port.sendRangeChange(); 19710140SN/A } 19810646Sandreas.hansson@arm.com 19910646Sandreas.hansson@arm.com // a bit of sanity checks on the interleaving, save it for here to 20010646Sandreas.hansson@arm.com // ensure that the system pointer is initialised 20110646Sandreas.hansson@arm.com if (range.interleaved()) { 20210646Sandreas.hansson@arm.com if (channels != range.stripes()) 20310646Sandreas.hansson@arm.com fatal("%s has %d interleaved address stripes but %d channel(s)\n", 20410646Sandreas.hansson@arm.com name(), range.stripes(), channels); 20510646Sandreas.hansson@arm.com 20610646Sandreas.hansson@arm.com if (addrMapping == Enums::RoRaBaChCo) { 20710646Sandreas.hansson@arm.com if (rowBufferSize != range.granularity()) { 20810646Sandreas.hansson@arm.com fatal("Channel interleaving of %s doesn't match RoRaBaChCo " 20910646Sandreas.hansson@arm.com "address map\n", name()); 21010646Sandreas.hansson@arm.com } 21110646Sandreas.hansson@arm.com } else if (addrMapping == Enums::RoRaBaCoCh || 21210646Sandreas.hansson@arm.com addrMapping == Enums::RoCoRaBaCh) { 21310646Sandreas.hansson@arm.com // for the interleavings with channel bits in the bottom, 21410646Sandreas.hansson@arm.com // if the system uses a channel striping granularity that 21510646Sandreas.hansson@arm.com // is larger than the DRAM burst size, then map the 21610646Sandreas.hansson@arm.com // sequential accesses within a stripe to a number of 21710646Sandreas.hansson@arm.com // columns in the DRAM, effectively placing some of the 21810646Sandreas.hansson@arm.com // lower-order column bits as the least-significant bits 21910646Sandreas.hansson@arm.com // of the address (above the ones denoting the burst size) 22010646Sandreas.hansson@arm.com assert(columnsPerStripe >= 1); 22110646Sandreas.hansson@arm.com 22210646Sandreas.hansson@arm.com // channel striping has to be done at a granularity that 22310646Sandreas.hansson@arm.com // is equal or larger to a cache line 22410646Sandreas.hansson@arm.com if (system()->cacheLineSize() > range.granularity()) { 22510646Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at least as large " 22610646Sandreas.hansson@arm.com "as the cache line size\n", name()); 22710646Sandreas.hansson@arm.com } 22810646Sandreas.hansson@arm.com 22910646Sandreas.hansson@arm.com // ...and equal or smaller than the row-buffer size 23010646Sandreas.hansson@arm.com if (rowBufferSize < range.granularity()) { 23110646Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at most as large " 23210646Sandreas.hansson@arm.com "as the row-buffer size\n", name()); 23310646Sandreas.hansson@arm.com } 23410646Sandreas.hansson@arm.com // this is essentially the check above, so just to be sure 23510646Sandreas.hansson@arm.com assert(columnsPerStripe <= columnsPerRowBuffer); 23610646Sandreas.hansson@arm.com } 23710646Sandreas.hansson@arm.com } 23810140SN/A} 23910140SN/A 24010140SN/Avoid 24110146Sandreas.hansson@arm.comDRAMCtrl::startup() 2429243SN/A{ 24310619Sandreas.hansson@arm.com // remember the memory system mode of operation 24410619Sandreas.hansson@arm.com isTimingMode = system()->isTimingMode(); 24510618SOmar.Naji@arm.com 24610619Sandreas.hansson@arm.com if (isTimingMode) { 24710619Sandreas.hansson@arm.com // timestamp offset should be in clock cycles for DRAMPower 24810619Sandreas.hansson@arm.com timeStampOffset = divCeil(curTick(), tCK); 24910619Sandreas.hansson@arm.com 25010619Sandreas.hansson@arm.com // update the start tick for the precharge accounting to the 25110619Sandreas.hansson@arm.com // current tick 25210619Sandreas.hansson@arm.com for (auto r : ranks) { 25310619Sandreas.hansson@arm.com r->startup(curTick() + tREFI - tRP); 25410619Sandreas.hansson@arm.com } 25510619Sandreas.hansson@arm.com 25610619Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 25710619Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 25810619Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 25910619Sandreas.hansson@arm.com // start of simulation 26012706Swendy.elsasser@arm.com nextBurstAt = curTick() + tRP + tRCD; 26110618SOmar.Naji@arm.com } 2629243SN/A} 2639243SN/A 2649243SN/ATick 26510146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 2669243SN/A{ 2679243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 2689243SN/A 26911334Sandreas.hansson@arm.com panic_if(pkt->cacheResponding(), "Should not see packets where cache " 27011334Sandreas.hansson@arm.com "is responding"); 27111334Sandreas.hansson@arm.com 2729243SN/A // do the actual memory access and turn the packet into a response 2739243SN/A access(pkt); 2749243SN/A 2759243SN/A Tick latency = 0; 27611334Sandreas.hansson@arm.com if (pkt->hasData()) { 2779243SN/A // this value is not supposed to be accurate, just enough to 2789243SN/A // keep things going, mimic a closed page 2799243SN/A latency = tRP + tRCD + tCL; 2809243SN/A } 2819243SN/A return latency; 2829243SN/A} 2839243SN/A 2849243SN/Abool 28510146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 2869243SN/A{ 2879831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 28812969SMatteo.Andreozzi@arm.com readBufferSize, totalReadQueueSize + respQueue.size(), 2899831SN/A neededEntries); 2909243SN/A 29112969SMatteo.Andreozzi@arm.com auto rdsize_new = totalReadQueueSize + respQueue.size() + neededEntries; 29212969SMatteo.Andreozzi@arm.com return rdsize_new > readBufferSize; 2939243SN/A} 2949243SN/A 2959243SN/Abool 29610146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 2979243SN/A{ 2989831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 29912969SMatteo.Andreozzi@arm.com writeBufferSize, totalWriteQueueSize, neededEntries); 30012969SMatteo.Andreozzi@arm.com 30112969SMatteo.Andreozzi@arm.com auto wrsize_new = (totalWriteQueueSize + neededEntries); 30212969SMatteo.Andreozzi@arm.com return wrsize_new > writeBufferSize; 3039243SN/A} 3049243SN/A 30510146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 30613857Sodanrc@yahoo.com.brDRAMCtrl::decodeAddr(const PacketPtr pkt, Addr dramPktAddr, unsigned size, 30713857Sodanrc@yahoo.com.br bool isRead) const 3089243SN/A{ 3099669SN/A // decode the address based on the address mapping scheme, with 31010136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 31110136SN/A // channel, respectively 3129243SN/A uint8_t rank; 3139967SN/A uint8_t bank; 31410245Sandreas.hansson@arm.com // use a 64-bit unsigned during the computations as the row is 31510245Sandreas.hansson@arm.com // always the top bits, and check before creating the DRAMPacket 31610245Sandreas.hansson@arm.com uint64_t row; 3179243SN/A 31810286Sandreas.hansson@arm.com // truncate the address to a DRAM burst, which makes it unique to 31910286Sandreas.hansson@arm.com // a specific column, row, bank, rank and channel 3209831SN/A Addr addr = dramPktAddr / burstSize; 3219243SN/A 3229491SN/A // we have removed the lowest order address bits that denote the 3239831SN/A // position within the column 32410136SN/A if (addrMapping == Enums::RoRaBaChCo) { 3259491SN/A // the lowest order bits denote the column to ensure that 3269491SN/A // sequential cache lines occupy the same row 3279831SN/A addr = addr / columnsPerRowBuffer; 3289243SN/A 3299669SN/A // take out the channel part of the address 3309566SN/A addr = addr / channels; 3319566SN/A 3329669SN/A // after the channel bits, get the bank bits to interleave 3339669SN/A // over the banks 3349669SN/A bank = addr % banksPerRank; 3359669SN/A addr = addr / banksPerRank; 3369669SN/A 3379669SN/A // after the bank, we get the rank bits which thus interleaves 3389669SN/A // over the ranks 3399669SN/A rank = addr % ranksPerChannel; 3409669SN/A addr = addr / ranksPerChannel; 3419669SN/A 34211189Sandreas.hansson@arm.com // lastly, get the row bits, no need to remove them from addr 3439669SN/A row = addr % rowsPerBank; 34410136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 34510286Sandreas.hansson@arm.com // take out the lower-order column bits 34610286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 34710286Sandreas.hansson@arm.com 3489669SN/A // take out the channel part of the address 3499669SN/A addr = addr / channels; 3509669SN/A 35110286Sandreas.hansson@arm.com // next, the higher-order column bites 35210286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3539669SN/A 3549669SN/A // after the column bits, we get the bank bits to interleave 3559491SN/A // over the banks 3569243SN/A bank = addr % banksPerRank; 3579243SN/A addr = addr / banksPerRank; 3589243SN/A 3599491SN/A // after the bank, we get the rank bits which thus interleaves 3609491SN/A // over the ranks 3619243SN/A rank = addr % ranksPerChannel; 3629243SN/A addr = addr / ranksPerChannel; 3639243SN/A 36411189Sandreas.hansson@arm.com // lastly, get the row bits, no need to remove them from addr 3659243SN/A row = addr % rowsPerBank; 36610136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 3679491SN/A // optimise for closed page mode and utilise maximum 3689491SN/A // parallelism of the DRAM (at the cost of power) 3699491SN/A 37010286Sandreas.hansson@arm.com // take out the lower-order column bits 37110286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 37210286Sandreas.hansson@arm.com 3739566SN/A // take out the channel part of the address, not that this has 3749566SN/A // to match with how accesses are interleaved between the 3759566SN/A // controllers in the address mapping 3769566SN/A addr = addr / channels; 3779566SN/A 3789491SN/A // start with the bank bits, as this provides the maximum 3799491SN/A // opportunity for parallelism between requests 3809243SN/A bank = addr % banksPerRank; 3819243SN/A addr = addr / banksPerRank; 3829243SN/A 3839491SN/A // next get the rank bits 3849243SN/A rank = addr % ranksPerChannel; 3859243SN/A addr = addr / ranksPerChannel; 3869243SN/A 38710286Sandreas.hansson@arm.com // next, the higher-order column bites 38810286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3899243SN/A 39011189Sandreas.hansson@arm.com // lastly, get the row bits, no need to remove them from addr 3919243SN/A row = addr % rowsPerBank; 3929243SN/A } else 3939243SN/A panic("Unknown address mapping policy chosen!"); 3949243SN/A 3959243SN/A assert(rank < ranksPerChannel); 3969243SN/A assert(bank < banksPerRank); 3979243SN/A assert(row < rowsPerBank); 39810245Sandreas.hansson@arm.com assert(row < Bank::NO_ROW); 3999243SN/A 4009243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 4019831SN/A dramPktAddr, rank, bank, row); 4029243SN/A 4039243SN/A // create the corresponding DRAM packet with the entry time and 4049567SN/A // ready time set to the current tick, the latter will be updated 4059567SN/A // later 4069967SN/A uint16_t bank_id = banksPerRank * rank + bank; 4079967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 40810618SOmar.Naji@arm.com size, ranks[rank]->banks[bank], *ranks[rank]); 4099243SN/A} 4109243SN/A 4119243SN/Avoid 41210146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 4139243SN/A{ 4149243SN/A // only add to the read queue here. whenever the request is 4159243SN/A // eventually done, set the readyTime, and call schedule() 4169243SN/A assert(!pkt->isWrite()); 4179243SN/A 4189831SN/A assert(pktCount != 0); 4199831SN/A 4209831SN/A // if the request size is larger than burst size, the pkt is split into 4219831SN/A // multiple DRAM packets 4229831SN/A // Note if the pkt starting address is not aligened to burst size, the 4239831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 4249831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 4259831SN/A // check read packets against packets in write queue. 4269243SN/A Addr addr = pkt->getAddr(); 4279831SN/A unsigned pktsServicedByWrQ = 0; 4289831SN/A BurstHelper* burst_helper = NULL; 4299831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4309831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4319831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4329831SN/A readPktSize[ceilLog2(size)]++; 4339831SN/A readBursts++; 43412969SMatteo.Andreozzi@arm.com masterReadAccesses[pkt->masterId()]++; 4359243SN/A 4369831SN/A // First check write buffer to see if the data is already at 4379831SN/A // the controller 4389831SN/A bool foundInWrQ = false; 43910889Sandreas.hansson@arm.com Addr burst_addr = burstAlign(addr); 44010889Sandreas.hansson@arm.com // if the burst address is not present then there is no need 44110889Sandreas.hansson@arm.com // looking any further 44210889Sandreas.hansson@arm.com if (isInWriteQueue.find(burst_addr) != isInWriteQueue.end()) { 44312969SMatteo.Andreozzi@arm.com for (const auto& vec : writeQueue) { 44412969SMatteo.Andreozzi@arm.com for (const auto& p : vec) { 44512969SMatteo.Andreozzi@arm.com // check if the read is subsumed in the write queue 44612969SMatteo.Andreozzi@arm.com // packet we are looking at 44712969SMatteo.Andreozzi@arm.com if (p->addr <= addr && 44812969SMatteo.Andreozzi@arm.com ((addr + size) <= (p->addr + p->size))) { 44912969SMatteo.Andreozzi@arm.com 45012969SMatteo.Andreozzi@arm.com foundInWrQ = true; 45112969SMatteo.Andreozzi@arm.com servicedByWrQ++; 45212969SMatteo.Andreozzi@arm.com pktsServicedByWrQ++; 45312969SMatteo.Andreozzi@arm.com DPRINTF(DRAM, 45412969SMatteo.Andreozzi@arm.com "Read to addr %lld with size %d serviced by " 45512969SMatteo.Andreozzi@arm.com "write queue\n", 45612969SMatteo.Andreozzi@arm.com addr, size); 45712969SMatteo.Andreozzi@arm.com bytesReadWrQ += burstSize; 45812969SMatteo.Andreozzi@arm.com break; 45912969SMatteo.Andreozzi@arm.com } 46010889Sandreas.hansson@arm.com } 4619831SN/A } 4629243SN/A } 4639831SN/A 4649831SN/A // If not found in the write q, make a DRAM packet and 4659831SN/A // push it onto the read queue 4669831SN/A if (!foundInWrQ) { 4679831SN/A 4689831SN/A // Make the burst helper for split packets 4699831SN/A if (pktCount > 1 && burst_helper == NULL) { 4709831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 4719831SN/A "dram requests\n", pkt->getAddr(), pktCount); 4729831SN/A burst_helper = new BurstHelper(pktCount); 4739831SN/A } 4749831SN/A 4759966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 4769831SN/A dram_pkt->burstHelper = burst_helper; 4779831SN/A 4789831SN/A assert(!readQueueFull(1)); 47912969SMatteo.Andreozzi@arm.com rdQLenPdf[totalReadQueueSize + respQueue.size()]++; 4809831SN/A 4819831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 4829831SN/A 48312969SMatteo.Andreozzi@arm.com readQueue[dram_pkt->qosValue()].push_back(dram_pkt); 48412969SMatteo.Andreozzi@arm.com 48511678Swendy.elsasser@arm.com ++dram_pkt->rankRef.readEntries; 48611678Swendy.elsasser@arm.com 48712969SMatteo.Andreozzi@arm.com // log packet 48812969SMatteo.Andreozzi@arm.com logRequest(MemCtrl::READ, pkt->masterId(), pkt->qosValue(), 48912969SMatteo.Andreozzi@arm.com dram_pkt->addr, 1); 49012969SMatteo.Andreozzi@arm.com 4919831SN/A // Update stats 49212969SMatteo.Andreozzi@arm.com avgRdQLen = totalReadQueueSize + respQueue.size(); 4939831SN/A } 4949831SN/A 4959831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 4969831SN/A addr = (addr | (burstSize - 1)) + 1; 4979243SN/A } 4989243SN/A 4999831SN/A // If all packets are serviced by write queue, we send the repsonse back 5009831SN/A if (pktsServicedByWrQ == pktCount) { 5019831SN/A accessAndRespond(pkt, frontendLatency); 5029831SN/A return; 5039831SN/A } 5049243SN/A 5059831SN/A // Update how many split packets are serviced by write queue 5069831SN/A if (burst_helper != NULL) 5079831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 5089243SN/A 50910206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 51010206Sandreas.hansson@arm.com // queue, do so now 51110206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 5129567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 5139567SN/A schedule(nextReqEvent, curTick()); 5149243SN/A } 5159243SN/A} 5169243SN/A 5179243SN/Avoid 51810146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 5199243SN/A{ 5209243SN/A // only add to the write queue here. whenever the request is 5219243SN/A // eventually done, set the readyTime, and call schedule() 5229243SN/A assert(pkt->isWrite()); 5239243SN/A 5249831SN/A // if the request size is larger than burst size, the pkt is split into 5259831SN/A // multiple DRAM packets 5269831SN/A Addr addr = pkt->getAddr(); 5279831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 5289831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 5299831SN/A pkt->getAddr() + pkt->getSize()) - addr; 5309831SN/A writePktSize[ceilLog2(size)]++; 5319831SN/A writeBursts++; 53212969SMatteo.Andreozzi@arm.com masterWriteAccesses[pkt->masterId()]++; 5339243SN/A 5349832SN/A // see if we can merge with an existing item in the write 53510889Sandreas.hansson@arm.com // queue and keep track of whether we have merged or not 53610889Sandreas.hansson@arm.com bool merged = isInWriteQueue.find(burstAlign(addr)) != 53710889Sandreas.hansson@arm.com isInWriteQueue.end(); 5389243SN/A 5399832SN/A // if the item was not merged we need to create a new write 5409832SN/A // and enqueue it 5419832SN/A if (!merged) { 5429966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 5439243SN/A 54412969SMatteo.Andreozzi@arm.com assert(totalWriteQueueSize < writeBufferSize); 54512969SMatteo.Andreozzi@arm.com wrQLenPdf[totalWriteQueueSize]++; 5469243SN/A 5479832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 5489831SN/A 54912969SMatteo.Andreozzi@arm.com writeQueue[dram_pkt->qosValue()].push_back(dram_pkt); 55010889Sandreas.hansson@arm.com isInWriteQueue.insert(burstAlign(addr)); 55112969SMatteo.Andreozzi@arm.com 55212969SMatteo.Andreozzi@arm.com // log packet 55312969SMatteo.Andreozzi@arm.com logRequest(MemCtrl::WRITE, pkt->masterId(), pkt->qosValue(), 55412969SMatteo.Andreozzi@arm.com dram_pkt->addr, 1); 55512969SMatteo.Andreozzi@arm.com 55612969SMatteo.Andreozzi@arm.com assert(totalWriteQueueSize == isInWriteQueue.size()); 5579831SN/A 5589832SN/A // Update stats 55912969SMatteo.Andreozzi@arm.com avgWrQLen = totalWriteQueueSize; 56011678Swendy.elsasser@arm.com 56111678Swendy.elsasser@arm.com // increment write entries of the rank 56211678Swendy.elsasser@arm.com ++dram_pkt->rankRef.writeEntries; 5639977SN/A } else { 56410889Sandreas.hansson@arm.com DPRINTF(DRAM, "Merging write burst with existing queue entry\n"); 56510889Sandreas.hansson@arm.com 5669977SN/A // keep track of the fact that this burst effectively 5679977SN/A // disappeared as it was merged with an existing one 5689977SN/A mergedWrBursts++; 5699832SN/A } 5709832SN/A 5719831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 5729831SN/A addr = (addr | (burstSize - 1)) + 1; 5739831SN/A } 5749243SN/A 5759243SN/A // we do not wait for the writes to be send to the actual memory, 5769243SN/A // but instead take responsibility for the consistency here and 5779243SN/A // snoop the write queue for any upcoming reads 5789831SN/A // @todo, if a pkt size is larger than burst size, we might need a 5799831SN/A // different front end latency 5809726SN/A accessAndRespond(pkt, frontendLatency); 5819243SN/A 58210206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 58310206Sandreas.hansson@arm.com // queue, do so now 58410206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 58510206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 58610206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 5879243SN/A } 5889243SN/A} 5899243SN/A 5909243SN/Avoid 59112969SMatteo.Andreozzi@arm.comDRAMCtrl::printQs() const 59212969SMatteo.Andreozzi@arm.com{ 59312969SMatteo.Andreozzi@arm.com#if TRACING_ON 5949243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 59512969SMatteo.Andreozzi@arm.com for (const auto& queue : readQueue) { 59612969SMatteo.Andreozzi@arm.com for (const auto& packet : queue) { 59712969SMatteo.Andreozzi@arm.com DPRINTF(DRAM, "Read %lu\n", packet->addr); 59812969SMatteo.Andreozzi@arm.com } 5999243SN/A } 60012969SMatteo.Andreozzi@arm.com 6019243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 60212969SMatteo.Andreozzi@arm.com for (const auto& packet : respQueue) { 60312969SMatteo.Andreozzi@arm.com DPRINTF(DRAM, "Response %lu\n", packet->addr); 6049243SN/A } 60512969SMatteo.Andreozzi@arm.com 6069243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 60712969SMatteo.Andreozzi@arm.com for (const auto& queue : writeQueue) { 60812969SMatteo.Andreozzi@arm.com for (const auto& packet : queue) { 60912969SMatteo.Andreozzi@arm.com DPRINTF(DRAM, "Write %lu\n", packet->addr); 61012969SMatteo.Andreozzi@arm.com } 6119243SN/A } 61212969SMatteo.Andreozzi@arm.com#endif // TRACING_ON 6139243SN/A} 6149243SN/A 6159243SN/Abool 61610146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 6179243SN/A{ 6189243SN/A // This is where we enter from the outside world 6199567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 6209831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 6219243SN/A 62211334Sandreas.hansson@arm.com panic_if(pkt->cacheResponding(), "Should not see packets where cache " 62311334Sandreas.hansson@arm.com "is responding"); 62411334Sandreas.hansson@arm.com 62511334Sandreas.hansson@arm.com panic_if(!(pkt->isRead() || pkt->isWrite()), 62611334Sandreas.hansson@arm.com "Should only see read and writes at memory controller\n"); 6279243SN/A 6289243SN/A // Calc avg gap between requests 6299243SN/A if (prevArrival != 0) { 6309243SN/A totGap += curTick() - prevArrival; 6319243SN/A } 6329243SN/A prevArrival = curTick(); 6339243SN/A 6349831SN/A 6359831SN/A // Find out how many dram packets a pkt translates to 6369831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 6379831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 6389831SN/A // multiple dram packets 6399243SN/A unsigned size = pkt->getSize(); 6409831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 6419831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 6429243SN/A 64312969SMatteo.Andreozzi@arm.com // run the QoS scheduler and assign a QoS priority value to the packet 64412969SMatteo.Andreozzi@arm.com qosSchedule( { &readQueue, &writeQueue }, burstSize, pkt); 64512969SMatteo.Andreozzi@arm.com 6469243SN/A // check local buffers and do not accept if full 64713834Sjason@lowepower.com if (pkt->isWrite()) { 64813834Sjason@lowepower.com assert(size != 0); 64913834Sjason@lowepower.com if (writeQueueFull(dram_pkt_count)) { 65013834Sjason@lowepower.com DPRINTF(DRAM, "Write queue full, not accepting\n"); 65113834Sjason@lowepower.com // remember that we have to retry this port 65213834Sjason@lowepower.com retryWrReq = true; 65313834Sjason@lowepower.com numWrRetry++; 65413834Sjason@lowepower.com return false; 65513834Sjason@lowepower.com } else { 65613834Sjason@lowepower.com addToWriteQueue(pkt, dram_pkt_count); 65713834Sjason@lowepower.com writeReqs++; 65813834Sjason@lowepower.com bytesWrittenSys += size; 65913834Sjason@lowepower.com } 66013834Sjason@lowepower.com } else { 66113834Sjason@lowepower.com assert(pkt->isRead()); 6629567SN/A assert(size != 0); 6639831SN/A if (readQueueFull(dram_pkt_count)) { 6649567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 6659243SN/A // remember that we have to retry this port 6669243SN/A retryRdReq = true; 6679243SN/A numRdRetry++; 6689243SN/A return false; 6699243SN/A } else { 6709831SN/A addToReadQueue(pkt, dram_pkt_count); 6719243SN/A readReqs++; 6729977SN/A bytesReadSys += size; 6739243SN/A } 6749243SN/A } 6759243SN/A 6769243SN/A return true; 6779243SN/A} 6789243SN/A 6799243SN/Avoid 68010146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 6819243SN/A{ 6829243SN/A DPRINTF(DRAM, 6839243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 6849243SN/A 6859831SN/A DRAMPacket* dram_pkt = respQueue.front(); 6869243SN/A 68711678Swendy.elsasser@arm.com // if a read has reached its ready-time, decrement the number of reads 68811678Swendy.elsasser@arm.com // At this point the packet has been handled and there is a possibility 68911678Swendy.elsasser@arm.com // to switch to low-power mode if no other packet is available 69011678Swendy.elsasser@arm.com --dram_pkt->rankRef.readEntries; 69111678Swendy.elsasser@arm.com DPRINTF(DRAM, "number of read entries for rank %d is %d\n", 69211678Swendy.elsasser@arm.com dram_pkt->rank, dram_pkt->rankRef.readEntries); 69311678Swendy.elsasser@arm.com 69411678Swendy.elsasser@arm.com // counter should at least indicate one outstanding request 69511678Swendy.elsasser@arm.com // for this read 69611678Swendy.elsasser@arm.com assert(dram_pkt->rankRef.outstandingEvents > 0); 69711678Swendy.elsasser@arm.com // read response received, decrement count 69811678Swendy.elsasser@arm.com --dram_pkt->rankRef.outstandingEvents; 69911678Swendy.elsasser@arm.com 70011846Swendy.elsasser@arm.com // at this moment should not have transitioned to a low-power state 70111846Swendy.elsasser@arm.com assert((dram_pkt->rankRef.pwrState != PWR_SREF) && 70211846Swendy.elsasser@arm.com (dram_pkt->rankRef.pwrState != PWR_PRE_PDN) && 70311846Swendy.elsasser@arm.com (dram_pkt->rankRef.pwrState != PWR_ACT_PDN)); 70411678Swendy.elsasser@arm.com 70511678Swendy.elsasser@arm.com // track if this is the last packet before idling 70611678Swendy.elsasser@arm.com // and that there are no outstanding commands to this rank 70712705Swendy.elsasser@arm.com if (dram_pkt->rankRef.isQueueEmpty() && 70812705Swendy.elsasser@arm.com dram_pkt->rankRef.outstandingEvents == 0) { 70911678Swendy.elsasser@arm.com // verify that there are no events scheduled 71011678Swendy.elsasser@arm.com assert(!dram_pkt->rankRef.activateEvent.scheduled()); 71111678Swendy.elsasser@arm.com assert(!dram_pkt->rankRef.prechargeEvent.scheduled()); 71211678Swendy.elsasser@arm.com 71311678Swendy.elsasser@arm.com // if coming from active state, schedule power event to 71411678Swendy.elsasser@arm.com // active power-down else go to precharge power-down 71511678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleep at tick %d; current power state is " 71611678Swendy.elsasser@arm.com "%d\n", dram_pkt->rank, curTick(), dram_pkt->rankRef.pwrState); 71711678Swendy.elsasser@arm.com 71811678Swendy.elsasser@arm.com // default to ACT power-down unless already in IDLE state 71911678Swendy.elsasser@arm.com // could be in IDLE if PRE issued before data returned 72011678Swendy.elsasser@arm.com PowerState next_pwr_state = PWR_ACT_PDN; 72111678Swendy.elsasser@arm.com if (dram_pkt->rankRef.pwrState == PWR_IDLE) { 72211678Swendy.elsasser@arm.com next_pwr_state = PWR_PRE_PDN; 72311678Swendy.elsasser@arm.com } 72411678Swendy.elsasser@arm.com 72511678Swendy.elsasser@arm.com dram_pkt->rankRef.powerDownSleep(next_pwr_state, curTick()); 72611678Swendy.elsasser@arm.com } 72711678Swendy.elsasser@arm.com 7289831SN/A if (dram_pkt->burstHelper) { 7299831SN/A // it is a split packet 7309831SN/A dram_pkt->burstHelper->burstsServiced++; 7319831SN/A if (dram_pkt->burstHelper->burstsServiced == 73210143SN/A dram_pkt->burstHelper->burstCount) { 7339831SN/A // we have now serviced all children packets of a system packet 7349831SN/A // so we can now respond to the requester 7359831SN/A // @todo we probably want to have a different front end and back 7369831SN/A // end latency for split packets 7379831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7389831SN/A delete dram_pkt->burstHelper; 7399831SN/A dram_pkt->burstHelper = NULL; 7409831SN/A } 7419831SN/A } else { 7429831SN/A // it is not a split packet 7439831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7449831SN/A } 7459243SN/A 7469831SN/A delete respQueue.front(); 7479831SN/A respQueue.pop_front(); 7489243SN/A 7499831SN/A if (!respQueue.empty()) { 7509831SN/A assert(respQueue.front()->readyTime >= curTick()); 7519831SN/A assert(!respondEvent.scheduled()); 7529831SN/A schedule(respondEvent, respQueue.front()->readyTime); 7539831SN/A } else { 7549831SN/A // if there is nothing left in any queue, signal a drain 75510913Sandreas.sandberg@arm.com if (drainState() == DrainState::Draining && 75612969SMatteo.Andreozzi@arm.com !totalWriteQueueSize && !totalReadQueueSize && allRanksDrained()) { 75710913Sandreas.sandberg@arm.com 75810509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 75910913Sandreas.sandberg@arm.com signalDrainDone(); 7609831SN/A } 7619831SN/A } 7629567SN/A 7639831SN/A // We have made a location in the queue available at this point, 7649831SN/A // so if there is a read that was forced to wait, retry now 7659831SN/A if (retryRdReq) { 7669831SN/A retryRdReq = false; 76710713Sandreas.hansson@arm.com port.sendRetryReq(); 7689831SN/A } 7699243SN/A} 7709243SN/A 77112969SMatteo.Andreozzi@arm.comDRAMCtrl::DRAMPacketQueue::iterator 77212969SMatteo.Andreozzi@arm.comDRAMCtrl::chooseNext(DRAMPacketQueue& queue, Tick extra_col_delay) 7739243SN/A{ 77412969SMatteo.Andreozzi@arm.com // This method does the arbitration between requests. 77512969SMatteo.Andreozzi@arm.com 77612969SMatteo.Andreozzi@arm.com DRAMCtrl::DRAMPacketQueue::iterator ret = queue.end(); 77712969SMatteo.Andreozzi@arm.com 77812969SMatteo.Andreozzi@arm.com if (!queue.empty()) { 77912969SMatteo.Andreozzi@arm.com if (queue.size() == 1) { 78012969SMatteo.Andreozzi@arm.com // available rank corresponds to state refresh idle 78112969SMatteo.Andreozzi@arm.com DRAMPacket* dram_pkt = *(queue.begin()); 78212969SMatteo.Andreozzi@arm.com if (ranks[dram_pkt->rank]->inRefIdleState()) { 78312969SMatteo.Andreozzi@arm.com ret = queue.begin(); 78412969SMatteo.Andreozzi@arm.com DPRINTF(DRAM, "Single request, going to a free rank\n"); 78512969SMatteo.Andreozzi@arm.com } else { 78612969SMatteo.Andreozzi@arm.com DPRINTF(DRAM, "Single request, going to a busy rank\n"); 78712969SMatteo.Andreozzi@arm.com } 78812969SMatteo.Andreozzi@arm.com } else if (memSchedPolicy == Enums::fcfs) { 78912969SMatteo.Andreozzi@arm.com // check if there is a packet going to a free rank 79012969SMatteo.Andreozzi@arm.com for (auto i = queue.begin(); i != queue.end(); ++i) { 79112969SMatteo.Andreozzi@arm.com DRAMPacket* dram_pkt = *i; 79212969SMatteo.Andreozzi@arm.com if (ranks[dram_pkt->rank]->inRefIdleState()) { 79312969SMatteo.Andreozzi@arm.com ret = i; 79412969SMatteo.Andreozzi@arm.com break; 79512969SMatteo.Andreozzi@arm.com } 79612969SMatteo.Andreozzi@arm.com } 79712969SMatteo.Andreozzi@arm.com } else if (memSchedPolicy == Enums::frfcfs) { 79812969SMatteo.Andreozzi@arm.com ret = chooseNextFRFCFS(queue, extra_col_delay); 79910618SOmar.Naji@arm.com } else { 80012969SMatteo.Andreozzi@arm.com panic("No scheduling policy chosen\n"); 80110618SOmar.Naji@arm.com } 8029243SN/A } 80312969SMatteo.Andreozzi@arm.com return ret; 8049243SN/A} 8059243SN/A 80612969SMatteo.Andreozzi@arm.comDRAMCtrl::DRAMPacketQueue::iterator 80712969SMatteo.Andreozzi@arm.comDRAMCtrl::chooseNextFRFCFS(DRAMPacketQueue& queue, Tick extra_col_delay) 8089974SN/A{ 80910890Swendy.elsasser@arm.com // Only determine this if needed 81012706Swendy.elsasser@arm.com vector<uint32_t> earliest_banks(ranksPerChannel, 0); 81112706Swendy.elsasser@arm.com 81212706Swendy.elsasser@arm.com // Has minBankPrep been called to populate earliest_banks? 81312706Swendy.elsasser@arm.com bool filled_earliest_banks = false; 81412706Swendy.elsasser@arm.com // can the PRE/ACT sequence be done without impacting utlization? 81510890Swendy.elsasser@arm.com bool hidden_bank_prep = false; 8169974SN/A 81710890Swendy.elsasser@arm.com // search for seamless row hits first, if no seamless row hit is 81810890Swendy.elsasser@arm.com // found then determine if there are other packets that can be issued 81910890Swendy.elsasser@arm.com // without incurring additional bus delay due to bank timing 82010890Swendy.elsasser@arm.com // Will select closed rows first to enable more open row possibilies 82110890Swendy.elsasser@arm.com // in future selections 82210890Swendy.elsasser@arm.com bool found_hidden_bank = false; 82310890Swendy.elsasser@arm.com 82410890Swendy.elsasser@arm.com // remember if we found a row hit, not seamless, but bank prepped 82510890Swendy.elsasser@arm.com // and ready 82610890Swendy.elsasser@arm.com bool found_prepped_pkt = false; 82710890Swendy.elsasser@arm.com 82810890Swendy.elsasser@arm.com // if we have no row hit, prepped or not, and no seamless packet, 82910890Swendy.elsasser@arm.com // just go for the earliest possible 8309974SN/A bool found_earliest_pkt = false; 83110890Swendy.elsasser@arm.com 83210618SOmar.Naji@arm.com auto selected_pkt_it = queue.end(); 8339974SN/A 83410890Swendy.elsasser@arm.com // time we need to issue a column command to be seamless 83512706Swendy.elsasser@arm.com const Tick min_col_at = std::max(nextBurstAt + extra_col_delay, curTick()); 83610890Swendy.elsasser@arm.com 8379974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 8389974SN/A DRAMPacket* dram_pkt = *i; 8399974SN/A const Bank& bank = dram_pkt->bankRef; 84012969SMatteo.Andreozzi@arm.com const Tick col_allowed_at = dram_pkt->isRead() ? bank.rdAllowedAt : 84112969SMatteo.Andreozzi@arm.com bank.wrAllowedAt; 84212969SMatteo.Andreozzi@arm.com 84312969SMatteo.Andreozzi@arm.com DPRINTF(DRAM, "%s checking packet in bank %d\n", 84412969SMatteo.Andreozzi@arm.com __func__, dram_pkt->bankRef.bank); 84510890Swendy.elsasser@arm.com 84612266Sradhika.jagtap@arm.com // check if rank is not doing a refresh and thus is available, if not, 84712266Sradhika.jagtap@arm.com // jump to the next packet 84812266Sradhika.jagtap@arm.com if (dram_pkt->rankRef.inRefIdleState()) { 84912969SMatteo.Andreozzi@arm.com 85012969SMatteo.Andreozzi@arm.com DPRINTF(DRAM, 85112969SMatteo.Andreozzi@arm.com "%s bank %d - Rank %d available\n", __func__, 85212969SMatteo.Andreozzi@arm.com dram_pkt->bankRef.bank, dram_pkt->rankRef.rank); 85312969SMatteo.Andreozzi@arm.com 85410890Swendy.elsasser@arm.com // check if it is a row hit 85510618SOmar.Naji@arm.com if (bank.openRow == dram_pkt->row) { 85610890Swendy.elsasser@arm.com // no additional rank-to-rank or same bank-group 85710890Swendy.elsasser@arm.com // delays, or we switched read/write and might as well 85810890Swendy.elsasser@arm.com // go for the row hit 85912706Swendy.elsasser@arm.com if (col_allowed_at <= min_col_at) { 86010890Swendy.elsasser@arm.com // FCFS within the hits, giving priority to 86110890Swendy.elsasser@arm.com // commands that can issue seamlessly, without 86210890Swendy.elsasser@arm.com // additional delay, such as same rank accesses 86310890Swendy.elsasser@arm.com // and/or different bank-group accesses 86412969SMatteo.Andreozzi@arm.com DPRINTF(DRAM, "%s Seamless row buffer hit\n", __func__); 86510618SOmar.Naji@arm.com selected_pkt_it = i; 86610890Swendy.elsasser@arm.com // no need to look through the remaining queue entries 86710618SOmar.Naji@arm.com break; 86810890Swendy.elsasser@arm.com } else if (!found_hidden_bank && !found_prepped_pkt) { 86910890Swendy.elsasser@arm.com // if we did not find a packet to a closed row that can 87010890Swendy.elsasser@arm.com // issue the bank commands without incurring delay, and 87110890Swendy.elsasser@arm.com // did not yet find a packet to a prepped row, remember 87210890Swendy.elsasser@arm.com // the current one 87310618SOmar.Naji@arm.com selected_pkt_it = i; 87410890Swendy.elsasser@arm.com found_prepped_pkt = true; 87512969SMatteo.Andreozzi@arm.com DPRINTF(DRAM, "%s Prepped row buffer hit\n", __func__); 87610618SOmar.Naji@arm.com } 87710890Swendy.elsasser@arm.com } else if (!found_earliest_pkt) { 87810890Swendy.elsasser@arm.com // if we have not initialised the bank status, do it 87910890Swendy.elsasser@arm.com // now, and only once per scheduling decisions 88012706Swendy.elsasser@arm.com if (!filled_earliest_banks) { 88110890Swendy.elsasser@arm.com // determine entries with earliest bank delay 88212706Swendy.elsasser@arm.com std::tie(earliest_banks, hidden_bank_prep) = 88310890Swendy.elsasser@arm.com minBankPrep(queue, min_col_at); 88412706Swendy.elsasser@arm.com filled_earliest_banks = true; 88510890Swendy.elsasser@arm.com } 88610211Sandreas.hansson@arm.com 88710890Swendy.elsasser@arm.com // bank is amongst first available banks 88810890Swendy.elsasser@arm.com // minBankPrep will give priority to packets that can 88910890Swendy.elsasser@arm.com // issue seamlessly 89012706Swendy.elsasser@arm.com if (bits(earliest_banks[dram_pkt->rank], 89112706Swendy.elsasser@arm.com dram_pkt->bank, dram_pkt->bank)) { 89210618SOmar.Naji@arm.com found_earliest_pkt = true; 89310890Swendy.elsasser@arm.com found_hidden_bank = hidden_bank_prep; 89410890Swendy.elsasser@arm.com 89510890Swendy.elsasser@arm.com // give priority to packets that can issue 89610890Swendy.elsasser@arm.com // bank commands 'behind the scenes' 89710890Swendy.elsasser@arm.com // any additional delay if any will be due to 89810890Swendy.elsasser@arm.com // col-to-col command requirements 89910890Swendy.elsasser@arm.com if (hidden_bank_prep || !found_prepped_pkt) 90010890Swendy.elsasser@arm.com selected_pkt_it = i; 90110618SOmar.Naji@arm.com } 9029974SN/A } 90312969SMatteo.Andreozzi@arm.com } else { 90412969SMatteo.Andreozzi@arm.com DPRINTF(DRAM, "%s bank %d - Rank %d not available\n", __func__, 90512969SMatteo.Andreozzi@arm.com dram_pkt->bankRef.bank, dram_pkt->rankRef.rank); 9069974SN/A } 9079974SN/A } 9089974SN/A 90912969SMatteo.Andreozzi@arm.com if (selected_pkt_it == queue.end()) { 91012969SMatteo.Andreozzi@arm.com DPRINTF(DRAM, "%s no available ranks found\n", __func__); 91110618SOmar.Naji@arm.com } 91210890Swendy.elsasser@arm.com 91312969SMatteo.Andreozzi@arm.com return selected_pkt_it; 9149974SN/A} 9159974SN/A 9169974SN/Avoid 91710146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 9189243SN/A{ 9199243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 9209243SN/A 9219243SN/A bool needsResponse = pkt->needsResponse(); 9229243SN/A // do the actual memory access which also turns the packet into a 9239243SN/A // response 9249243SN/A access(pkt); 9259243SN/A 9269243SN/A // turn packet around to go back to requester if response expected 9279243SN/A if (needsResponse) { 9289243SN/A // access already turned the packet into a response 9299243SN/A assert(pkt->isResponse()); 93010721SMarco.Balboni@ARM.com // response_time consumes the static latency and is charged also 93110721SMarco.Balboni@ARM.com // with headerDelay that takes into account the delay provided by 93210721SMarco.Balboni@ARM.com // the xbar and also the payloadDelay that takes into account the 93310721SMarco.Balboni@ARM.com // number of data beats. 93410721SMarco.Balboni@ARM.com Tick response_time = curTick() + static_latency + pkt->headerDelay + 93510721SMarco.Balboni@ARM.com pkt->payloadDelay; 93610721SMarco.Balboni@ARM.com // Here we reset the timing of the packet before sending it out. 93710694SMarco.Balboni@ARM.com pkt->headerDelay = pkt->payloadDelay = 0; 9389549SN/A 9399726SN/A // queue the packet in the response queue to be sent out after 9409726SN/A // the static latency has passed 94113564Snikos.nikoleris@arm.com port.schedTimingResp(pkt, response_time); 9429243SN/A } else { 9439587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 9449587SN/A // is still having a pointer to it 94511190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 9469243SN/A } 9479243SN/A 9489243SN/A DPRINTF(DRAM, "Done\n"); 9499243SN/A 9509243SN/A return; 9519243SN/A} 9529243SN/A 9539243SN/Avoid 95410618SOmar.Naji@arm.comDRAMCtrl::activateBank(Rank& rank_ref, Bank& bank_ref, 95510618SOmar.Naji@arm.com Tick act_tick, uint32_t row) 9569488SN/A{ 95710618SOmar.Naji@arm.com assert(rank_ref.actTicks.size() == activationLimit); 9589488SN/A 9599488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 9609488SN/A 96110207Sandreas.hansson@arm.com // update the open row 96210618SOmar.Naji@arm.com assert(bank_ref.openRow == Bank::NO_ROW); 96310618SOmar.Naji@arm.com bank_ref.openRow = row; 96410207Sandreas.hansson@arm.com 96510207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 96610207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 96710207Sandreas.hansson@arm.com // precharge 96810618SOmar.Naji@arm.com bank_ref.bytesAccessed = 0; 96910618SOmar.Naji@arm.com bank_ref.rowAccesses = 0; 97010207Sandreas.hansson@arm.com 97110618SOmar.Naji@arm.com ++rank_ref.numBanksActive; 97210618SOmar.Naji@arm.com assert(rank_ref.numBanksActive <= banksPerRank); 97310207Sandreas.hansson@arm.com 97410247Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n", 97510618SOmar.Naji@arm.com bank_ref.bank, rank_ref.rank, act_tick, 97610618SOmar.Naji@arm.com ranks[rank_ref.rank]->numBanksActive); 97710247Sandreas.hansson@arm.com 97811675Swendy.elsasser@arm.com rank_ref.cmdList.push_back(Command(MemCommand::ACT, bank_ref.bank, 97911675Swendy.elsasser@arm.com act_tick)); 98010432SOmar.Naji@arm.com 98110432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK) - 98210618SOmar.Naji@arm.com timeStampOffset, bank_ref.bank, rank_ref.rank); 9839975SN/A 98410211Sandreas.hansson@arm.com // The next access has to respect tRAS for this bank 98510618SOmar.Naji@arm.com bank_ref.preAllowedAt = act_tick + tRAS; 98610211Sandreas.hansson@arm.com 98712706Swendy.elsasser@arm.com // Respect the row-to-column command delay for both read and write cmds 98812706Swendy.elsasser@arm.com bank_ref.rdAllowedAt = std::max(act_tick + tRCD, bank_ref.rdAllowedAt); 98912706Swendy.elsasser@arm.com bank_ref.wrAllowedAt = std::max(act_tick + tRCD, bank_ref.wrAllowedAt); 99010211Sandreas.hansson@arm.com 9919971SN/A // start by enforcing tRRD 99211321Ssteve.reinhardt@amd.com for (int i = 0; i < banksPerRank; i++) { 99310210Sandreas.hansson@arm.com // next activate to any bank in this rank must not happen 99410210Sandreas.hansson@arm.com // before tRRD 99510618SOmar.Naji@arm.com if (bankGroupArch && (bank_ref.bankgr == rank_ref.banks[i].bankgr)) { 99610394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 99710394Swendy.elsasser@arm.com // ACT commands within the same bank group. Use tRRD_L 99810394Swendy.elsasser@arm.com // in this case 99910618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD_L, 100010618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt); 100110394Swendy.elsasser@arm.com } else { 100210394Swendy.elsasser@arm.com // use shorter tRRD value when either 100310394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 100410394Swendy.elsasser@arm.com // 2) bank is in a different bank group 100510618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD, 100610618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt); 100710394Swendy.elsasser@arm.com } 10089971SN/A } 100910208Sandreas.hansson@arm.com 10109971SN/A // next, we deal with tXAW, if the activation limit is disabled 101110492SOmar.Naji@arm.com // then we directly schedule an activate power event 101210618SOmar.Naji@arm.com if (!rank_ref.actTicks.empty()) { 101310492SOmar.Naji@arm.com // sanity check 101410618SOmar.Naji@arm.com if (rank_ref.actTicks.back() && 101510618SOmar.Naji@arm.com (act_tick - rank_ref.actTicks.back()) < tXAW) { 101610492SOmar.Naji@arm.com panic("Got %d activates in window %d (%llu - %llu) which " 101710492SOmar.Naji@arm.com "is smaller than %llu\n", activationLimit, act_tick - 101810618SOmar.Naji@arm.com rank_ref.actTicks.back(), act_tick, 101910618SOmar.Naji@arm.com rank_ref.actTicks.back(), tXAW); 102010492SOmar.Naji@arm.com } 10219824SN/A 102210492SOmar.Naji@arm.com // shift the times used for the book keeping, the last element 102310492SOmar.Naji@arm.com // (highest index) is the oldest one and hence the lowest value 102410618SOmar.Naji@arm.com rank_ref.actTicks.pop_back(); 10259488SN/A 102610492SOmar.Naji@arm.com // record an new activation (in the future) 102710618SOmar.Naji@arm.com rank_ref.actTicks.push_front(act_tick); 10289488SN/A 102910492SOmar.Naji@arm.com // cannot activate more than X times in time window tXAW, push the 103010492SOmar.Naji@arm.com // next one (the X + 1'st activate) to be tXAW away from the 103110492SOmar.Naji@arm.com // oldest in our window of X 103210618SOmar.Naji@arm.com if (rank_ref.actTicks.back() && 103310618SOmar.Naji@arm.com (act_tick - rank_ref.actTicks.back()) < tXAW) { 103410492SOmar.Naji@arm.com DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate " 103510492SOmar.Naji@arm.com "no earlier than %llu\n", activationLimit, 103610618SOmar.Naji@arm.com rank_ref.actTicks.back() + tXAW); 103711321Ssteve.reinhardt@amd.com for (int j = 0; j < banksPerRank; j++) 10389488SN/A // next activate must not happen before end of window 103910618SOmar.Naji@arm.com rank_ref.banks[j].actAllowedAt = 104010618SOmar.Naji@arm.com std::max(rank_ref.actTicks.back() + tXAW, 104110618SOmar.Naji@arm.com rank_ref.banks[j].actAllowedAt); 104210492SOmar.Naji@arm.com } 10439488SN/A } 104410208Sandreas.hansson@arm.com 104510208Sandreas.hansson@arm.com // at the point when this activate takes place, make sure we 104610208Sandreas.hansson@arm.com // transition to the active power state 104710618SOmar.Naji@arm.com if (!rank_ref.activateEvent.scheduled()) 104810618SOmar.Naji@arm.com schedule(rank_ref.activateEvent, act_tick); 104910618SOmar.Naji@arm.com else if (rank_ref.activateEvent.when() > act_tick) 105010208Sandreas.hansson@arm.com // move it sooner in time 105110618SOmar.Naji@arm.com reschedule(rank_ref.activateEvent, act_tick); 105210208Sandreas.hansson@arm.com} 105310208Sandreas.hansson@arm.com 105410208Sandreas.hansson@arm.comvoid 105510618SOmar.Naji@arm.comDRAMCtrl::prechargeBank(Rank& rank_ref, Bank& bank, Tick pre_at, bool trace) 105610207Sandreas.hansson@arm.com{ 105710207Sandreas.hansson@arm.com // make sure the bank has an open row 105810207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 105910207Sandreas.hansson@arm.com 106010207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 106110207Sandreas.hansson@arm.com // the page 106210207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 106310207Sandreas.hansson@arm.com 106410207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 106510207Sandreas.hansson@arm.com 106610214Sandreas.hansson@arm.com // no precharge allowed before this one 106710214Sandreas.hansson@arm.com bank.preAllowedAt = pre_at; 106810214Sandreas.hansson@arm.com 106910211Sandreas.hansson@arm.com Tick pre_done_at = pre_at + tRP; 107010211Sandreas.hansson@arm.com 107110211Sandreas.hansson@arm.com bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at); 107210207Sandreas.hansson@arm.com 107310618SOmar.Naji@arm.com assert(rank_ref.numBanksActive != 0); 107410618SOmar.Naji@arm.com --rank_ref.numBanksActive; 107510207Sandreas.hansson@arm.com 107610247Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got " 107710618SOmar.Naji@arm.com "%d active\n", bank.bank, rank_ref.rank, pre_at, 107810618SOmar.Naji@arm.com rank_ref.numBanksActive); 107910247Sandreas.hansson@arm.com 108010432SOmar.Naji@arm.com if (trace) { 108110207Sandreas.hansson@arm.com 108211675Swendy.elsasser@arm.com rank_ref.cmdList.push_back(Command(MemCommand::PRE, bank.bank, 108311675Swendy.elsasser@arm.com pre_at)); 108410432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK) - 108510618SOmar.Naji@arm.com timeStampOffset, bank.bank, rank_ref.rank); 108610432SOmar.Naji@arm.com } 108710208Sandreas.hansson@arm.com // if we look at the current number of active banks we might be 108810208Sandreas.hansson@arm.com // tempted to think the DRAM is now idle, however this can be 108910208Sandreas.hansson@arm.com // undone by an activate that is scheduled to happen before we 109010208Sandreas.hansson@arm.com // would have reached the idle state, so schedule an event and 109110208Sandreas.hansson@arm.com // rather check once we actually make it to the point in time when 109210208Sandreas.hansson@arm.com // the (last) precharge takes place 109311678Swendy.elsasser@arm.com if (!rank_ref.prechargeEvent.scheduled()) { 109410618SOmar.Naji@arm.com schedule(rank_ref.prechargeEvent, pre_done_at); 109511678Swendy.elsasser@arm.com // New event, increment count 109611678Swendy.elsasser@arm.com ++rank_ref.outstandingEvents; 109711678Swendy.elsasser@arm.com } else if (rank_ref.prechargeEvent.when() < pre_done_at) { 109810618SOmar.Naji@arm.com reschedule(rank_ref.prechargeEvent, pre_done_at); 109911678Swendy.elsasser@arm.com } 110010207Sandreas.hansson@arm.com} 110110207Sandreas.hansson@arm.com 110210207Sandreas.hansson@arm.comvoid 110310146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 11049243SN/A{ 11059243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 11069243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 11079243SN/A 110810618SOmar.Naji@arm.com // get the rank 110910618SOmar.Naji@arm.com Rank& rank = dram_pkt->rankRef; 111010618SOmar.Naji@arm.com 111111678Swendy.elsasser@arm.com // are we in or transitioning to a low-power state and have not scheduled 111211678Swendy.elsasser@arm.com // a power-up event? 111311678Swendy.elsasser@arm.com // if so, wake up from power down to issue RD/WR burst 111411678Swendy.elsasser@arm.com if (rank.inLowPowerState) { 111511678Swendy.elsasser@arm.com assert(rank.pwrState != PWR_SREF); 111611678Swendy.elsasser@arm.com rank.scheduleWakeUpEvent(tXP); 111711678Swendy.elsasser@arm.com } 111811678Swendy.elsasser@arm.com 111910211Sandreas.hansson@arm.com // get the bank 11209967SN/A Bank& bank = dram_pkt->bankRef; 11219243SN/A 112210211Sandreas.hansson@arm.com // for the state we need to track if it is a row hit or not 112310211Sandreas.hansson@arm.com bool row_hit = true; 112410211Sandreas.hansson@arm.com 112510211Sandreas.hansson@arm.com // Determine the access latency and update the bank state 112610211Sandreas.hansson@arm.com if (bank.openRow == dram_pkt->row) { 112710211Sandreas.hansson@arm.com // nothing to do 112810209Sandreas.hansson@arm.com } else { 112910211Sandreas.hansson@arm.com row_hit = false; 113010211Sandreas.hansson@arm.com 113110209Sandreas.hansson@arm.com // If there is a page open, precharge it. 113210209Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 113310618SOmar.Naji@arm.com prechargeBank(rank, bank, std::max(bank.preAllowedAt, curTick())); 11349488SN/A } 11359973SN/A 113610211Sandreas.hansson@arm.com // next we need to account for the delay in activating the 113710211Sandreas.hansson@arm.com // page 113810211Sandreas.hansson@arm.com Tick act_tick = std::max(bank.actAllowedAt, curTick()); 11399973SN/A 114010210Sandreas.hansson@arm.com // Record the activation and deal with all the global timing 114110210Sandreas.hansson@arm.com // constraints caused be a new activation (tRRD and tXAW) 114210618SOmar.Naji@arm.com activateBank(rank, bank, act_tick, dram_pkt->row); 114310209Sandreas.hansson@arm.com } 114410209Sandreas.hansson@arm.com 114512706Swendy.elsasser@arm.com // respect any constraints on the command (e.g. tRCD or tCCD) 114612969SMatteo.Andreozzi@arm.com const Tick col_allowed_at = dram_pkt->isRead() ? 114712706Swendy.elsasser@arm.com bank.rdAllowedAt : bank.wrAllowedAt; 114812706Swendy.elsasser@arm.com 114910211Sandreas.hansson@arm.com // we need to wait until the bus is available before we can issue 115012706Swendy.elsasser@arm.com // the command; need minimum of tBURST between commands 115112706Swendy.elsasser@arm.com Tick cmd_at = std::max({col_allowed_at, nextBurstAt, curTick()}); 115210211Sandreas.hansson@arm.com 115310211Sandreas.hansson@arm.com // update the packet ready time 115410211Sandreas.hansson@arm.com dram_pkt->readyTime = cmd_at + tCL + tBURST; 115510211Sandreas.hansson@arm.com 115610394Swendy.elsasser@arm.com // update the time for the next read/write burst for each 115712706Swendy.elsasser@arm.com // bank (add a max with tCCD/tCCD_L/tCCD_L_WR here) 115812706Swendy.elsasser@arm.com Tick dly_to_rd_cmd; 115912706Swendy.elsasser@arm.com Tick dly_to_wr_cmd; 116011321Ssteve.reinhardt@amd.com for (int j = 0; j < ranksPerChannel; j++) { 116111321Ssteve.reinhardt@amd.com for (int i = 0; i < banksPerRank; i++) { 116210394Swendy.elsasser@arm.com // next burst to same bank group in this rank must not happen 116310394Swendy.elsasser@arm.com // before tCCD_L. Different bank group timing requirement is 116410394Swendy.elsasser@arm.com // tBURST; Add tCS for different ranks 116510394Swendy.elsasser@arm.com if (dram_pkt->rank == j) { 116610618SOmar.Naji@arm.com if (bankGroupArch && 116710618SOmar.Naji@arm.com (bank.bankgr == ranks[j]->banks[i].bankgr)) { 116810394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 116910394Swendy.elsasser@arm.com // RD/WR burst commands to the same bank group. 117012706Swendy.elsasser@arm.com // tCCD_L is default requirement for same BG timing 117112706Swendy.elsasser@arm.com // tCCD_L_WR is required for write-to-write 117212706Swendy.elsasser@arm.com // Need to also take bus turnaround delays into account 117312969SMatteo.Andreozzi@arm.com dly_to_rd_cmd = dram_pkt->isRead() ? 117412706Swendy.elsasser@arm.com tCCD_L : std::max(tCCD_L, wrToRdDly); 117512969SMatteo.Andreozzi@arm.com dly_to_wr_cmd = dram_pkt->isRead() ? 117612706Swendy.elsasser@arm.com std::max(tCCD_L, rdToWrDly) : tCCD_L_WR; 117710394Swendy.elsasser@arm.com } else { 117812706Swendy.elsasser@arm.com // tBURST is default requirement for diff BG timing 117912706Swendy.elsasser@arm.com // Need to also take bus turnaround delays into account 118012969SMatteo.Andreozzi@arm.com dly_to_rd_cmd = dram_pkt->isRead() ? tBURST : wrToRdDly; 118112969SMatteo.Andreozzi@arm.com dly_to_wr_cmd = dram_pkt->isRead() ? rdToWrDly : tBURST; 118210394Swendy.elsasser@arm.com } 118310394Swendy.elsasser@arm.com } else { 118412706Swendy.elsasser@arm.com // different rank is by default in a different bank group and 118512706Swendy.elsasser@arm.com // doesn't require longer tCCD or additional RTW, WTR delays 118612706Swendy.elsasser@arm.com // Need to account for rank-to-rank switching with tCS 118712706Swendy.elsasser@arm.com dly_to_wr_cmd = rankToRankDly; 118812706Swendy.elsasser@arm.com dly_to_rd_cmd = rankToRankDly; 118910394Swendy.elsasser@arm.com } 119012706Swendy.elsasser@arm.com ranks[j]->banks[i].rdAllowedAt = std::max(cmd_at + dly_to_rd_cmd, 119112706Swendy.elsasser@arm.com ranks[j]->banks[i].rdAllowedAt); 119212706Swendy.elsasser@arm.com ranks[j]->banks[i].wrAllowedAt = std::max(cmd_at + dly_to_wr_cmd, 119312706Swendy.elsasser@arm.com ranks[j]->banks[i].wrAllowedAt); 119410394Swendy.elsasser@arm.com } 119510394Swendy.elsasser@arm.com } 119610211Sandreas.hansson@arm.com 119710393Swendy.elsasser@arm.com // Save rank of current access 119810393Swendy.elsasser@arm.com activeRank = dram_pkt->rank; 119910393Swendy.elsasser@arm.com 120010212Sandreas.hansson@arm.com // If this is a write, we also need to respect the write recovery 120110212Sandreas.hansson@arm.com // time before a precharge, in the case of a read, respect the 120210212Sandreas.hansson@arm.com // read to precharge constraint 120310212Sandreas.hansson@arm.com bank.preAllowedAt = std::max(bank.preAllowedAt, 120412969SMatteo.Andreozzi@arm.com dram_pkt->isRead() ? cmd_at + tRTP : 120510212Sandreas.hansson@arm.com dram_pkt->readyTime + tWR); 120610210Sandreas.hansson@arm.com 120710209Sandreas.hansson@arm.com // increment the bytes accessed and the accesses per row 120810209Sandreas.hansson@arm.com bank.bytesAccessed += burstSize; 120910209Sandreas.hansson@arm.com ++bank.rowAccesses; 121010209Sandreas.hansson@arm.com 121110209Sandreas.hansson@arm.com // if we reached the max, then issue with an auto-precharge 121210209Sandreas.hansson@arm.com bool auto_precharge = pageMgmt == Enums::close || 121310209Sandreas.hansson@arm.com bank.rowAccesses == maxAccessesPerRow; 121410209Sandreas.hansson@arm.com 121510209Sandreas.hansson@arm.com // if we did not hit the limit, we might still want to 121610209Sandreas.hansson@arm.com // auto-precharge 121710209Sandreas.hansson@arm.com if (!auto_precharge && 121810209Sandreas.hansson@arm.com (pageMgmt == Enums::open_adaptive || 121910209Sandreas.hansson@arm.com pageMgmt == Enums::close_adaptive)) { 122010209Sandreas.hansson@arm.com // a twist on the open and close page policies: 122110209Sandreas.hansson@arm.com // 1) open_adaptive page policy does not blindly keep the 122210209Sandreas.hansson@arm.com // page open, but close it if there are no row hits, and there 122310209Sandreas.hansson@arm.com // are bank conflicts in the queue 122410209Sandreas.hansson@arm.com // 2) close_adaptive page policy does not blindly close the 122510209Sandreas.hansson@arm.com // page, but closes it only if there are no row hits in the queue. 122610209Sandreas.hansson@arm.com // In this case, only force an auto precharge when there 122710209Sandreas.hansson@arm.com // are no same page hits in the queue 122810209Sandreas.hansson@arm.com bool got_more_hits = false; 122910209Sandreas.hansson@arm.com bool got_bank_conflict = false; 123010209Sandreas.hansson@arm.com 123110209Sandreas.hansson@arm.com // either look at the read queue or write queue 123212969SMatteo.Andreozzi@arm.com const std::vector<DRAMPacketQueue>& queue = 123312969SMatteo.Andreozzi@arm.com dram_pkt->isRead() ? readQueue : writeQueue; 123412969SMatteo.Andreozzi@arm.com 123512969SMatteo.Andreozzi@arm.com for (uint8_t i = 0; i < numPriorities(); ++i) { 123612969SMatteo.Andreozzi@arm.com auto p = queue[i].begin(); 123712969SMatteo.Andreozzi@arm.com // keep on looking until we find a hit or reach the end of the queue 123812969SMatteo.Andreozzi@arm.com // 1) if a hit is found, then both open and close adaptive policies keep 123912969SMatteo.Andreozzi@arm.com // the page open 124012969SMatteo.Andreozzi@arm.com // 2) if no hit is found, got_bank_conflict is set to true if a bank 124112969SMatteo.Andreozzi@arm.com // conflict request is waiting in the queue 124212969SMatteo.Andreozzi@arm.com // 3) make sure we are not considering the packet that we are 124312969SMatteo.Andreozzi@arm.com // currently dealing with 124412969SMatteo.Andreozzi@arm.com while (!got_more_hits && p != queue[i].end()) { 124512969SMatteo.Andreozzi@arm.com if (dram_pkt != (*p)) { 124612969SMatteo.Andreozzi@arm.com bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 124712969SMatteo.Andreozzi@arm.com (dram_pkt->bank == (*p)->bank); 124812969SMatteo.Andreozzi@arm.com 124912969SMatteo.Andreozzi@arm.com bool same_row = dram_pkt->row == (*p)->row; 125012969SMatteo.Andreozzi@arm.com got_more_hits |= same_rank_bank && same_row; 125112969SMatteo.Andreozzi@arm.com got_bank_conflict |= same_rank_bank && !same_row; 125212969SMatteo.Andreozzi@arm.com } 125312969SMatteo.Andreozzi@arm.com ++p; 125412969SMatteo.Andreozzi@arm.com } 125512969SMatteo.Andreozzi@arm.com 125612969SMatteo.Andreozzi@arm.com if (got_more_hits) 125712969SMatteo.Andreozzi@arm.com break; 125810141SN/A } 125910141SN/A 126010209Sandreas.hansson@arm.com // auto pre-charge when either 126110209Sandreas.hansson@arm.com // 1) open_adaptive policy, we have not got any more hits, and 126210209Sandreas.hansson@arm.com // have a bank conflict 126310209Sandreas.hansson@arm.com // 2) close_adaptive policy and we have not got any more hits 126410209Sandreas.hansson@arm.com auto_precharge = !got_more_hits && 126510209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive); 126610209Sandreas.hansson@arm.com } 126710142SN/A 126810247Sandreas.hansson@arm.com // DRAMPower trace command to be written 126912969SMatteo.Andreozzi@arm.com std::string mem_cmd = dram_pkt->isRead() ? "RD" : "WR"; 127010247Sandreas.hansson@arm.com 127110432SOmar.Naji@arm.com // MemCommand required for DRAMPower library 127210432SOmar.Naji@arm.com MemCommand::cmds command = (mem_cmd == "RD") ? MemCommand::RD : 127310432SOmar.Naji@arm.com MemCommand::WR; 127410432SOmar.Naji@arm.com 127512706Swendy.elsasser@arm.com // Update bus state to reflect when previous command was issued 127612706Swendy.elsasser@arm.com nextBurstAt = cmd_at + tBURST; 127712706Swendy.elsasser@arm.com 127812706Swendy.elsasser@arm.com DPRINTF(DRAM, "Access to %lld, ready at %lld next burst at %lld.\n", 127912706Swendy.elsasser@arm.com dram_pkt->addr, dram_pkt->readyTime, nextBurstAt); 128011675Swendy.elsasser@arm.com 128111675Swendy.elsasser@arm.com dram_pkt->rankRef.cmdList.push_back(Command(command, dram_pkt->bank, 128211675Swendy.elsasser@arm.com cmd_at)); 128311675Swendy.elsasser@arm.com 128411675Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK) - 128511675Swendy.elsasser@arm.com timeStampOffset, mem_cmd, dram_pkt->bank, dram_pkt->rank); 128611675Swendy.elsasser@arm.com 128710209Sandreas.hansson@arm.com // if this access should use auto-precharge, then we are 128811675Swendy.elsasser@arm.com // closing the row after the read/write burst 128910209Sandreas.hansson@arm.com if (auto_precharge) { 129010432SOmar.Naji@arm.com // if auto-precharge push a PRE command at the correct tick to the 129110432SOmar.Naji@arm.com // list used by DRAMPower library to calculate power 129210618SOmar.Naji@arm.com prechargeBank(rank, bank, std::max(curTick(), bank.preAllowedAt)); 12939973SN/A 129410209Sandreas.hansson@arm.com DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 129510209Sandreas.hansson@arm.com } 12969963SN/A 129710206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 129810206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 129910206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 130010206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 130112706Swendy.elsasser@arm.com nextReqTime = nextBurstAt - (tRP + tRCD); 13029972SN/A 130310206Sandreas.hansson@arm.com // Update the stats and schedule the next request 130412969SMatteo.Andreozzi@arm.com if (dram_pkt->isRead()) { 130510147Sandreas.hansson@arm.com ++readsThisTime; 130610211Sandreas.hansson@arm.com if (row_hit) 13079977SN/A readRowHits++; 13089977SN/A bytesReadDRAM += burstSize; 13099977SN/A perBankRdBursts[dram_pkt->bankId]++; 131010206Sandreas.hansson@arm.com 131110206Sandreas.hansson@arm.com // Update latency stats 131210206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 131312969SMatteo.Andreozzi@arm.com masterReadTotalLat[dram_pkt->masterId()] += 131412969SMatteo.Andreozzi@arm.com dram_pkt->readyTime - dram_pkt->entryTime; 131512969SMatteo.Andreozzi@arm.com 131610206Sandreas.hansson@arm.com totBusLat += tBURST; 131710211Sandreas.hansson@arm.com totQLat += cmd_at - dram_pkt->entryTime; 131812969SMatteo.Andreozzi@arm.com masterReadBytes[dram_pkt->masterId()] += dram_pkt->size; 13199977SN/A } else { 132010147Sandreas.hansson@arm.com ++writesThisTime; 132110211Sandreas.hansson@arm.com if (row_hit) 13229977SN/A writeRowHits++; 13239977SN/A bytesWritten += burstSize; 13249977SN/A perBankWrBursts[dram_pkt->bankId]++; 132512969SMatteo.Andreozzi@arm.com masterWriteBytes[dram_pkt->masterId()] += dram_pkt->size; 132612969SMatteo.Andreozzi@arm.com masterWriteTotalLat[dram_pkt->masterId()] += 132712969SMatteo.Andreozzi@arm.com dram_pkt->readyTime - dram_pkt->entryTime; 13289243SN/A } 13299243SN/A} 13309243SN/A 13319243SN/Avoid 133210206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 13339243SN/A{ 133412969SMatteo.Andreozzi@arm.com // transition is handled by QoS algorithm if enabled 133512969SMatteo.Andreozzi@arm.com if (turnPolicy) { 133612969SMatteo.Andreozzi@arm.com // select bus state - only done if QoS algorithms are in use 133712969SMatteo.Andreozzi@arm.com busStateNext = selectNextBusState(); 133812969SMatteo.Andreozzi@arm.com } 133912969SMatteo.Andreozzi@arm.com 134012969SMatteo.Andreozzi@arm.com // detect bus state change 134112969SMatteo.Andreozzi@arm.com bool switched_cmd_type = (busState != busStateNext); 134212969SMatteo.Andreozzi@arm.com // record stats 134312969SMatteo.Andreozzi@arm.com recordTurnaroundStats(); 134412969SMatteo.Andreozzi@arm.com 134512969SMatteo.Andreozzi@arm.com DPRINTF(DRAM, "QoS Turnarounds selected state %s %s\n", 134612969SMatteo.Andreozzi@arm.com (busState==MemCtrl::READ)?"READ":"WRITE", 134712969SMatteo.Andreozzi@arm.com switched_cmd_type?"[turnaround triggered]":""); 134812969SMatteo.Andreozzi@arm.com 134912969SMatteo.Andreozzi@arm.com if (switched_cmd_type) { 135012969SMatteo.Andreozzi@arm.com if (busState == READ) { 135112969SMatteo.Andreozzi@arm.com DPRINTF(DRAM, 135212969SMatteo.Andreozzi@arm.com "Switching to writes after %d reads with %d reads " 135312969SMatteo.Andreozzi@arm.com "waiting\n", readsThisTime, totalReadQueueSize); 135412969SMatteo.Andreozzi@arm.com rdPerTurnAround.sample(readsThisTime); 135512969SMatteo.Andreozzi@arm.com readsThisTime = 0; 135612969SMatteo.Andreozzi@arm.com } else { 135712969SMatteo.Andreozzi@arm.com DPRINTF(DRAM, 135812969SMatteo.Andreozzi@arm.com "Switching to reads after %d writes with %d writes " 135912969SMatteo.Andreozzi@arm.com "waiting\n", writesThisTime, totalWriteQueueSize); 136012969SMatteo.Andreozzi@arm.com wrPerTurnAround.sample(writesThisTime); 136112969SMatteo.Andreozzi@arm.com writesThisTime = 0; 136212969SMatteo.Andreozzi@arm.com } 136312969SMatteo.Andreozzi@arm.com } 136412969SMatteo.Andreozzi@arm.com 136512969SMatteo.Andreozzi@arm.com // updates current state 136612969SMatteo.Andreozzi@arm.com busState = busStateNext; 136712969SMatteo.Andreozzi@arm.com 136812969SMatteo.Andreozzi@arm.com // check ranks for refresh/wakeup - uses busStateNext, so done after turnaround 136912969SMatteo.Andreozzi@arm.com // decisions 137010618SOmar.Naji@arm.com int busyRanks = 0; 137110618SOmar.Naji@arm.com for (auto r : ranks) { 137212266Sradhika.jagtap@arm.com if (!r->inRefIdleState()) { 137311678Swendy.elsasser@arm.com if (r->pwrState != PWR_SREF) { 137411678Swendy.elsasser@arm.com // rank is busy refreshing 137511678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d is not available\n", r->rank); 137611678Swendy.elsasser@arm.com busyRanks++; 137711678Swendy.elsasser@arm.com 137811678Swendy.elsasser@arm.com // let the rank know that if it was waiting to drain, it 137911678Swendy.elsasser@arm.com // is now done and ready to proceed 138011678Swendy.elsasser@arm.com r->checkDrainDone(); 138111678Swendy.elsasser@arm.com } 138211678Swendy.elsasser@arm.com 138311678Swendy.elsasser@arm.com // check if we were in self-refresh and haven't started 138411678Swendy.elsasser@arm.com // to transition out 138511678Swendy.elsasser@arm.com if ((r->pwrState == PWR_SREF) && r->inLowPowerState) { 138611678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d is in self-refresh\n", r->rank); 138711678Swendy.elsasser@arm.com // if we have commands queued to this rank and we don't have 138811678Swendy.elsasser@arm.com // a minimum number of active commands enqueued, 138911678Swendy.elsasser@arm.com // exit self-refresh 139011678Swendy.elsasser@arm.com if (r->forceSelfRefreshExit()) { 139111678Swendy.elsasser@arm.com DPRINTF(DRAMState, "rank %d was in self refresh and" 139211678Swendy.elsasser@arm.com " should wake up\n", r->rank); 139311678Swendy.elsasser@arm.com //wake up from self-refresh 139411678Swendy.elsasser@arm.com r->scheduleWakeUpEvent(tXS); 139511678Swendy.elsasser@arm.com // things are brought back into action once a refresh is 139611678Swendy.elsasser@arm.com // performed after self-refresh 139711678Swendy.elsasser@arm.com // continue with selection for other ranks 139811678Swendy.elsasser@arm.com } 139911678Swendy.elsasser@arm.com } 140010618SOmar.Naji@arm.com } 140110618SOmar.Naji@arm.com } 140210618SOmar.Naji@arm.com 140310618SOmar.Naji@arm.com if (busyRanks == ranksPerChannel) { 140410618SOmar.Naji@arm.com // if all ranks are refreshing wait for them to finish 140510618SOmar.Naji@arm.com // and stall this state machine without taking any further 140610618SOmar.Naji@arm.com // action, and do not schedule a new nextReqEvent 140710618SOmar.Naji@arm.com return; 140810618SOmar.Naji@arm.com } 140910618SOmar.Naji@arm.com 141010206Sandreas.hansson@arm.com // when we get here it is either a read or a write 141110206Sandreas.hansson@arm.com if (busState == READ) { 141210206Sandreas.hansson@arm.com 141310206Sandreas.hansson@arm.com // track if we should switch or not 141410206Sandreas.hansson@arm.com bool switch_to_writes = false; 141510206Sandreas.hansson@arm.com 141612969SMatteo.Andreozzi@arm.com if (totalReadQueueSize == 0) { 141710206Sandreas.hansson@arm.com // In the case there is no read request to go next, 141810206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 141910206Sandreas.hansson@arm.com // if we are draining) 142012969SMatteo.Andreozzi@arm.com if (!(totalWriteQueueSize == 0) && 142110913Sandreas.sandberg@arm.com (drainState() == DrainState::Draining || 142212969SMatteo.Andreozzi@arm.com totalWriteQueueSize > writeLowThreshold)) { 142312969SMatteo.Andreozzi@arm.com 142412969SMatteo.Andreozzi@arm.com DPRINTF(DRAM, "Switching to writes due to read queue empty\n"); 142510206Sandreas.hansson@arm.com switch_to_writes = true; 142610206Sandreas.hansson@arm.com } else { 142710206Sandreas.hansson@arm.com // check if we are drained 142811676Swendy.elsasser@arm.com // not done draining until in PWR_IDLE state 142911676Swendy.elsasser@arm.com // ensuring all banks are closed and 143011676Swendy.elsasser@arm.com // have exited low power states 143110913Sandreas.sandberg@arm.com if (drainState() == DrainState::Draining && 143211676Swendy.elsasser@arm.com respQueue.empty() && allRanksDrained()) { 143310913Sandreas.sandberg@arm.com 143410509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 143510913Sandreas.sandberg@arm.com signalDrainDone(); 143610206Sandreas.hansson@arm.com } 143710206Sandreas.hansson@arm.com 143810206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 143910206Sandreas.hansson@arm.com // event for the next request 144010206Sandreas.hansson@arm.com return; 144110206Sandreas.hansson@arm.com } 144210206Sandreas.hansson@arm.com } else { 144312969SMatteo.Andreozzi@arm.com 144412969SMatteo.Andreozzi@arm.com bool read_found = false; 144512969SMatteo.Andreozzi@arm.com DRAMPacketQueue::iterator to_read; 144612969SMatteo.Andreozzi@arm.com uint8_t prio = numPriorities(); 144712969SMatteo.Andreozzi@arm.com 144812969SMatteo.Andreozzi@arm.com for (auto queue = readQueue.rbegin(); 144912969SMatteo.Andreozzi@arm.com queue != readQueue.rend(); ++queue) { 145012969SMatteo.Andreozzi@arm.com 145112969SMatteo.Andreozzi@arm.com prio--; 145212969SMatteo.Andreozzi@arm.com 145312969SMatteo.Andreozzi@arm.com DPRINTF(QOS, 145412969SMatteo.Andreozzi@arm.com "DRAM controller checking READ queue [%d] priority [%d elements]\n", 145512969SMatteo.Andreozzi@arm.com prio, queue->size()); 145612969SMatteo.Andreozzi@arm.com 145712969SMatteo.Andreozzi@arm.com // Figure out which read request goes next 145812969SMatteo.Andreozzi@arm.com // If we are changing command type, incorporate the minimum 145912969SMatteo.Andreozzi@arm.com // bus turnaround delay which will be tCS (different rank) case 146012969SMatteo.Andreozzi@arm.com to_read = chooseNext((*queue), switched_cmd_type ? tCS : 0); 146112969SMatteo.Andreozzi@arm.com 146212969SMatteo.Andreozzi@arm.com if (to_read != queue->end()) { 146312969SMatteo.Andreozzi@arm.com // candidate read found 146412969SMatteo.Andreozzi@arm.com read_found = true; 146512969SMatteo.Andreozzi@arm.com break; 146612969SMatteo.Andreozzi@arm.com } 146712969SMatteo.Andreozzi@arm.com } 146810618SOmar.Naji@arm.com 146910618SOmar.Naji@arm.com // if no read to an available rank is found then return 147010618SOmar.Naji@arm.com // at this point. There could be writes to the available ranks 147110618SOmar.Naji@arm.com // which are above the required threshold. However, to 147210618SOmar.Naji@arm.com // avoid adding more complexity to the code, return and wait 147310618SOmar.Naji@arm.com // for a refresh event to kick things into action again. 147412969SMatteo.Andreozzi@arm.com if (!read_found) { 147512969SMatteo.Andreozzi@arm.com DPRINTF(DRAM, "No Reads Found - exiting\n"); 147610618SOmar.Naji@arm.com return; 147712969SMatteo.Andreozzi@arm.com } 147812969SMatteo.Andreozzi@arm.com 147912969SMatteo.Andreozzi@arm.com auto dram_pkt = *to_read; 148012969SMatteo.Andreozzi@arm.com 148112266Sradhika.jagtap@arm.com assert(dram_pkt->rankRef.inRefIdleState()); 148211678Swendy.elsasser@arm.com 148310215Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 148410206Sandreas.hansson@arm.com 148511678Swendy.elsasser@arm.com // Every respQueue which will generate an event, increment count 148611678Swendy.elsasser@arm.com ++dram_pkt->rankRef.outstandingEvents; 148710215Sandreas.hansson@arm.com // sanity check 148810215Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 148910215Sandreas.hansson@arm.com assert(dram_pkt->readyTime >= curTick()); 149010215Sandreas.hansson@arm.com 149112969SMatteo.Andreozzi@arm.com // log the response 149212969SMatteo.Andreozzi@arm.com logResponse(MemCtrl::READ, (*to_read)->masterId(), 149312969SMatteo.Andreozzi@arm.com dram_pkt->qosValue(), dram_pkt->getAddr(), 1, 149412969SMatteo.Andreozzi@arm.com dram_pkt->readyTime - dram_pkt->entryTime); 149512969SMatteo.Andreozzi@arm.com 149612969SMatteo.Andreozzi@arm.com 149710215Sandreas.hansson@arm.com // Insert into response queue. It will be sent back to the 149812969SMatteo.Andreozzi@arm.com // requester at its readyTime 149910215Sandreas.hansson@arm.com if (respQueue.empty()) { 150010215Sandreas.hansson@arm.com assert(!respondEvent.scheduled()); 150110215Sandreas.hansson@arm.com schedule(respondEvent, dram_pkt->readyTime); 150210215Sandreas.hansson@arm.com } else { 150310215Sandreas.hansson@arm.com assert(respQueue.back()->readyTime <= dram_pkt->readyTime); 150410215Sandreas.hansson@arm.com assert(respondEvent.scheduled()); 150510215Sandreas.hansson@arm.com } 150610215Sandreas.hansson@arm.com 150710215Sandreas.hansson@arm.com respQueue.push_back(dram_pkt); 150810206Sandreas.hansson@arm.com 150910206Sandreas.hansson@arm.com // we have so many writes that we have to transition 151012969SMatteo.Andreozzi@arm.com if (totalWriteQueueSize > writeHighThreshold) { 151110206Sandreas.hansson@arm.com switch_to_writes = true; 151210206Sandreas.hansson@arm.com } 151312969SMatteo.Andreozzi@arm.com 151412969SMatteo.Andreozzi@arm.com // remove the request from the queue - the iterator is no longer valid . 151512969SMatteo.Andreozzi@arm.com readQueue[dram_pkt->qosValue()].erase(to_read); 151610206Sandreas.hansson@arm.com } 151710206Sandreas.hansson@arm.com 151810206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 151910206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 152010206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 152110206Sandreas.hansson@arm.com if (switch_to_writes) { 152210206Sandreas.hansson@arm.com // transition to writing 152311678Swendy.elsasser@arm.com busStateNext = WRITE; 152410206Sandreas.hansson@arm.com } 15259352SN/A } else { 152612969SMatteo.Andreozzi@arm.com 152712969SMatteo.Andreozzi@arm.com bool write_found = false; 152812969SMatteo.Andreozzi@arm.com DRAMPacketQueue::iterator to_write; 152912969SMatteo.Andreozzi@arm.com uint8_t prio = numPriorities(); 153012969SMatteo.Andreozzi@arm.com 153112969SMatteo.Andreozzi@arm.com for (auto queue = writeQueue.rbegin(); 153212969SMatteo.Andreozzi@arm.com queue != writeQueue.rend(); ++queue) { 153312969SMatteo.Andreozzi@arm.com 153412969SMatteo.Andreozzi@arm.com prio--; 153512969SMatteo.Andreozzi@arm.com 153612969SMatteo.Andreozzi@arm.com DPRINTF(QOS, 153712969SMatteo.Andreozzi@arm.com "DRAM controller checking WRITE queue [%d] priority [%d elements]\n", 153812969SMatteo.Andreozzi@arm.com prio, queue->size()); 153912969SMatteo.Andreozzi@arm.com 154012969SMatteo.Andreozzi@arm.com // If we are changing command type, incorporate the minimum 154112969SMatteo.Andreozzi@arm.com // bus turnaround delay 154212969SMatteo.Andreozzi@arm.com to_write = chooseNext((*queue), 154312969SMatteo.Andreozzi@arm.com switched_cmd_type ? std::min(tRTW, tCS) : 0); 154412969SMatteo.Andreozzi@arm.com 154512969SMatteo.Andreozzi@arm.com if (to_write != queue->end()) { 154612969SMatteo.Andreozzi@arm.com write_found = true; 154712969SMatteo.Andreozzi@arm.com break; 154812969SMatteo.Andreozzi@arm.com } 154912969SMatteo.Andreozzi@arm.com } 155010618SOmar.Naji@arm.com 155112266Sradhika.jagtap@arm.com // if there are no writes to a rank that is available to service 155212266Sradhika.jagtap@arm.com // requests (i.e. rank is in refresh idle state) are found then 155312266Sradhika.jagtap@arm.com // return. There could be reads to the available ranks. However, to 155412266Sradhika.jagtap@arm.com // avoid adding more complexity to the code, return at this point and 155512266Sradhika.jagtap@arm.com // wait for a refresh event to kick things into action again. 155612969SMatteo.Andreozzi@arm.com if (!write_found) { 155712969SMatteo.Andreozzi@arm.com DPRINTF(DRAM, "No Writes Found - exiting\n"); 155810618SOmar.Naji@arm.com return; 155912969SMatteo.Andreozzi@arm.com } 156012969SMatteo.Andreozzi@arm.com 156112969SMatteo.Andreozzi@arm.com auto dram_pkt = *to_write; 156212969SMatteo.Andreozzi@arm.com 156312266Sradhika.jagtap@arm.com assert(dram_pkt->rankRef.inRefIdleState()); 156410206Sandreas.hansson@arm.com // sanity check 156510206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 156610393Swendy.elsasser@arm.com 156710206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 156810206Sandreas.hansson@arm.com 156911678Swendy.elsasser@arm.com // removed write from queue, decrement count 157011678Swendy.elsasser@arm.com --dram_pkt->rankRef.writeEntries; 157111678Swendy.elsasser@arm.com 157211678Swendy.elsasser@arm.com // Schedule write done event to decrement event count 157311678Swendy.elsasser@arm.com // after the readyTime has been reached 157411678Swendy.elsasser@arm.com // Only schedule latest write event to minimize events 157511678Swendy.elsasser@arm.com // required; only need to ensure that final event scheduled covers 157611678Swendy.elsasser@arm.com // the time that writes are outstanding and bus is active 157711678Swendy.elsasser@arm.com // to holdoff power-down entry events 157811678Swendy.elsasser@arm.com if (!dram_pkt->rankRef.writeDoneEvent.scheduled()) { 157911678Swendy.elsasser@arm.com schedule(dram_pkt->rankRef.writeDoneEvent, dram_pkt->readyTime); 158011678Swendy.elsasser@arm.com // New event, increment count 158111678Swendy.elsasser@arm.com ++dram_pkt->rankRef.outstandingEvents; 158211678Swendy.elsasser@arm.com 158311678Swendy.elsasser@arm.com } else if (dram_pkt->rankRef.writeDoneEvent.when() < 158412969SMatteo.Andreozzi@arm.com dram_pkt->readyTime) { 158512969SMatteo.Andreozzi@arm.com 158611678Swendy.elsasser@arm.com reschedule(dram_pkt->rankRef.writeDoneEvent, dram_pkt->readyTime); 158711678Swendy.elsasser@arm.com } 158811678Swendy.elsasser@arm.com 158910889Sandreas.hansson@arm.com isInWriteQueue.erase(burstAlign(dram_pkt->addr)); 159012969SMatteo.Andreozzi@arm.com 159112969SMatteo.Andreozzi@arm.com // log the response 159212969SMatteo.Andreozzi@arm.com logResponse(MemCtrl::WRITE, dram_pkt->masterId(), 159312969SMatteo.Andreozzi@arm.com dram_pkt->qosValue(), dram_pkt->getAddr(), 1, 159412969SMatteo.Andreozzi@arm.com dram_pkt->readyTime - dram_pkt->entryTime); 159512969SMatteo.Andreozzi@arm.com 159612969SMatteo.Andreozzi@arm.com 159712969SMatteo.Andreozzi@arm.com // remove the request from the queue - the iterator is no longer valid 159812969SMatteo.Andreozzi@arm.com writeQueue[dram_pkt->qosValue()].erase(to_write); 159912969SMatteo.Andreozzi@arm.com 160010206Sandreas.hansson@arm.com delete dram_pkt; 160110206Sandreas.hansson@arm.com 160210206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 160310206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 160410206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 160510206Sandreas.hansson@arm.com // writes, then switch to reads. 160612969SMatteo.Andreozzi@arm.com bool below_threshold = 160712969SMatteo.Andreozzi@arm.com totalWriteQueueSize + minWritesPerSwitch < writeLowThreshold; 160812969SMatteo.Andreozzi@arm.com 160912969SMatteo.Andreozzi@arm.com if (totalWriteQueueSize == 0 || 161012969SMatteo.Andreozzi@arm.com (below_threshold && drainState() != DrainState::Draining) || 161112969SMatteo.Andreozzi@arm.com (totalReadQueueSize && writesThisTime >= minWritesPerSwitch)) { 161212969SMatteo.Andreozzi@arm.com 161310206Sandreas.hansson@arm.com // turn the bus back around for reads again 161411678Swendy.elsasser@arm.com busStateNext = READ; 161510206Sandreas.hansson@arm.com 161610206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 161710206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 161810206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 161910206Sandreas.hansson@arm.com // nothing to do 162010206Sandreas.hansson@arm.com } 162110206Sandreas.hansson@arm.com } 162210618SOmar.Naji@arm.com // It is possible that a refresh to another rank kicks things back into 162310618SOmar.Naji@arm.com // action before reaching this point. 162410618SOmar.Naji@arm.com if (!nextReqEvent.scheduled()) 162510618SOmar.Naji@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 162610206Sandreas.hansson@arm.com 162710206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 162810206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 162910206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 163010206Sandreas.hansson@arm.com // the next request processing 163112969SMatteo.Andreozzi@arm.com if (retryWrReq && totalWriteQueueSize < writeBufferSize) { 163210206Sandreas.hansson@arm.com retryWrReq = false; 163310713Sandreas.hansson@arm.com port.sendRetryReq(); 16349352SN/A } 16359243SN/A} 16369243SN/A 163712706Swendy.elsasser@arm.compair<vector<uint32_t>, bool> 163812969SMatteo.Andreozzi@arm.comDRAMCtrl::minBankPrep(const DRAMPacketQueue& queue, 163910890Swendy.elsasser@arm.com Tick min_col_at) const 16409967SN/A{ 164110211Sandreas.hansson@arm.com Tick min_act_at = MaxTick; 164212706Swendy.elsasser@arm.com vector<uint32_t> bank_mask(ranksPerChannel, 0); 16439967SN/A 164410890Swendy.elsasser@arm.com // latest Tick for which ACT can occur without incurring additoinal 164510890Swendy.elsasser@arm.com // delay on the data bus 164610890Swendy.elsasser@arm.com const Tick hidden_act_max = std::max(min_col_at - tRCD, curTick()); 164710393Swendy.elsasser@arm.com 164810890Swendy.elsasser@arm.com // Flag condition when burst can issue back-to-back with previous burst 164910890Swendy.elsasser@arm.com bool found_seamless_bank = false; 165010890Swendy.elsasser@arm.com 165110890Swendy.elsasser@arm.com // Flag condition when bank can be opened without incurring additional 165210890Swendy.elsasser@arm.com // delay on the data bus 165310890Swendy.elsasser@arm.com bool hidden_bank_prep = false; 165410393Swendy.elsasser@arm.com 165510393Swendy.elsasser@arm.com // determine if we have queued transactions targetting the 16569967SN/A // bank in question 16579967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 165810618SOmar.Naji@arm.com for (const auto& p : queue) { 165912266Sradhika.jagtap@arm.com if (p->rankRef.inRefIdleState()) 166010618SOmar.Naji@arm.com got_waiting[p->bankId] = true; 16619967SN/A } 16629967SN/A 166310890Swendy.elsasser@arm.com // Find command with optimal bank timing 166410890Swendy.elsasser@arm.com // Will prioritize commands that can issue seamlessly. 16659967SN/A for (int i = 0; i < ranksPerChannel; i++) { 16669967SN/A for (int j = 0; j < banksPerRank; j++) { 166710618SOmar.Naji@arm.com uint16_t bank_id = i * banksPerRank + j; 166810211Sandreas.hansson@arm.com 16699967SN/A // if we have waiting requests for the bank, and it is 16709967SN/A // amongst the first available, update the mask 167110211Sandreas.hansson@arm.com if (got_waiting[bank_id]) { 167210618SOmar.Naji@arm.com // make sure this rank is not currently refreshing. 167312266Sradhika.jagtap@arm.com assert(ranks[i]->inRefIdleState()); 167410211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue 167510211Sandreas.hansson@arm.com // an activate, ignoring any rank-to-rank switching 167610393Swendy.elsasser@arm.com // cost in this calculation 167710618SOmar.Naji@arm.com Tick act_at = ranks[i]->banks[j].openRow == Bank::NO_ROW ? 167810890Swendy.elsasser@arm.com std::max(ranks[i]->banks[j].actAllowedAt, curTick()) : 167910618SOmar.Naji@arm.com std::max(ranks[i]->banks[j].preAllowedAt, curTick()) + tRP; 168010211Sandreas.hansson@arm.com 168110890Swendy.elsasser@arm.com // When is the earliest the R/W burst can issue? 168212706Swendy.elsasser@arm.com const Tick col_allowed_at = (busState == READ) ? 168312706Swendy.elsasser@arm.com ranks[i]->banks[j].rdAllowedAt : 168412706Swendy.elsasser@arm.com ranks[i]->banks[j].wrAllowedAt; 168512706Swendy.elsasser@arm.com Tick col_at = std::max(col_allowed_at, act_at + tRCD); 168610393Swendy.elsasser@arm.com 168710890Swendy.elsasser@arm.com // bank can issue burst back-to-back (seamlessly) with 168810890Swendy.elsasser@arm.com // previous burst 168910890Swendy.elsasser@arm.com bool new_seamless_bank = col_at <= min_col_at; 169010393Swendy.elsasser@arm.com 169110890Swendy.elsasser@arm.com // if we found a new seamless bank or we have no 169210890Swendy.elsasser@arm.com // seamless banks, and got a bank with an earlier 169310890Swendy.elsasser@arm.com // activate time, it should be added to the bit mask 169410890Swendy.elsasser@arm.com if (new_seamless_bank || 169510890Swendy.elsasser@arm.com (!found_seamless_bank && act_at <= min_act_at)) { 169610890Swendy.elsasser@arm.com // if we did not have a seamless bank before, and 169710890Swendy.elsasser@arm.com // we do now, reset the bank mask, also reset it 169810890Swendy.elsasser@arm.com // if we have not yet found a seamless bank and 169910890Swendy.elsasser@arm.com // the activate time is smaller than what we have 170010890Swendy.elsasser@arm.com // seen so far 170110890Swendy.elsasser@arm.com if (!found_seamless_bank && 170210890Swendy.elsasser@arm.com (new_seamless_bank || act_at < min_act_at)) { 170312706Swendy.elsasser@arm.com std::fill(bank_mask.begin(), bank_mask.end(), 0); 170410393Swendy.elsasser@arm.com } 170510890Swendy.elsasser@arm.com 170610890Swendy.elsasser@arm.com found_seamless_bank |= new_seamless_bank; 170710890Swendy.elsasser@arm.com 170810890Swendy.elsasser@arm.com // ACT can occur 'behind the scenes' 170910890Swendy.elsasser@arm.com hidden_bank_prep = act_at <= hidden_act_max; 171010890Swendy.elsasser@arm.com 171110890Swendy.elsasser@arm.com // set the bit corresponding to the available bank 171212706Swendy.elsasser@arm.com replaceBits(bank_mask[i], j, j, 1); 171310890Swendy.elsasser@arm.com min_act_at = act_at; 171410211Sandreas.hansson@arm.com } 17159967SN/A } 17169967SN/A } 17179967SN/A } 171810211Sandreas.hansson@arm.com 171910890Swendy.elsasser@arm.com return make_pair(bank_mask, hidden_bank_prep); 17209967SN/A} 17219967SN/A 172212081Sspwilson2@wisc.eduDRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p, int rank) 172310618SOmar.Naji@arm.com : EventManager(&_memory), memory(_memory), 172411678Swendy.elsasser@arm.com pwrStateTrans(PWR_IDLE), pwrStatePostRefresh(PWR_IDLE), 172511678Swendy.elsasser@arm.com pwrStateTick(0), refreshDueAt(0), pwrState(PWR_IDLE), 172612081Sspwilson2@wisc.edu refreshState(REF_IDLE), inLowPowerState(false), rank(rank), 172711678Swendy.elsasser@arm.com readEntries(0), writeEntries(0), outstandingEvents(0), 172812081Sspwilson2@wisc.edu wakeUpAllowedAt(0), power(_p, false), banks(_p->banks_per_rank), 172912081Sspwilson2@wisc.edu numBanksActive(0), actTicks(_p->activation_limit, 0), 173012084Sspwilson2@wisc.edu writeDoneEvent([this]{ processWriteDoneEvent(); }, name()), 173112084Sspwilson2@wisc.edu activateEvent([this]{ processActivateEvent(); }, name()), 173212084Sspwilson2@wisc.edu prechargeEvent([this]{ processPrechargeEvent(); }, name()), 173312084Sspwilson2@wisc.edu refreshEvent([this]{ processRefreshEvent(); }, name()), 173412084Sspwilson2@wisc.edu powerEvent([this]{ processPowerEvent(); }, name()), 173512084Sspwilson2@wisc.edu wakeUpEvent([this]{ processWakeUpEvent(); }, name()) 173612081Sspwilson2@wisc.edu{ 173712081Sspwilson2@wisc.edu for (int b = 0; b < _p->banks_per_rank; b++) { 173812081Sspwilson2@wisc.edu banks[b].bank = b; 173912081Sspwilson2@wisc.edu // GDDR addressing of banks to BG is linear. 174012081Sspwilson2@wisc.edu // Here we assume that all DRAM generations address bank groups as 174112081Sspwilson2@wisc.edu // follows: 174212081Sspwilson2@wisc.edu if (_p->bank_groups_per_rank > 0) { 174312081Sspwilson2@wisc.edu // Simply assign lower bits to bank group in order to 174412081Sspwilson2@wisc.edu // rotate across bank groups as banks are incremented 174512081Sspwilson2@wisc.edu // e.g. with 4 banks per bank group and 16 banks total: 174612081Sspwilson2@wisc.edu // banks 0,4,8,12 are in bank group 0 174712081Sspwilson2@wisc.edu // banks 1,5,9,13 are in bank group 1 174812081Sspwilson2@wisc.edu // banks 2,6,10,14 are in bank group 2 174912081Sspwilson2@wisc.edu // banks 3,7,11,15 are in bank group 3 175012081Sspwilson2@wisc.edu banks[b].bankgr = b % _p->bank_groups_per_rank; 175112081Sspwilson2@wisc.edu } else { 175212081Sspwilson2@wisc.edu // No bank groups; simply assign to bank number 175312081Sspwilson2@wisc.edu banks[b].bankgr = b; 175412081Sspwilson2@wisc.edu } 175512081Sspwilson2@wisc.edu } 175612081Sspwilson2@wisc.edu} 175710618SOmar.Naji@arm.com 17589243SN/Avoid 175910618SOmar.Naji@arm.comDRAMCtrl::Rank::startup(Tick ref_tick) 176010618SOmar.Naji@arm.com{ 176110618SOmar.Naji@arm.com assert(ref_tick > curTick()); 176210618SOmar.Naji@arm.com 176310618SOmar.Naji@arm.com pwrStateTick = curTick(); 176410618SOmar.Naji@arm.com 176510618SOmar.Naji@arm.com // kick off the refresh, and give ourselves enough time to 176610618SOmar.Naji@arm.com // precharge 176710618SOmar.Naji@arm.com schedule(refreshEvent, ref_tick); 176810618SOmar.Naji@arm.com} 176910618SOmar.Naji@arm.com 177010618SOmar.Naji@arm.comvoid 177110619Sandreas.hansson@arm.comDRAMCtrl::Rank::suspend() 177210619Sandreas.hansson@arm.com{ 177310619Sandreas.hansson@arm.com deschedule(refreshEvent); 177411676Swendy.elsasser@arm.com 177511676Swendy.elsasser@arm.com // Update the stats 177611676Swendy.elsasser@arm.com updatePowerStats(); 177711678Swendy.elsasser@arm.com 177811678Swendy.elsasser@arm.com // don't automatically transition back to LP state after next REF 177911678Swendy.elsasser@arm.com pwrStatePostRefresh = PWR_IDLE; 178011678Swendy.elsasser@arm.com} 178111678Swendy.elsasser@arm.com 178211678Swendy.elsasser@arm.combool 178312705Swendy.elsasser@arm.comDRAMCtrl::Rank::isQueueEmpty() const 178411678Swendy.elsasser@arm.com{ 178512705Swendy.elsasser@arm.com // check commmands in Q based on current bus direction 178611678Swendy.elsasser@arm.com bool no_queued_cmds = ((memory.busStateNext == READ) && (readEntries == 0)) 178711678Swendy.elsasser@arm.com || ((memory.busStateNext == WRITE) && 178811678Swendy.elsasser@arm.com (writeEntries == 0)); 178912705Swendy.elsasser@arm.com return no_queued_cmds; 179010619Sandreas.hansson@arm.com} 179110619Sandreas.hansson@arm.com 179210619Sandreas.hansson@arm.comvoid 179310618SOmar.Naji@arm.comDRAMCtrl::Rank::checkDrainDone() 179410618SOmar.Naji@arm.com{ 179510618SOmar.Naji@arm.com // if this rank was waiting to drain it is now able to proceed to 179610618SOmar.Naji@arm.com // precharge 179710618SOmar.Naji@arm.com if (refreshState == REF_DRAIN) { 179810618SOmar.Naji@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 179910618SOmar.Naji@arm.com 180011678Swendy.elsasser@arm.com refreshState = REF_PD_EXIT; 180110618SOmar.Naji@arm.com 180210618SOmar.Naji@arm.com // hand control back to the refresh event loop 180310618SOmar.Naji@arm.com schedule(refreshEvent, curTick()); 180410618SOmar.Naji@arm.com } 180510618SOmar.Naji@arm.com} 180610618SOmar.Naji@arm.com 180710618SOmar.Naji@arm.comvoid 180811675Swendy.elsasser@arm.comDRAMCtrl::Rank::flushCmdList() 180911675Swendy.elsasser@arm.com{ 181011675Swendy.elsasser@arm.com // at the moment sort the list of commands and update the counters 181111675Swendy.elsasser@arm.com // for DRAMPower libray when doing a refresh 181211675Swendy.elsasser@arm.com sort(cmdList.begin(), cmdList.end(), DRAMCtrl::sortTime); 181311675Swendy.elsasser@arm.com 181411675Swendy.elsasser@arm.com auto next_iter = cmdList.begin(); 181511675Swendy.elsasser@arm.com // push to commands to DRAMPower 181611675Swendy.elsasser@arm.com for ( ; next_iter != cmdList.end() ; ++next_iter) { 181711675Swendy.elsasser@arm.com Command cmd = *next_iter; 181811675Swendy.elsasser@arm.com if (cmd.timeStamp <= curTick()) { 181911675Swendy.elsasser@arm.com // Move all commands at or before curTick to DRAMPower 182011675Swendy.elsasser@arm.com power.powerlib.doCommand(cmd.type, cmd.bank, 182111675Swendy.elsasser@arm.com divCeil(cmd.timeStamp, memory.tCK) - 182211675Swendy.elsasser@arm.com memory.timeStampOffset); 182311675Swendy.elsasser@arm.com } else { 182411675Swendy.elsasser@arm.com // done - found all commands at or before curTick() 182511675Swendy.elsasser@arm.com // next_iter references the 1st command after curTick 182611675Swendy.elsasser@arm.com break; 182711675Swendy.elsasser@arm.com } 182811675Swendy.elsasser@arm.com } 182911675Swendy.elsasser@arm.com // reset cmdList to only contain commands after curTick 183011675Swendy.elsasser@arm.com // if there are no commands after curTick, updated cmdList will be empty 183111675Swendy.elsasser@arm.com // in this case, next_iter is cmdList.end() 183211675Swendy.elsasser@arm.com cmdList.assign(next_iter, cmdList.end()); 183311675Swendy.elsasser@arm.com} 183411675Swendy.elsasser@arm.com 183511675Swendy.elsasser@arm.comvoid 183610618SOmar.Naji@arm.comDRAMCtrl::Rank::processActivateEvent() 183710618SOmar.Naji@arm.com{ 183810618SOmar.Naji@arm.com // we should transition to the active state as soon as any bank is active 183910618SOmar.Naji@arm.com if (pwrState != PWR_ACT) 184010618SOmar.Naji@arm.com // note that at this point numBanksActive could be back at 184110618SOmar.Naji@arm.com // zero again due to a precharge scheduled in the future 184210618SOmar.Naji@arm.com schedulePowerEvent(PWR_ACT, curTick()); 184310618SOmar.Naji@arm.com} 184410618SOmar.Naji@arm.com 184510618SOmar.Naji@arm.comvoid 184610618SOmar.Naji@arm.comDRAMCtrl::Rank::processPrechargeEvent() 184710618SOmar.Naji@arm.com{ 184811678Swendy.elsasser@arm.com // counter should at least indicate one outstanding request 184911678Swendy.elsasser@arm.com // for this precharge 185011678Swendy.elsasser@arm.com assert(outstandingEvents > 0); 185111678Swendy.elsasser@arm.com // precharge complete, decrement count 185211678Swendy.elsasser@arm.com --outstandingEvents; 185311678Swendy.elsasser@arm.com 185410618SOmar.Naji@arm.com // if we reached zero, then special conditions apply as we track 185510618SOmar.Naji@arm.com // if all banks are precharged for the power models 185610618SOmar.Naji@arm.com if (numBanksActive == 0) { 185711678Swendy.elsasser@arm.com // no reads to this rank in the Q and no pending 185811678Swendy.elsasser@arm.com // RD/WR or refresh commands 185912705Swendy.elsasser@arm.com if (isQueueEmpty() && outstandingEvents == 0) { 186011678Swendy.elsasser@arm.com // should still be in ACT state since bank still open 186111678Swendy.elsasser@arm.com assert(pwrState == PWR_ACT); 186211678Swendy.elsasser@arm.com 186311678Swendy.elsasser@arm.com // All banks closed - switch to precharge power down state. 186411678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleep at tick %d\n", 186511678Swendy.elsasser@arm.com rank, curTick()); 186611678Swendy.elsasser@arm.com powerDownSleep(PWR_PRE_PDN, curTick()); 186711678Swendy.elsasser@arm.com } else { 186811678Swendy.elsasser@arm.com // we should transition to the idle state when the last bank 186911678Swendy.elsasser@arm.com // is precharged 187011678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 187111678Swendy.elsasser@arm.com } 187210618SOmar.Naji@arm.com } 187310618SOmar.Naji@arm.com} 187410618SOmar.Naji@arm.com 187510618SOmar.Naji@arm.comvoid 187611678Swendy.elsasser@arm.comDRAMCtrl::Rank::processWriteDoneEvent() 187711678Swendy.elsasser@arm.com{ 187811678Swendy.elsasser@arm.com // counter should at least indicate one outstanding request 187911678Swendy.elsasser@arm.com // for this write 188011678Swendy.elsasser@arm.com assert(outstandingEvents > 0); 188111678Swendy.elsasser@arm.com // Write transfer on bus has completed 188211678Swendy.elsasser@arm.com // decrement per rank counter 188311678Swendy.elsasser@arm.com --outstandingEvents; 188411678Swendy.elsasser@arm.com} 188511678Swendy.elsasser@arm.com 188611678Swendy.elsasser@arm.comvoid 188710618SOmar.Naji@arm.comDRAMCtrl::Rank::processRefreshEvent() 18889243SN/A{ 188910207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 189011678Swendy.elsasser@arm.com if ((refreshState == REF_IDLE) || (refreshState == REF_SREF_EXIT)) { 189110207Sandreas.hansson@arm.com // remember when the refresh is due 189210207Sandreas.hansson@arm.com refreshDueAt = curTick(); 18939243SN/A 189410207Sandreas.hansson@arm.com // proceed to drain 189510207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 18969243SN/A 189711678Swendy.elsasser@arm.com // make nonzero while refresh is pending to ensure 189811678Swendy.elsasser@arm.com // power down and self-refresh are not entered 189911678Swendy.elsasser@arm.com ++outstandingEvents; 190011678Swendy.elsasser@arm.com 190110207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 190210207Sandreas.hansson@arm.com } 190310207Sandreas.hansson@arm.com 190410618SOmar.Naji@arm.com // let any scheduled read or write to the same rank go ahead, 190510618SOmar.Naji@arm.com // after which it will 190610207Sandreas.hansson@arm.com // hand control back to this event loop 190710207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 190810618SOmar.Naji@arm.com // if a request is at the moment being handled and this request is 190910618SOmar.Naji@arm.com // accessing the current rank then wait for it to finish 191010618SOmar.Naji@arm.com if ((rank == memory.activeRank) 191110618SOmar.Naji@arm.com && (memory.nextReqEvent.scheduled())) { 191210207Sandreas.hansson@arm.com // hand control over to the request loop until it is 191310207Sandreas.hansson@arm.com // evaluated next 191410207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 191510207Sandreas.hansson@arm.com 191610207Sandreas.hansson@arm.com return; 191710207Sandreas.hansson@arm.com } else { 191811678Swendy.elsasser@arm.com refreshState = REF_PD_EXIT; 191911678Swendy.elsasser@arm.com } 192011678Swendy.elsasser@arm.com } 192111678Swendy.elsasser@arm.com 192211678Swendy.elsasser@arm.com // at this point, ensure that rank is not in a power-down state 192311678Swendy.elsasser@arm.com if (refreshState == REF_PD_EXIT) { 192411678Swendy.elsasser@arm.com // if rank was sleeping and we have't started exit process, 192511678Swendy.elsasser@arm.com // wake-up for refresh 192611678Swendy.elsasser@arm.com if (inLowPowerState) { 192711678Swendy.elsasser@arm.com DPRINTF(DRAM, "Wake Up for refresh\n"); 192811678Swendy.elsasser@arm.com // save state and return after refresh completes 192911678Swendy.elsasser@arm.com scheduleWakeUpEvent(memory.tXP); 193011678Swendy.elsasser@arm.com return; 193111678Swendy.elsasser@arm.com } else { 193210207Sandreas.hansson@arm.com refreshState = REF_PRE; 193310207Sandreas.hansson@arm.com } 193410207Sandreas.hansson@arm.com } 193510207Sandreas.hansson@arm.com 193610207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 193710207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 193811678Swendy.elsasser@arm.com // precharge any active bank 193911678Swendy.elsasser@arm.com if (numBanksActive != 0) { 194010214Sandreas.hansson@arm.com // at the moment, we use a precharge all even if there is 194110214Sandreas.hansson@arm.com // only a single bank open 194210208Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 194310214Sandreas.hansson@arm.com 194410214Sandreas.hansson@arm.com // first determine when we can precharge 194510214Sandreas.hansson@arm.com Tick pre_at = curTick(); 194610618SOmar.Naji@arm.com 194710618SOmar.Naji@arm.com for (auto &b : banks) { 194810618SOmar.Naji@arm.com // respect both causality and any existing bank 194910618SOmar.Naji@arm.com // constraints, some banks could already have a 195010618SOmar.Naji@arm.com // (auto) precharge scheduled 195110618SOmar.Naji@arm.com pre_at = std::max(b.preAllowedAt, pre_at); 195210618SOmar.Naji@arm.com } 195310618SOmar.Naji@arm.com 195410618SOmar.Naji@arm.com // make sure all banks per rank are precharged, and for those that 195510618SOmar.Naji@arm.com // already are, update their availability 195610618SOmar.Naji@arm.com Tick act_allowed_at = pre_at + memory.tRP; 195710618SOmar.Naji@arm.com 195810618SOmar.Naji@arm.com for (auto &b : banks) { 195910618SOmar.Naji@arm.com if (b.openRow != Bank::NO_ROW) { 196010618SOmar.Naji@arm.com memory.prechargeBank(*this, b, pre_at, false); 196110618SOmar.Naji@arm.com } else { 196210618SOmar.Naji@arm.com b.actAllowedAt = std::max(b.actAllowedAt, act_allowed_at); 196310618SOmar.Naji@arm.com b.preAllowedAt = std::max(b.preAllowedAt, pre_at); 196410214Sandreas.hansson@arm.com } 196510214Sandreas.hansson@arm.com } 196610214Sandreas.hansson@arm.com 196710618SOmar.Naji@arm.com // precharge all banks in rank 196811675Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PREA, 0, pre_at)); 196910214Sandreas.hansson@arm.com 197010618SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PREA,0,%d\n", 197110618SOmar.Naji@arm.com divCeil(pre_at, memory.tCK) - 197210618SOmar.Naji@arm.com memory.timeStampOffset, rank); 197311678Swendy.elsasser@arm.com } else if ((pwrState == PWR_IDLE) && (outstandingEvents == 1)) { 197411678Swendy.elsasser@arm.com // Banks are closed, have transitioned to IDLE state, and 197511678Swendy.elsasser@arm.com // no outstanding ACT,RD/WR,Auto-PRE sequence scheduled 197610208Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 197710208Sandreas.hansson@arm.com 197811678Swendy.elsasser@arm.com // go ahead and kick the power state machine into gear since 197910208Sandreas.hansson@arm.com // we are already idle 198010208Sandreas.hansson@arm.com schedulePowerEvent(PWR_REF, curTick()); 198111678Swendy.elsasser@arm.com } else { 198211678Swendy.elsasser@arm.com // banks state is closed but haven't transitioned pwrState to IDLE 198311678Swendy.elsasser@arm.com // or have outstanding ACT,RD/WR,Auto-PRE sequence scheduled 198411678Swendy.elsasser@arm.com // should have outstanding precharge event in this case 198511678Swendy.elsasser@arm.com assert(prechargeEvent.scheduled()); 198611678Swendy.elsasser@arm.com // will start refresh when pwrState transitions to IDLE 19879975SN/A } 19889975SN/A 198910208Sandreas.hansson@arm.com assert(numBanksActive == 0); 19909243SN/A 199110208Sandreas.hansson@arm.com // wait for all banks to be precharged, at which point the 199210208Sandreas.hansson@arm.com // power state machine will transition to the idle state, and 199310208Sandreas.hansson@arm.com // automatically move to a refresh, at that point it will also 199410208Sandreas.hansson@arm.com // call this method to get the refresh event loop going again 199510207Sandreas.hansson@arm.com return; 199610207Sandreas.hansson@arm.com } 199710207Sandreas.hansson@arm.com 199810207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 199911678Swendy.elsasser@arm.com if (refreshState == REF_START) { 200011678Swendy.elsasser@arm.com // should never get here with any banks active 200111678Swendy.elsasser@arm.com assert(numBanksActive == 0); 200211678Swendy.elsasser@arm.com assert(pwrState == PWR_REF); 200311678Swendy.elsasser@arm.com 200411678Swendy.elsasser@arm.com Tick ref_done_at = curTick() + memory.tRFC; 200511678Swendy.elsasser@arm.com 200611678Swendy.elsasser@arm.com for (auto &b : banks) { 200711678Swendy.elsasser@arm.com b.actAllowedAt = ref_done_at; 200811678Swendy.elsasser@arm.com } 200911678Swendy.elsasser@arm.com 201011678Swendy.elsasser@arm.com // at the moment this affects all ranks 201111678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::REF, 0, curTick())); 201211678Swendy.elsasser@arm.com 201311678Swendy.elsasser@arm.com // Update the stats 201411678Swendy.elsasser@arm.com updatePowerStats(); 201511678Swendy.elsasser@arm.com 201611678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), memory.tCK) - 201711678Swendy.elsasser@arm.com memory.timeStampOffset, rank); 201811678Swendy.elsasser@arm.com 201911678Swendy.elsasser@arm.com // Update for next refresh 202011678Swendy.elsasser@arm.com refreshDueAt += memory.tREFI; 202111678Swendy.elsasser@arm.com 202211678Swendy.elsasser@arm.com // make sure we did not wait so long that we cannot make up 202311678Swendy.elsasser@arm.com // for it 202411678Swendy.elsasser@arm.com if (refreshDueAt < ref_done_at) { 202511678Swendy.elsasser@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 202611678Swendy.elsasser@arm.com } 202711678Swendy.elsasser@arm.com 202811678Swendy.elsasser@arm.com // Run the refresh and schedule event to transition power states 202911678Swendy.elsasser@arm.com // when refresh completes 203011678Swendy.elsasser@arm.com refreshState = REF_RUN; 203111678Swendy.elsasser@arm.com schedule(refreshEvent, ref_done_at); 203211678Swendy.elsasser@arm.com return; 203311678Swendy.elsasser@arm.com } 203411678Swendy.elsasser@arm.com 203510207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 203610207Sandreas.hansson@arm.com // should never get here with any banks active 203710207Sandreas.hansson@arm.com assert(numBanksActive == 0); 203810208Sandreas.hansson@arm.com assert(pwrState == PWR_REF); 203910207Sandreas.hansson@arm.com 204011678Swendy.elsasser@arm.com assert(!powerEvent.scheduled()); 204111678Swendy.elsasser@arm.com 204211678Swendy.elsasser@arm.com if ((memory.drainState() == DrainState::Draining) || 204311678Swendy.elsasser@arm.com (memory.drainState() == DrainState::Drained)) { 204411678Swendy.elsasser@arm.com // if draining, do not re-enter low-power mode. 204511678Swendy.elsasser@arm.com // simply go to IDLE and wait 204611678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 204711678Swendy.elsasser@arm.com } else { 204811678Swendy.elsasser@arm.com // At the moment, we sleep when the refresh ends and wait to be 204911678Swendy.elsasser@arm.com // woken up again if previously in a low-power state. 205011678Swendy.elsasser@arm.com if (pwrStatePostRefresh != PWR_IDLE) { 205111678Swendy.elsasser@arm.com // power State should be power Refresh 205211678Swendy.elsasser@arm.com assert(pwrState == PWR_REF); 205311678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleeping after refresh and was in " 205411678Swendy.elsasser@arm.com "power state %d before refreshing\n", rank, 205511678Swendy.elsasser@arm.com pwrStatePostRefresh); 205611678Swendy.elsasser@arm.com powerDownSleep(pwrState, curTick()); 205711678Swendy.elsasser@arm.com 205811678Swendy.elsasser@arm.com // Force PRE power-down if there are no outstanding commands 205911678Swendy.elsasser@arm.com // in Q after refresh. 206012705Swendy.elsasser@arm.com } else if (isQueueEmpty()) { 206112705Swendy.elsasser@arm.com // still have refresh event outstanding but there should 206212705Swendy.elsasser@arm.com // be no other events outstanding 206312705Swendy.elsasser@arm.com assert(outstandingEvents == 1); 206411678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleeping after refresh but was NOT" 206511678Swendy.elsasser@arm.com " in a low power state before refreshing\n", rank); 206611678Swendy.elsasser@arm.com powerDownSleep(PWR_PRE_PDN, curTick()); 206711678Swendy.elsasser@arm.com 206811678Swendy.elsasser@arm.com } else { 206911678Swendy.elsasser@arm.com // move to the idle power state once the refresh is done, this 207011678Swendy.elsasser@arm.com // will also move the refresh state machine to the refresh 207111678Swendy.elsasser@arm.com // idle state 207211678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 207311678Swendy.elsasser@arm.com } 207410618SOmar.Naji@arm.com } 207510247Sandreas.hansson@arm.com 207612705Swendy.elsasser@arm.com // At this point, we have completed the current refresh. 207712705Swendy.elsasser@arm.com // In the SREF bypass case, we do not get to this state in the 207812705Swendy.elsasser@arm.com // refresh STM and therefore can always schedule next event. 207912705Swendy.elsasser@arm.com // Compensate for the delay in actually performing the refresh 208012705Swendy.elsasser@arm.com // when scheduling the next one 208112705Swendy.elsasser@arm.com schedule(refreshEvent, refreshDueAt - memory.tRP); 208212705Swendy.elsasser@arm.com 208312705Swendy.elsasser@arm.com DPRINTF(DRAMState, "Refresh done at %llu and next refresh" 208412705Swendy.elsasser@arm.com " at %llu\n", curTick(), refreshDueAt); 208510208Sandreas.hansson@arm.com } 208610208Sandreas.hansson@arm.com} 208710208Sandreas.hansson@arm.com 208810208Sandreas.hansson@arm.comvoid 208910618SOmar.Naji@arm.comDRAMCtrl::Rank::schedulePowerEvent(PowerState pwr_state, Tick tick) 209010208Sandreas.hansson@arm.com{ 209110208Sandreas.hansson@arm.com // respect causality 209210208Sandreas.hansson@arm.com assert(tick >= curTick()); 209310208Sandreas.hansson@arm.com 209410208Sandreas.hansson@arm.com if (!powerEvent.scheduled()) { 209510208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 209610208Sandreas.hansson@arm.com tick, pwr_state); 209710208Sandreas.hansson@arm.com 209810208Sandreas.hansson@arm.com // insert the new transition 209910208Sandreas.hansson@arm.com pwrStateTrans = pwr_state; 210010208Sandreas.hansson@arm.com 210110208Sandreas.hansson@arm.com schedule(powerEvent, tick); 210210208Sandreas.hansson@arm.com } else { 210310208Sandreas.hansson@arm.com panic("Scheduled power event at %llu to state %d, " 210410208Sandreas.hansson@arm.com "with scheduled event at %llu to %d\n", tick, pwr_state, 210510208Sandreas.hansson@arm.com powerEvent.when(), pwrStateTrans); 210610208Sandreas.hansson@arm.com } 210710208Sandreas.hansson@arm.com} 210810208Sandreas.hansson@arm.com 210910208Sandreas.hansson@arm.comvoid 211011678Swendy.elsasser@arm.comDRAMCtrl::Rank::powerDownSleep(PowerState pwr_state, Tick tick) 211111678Swendy.elsasser@arm.com{ 211211678Swendy.elsasser@arm.com // if low power state is active low, schedule to active low power state. 211311678Swendy.elsasser@arm.com // in reality tCKE is needed to enter active low power. This is neglected 211411678Swendy.elsasser@arm.com // here and could be added in the future. 211511678Swendy.elsasser@arm.com if (pwr_state == PWR_ACT_PDN) { 211611678Swendy.elsasser@arm.com schedulePowerEvent(pwr_state, tick); 211711678Swendy.elsasser@arm.com // push command to DRAMPower 211811678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PDN_F_ACT, 0, tick)); 211911678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PDN_F_ACT,0,%d\n", divCeil(tick, 212011678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 212111678Swendy.elsasser@arm.com } else if (pwr_state == PWR_PRE_PDN) { 212211678Swendy.elsasser@arm.com // if low power state is precharge low, schedule to precharge low 212311678Swendy.elsasser@arm.com // power state. In reality tCKE is needed to enter active low power. 212411678Swendy.elsasser@arm.com // This is neglected here. 212511678Swendy.elsasser@arm.com schedulePowerEvent(pwr_state, tick); 212611678Swendy.elsasser@arm.com //push Command to DRAMPower 212711678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PDN_F_PRE, 0, tick)); 212811678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PDN_F_PRE,0,%d\n", divCeil(tick, 212911678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 213011678Swendy.elsasser@arm.com } else if (pwr_state == PWR_REF) { 213112705Swendy.elsasser@arm.com // if a refresh just occurred 213211678Swendy.elsasser@arm.com // transition to PRE_PDN now that all banks are closed 213312705Swendy.elsasser@arm.com // precharge power down requires tCKE to enter. For simplicity 213412705Swendy.elsasser@arm.com // this is not considered. 213512705Swendy.elsasser@arm.com schedulePowerEvent(PWR_PRE_PDN, tick); 213612705Swendy.elsasser@arm.com //push Command to DRAMPower 213712705Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PDN_F_PRE, 0, tick)); 213812705Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PDN_F_PRE,0,%d\n", divCeil(tick, 213912705Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 214012705Swendy.elsasser@arm.com } else if (pwr_state == PWR_SREF) { 214112705Swendy.elsasser@arm.com // should only enter SREF after PRE-PD wakeup to do a refresh 214212705Swendy.elsasser@arm.com assert(pwrStatePostRefresh == PWR_PRE_PDN); 214312705Swendy.elsasser@arm.com // self refresh requires time tCKESR to enter. For simplicity, 214412705Swendy.elsasser@arm.com // this is not considered. 214512705Swendy.elsasser@arm.com schedulePowerEvent(PWR_SREF, tick); 214612705Swendy.elsasser@arm.com // push Command to DRAMPower 214712705Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::SREN, 0, tick)); 214812705Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,SREN,0,%d\n", divCeil(tick, 214912705Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 215011678Swendy.elsasser@arm.com } 215111678Swendy.elsasser@arm.com // Ensure that we don't power-down and back up in same tick 215211678Swendy.elsasser@arm.com // Once we commit to PD entry, do it and wait for at least 1tCK 215311678Swendy.elsasser@arm.com // This could be replaced with tCKE if/when that is added to the model 215411678Swendy.elsasser@arm.com wakeUpAllowedAt = tick + memory.tCK; 215511678Swendy.elsasser@arm.com 215611678Swendy.elsasser@arm.com // Transitioning to a low power state, set flag 215711678Swendy.elsasser@arm.com inLowPowerState = true; 215811678Swendy.elsasser@arm.com} 215911678Swendy.elsasser@arm.com 216011678Swendy.elsasser@arm.comvoid 216111678Swendy.elsasser@arm.comDRAMCtrl::Rank::scheduleWakeUpEvent(Tick exit_delay) 216211678Swendy.elsasser@arm.com{ 216311678Swendy.elsasser@arm.com Tick wake_up_tick = std::max(curTick(), wakeUpAllowedAt); 216411678Swendy.elsasser@arm.com 216511678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Scheduling wake-up for rank %d at tick %d\n", 216611678Swendy.elsasser@arm.com rank, wake_up_tick); 216711678Swendy.elsasser@arm.com 216811678Swendy.elsasser@arm.com // if waking for refresh, hold previous state 216911678Swendy.elsasser@arm.com // else reset state back to IDLE 217011678Swendy.elsasser@arm.com if (refreshState == REF_PD_EXIT) { 217111678Swendy.elsasser@arm.com pwrStatePostRefresh = pwrState; 217211678Swendy.elsasser@arm.com } else { 217311678Swendy.elsasser@arm.com // don't automatically transition back to LP state after next REF 217411678Swendy.elsasser@arm.com pwrStatePostRefresh = PWR_IDLE; 217511678Swendy.elsasser@arm.com } 217611678Swendy.elsasser@arm.com 217711678Swendy.elsasser@arm.com // schedule wake-up with event to ensure entry has completed before 217811678Swendy.elsasser@arm.com // we try to wake-up 217911678Swendy.elsasser@arm.com schedule(wakeUpEvent, wake_up_tick); 218011678Swendy.elsasser@arm.com 218111678Swendy.elsasser@arm.com for (auto &b : banks) { 218211678Swendy.elsasser@arm.com // respect both causality and any existing bank 218311678Swendy.elsasser@arm.com // constraints, some banks could already have a 218411678Swendy.elsasser@arm.com // (auto) precharge scheduled 218512706Swendy.elsasser@arm.com b.wrAllowedAt = std::max(wake_up_tick + exit_delay, b.wrAllowedAt); 218612706Swendy.elsasser@arm.com b.rdAllowedAt = std::max(wake_up_tick + exit_delay, b.rdAllowedAt); 218711678Swendy.elsasser@arm.com b.preAllowedAt = std::max(wake_up_tick + exit_delay, b.preAllowedAt); 218811678Swendy.elsasser@arm.com b.actAllowedAt = std::max(wake_up_tick + exit_delay, b.actAllowedAt); 218911678Swendy.elsasser@arm.com } 219011678Swendy.elsasser@arm.com // Transitioning out of low power state, clear flag 219111678Swendy.elsasser@arm.com inLowPowerState = false; 219211678Swendy.elsasser@arm.com 219311678Swendy.elsasser@arm.com // push to DRAMPower 219411678Swendy.elsasser@arm.com // use pwrStateTrans for cases where we have a power event scheduled 219511678Swendy.elsasser@arm.com // to enter low power that has not yet been processed 219611678Swendy.elsasser@arm.com if (pwrStateTrans == PWR_ACT_PDN) { 219711678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PUP_ACT, 0, wake_up_tick)); 219811678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PUP_ACT,0,%d\n", divCeil(wake_up_tick, 219911678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 220011678Swendy.elsasser@arm.com 220111678Swendy.elsasser@arm.com } else if (pwrStateTrans == PWR_PRE_PDN) { 220211678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PUP_PRE, 0, wake_up_tick)); 220311678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PUP_PRE,0,%d\n", divCeil(wake_up_tick, 220411678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 220511678Swendy.elsasser@arm.com } else if (pwrStateTrans == PWR_SREF) { 220611678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::SREX, 0, wake_up_tick)); 220711678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,SREX,0,%d\n", divCeil(wake_up_tick, 220811678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 220911678Swendy.elsasser@arm.com } 221011678Swendy.elsasser@arm.com} 221111678Swendy.elsasser@arm.com 221211678Swendy.elsasser@arm.comvoid 221311678Swendy.elsasser@arm.comDRAMCtrl::Rank::processWakeUpEvent() 221411678Swendy.elsasser@arm.com{ 221511678Swendy.elsasser@arm.com // Should be in a power-down or self-refresh state 221611678Swendy.elsasser@arm.com assert((pwrState == PWR_ACT_PDN) || (pwrState == PWR_PRE_PDN) || 221711678Swendy.elsasser@arm.com (pwrState == PWR_SREF)); 221811678Swendy.elsasser@arm.com 221911678Swendy.elsasser@arm.com // Check current state to determine transition state 222011678Swendy.elsasser@arm.com if (pwrState == PWR_ACT_PDN) { 222111678Swendy.elsasser@arm.com // banks still open, transition to PWR_ACT 222211678Swendy.elsasser@arm.com schedulePowerEvent(PWR_ACT, curTick()); 222311678Swendy.elsasser@arm.com } else { 222411678Swendy.elsasser@arm.com // transitioning from a precharge power-down or self-refresh state 222511678Swendy.elsasser@arm.com // banks are closed - transition to PWR_IDLE 222611678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 222711678Swendy.elsasser@arm.com } 222811678Swendy.elsasser@arm.com} 222911678Swendy.elsasser@arm.com 223011678Swendy.elsasser@arm.comvoid 223110618SOmar.Naji@arm.comDRAMCtrl::Rank::processPowerEvent() 223210208Sandreas.hansson@arm.com{ 223311678Swendy.elsasser@arm.com assert(curTick() >= pwrStateTick); 223410208Sandreas.hansson@arm.com // remember where we were, and for how long 223510208Sandreas.hansson@arm.com Tick duration = curTick() - pwrStateTick; 223610208Sandreas.hansson@arm.com PowerState prev_state = pwrState; 223710208Sandreas.hansson@arm.com 223810208Sandreas.hansson@arm.com // update the accounting 223910208Sandreas.hansson@arm.com pwrStateTime[prev_state] += duration; 224010208Sandreas.hansson@arm.com 224111678Swendy.elsasser@arm.com // track to total idle time 224211678Swendy.elsasser@arm.com if ((prev_state == PWR_PRE_PDN) || (prev_state == PWR_ACT_PDN) || 224311678Swendy.elsasser@arm.com (prev_state == PWR_SREF)) { 224411678Swendy.elsasser@arm.com totalIdleTime += duration; 224511678Swendy.elsasser@arm.com } 224611678Swendy.elsasser@arm.com 224710208Sandreas.hansson@arm.com pwrState = pwrStateTrans; 224810208Sandreas.hansson@arm.com pwrStateTick = curTick(); 224910208Sandreas.hansson@arm.com 225011678Swendy.elsasser@arm.com // if rank was refreshing, make sure to start scheduling requests again 225111678Swendy.elsasser@arm.com if (prev_state == PWR_REF) { 225211678Swendy.elsasser@arm.com // bus IDLED prior to REF 225311678Swendy.elsasser@arm.com // counter should be one for refresh command only 225411678Swendy.elsasser@arm.com assert(outstandingEvents == 1); 225512705Swendy.elsasser@arm.com // REF complete, decrement count and go back to IDLE 225611678Swendy.elsasser@arm.com --outstandingEvents; 225712705Swendy.elsasser@arm.com refreshState = REF_IDLE; 225811678Swendy.elsasser@arm.com 225911678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 226012705Swendy.elsasser@arm.com // if moving back to power-down after refresh 226111678Swendy.elsasser@arm.com if (pwrState != PWR_IDLE) { 226212705Swendy.elsasser@arm.com assert(pwrState == PWR_PRE_PDN); 226311678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Switching to power down state after refreshing" 226411678Swendy.elsasser@arm.com " rank %d at %llu tick\n", rank, curTick()); 226511678Swendy.elsasser@arm.com } 226612705Swendy.elsasser@arm.com 226712705Swendy.elsasser@arm.com // completed refresh event, ensure next request is scheduled 226811678Swendy.elsasser@arm.com if (!memory.nextReqEvent.scheduled()) { 226912705Swendy.elsasser@arm.com DPRINTF(DRAM, "Scheduling next request after refreshing" 227012705Swendy.elsasser@arm.com " rank %d\n", rank); 227111678Swendy.elsasser@arm.com schedule(memory.nextReqEvent, curTick()); 227211678Swendy.elsasser@arm.com } 227312705Swendy.elsasser@arm.com } 227412705Swendy.elsasser@arm.com 227512705Swendy.elsasser@arm.com if ((pwrState == PWR_ACT) && (refreshState == REF_PD_EXIT)) { 227612705Swendy.elsasser@arm.com // have exited ACT PD 227712705Swendy.elsasser@arm.com assert(prev_state == PWR_ACT_PDN); 227812705Swendy.elsasser@arm.com 227912705Swendy.elsasser@arm.com // go back to REF event and close banks 228012705Swendy.elsasser@arm.com refreshState = REF_PRE; 228112705Swendy.elsasser@arm.com schedule(refreshEvent, curTick()); 228211678Swendy.elsasser@arm.com } else if (pwrState == PWR_IDLE) { 228310208Sandreas.hansson@arm.com DPRINTF(DRAMState, "All banks precharged\n"); 228411678Swendy.elsasser@arm.com if (prev_state == PWR_SREF) { 228512266Sradhika.jagtap@arm.com // set refresh state to REF_SREF_EXIT, ensuring inRefIdleState 228611678Swendy.elsasser@arm.com // continues to return false during tXS after SREF exit 228711678Swendy.elsasser@arm.com // Schedule a refresh which kicks things back into action 228811678Swendy.elsasser@arm.com // when it finishes 228911678Swendy.elsasser@arm.com refreshState = REF_SREF_EXIT; 229011678Swendy.elsasser@arm.com schedule(refreshEvent, curTick() + memory.tXS); 229110208Sandreas.hansson@arm.com } else { 229210208Sandreas.hansson@arm.com // if we have a pending refresh, and are now moving to 229312705Swendy.elsasser@arm.com // the idle state, directly transition to, or schedule refresh 229411678Swendy.elsasser@arm.com if ((refreshState == REF_PRE) || (refreshState == REF_PD_EXIT)) { 229511678Swendy.elsasser@arm.com // ensure refresh is restarted only after final PRE command. 229611678Swendy.elsasser@arm.com // do not restart refresh if controller is in an intermediate 229711678Swendy.elsasser@arm.com // state, after PRE_PDN exit, when banks are IDLE but an 229811678Swendy.elsasser@arm.com // ACT is scheduled. 229911678Swendy.elsasser@arm.com if (!activateEvent.scheduled()) { 230011678Swendy.elsasser@arm.com // there should be nothing waiting at this point 230111678Swendy.elsasser@arm.com assert(!powerEvent.scheduled()); 230212705Swendy.elsasser@arm.com if (refreshState == REF_PD_EXIT) { 230312705Swendy.elsasser@arm.com // exiting PRE PD, will be in IDLE until tXP expires 230412705Swendy.elsasser@arm.com // and then should transition to PWR_REF state 230512705Swendy.elsasser@arm.com assert(prev_state == PWR_PRE_PDN); 230612705Swendy.elsasser@arm.com schedulePowerEvent(PWR_REF, curTick() + memory.tXP); 230712705Swendy.elsasser@arm.com } else if (refreshState == REF_PRE) { 230812705Swendy.elsasser@arm.com // can directly move to PWR_REF state and proceed below 230912705Swendy.elsasser@arm.com pwrState = PWR_REF; 231012705Swendy.elsasser@arm.com } 231111678Swendy.elsasser@arm.com } else { 231211678Swendy.elsasser@arm.com // must have PRE scheduled to transition back to IDLE 231311678Swendy.elsasser@arm.com // and re-kick off refresh 231411678Swendy.elsasser@arm.com assert(prechargeEvent.scheduled()); 231511678Swendy.elsasser@arm.com } 231610208Sandreas.hansson@arm.com } 231712705Swendy.elsasser@arm.com } 231810208Sandreas.hansson@arm.com } 231910208Sandreas.hansson@arm.com 232012705Swendy.elsasser@arm.com // transition to the refresh state and re-start refresh process 232112705Swendy.elsasser@arm.com // refresh state machine will schedule the next power state transition 232210208Sandreas.hansson@arm.com if (pwrState == PWR_REF) { 232312705Swendy.elsasser@arm.com // completed final PRE for refresh or exiting power-down 232411678Swendy.elsasser@arm.com assert(refreshState == REF_PRE || refreshState == REF_PD_EXIT); 232512705Swendy.elsasser@arm.com 232612705Swendy.elsasser@arm.com // exited PRE PD for refresh, with no pending commands 232712705Swendy.elsasser@arm.com // bypass auto-refresh and go straight to SREF, where memory 232812705Swendy.elsasser@arm.com // will issue refresh immediately upon entry 232912705Swendy.elsasser@arm.com if (pwrStatePostRefresh == PWR_PRE_PDN && isQueueEmpty() && 233012705Swendy.elsasser@arm.com (memory.drainState() != DrainState::Draining) && 233112705Swendy.elsasser@arm.com (memory.drainState() != DrainState::Drained)) { 233212705Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d bypassing refresh and transitioning " 233312705Swendy.elsasser@arm.com "to self refresh at %11u tick\n", rank, curTick()); 233412705Swendy.elsasser@arm.com powerDownSleep(PWR_SREF, curTick()); 233512705Swendy.elsasser@arm.com 233612705Swendy.elsasser@arm.com // Since refresh was bypassed, remove event by decrementing count 233712705Swendy.elsasser@arm.com assert(outstandingEvents == 1); 233812705Swendy.elsasser@arm.com --outstandingEvents; 233912705Swendy.elsasser@arm.com 234012705Swendy.elsasser@arm.com // reset state back to IDLE temporarily until SREF is entered 234112705Swendy.elsasser@arm.com pwrState = PWR_IDLE; 234212705Swendy.elsasser@arm.com 234312705Swendy.elsasser@arm.com // Not bypassing refresh for SREF entry 234411678Swendy.elsasser@arm.com } else { 234512705Swendy.elsasser@arm.com DPRINTF(DRAMState, "Refreshing\n"); 234612705Swendy.elsasser@arm.com 234712705Swendy.elsasser@arm.com // there should be nothing waiting at this point 234812705Swendy.elsasser@arm.com assert(!powerEvent.scheduled()); 234912705Swendy.elsasser@arm.com 235012705Swendy.elsasser@arm.com // kick the refresh event loop into action again, and that 235112705Swendy.elsasser@arm.com // in turn will schedule a transition to the idle power 235212705Swendy.elsasser@arm.com // state once the refresh is done 235311678Swendy.elsasser@arm.com schedule(refreshEvent, curTick()); 235412705Swendy.elsasser@arm.com 235512705Swendy.elsasser@arm.com // Banks transitioned to IDLE, start REF 235612705Swendy.elsasser@arm.com refreshState = REF_START; 235711678Swendy.elsasser@arm.com } 235810207Sandreas.hansson@arm.com } 235912705Swendy.elsasser@arm.com 23609243SN/A} 23619243SN/A 23629243SN/Avoid 236310618SOmar.Naji@arm.comDRAMCtrl::Rank::updatePowerStats() 236410432SOmar.Naji@arm.com{ 236511676Swendy.elsasser@arm.com // All commands up to refresh have completed 236611676Swendy.elsasser@arm.com // flush cmdList to DRAMPower 236711676Swendy.elsasser@arm.com flushCmdList(); 236811676Swendy.elsasser@arm.com 236912266Sradhika.jagtap@arm.com // Call the function that calculates window energy at intermediate update 237012266Sradhika.jagtap@arm.com // events like at refresh, stats dump as well as at simulation exit. 237112266Sradhika.jagtap@arm.com // Window starts at the last time the calcWindowEnergy function was called 237212266Sradhika.jagtap@arm.com // and is upto current time. 237312266Sradhika.jagtap@arm.com power.powerlib.calcWindowEnergy(divCeil(curTick(), memory.tCK) - 237412266Sradhika.jagtap@arm.com memory.timeStampOffset); 237512266Sradhika.jagtap@arm.com 237612266Sradhika.jagtap@arm.com // Get the energy from DRAMPower 237712266Sradhika.jagtap@arm.com Data::MemoryPowerModel::Energy energy = power.powerlib.getEnergy(); 237812266Sradhika.jagtap@arm.com 237912266Sradhika.jagtap@arm.com // The energy components inside the power lib are calculated over 238012266Sradhika.jagtap@arm.com // the window so accumulate into the corresponding gem5 stat 238112266Sradhika.jagtap@arm.com actEnergy += energy.act_energy * memory.devicesPerRank; 238212266Sradhika.jagtap@arm.com preEnergy += energy.pre_energy * memory.devicesPerRank; 238312266Sradhika.jagtap@arm.com readEnergy += energy.read_energy * memory.devicesPerRank; 238412266Sradhika.jagtap@arm.com writeEnergy += energy.write_energy * memory.devicesPerRank; 238512266Sradhika.jagtap@arm.com refreshEnergy += energy.ref_energy * memory.devicesPerRank; 238612266Sradhika.jagtap@arm.com actBackEnergy += energy.act_stdby_energy * memory.devicesPerRank; 238712266Sradhika.jagtap@arm.com preBackEnergy += energy.pre_stdby_energy * memory.devicesPerRank; 238812266Sradhika.jagtap@arm.com actPowerDownEnergy += energy.f_act_pd_energy * memory.devicesPerRank; 238912266Sradhika.jagtap@arm.com prePowerDownEnergy += energy.f_pre_pd_energy * memory.devicesPerRank; 239012266Sradhika.jagtap@arm.com selfRefreshEnergy += energy.sref_energy * memory.devicesPerRank; 239112266Sradhika.jagtap@arm.com 239212266Sradhika.jagtap@arm.com // Accumulate window energy into the total energy. 239312266Sradhika.jagtap@arm.com totalEnergy += energy.window_energy * memory.devicesPerRank; 239412266Sradhika.jagtap@arm.com // Average power must not be accumulated but calculated over the time 239512266Sradhika.jagtap@arm.com // since last stats reset. SimClock::Frequency is tick period not tick 239612266Sradhika.jagtap@arm.com // frequency. 239712266Sradhika.jagtap@arm.com // energy (pJ) 1e-9 239812266Sradhika.jagtap@arm.com // power (mW) = ----------- * ---------- 239912266Sradhika.jagtap@arm.com // time (tick) tick_frequency 240012266Sradhika.jagtap@arm.com averagePower = (totalEnergy.value() / 240112266Sradhika.jagtap@arm.com (curTick() - memory.lastStatsResetTick)) * 240212266Sradhika.jagtap@arm.com (SimClock::Frequency / 1000000000.0); 240310432SOmar.Naji@arm.com} 240410432SOmar.Naji@arm.com 240510432SOmar.Naji@arm.comvoid 240611677Swendy.elsasser@arm.comDRAMCtrl::Rank::computeStats() 240711677Swendy.elsasser@arm.com{ 240812266Sradhika.jagtap@arm.com DPRINTF(DRAM,"Computing stats due to a dump callback\n"); 240911677Swendy.elsasser@arm.com 241011677Swendy.elsasser@arm.com // Update the stats 241111677Swendy.elsasser@arm.com updatePowerStats(); 241211677Swendy.elsasser@arm.com 241311677Swendy.elsasser@arm.com // final update of power state times 241411677Swendy.elsasser@arm.com pwrStateTime[pwrState] += (curTick() - pwrStateTick); 241511677Swendy.elsasser@arm.com pwrStateTick = curTick(); 241611677Swendy.elsasser@arm.com 241711677Swendy.elsasser@arm.com} 241811677Swendy.elsasser@arm.com 241911677Swendy.elsasser@arm.comvoid 242012266Sradhika.jagtap@arm.comDRAMCtrl::Rank::resetStats() { 242112266Sradhika.jagtap@arm.com // The only way to clear the counters in DRAMPower is to call 242212266Sradhika.jagtap@arm.com // calcWindowEnergy function as that then calls clearCounters. The 242312266Sradhika.jagtap@arm.com // clearCounters method itself is private. 242412266Sradhika.jagtap@arm.com power.powerlib.calcWindowEnergy(divCeil(curTick(), memory.tCK) - 242512266Sradhika.jagtap@arm.com memory.timeStampOffset); 242612266Sradhika.jagtap@arm.com 242712266Sradhika.jagtap@arm.com} 242812266Sradhika.jagtap@arm.com 242912266Sradhika.jagtap@arm.comvoid 243010618SOmar.Naji@arm.comDRAMCtrl::Rank::regStats() 243110618SOmar.Naji@arm.com{ 243210618SOmar.Naji@arm.com pwrStateTime 243311678Swendy.elsasser@arm.com .init(6) 243410618SOmar.Naji@arm.com .name(name() + ".memoryStateTime") 243510618SOmar.Naji@arm.com .desc("Time in different power states"); 243610618SOmar.Naji@arm.com pwrStateTime.subname(0, "IDLE"); 243710618SOmar.Naji@arm.com pwrStateTime.subname(1, "REF"); 243811678Swendy.elsasser@arm.com pwrStateTime.subname(2, "SREF"); 243911678Swendy.elsasser@arm.com pwrStateTime.subname(3, "PRE_PDN"); 244011678Swendy.elsasser@arm.com pwrStateTime.subname(4, "ACT"); 244111678Swendy.elsasser@arm.com pwrStateTime.subname(5, "ACT_PDN"); 244210618SOmar.Naji@arm.com 244310618SOmar.Naji@arm.com actEnergy 244410618SOmar.Naji@arm.com .name(name() + ".actEnergy") 244510618SOmar.Naji@arm.com .desc("Energy for activate commands per rank (pJ)"); 244610618SOmar.Naji@arm.com 244710618SOmar.Naji@arm.com preEnergy 244810618SOmar.Naji@arm.com .name(name() + ".preEnergy") 244910618SOmar.Naji@arm.com .desc("Energy for precharge commands per rank (pJ)"); 245010618SOmar.Naji@arm.com 245110618SOmar.Naji@arm.com readEnergy 245210618SOmar.Naji@arm.com .name(name() + ".readEnergy") 245310618SOmar.Naji@arm.com .desc("Energy for read commands per rank (pJ)"); 245410618SOmar.Naji@arm.com 245510618SOmar.Naji@arm.com writeEnergy 245610618SOmar.Naji@arm.com .name(name() + ".writeEnergy") 245710618SOmar.Naji@arm.com .desc("Energy for write commands per rank (pJ)"); 245810618SOmar.Naji@arm.com 245910618SOmar.Naji@arm.com refreshEnergy 246010618SOmar.Naji@arm.com .name(name() + ".refreshEnergy") 246110618SOmar.Naji@arm.com .desc("Energy for refresh commands per rank (pJ)"); 246210618SOmar.Naji@arm.com 246310618SOmar.Naji@arm.com actBackEnergy 246410618SOmar.Naji@arm.com .name(name() + ".actBackEnergy") 246510618SOmar.Naji@arm.com .desc("Energy for active background per rank (pJ)"); 246610618SOmar.Naji@arm.com 246710618SOmar.Naji@arm.com preBackEnergy 246810618SOmar.Naji@arm.com .name(name() + ".preBackEnergy") 246910618SOmar.Naji@arm.com .desc("Energy for precharge background per rank (pJ)"); 247010618SOmar.Naji@arm.com 247111678Swendy.elsasser@arm.com actPowerDownEnergy 247211678Swendy.elsasser@arm.com .name(name() + ".actPowerDownEnergy") 247311678Swendy.elsasser@arm.com .desc("Energy for active power-down per rank (pJ)"); 247411678Swendy.elsasser@arm.com 247511678Swendy.elsasser@arm.com prePowerDownEnergy 247611678Swendy.elsasser@arm.com .name(name() + ".prePowerDownEnergy") 247711678Swendy.elsasser@arm.com .desc("Energy for precharge power-down per rank (pJ)"); 247811678Swendy.elsasser@arm.com 247911678Swendy.elsasser@arm.com selfRefreshEnergy 248011678Swendy.elsasser@arm.com .name(name() + ".selfRefreshEnergy") 248111678Swendy.elsasser@arm.com .desc("Energy for self refresh per rank (pJ)"); 248211678Swendy.elsasser@arm.com 248310618SOmar.Naji@arm.com totalEnergy 248410618SOmar.Naji@arm.com .name(name() + ".totalEnergy") 248510618SOmar.Naji@arm.com .desc("Total energy per rank (pJ)"); 248610618SOmar.Naji@arm.com 248710618SOmar.Naji@arm.com averagePower 248810618SOmar.Naji@arm.com .name(name() + ".averagePower") 248910618SOmar.Naji@arm.com .desc("Core power per rank (mW)"); 249011677Swendy.elsasser@arm.com 249111678Swendy.elsasser@arm.com totalIdleTime 249211678Swendy.elsasser@arm.com .name(name() + ".totalIdleTime") 249311678Swendy.elsasser@arm.com .desc("Total Idle time Per DRAM Rank"); 249411678Swendy.elsasser@arm.com 249512637Sodanrc@yahoo.com.br Stats::registerDumpCallback(new RankDumpCallback(this)); 249612637Sodanrc@yahoo.com.br Stats::registerResetCallback(new RankResetCallback(this)); 249710618SOmar.Naji@arm.com} 249810618SOmar.Naji@arm.comvoid 249910146Sandreas.hansson@arm.comDRAMCtrl::regStats() 25009243SN/A{ 25019243SN/A using namespace Stats; 25029243SN/A 250312969SMatteo.Andreozzi@arm.com MemCtrl::regStats(); 25049243SN/A 250510618SOmar.Naji@arm.com for (auto r : ranks) { 250610618SOmar.Naji@arm.com r->regStats(); 250710618SOmar.Naji@arm.com } 250810618SOmar.Naji@arm.com 250912266Sradhika.jagtap@arm.com registerResetCallback(new MemResetCallback(this)); 251012266Sradhika.jagtap@arm.com 25119243SN/A readReqs 25129243SN/A .name(name() + ".readReqs") 25139977SN/A .desc("Number of read requests accepted"); 25149243SN/A 25159243SN/A writeReqs 25169243SN/A .name(name() + ".writeReqs") 25179977SN/A .desc("Number of write requests accepted"); 25189831SN/A 25199831SN/A readBursts 25209831SN/A .name(name() + ".readBursts") 25219977SN/A .desc("Number of DRAM read bursts, " 25229977SN/A "including those serviced by the write queue"); 25239831SN/A 25249831SN/A writeBursts 25259831SN/A .name(name() + ".writeBursts") 25269977SN/A .desc("Number of DRAM write bursts, " 25279977SN/A "including those merged in the write queue"); 25289243SN/A 25299243SN/A servicedByWrQ 25309243SN/A .name(name() + ".servicedByWrQ") 25319977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 25329977SN/A 25339977SN/A mergedWrBursts 25349977SN/A .name(name() + ".mergedWrBursts") 25359977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 25369243SN/A 25379243SN/A neitherReadNorWrite 25389977SN/A .name(name() + ".neitherReadNorWriteReqs") 25399977SN/A .desc("Number of requests that are neither read nor write"); 25409243SN/A 25419977SN/A perBankRdBursts 25429243SN/A .init(banksPerRank * ranksPerChannel) 25439977SN/A .name(name() + ".perBankRdBursts") 25449977SN/A .desc("Per bank write bursts"); 25459243SN/A 25469977SN/A perBankWrBursts 25479243SN/A .init(banksPerRank * ranksPerChannel) 25489977SN/A .name(name() + ".perBankWrBursts") 25499977SN/A .desc("Per bank write bursts"); 25509243SN/A 25519243SN/A avgRdQLen 25529243SN/A .name(name() + ".avgRdQLen") 25539977SN/A .desc("Average read queue length when enqueuing") 25549243SN/A .precision(2); 25559243SN/A 25569243SN/A avgWrQLen 25579243SN/A .name(name() + ".avgWrQLen") 25589977SN/A .desc("Average write queue length when enqueuing") 25599243SN/A .precision(2); 25609243SN/A 25619243SN/A totQLat 25629243SN/A .name(name() + ".totQLat") 25639977SN/A .desc("Total ticks spent queuing"); 25649243SN/A 25659243SN/A totBusLat 25669243SN/A .name(name() + ".totBusLat") 25679977SN/A .desc("Total ticks spent in databus transfers"); 25689243SN/A 25699243SN/A totMemAccLat 25709243SN/A .name(name() + ".totMemAccLat") 25719977SN/A .desc("Total ticks spent from burst creation until serviced " 25729977SN/A "by the DRAM"); 25739243SN/A 25749243SN/A avgQLat 25759243SN/A .name(name() + ".avgQLat") 25769977SN/A .desc("Average queueing delay per DRAM burst") 25779243SN/A .precision(2); 25789243SN/A 25799831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 25809243SN/A 25819243SN/A avgBusLat 25829243SN/A .name(name() + ".avgBusLat") 25839977SN/A .desc("Average bus latency per DRAM burst") 25849243SN/A .precision(2); 25859243SN/A 25869831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 25879243SN/A 25889243SN/A avgMemAccLat 25899243SN/A .name(name() + ".avgMemAccLat") 25909977SN/A .desc("Average memory access latency per DRAM burst") 25919243SN/A .precision(2); 25929243SN/A 25939831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 25949243SN/A 25959243SN/A numRdRetry 25969243SN/A .name(name() + ".numRdRetry") 25979977SN/A .desc("Number of times read queue was full causing retry"); 25989243SN/A 25999243SN/A numWrRetry 26009243SN/A .name(name() + ".numWrRetry") 26019977SN/A .desc("Number of times write queue was full causing retry"); 26029243SN/A 26039243SN/A readRowHits 26049243SN/A .name(name() + ".readRowHits") 26059243SN/A .desc("Number of row buffer hits during reads"); 26069243SN/A 26079243SN/A writeRowHits 26089243SN/A .name(name() + ".writeRowHits") 26099243SN/A .desc("Number of row buffer hits during writes"); 26109243SN/A 26119243SN/A readRowHitRate 26129243SN/A .name(name() + ".readRowHitRate") 26139243SN/A .desc("Row buffer hit rate for reads") 26149243SN/A .precision(2); 26159243SN/A 26169831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 26179243SN/A 26189243SN/A writeRowHitRate 26199243SN/A .name(name() + ".writeRowHitRate") 26209243SN/A .desc("Row buffer hit rate for writes") 26219243SN/A .precision(2); 26229243SN/A 26239977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 26249243SN/A 26259243SN/A readPktSize 26269831SN/A .init(ceilLog2(burstSize) + 1) 26279243SN/A .name(name() + ".readPktSize") 26289977SN/A .desc("Read request sizes (log2)"); 26299243SN/A 26309243SN/A writePktSize 26319831SN/A .init(ceilLog2(burstSize) + 1) 26329243SN/A .name(name() + ".writePktSize") 26339977SN/A .desc("Write request sizes (log2)"); 26349243SN/A 26359243SN/A rdQLenPdf 26369567SN/A .init(readBufferSize) 26379243SN/A .name(name() + ".rdQLenPdf") 26389243SN/A .desc("What read queue length does an incoming req see"); 26399243SN/A 26409243SN/A wrQLenPdf 26419567SN/A .init(writeBufferSize) 26429243SN/A .name(name() + ".wrQLenPdf") 26439243SN/A .desc("What write queue length does an incoming req see"); 26449243SN/A 26459727SN/A bytesPerActivate 264612969SMatteo.Andreozzi@arm.com .init(maxAccessesPerRow ? maxAccessesPerRow : rowBufferSize) 26479727SN/A .name(name() + ".bytesPerActivate") 26489727SN/A .desc("Bytes accessed per row activation") 26499727SN/A .flags(nozero); 26509243SN/A 265110147Sandreas.hansson@arm.com rdPerTurnAround 265210147Sandreas.hansson@arm.com .init(readBufferSize) 265310147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 265410147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 265510147Sandreas.hansson@arm.com .flags(nozero); 265610147Sandreas.hansson@arm.com 265710147Sandreas.hansson@arm.com wrPerTurnAround 265810147Sandreas.hansson@arm.com .init(writeBufferSize) 265910147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 266010147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 266110147Sandreas.hansson@arm.com .flags(nozero); 266210147Sandreas.hansson@arm.com 26639975SN/A bytesReadDRAM 26649975SN/A .name(name() + ".bytesReadDRAM") 26659975SN/A .desc("Total number of bytes read from DRAM"); 26669975SN/A 26679975SN/A bytesReadWrQ 26689975SN/A .name(name() + ".bytesReadWrQ") 26699975SN/A .desc("Total number of bytes read from write queue"); 26709243SN/A 26719243SN/A bytesWritten 26729243SN/A .name(name() + ".bytesWritten") 26739977SN/A .desc("Total number of bytes written to DRAM"); 26749243SN/A 26759977SN/A bytesReadSys 26769977SN/A .name(name() + ".bytesReadSys") 26779977SN/A .desc("Total read bytes from the system interface side"); 26789243SN/A 26799977SN/A bytesWrittenSys 26809977SN/A .name(name() + ".bytesWrittenSys") 26819977SN/A .desc("Total written bytes from the system interface side"); 26829243SN/A 26839243SN/A avgRdBW 26849243SN/A .name(name() + ".avgRdBW") 26859977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 26869243SN/A .precision(2); 26879243SN/A 26889977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 26899243SN/A 26909243SN/A avgWrBW 26919243SN/A .name(name() + ".avgWrBW") 26929977SN/A .desc("Average achieved write bandwidth in MiByte/s") 26939243SN/A .precision(2); 26949243SN/A 26959243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 26969243SN/A 26979977SN/A avgRdBWSys 26989977SN/A .name(name() + ".avgRdBWSys") 26999977SN/A .desc("Average system read bandwidth in MiByte/s") 27009243SN/A .precision(2); 27019243SN/A 27029977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 27039243SN/A 27049977SN/A avgWrBWSys 27059977SN/A .name(name() + ".avgWrBWSys") 27069977SN/A .desc("Average system write bandwidth in MiByte/s") 27079243SN/A .precision(2); 27089243SN/A 27099977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 27109243SN/A 27119243SN/A peakBW 27129243SN/A .name(name() + ".peakBW") 27139977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 27149243SN/A .precision(2); 27159243SN/A 27169831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 27179243SN/A 27189243SN/A busUtil 27199243SN/A .name(name() + ".busUtil") 27209243SN/A .desc("Data bus utilization in percentage") 27219243SN/A .precision(2); 27229243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 27239243SN/A 27249243SN/A totGap 27259243SN/A .name(name() + ".totGap") 27269243SN/A .desc("Total gap between requests"); 27279243SN/A 27289243SN/A avgGap 27299243SN/A .name(name() + ".avgGap") 27309243SN/A .desc("Average gap between requests") 27319243SN/A .precision(2); 27329243SN/A 27339243SN/A avgGap = totGap / (readReqs + writeReqs); 27349975SN/A 27359975SN/A // Stats for DRAM Power calculation based on Micron datasheet 27369975SN/A busUtilRead 27379975SN/A .name(name() + ".busUtilRead") 27389975SN/A .desc("Data bus utilization in percentage for reads") 27399975SN/A .precision(2); 27409975SN/A 27419975SN/A busUtilRead = avgRdBW / peakBW * 100; 27429975SN/A 27439975SN/A busUtilWrite 27449975SN/A .name(name() + ".busUtilWrite") 27459975SN/A .desc("Data bus utilization in percentage for writes") 27469975SN/A .precision(2); 27479975SN/A 27489975SN/A busUtilWrite = avgWrBW / peakBW * 100; 27499975SN/A 27509975SN/A pageHitRate 27519975SN/A .name(name() + ".pageHitRate") 27529975SN/A .desc("Row buffer hit rate, read and write combined") 27539975SN/A .precision(2); 27549975SN/A 27559977SN/A pageHitRate = (writeRowHits + readRowHits) / 27569977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 275712969SMatteo.Andreozzi@arm.com 275812969SMatteo.Andreozzi@arm.com // per-master bytes read and written to memory 275912969SMatteo.Andreozzi@arm.com masterReadBytes 276012969SMatteo.Andreozzi@arm.com .init(_system->maxMasters()) 276112969SMatteo.Andreozzi@arm.com .name(name() + ".masterReadBytes") 276212969SMatteo.Andreozzi@arm.com .desc("Per-master bytes read from memory") 276312969SMatteo.Andreozzi@arm.com .flags(nozero | nonan); 276412969SMatteo.Andreozzi@arm.com 276512969SMatteo.Andreozzi@arm.com masterWriteBytes 276612969SMatteo.Andreozzi@arm.com .init(_system->maxMasters()) 276712969SMatteo.Andreozzi@arm.com .name(name() + ".masterWriteBytes") 276812969SMatteo.Andreozzi@arm.com .desc("Per-master bytes write to memory") 276912969SMatteo.Andreozzi@arm.com .flags(nozero | nonan); 277012969SMatteo.Andreozzi@arm.com 277112969SMatteo.Andreozzi@arm.com // per-master bytes read and written to memory rate 277212969SMatteo.Andreozzi@arm.com masterReadRate.name(name() + ".masterReadRate") 277312969SMatteo.Andreozzi@arm.com .desc("Per-master bytes read from memory rate (Bytes/sec)") 277412969SMatteo.Andreozzi@arm.com .flags(nozero | nonan) 277512969SMatteo.Andreozzi@arm.com .precision(12); 277612969SMatteo.Andreozzi@arm.com 277712969SMatteo.Andreozzi@arm.com masterReadRate = masterReadBytes/simSeconds; 277812969SMatteo.Andreozzi@arm.com 277912969SMatteo.Andreozzi@arm.com masterWriteRate 278012969SMatteo.Andreozzi@arm.com .name(name() + ".masterWriteRate") 278112969SMatteo.Andreozzi@arm.com .desc("Per-master bytes write to memory rate (Bytes/sec)") 278212969SMatteo.Andreozzi@arm.com .flags(nozero | nonan) 278312969SMatteo.Andreozzi@arm.com .precision(12); 278412969SMatteo.Andreozzi@arm.com 278512969SMatteo.Andreozzi@arm.com masterWriteRate = masterWriteBytes/simSeconds; 278612969SMatteo.Andreozzi@arm.com 278712969SMatteo.Andreozzi@arm.com masterReadAccesses 278812969SMatteo.Andreozzi@arm.com .init(_system->maxMasters()) 278912969SMatteo.Andreozzi@arm.com .name(name() + ".masterReadAccesses") 279012969SMatteo.Andreozzi@arm.com .desc("Per-master read serviced memory accesses") 279112969SMatteo.Andreozzi@arm.com .flags(nozero); 279212969SMatteo.Andreozzi@arm.com 279312969SMatteo.Andreozzi@arm.com masterWriteAccesses 279412969SMatteo.Andreozzi@arm.com .init(_system->maxMasters()) 279512969SMatteo.Andreozzi@arm.com .name(name() + ".masterWriteAccesses") 279612969SMatteo.Andreozzi@arm.com .desc("Per-master write serviced memory accesses") 279712969SMatteo.Andreozzi@arm.com .flags(nozero); 279812969SMatteo.Andreozzi@arm.com 279912969SMatteo.Andreozzi@arm.com 280012969SMatteo.Andreozzi@arm.com masterReadTotalLat 280112969SMatteo.Andreozzi@arm.com .init(_system->maxMasters()) 280212969SMatteo.Andreozzi@arm.com .name(name() + ".masterReadTotalLat") 280312969SMatteo.Andreozzi@arm.com .desc("Per-master read total memory access latency") 280412969SMatteo.Andreozzi@arm.com .flags(nozero | nonan); 280512969SMatteo.Andreozzi@arm.com 280612969SMatteo.Andreozzi@arm.com masterReadAvgLat.name(name() + ".masterReadAvgLat") 280712969SMatteo.Andreozzi@arm.com .desc("Per-master read average memory access latency") 280812969SMatteo.Andreozzi@arm.com .flags(nonan) 280912969SMatteo.Andreozzi@arm.com .precision(2); 281012969SMatteo.Andreozzi@arm.com 281112969SMatteo.Andreozzi@arm.com masterReadAvgLat = masterReadTotalLat/masterReadAccesses; 281212969SMatteo.Andreozzi@arm.com 281312969SMatteo.Andreozzi@arm.com masterWriteTotalLat 281412969SMatteo.Andreozzi@arm.com .init(_system->maxMasters()) 281512969SMatteo.Andreozzi@arm.com .name(name() + ".masterWriteTotalLat") 281612969SMatteo.Andreozzi@arm.com .desc("Per-master write total memory access latency") 281712969SMatteo.Andreozzi@arm.com .flags(nozero | nonan); 281812969SMatteo.Andreozzi@arm.com 281912969SMatteo.Andreozzi@arm.com masterWriteAvgLat.name(name() + ".masterWriteAvgLat") 282012969SMatteo.Andreozzi@arm.com .desc("Per-master write average memory access latency") 282112969SMatteo.Andreozzi@arm.com .flags(nonan) 282212969SMatteo.Andreozzi@arm.com .precision(2); 282312969SMatteo.Andreozzi@arm.com 282412969SMatteo.Andreozzi@arm.com masterWriteAvgLat = masterWriteTotalLat/masterWriteAccesses; 282512969SMatteo.Andreozzi@arm.com 282612969SMatteo.Andreozzi@arm.com for (int i = 0; i < _system->maxMasters(); i++) { 282712969SMatteo.Andreozzi@arm.com const std::string master = _system->getMasterName(i); 282812969SMatteo.Andreozzi@arm.com masterReadBytes.subname(i, master); 282912969SMatteo.Andreozzi@arm.com masterReadRate.subname(i, master); 283012969SMatteo.Andreozzi@arm.com masterWriteBytes.subname(i, master); 283112969SMatteo.Andreozzi@arm.com masterWriteRate.subname(i, master); 283212969SMatteo.Andreozzi@arm.com masterReadAccesses.subname(i, master); 283312969SMatteo.Andreozzi@arm.com masterWriteAccesses.subname(i, master); 283412969SMatteo.Andreozzi@arm.com masterReadTotalLat.subname(i, master); 283512969SMatteo.Andreozzi@arm.com masterReadAvgLat.subname(i, master); 283612969SMatteo.Andreozzi@arm.com masterWriteTotalLat.subname(i, master); 283712969SMatteo.Andreozzi@arm.com masterWriteAvgLat.subname(i, master); 283812969SMatteo.Andreozzi@arm.com } 28399243SN/A} 28409243SN/A 28419243SN/Avoid 284210146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 28439243SN/A{ 28449243SN/A // rely on the abstract memory 28459243SN/A functionalAccess(pkt); 28469243SN/A} 28479243SN/A 284813784Sgabeblack@google.comPort & 284913784Sgabeblack@google.comDRAMCtrl::getPort(const string &if_name, PortID idx) 28509243SN/A{ 28519243SN/A if (if_name != "port") { 285213784Sgabeblack@google.com return MemObject::getPort(if_name, idx); 28539243SN/A } else { 28549243SN/A return port; 28559243SN/A } 28569243SN/A} 28579243SN/A 285810913Sandreas.sandberg@arm.comDrainState 285910913Sandreas.sandberg@arm.comDRAMCtrl::drain() 28609243SN/A{ 28619243SN/A // if there is anything in any of our internal queues, keep track 28629243SN/A // of that as well 286312969SMatteo.Andreozzi@arm.com if (!(!totalWriteQueueSize && !totalReadQueueSize && respQueue.empty() && 286411676Swendy.elsasser@arm.com allRanksDrained())) { 286511676Swendy.elsasser@arm.com 28669352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 286712969SMatteo.Andreozzi@arm.com " resp: %d\n", totalWriteQueueSize, totalReadQueueSize, 28689567SN/A respQueue.size()); 286910206Sandreas.hansson@arm.com 287011678Swendy.elsasser@arm.com // the only queue that is not drained automatically over time 287110206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 287212969SMatteo.Andreozzi@arm.com if (!totalWriteQueueSize && !nextReqEvent.scheduled()) { 287310206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 287410206Sandreas.hansson@arm.com } 287511678Swendy.elsasser@arm.com 287611678Swendy.elsasser@arm.com // also need to kick off events to exit self-refresh 287711678Swendy.elsasser@arm.com for (auto r : ranks) { 287811678Swendy.elsasser@arm.com // force self-refresh exit, which in turn will issue auto-refresh 287911678Swendy.elsasser@arm.com if (r->pwrState == PWR_SREF) { 288011678Swendy.elsasser@arm.com DPRINTF(DRAM,"Rank%d: Forcing self-refresh wakeup in drain\n", 288111678Swendy.elsasser@arm.com r->rank); 288211678Swendy.elsasser@arm.com r->scheduleWakeUpEvent(tXS); 288311678Swendy.elsasser@arm.com } 288411678Swendy.elsasser@arm.com } 288511678Swendy.elsasser@arm.com 288610913Sandreas.sandberg@arm.com return DrainState::Draining; 288710912Sandreas.sandberg@arm.com } else { 288810913Sandreas.sandberg@arm.com return DrainState::Drained; 28899243SN/A } 28909243SN/A} 28919243SN/A 289211676Swendy.elsasser@arm.combool 289311676Swendy.elsasser@arm.comDRAMCtrl::allRanksDrained() const 289411676Swendy.elsasser@arm.com{ 289511676Swendy.elsasser@arm.com // true until proven false 289611676Swendy.elsasser@arm.com bool all_ranks_drained = true; 289711676Swendy.elsasser@arm.com for (auto r : ranks) { 289812266Sradhika.jagtap@arm.com // then verify that the power state is IDLE ensuring all banks are 289912266Sradhika.jagtap@arm.com // closed and rank is not in a low power state. Also verify that rank 290012266Sradhika.jagtap@arm.com // is idle from a refresh point of view. 290112266Sradhika.jagtap@arm.com all_ranks_drained = r->inPwrIdleState() && r->inRefIdleState() && 290212266Sradhika.jagtap@arm.com all_ranks_drained; 290311676Swendy.elsasser@arm.com } 290411676Swendy.elsasser@arm.com return all_ranks_drained; 290511676Swendy.elsasser@arm.com} 290611676Swendy.elsasser@arm.com 290710619Sandreas.hansson@arm.comvoid 290810619Sandreas.hansson@arm.comDRAMCtrl::drainResume() 290910619Sandreas.hansson@arm.com{ 291010619Sandreas.hansson@arm.com if (!isTimingMode && system()->isTimingMode()) { 291110619Sandreas.hansson@arm.com // if we switched to timing mode, kick things into action, 291210619Sandreas.hansson@arm.com // and behave as if we restored from a checkpoint 291310619Sandreas.hansson@arm.com startup(); 291410619Sandreas.hansson@arm.com } else if (isTimingMode && !system()->isTimingMode()) { 291510619Sandreas.hansson@arm.com // if we switch from timing mode, stop the refresh events to 291610619Sandreas.hansson@arm.com // not cause issues with KVM 291710619Sandreas.hansson@arm.com for (auto r : ranks) { 291810619Sandreas.hansson@arm.com r->suspend(); 291910619Sandreas.hansson@arm.com } 292010619Sandreas.hansson@arm.com } 292110619Sandreas.hansson@arm.com 292210619Sandreas.hansson@arm.com // update the mode 292310619Sandreas.hansson@arm.com isTimingMode = system()->isTimingMode(); 292410619Sandreas.hansson@arm.com} 292510619Sandreas.hansson@arm.com 292610146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 292713564Snikos.nikoleris@arm.com : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this, true), 29289243SN/A memory(_memory) 29299243SN/A{ } 29309243SN/A 29319243SN/AAddrRangeList 293210146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 29339243SN/A{ 29349243SN/A AddrRangeList ranges; 29359243SN/A ranges.push_back(memory.getAddrRange()); 29369243SN/A return ranges; 29379243SN/A} 29389243SN/A 29399243SN/Avoid 294010146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 29419243SN/A{ 29429243SN/A pkt->pushLabel(memory.name()); 29439243SN/A 294412823Srmk35@cl.cam.ac.uk if (!queue.trySatisfyFunctional(pkt)) { 29459243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 29469243SN/A // calls recvAtomic() and throws away the latency; we can save a 29479243SN/A // little here by just not calculating the latency. 29489243SN/A memory.recvFunctional(pkt); 29499243SN/A } 29509243SN/A 29519243SN/A pkt->popLabel(); 29529243SN/A} 29539243SN/A 29549243SN/ATick 295510146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 29569243SN/A{ 29579243SN/A return memory.recvAtomic(pkt); 29589243SN/A} 29599243SN/A 29609243SN/Abool 296110146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 29629243SN/A{ 29639243SN/A // pass it to the memory controller 29649243SN/A return memory.recvTimingReq(pkt); 29659243SN/A} 29669243SN/A 296710146Sandreas.hansson@arm.comDRAMCtrl* 296810146Sandreas.hansson@arm.comDRAMCtrlParams::create() 29699243SN/A{ 297010146Sandreas.hansson@arm.com return new DRAMCtrl(this); 29719243SN/A} 2972