dram_ctrl.cc revision 12637
19243SN/A/* 211846Swendy.elsasser@arm.com * Copyright (c) 2010-2017 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 4310618SOmar.Naji@arm.com * Omar Naji 4411678Swendy.elsasser@arm.com * Wendy Elsasser 4512266Sradhika.jagtap@arm.com * Radhika Jagtap 469243SN/A */ 479243SN/A 4811793Sbrandon.potter@amd.com#include "mem/dram_ctrl.hh" 4911793Sbrandon.potter@amd.com 5010146Sandreas.hansson@arm.com#include "base/bitfield.hh" 519356SN/A#include "base/trace.hh" 5210146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 5310247Sandreas.hansson@arm.com#include "debug/DRAMPower.hh" 5410208Sandreas.hansson@arm.com#include "debug/DRAMState.hh" 559352SN/A#include "debug/Drain.hh" 569814SN/A#include "sim/system.hh" 579243SN/A 589243SN/Ausing namespace std; 5910432SOmar.Naji@arm.comusing namespace Data; 609243SN/A 6110146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 629243SN/A AbstractMemory(p), 6310619Sandreas.hansson@arm.com port(name() + ".port", *this), isTimingMode(false), 649243SN/A retryRdReq(false), retryWrReq(false), 6510211Sandreas.hansson@arm.com busState(READ), 6611678Swendy.elsasser@arm.com busStateNext(READ), 6712084Sspwilson2@wisc.edu nextReqEvent([this]{ processNextReqEvent(); }, name()), 6812084Sspwilson2@wisc.edu respondEvent([this]{ processRespondEvent(); }, name()), 6910489SOmar.Naji@arm.com deviceSize(p->device_size), 709831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 719831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 729831SN/A devicesPerRank(p->devices_per_rank), 739831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 749831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 7510140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 7610646Sandreas.hansson@arm.com columnsPerStripe(range.interleaved() ? range.granularity() / burstSize : 1), 779243SN/A ranksPerChannel(p->ranks_per_channel), 7810394Swendy.elsasser@arm.com bankGroupsPerRank(p->bank_groups_per_rank), 7910394Swendy.elsasser@arm.com bankGroupArch(p->bank_groups_per_rank > 0), 809566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 819243SN/A readBufferSize(p->read_buffer_size), 829243SN/A writeBufferSize(p->write_buffer_size), 8310140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 8410140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 8510147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 8610147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 8710393Swendy.elsasser@arm.com tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST), 8810394Swendy.elsasser@arm.com tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), 8910394Swendy.elsasser@arm.com tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 9011673SOmar.Naji@arm.com tRRD_L(p->tRRD_L), tXAW(p->tXAW), tXP(p->tXP), tXS(p->tXS), 9111673SOmar.Naji@arm.com activationLimit(p->activation_limit), 929243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 939243SN/A pageMgmt(p->page_policy), 9410141SN/A maxAccessesPerRow(p->max_accesses_per_row), 959726SN/A frontendLatency(p->static_frontend_latency), 969726SN/A backendLatency(p->static_backend_latency), 9710618SOmar.Naji@arm.com busBusyUntil(0), prevArrival(0), 9812266Sradhika.jagtap@arm.com nextReqTime(0), activeRank(0), timeStampOffset(0), 9912266Sradhika.jagtap@arm.com lastStatsResetTick(0) 1009243SN/A{ 10110620Sandreas.hansson@arm.com // sanity check the ranks since we rely on bit slicing for the 10210620Sandreas.hansson@arm.com // address decoding 10310620Sandreas.hansson@arm.com fatal_if(!isPowerOf2(ranksPerChannel), "DRAM rank count of %d is not " 10410620Sandreas.hansson@arm.com "allowed, must be a power of two\n", ranksPerChannel); 10510620Sandreas.hansson@arm.com 10610889Sandreas.hansson@arm.com fatal_if(!isPowerOf2(burstSize), "DRAM burst size %d is not allowed, " 10710889Sandreas.hansson@arm.com "must be a power of two\n", burstSize); 10810889Sandreas.hansson@arm.com 10910618SOmar.Naji@arm.com for (int i = 0; i < ranksPerChannel; i++) { 11012081Sspwilson2@wisc.edu Rank* rank = new Rank(*this, p, i); 11110618SOmar.Naji@arm.com ranks.push_back(rank); 11210246Sandreas.hansson@arm.com } 11310246Sandreas.hansson@arm.com 11410140SN/A // perform a basic check of the write thresholds 11510140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 11610140SN/A fatal("Write buffer low threshold %d must be smaller than the " 11710140SN/A "high threshold %d\n", p->write_low_thresh_perc, 11810140SN/A p->write_high_thresh_perc); 1199243SN/A 1209243SN/A // determine the rows per bank by looking at the total capacity 1219567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1229243SN/A 12310489SOmar.Naji@arm.com // determine the dram actual capacity from the DRAM config in Mbytes 12410489SOmar.Naji@arm.com uint64_t deviceCapacity = deviceSize / (1024 * 1024) * devicesPerRank * 12510489SOmar.Naji@arm.com ranksPerChannel; 12610489SOmar.Naji@arm.com 12710489SOmar.Naji@arm.com // if actual DRAM size does not match memory capacity in system warn! 12810489SOmar.Naji@arm.com if (deviceCapacity != capacity / (1024 * 1024)) 12910489SOmar.Naji@arm.com warn("DRAM device capacity (%d Mbytes) does not match the " 13010489SOmar.Naji@arm.com "address range assigned (%d Mbytes)\n", deviceCapacity, 13110489SOmar.Naji@arm.com capacity / (1024 * 1024)); 13210489SOmar.Naji@arm.com 1339243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1349243SN/A AbstractMemory::size()); 1359831SN/A 1369831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1379831SN/A rowBufferSize, columnsPerRowBuffer); 1389831SN/A 1399831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1409243SN/A 14110207Sandreas.hansson@arm.com // some basic sanity checks 14210207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 14310207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 14410207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 14510207Sandreas.hansson@arm.com } 14610394Swendy.elsasser@arm.com 14710394Swendy.elsasser@arm.com // basic bank group architecture checks -> 14810394Swendy.elsasser@arm.com if (bankGroupArch) { 14910394Swendy.elsasser@arm.com // must have at least one bank per bank group 15010394Swendy.elsasser@arm.com if (bankGroupsPerRank > banksPerRank) { 15110394Swendy.elsasser@arm.com fatal("banks per rank (%d) must be equal to or larger than " 15210394Swendy.elsasser@arm.com "banks groups per rank (%d)\n", 15310394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 15410394Swendy.elsasser@arm.com } 15510394Swendy.elsasser@arm.com // must have same number of banks in each bank group 15610394Swendy.elsasser@arm.com if ((banksPerRank % bankGroupsPerRank) != 0) { 15710394Swendy.elsasser@arm.com fatal("Banks per rank (%d) must be evenly divisible by bank groups " 15810394Swendy.elsasser@arm.com "per rank (%d) for equal banks per bank group\n", 15910394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 16010394Swendy.elsasser@arm.com } 16110394Swendy.elsasser@arm.com // tCCD_L should be greater than minimal, back-to-back burst delay 16210394Swendy.elsasser@arm.com if (tCCD_L <= tBURST) { 16310394Swendy.elsasser@arm.com fatal("tCCD_L (%d) should be larger than tBURST (%d) when " 16410394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 16510394Swendy.elsasser@arm.com tCCD_L, tBURST, bankGroupsPerRank); 16610394Swendy.elsasser@arm.com } 16710394Swendy.elsasser@arm.com // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay 16810561SOmar.Naji@arm.com // some datasheets might specify it equal to tRRD 16910561SOmar.Naji@arm.com if (tRRD_L < tRRD) { 17010394Swendy.elsasser@arm.com fatal("tRRD_L (%d) should be larger than tRRD (%d) when " 17110394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 17210394Swendy.elsasser@arm.com tRRD_L, tRRD, bankGroupsPerRank); 17310394Swendy.elsasser@arm.com } 17410394Swendy.elsasser@arm.com } 17510394Swendy.elsasser@arm.com 1769243SN/A} 1779243SN/A 1789243SN/Avoid 17910146Sandreas.hansson@arm.comDRAMCtrl::init() 18010140SN/A{ 18110466Sandreas.hansson@arm.com AbstractMemory::init(); 18210466Sandreas.hansson@arm.com 18310466Sandreas.hansson@arm.com if (!port.isConnected()) { 18410146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 18510140SN/A } else { 18610140SN/A port.sendRangeChange(); 18710140SN/A } 18810646Sandreas.hansson@arm.com 18910646Sandreas.hansson@arm.com // a bit of sanity checks on the interleaving, save it for here to 19010646Sandreas.hansson@arm.com // ensure that the system pointer is initialised 19110646Sandreas.hansson@arm.com if (range.interleaved()) { 19210646Sandreas.hansson@arm.com if (channels != range.stripes()) 19310646Sandreas.hansson@arm.com fatal("%s has %d interleaved address stripes but %d channel(s)\n", 19410646Sandreas.hansson@arm.com name(), range.stripes(), channels); 19510646Sandreas.hansson@arm.com 19610646Sandreas.hansson@arm.com if (addrMapping == Enums::RoRaBaChCo) { 19710646Sandreas.hansson@arm.com if (rowBufferSize != range.granularity()) { 19810646Sandreas.hansson@arm.com fatal("Channel interleaving of %s doesn't match RoRaBaChCo " 19910646Sandreas.hansson@arm.com "address map\n", name()); 20010646Sandreas.hansson@arm.com } 20110646Sandreas.hansson@arm.com } else if (addrMapping == Enums::RoRaBaCoCh || 20210646Sandreas.hansson@arm.com addrMapping == Enums::RoCoRaBaCh) { 20310646Sandreas.hansson@arm.com // for the interleavings with channel bits in the bottom, 20410646Sandreas.hansson@arm.com // if the system uses a channel striping granularity that 20510646Sandreas.hansson@arm.com // is larger than the DRAM burst size, then map the 20610646Sandreas.hansson@arm.com // sequential accesses within a stripe to a number of 20710646Sandreas.hansson@arm.com // columns in the DRAM, effectively placing some of the 20810646Sandreas.hansson@arm.com // lower-order column bits as the least-significant bits 20910646Sandreas.hansson@arm.com // of the address (above the ones denoting the burst size) 21010646Sandreas.hansson@arm.com assert(columnsPerStripe >= 1); 21110646Sandreas.hansson@arm.com 21210646Sandreas.hansson@arm.com // channel striping has to be done at a granularity that 21310646Sandreas.hansson@arm.com // is equal or larger to a cache line 21410646Sandreas.hansson@arm.com if (system()->cacheLineSize() > range.granularity()) { 21510646Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at least as large " 21610646Sandreas.hansson@arm.com "as the cache line size\n", name()); 21710646Sandreas.hansson@arm.com } 21810646Sandreas.hansson@arm.com 21910646Sandreas.hansson@arm.com // ...and equal or smaller than the row-buffer size 22010646Sandreas.hansson@arm.com if (rowBufferSize < range.granularity()) { 22110646Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at most as large " 22210646Sandreas.hansson@arm.com "as the row-buffer size\n", name()); 22310646Sandreas.hansson@arm.com } 22410646Sandreas.hansson@arm.com // this is essentially the check above, so just to be sure 22510646Sandreas.hansson@arm.com assert(columnsPerStripe <= columnsPerRowBuffer); 22610646Sandreas.hansson@arm.com } 22710646Sandreas.hansson@arm.com } 22810140SN/A} 22910140SN/A 23010140SN/Avoid 23110146Sandreas.hansson@arm.comDRAMCtrl::startup() 2329243SN/A{ 23310619Sandreas.hansson@arm.com // remember the memory system mode of operation 23410619Sandreas.hansson@arm.com isTimingMode = system()->isTimingMode(); 23510618SOmar.Naji@arm.com 23610619Sandreas.hansson@arm.com if (isTimingMode) { 23710619Sandreas.hansson@arm.com // timestamp offset should be in clock cycles for DRAMPower 23810619Sandreas.hansson@arm.com timeStampOffset = divCeil(curTick(), tCK); 23910619Sandreas.hansson@arm.com 24010619Sandreas.hansson@arm.com // update the start tick for the precharge accounting to the 24110619Sandreas.hansson@arm.com // current tick 24210619Sandreas.hansson@arm.com for (auto r : ranks) { 24310619Sandreas.hansson@arm.com r->startup(curTick() + tREFI - tRP); 24410619Sandreas.hansson@arm.com } 24510619Sandreas.hansson@arm.com 24610619Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 24710619Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 24810619Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 24910619Sandreas.hansson@arm.com // start of simulation 25010619Sandreas.hansson@arm.com busBusyUntil = curTick() + tRP + tRCD + tCL; 25110618SOmar.Naji@arm.com } 2529243SN/A} 2539243SN/A 2549243SN/ATick 25510146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 2569243SN/A{ 2579243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 2589243SN/A 25911334Sandreas.hansson@arm.com panic_if(pkt->cacheResponding(), "Should not see packets where cache " 26011334Sandreas.hansson@arm.com "is responding"); 26111334Sandreas.hansson@arm.com 2629243SN/A // do the actual memory access and turn the packet into a response 2639243SN/A access(pkt); 2649243SN/A 2659243SN/A Tick latency = 0; 26611334Sandreas.hansson@arm.com if (pkt->hasData()) { 2679243SN/A // this value is not supposed to be accurate, just enough to 2689243SN/A // keep things going, mimic a closed page 2699243SN/A latency = tRP + tRCD + tCL; 2709243SN/A } 2719243SN/A return latency; 2729243SN/A} 2739243SN/A 2749243SN/Abool 27510146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 2769243SN/A{ 2779831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 2789831SN/A readBufferSize, readQueue.size() + respQueue.size(), 2799831SN/A neededEntries); 2809243SN/A 2819831SN/A return 2829831SN/A (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 2839243SN/A} 2849243SN/A 2859243SN/Abool 28610146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 2879243SN/A{ 2889831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 2899831SN/A writeBufferSize, writeQueue.size(), neededEntries); 2909831SN/A return (writeQueue.size() + neededEntries) > writeBufferSize; 2919243SN/A} 2929243SN/A 29310146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 29410146Sandreas.hansson@arm.comDRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 29510143SN/A bool isRead) 2969243SN/A{ 2979669SN/A // decode the address based on the address mapping scheme, with 29810136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 29910136SN/A // channel, respectively 3009243SN/A uint8_t rank; 3019967SN/A uint8_t bank; 30210245Sandreas.hansson@arm.com // use a 64-bit unsigned during the computations as the row is 30310245Sandreas.hansson@arm.com // always the top bits, and check before creating the DRAMPacket 30410245Sandreas.hansson@arm.com uint64_t row; 3059243SN/A 30610286Sandreas.hansson@arm.com // truncate the address to a DRAM burst, which makes it unique to 30710286Sandreas.hansson@arm.com // a specific column, row, bank, rank and channel 3089831SN/A Addr addr = dramPktAddr / burstSize; 3099243SN/A 3109491SN/A // we have removed the lowest order address bits that denote the 3119831SN/A // position within the column 31210136SN/A if (addrMapping == Enums::RoRaBaChCo) { 3139491SN/A // the lowest order bits denote the column to ensure that 3149491SN/A // sequential cache lines occupy the same row 3159831SN/A addr = addr / columnsPerRowBuffer; 3169243SN/A 3179669SN/A // take out the channel part of the address 3189566SN/A addr = addr / channels; 3199566SN/A 3209669SN/A // after the channel bits, get the bank bits to interleave 3219669SN/A // over the banks 3229669SN/A bank = addr % banksPerRank; 3239669SN/A addr = addr / banksPerRank; 3249669SN/A 3259669SN/A // after the bank, we get the rank bits which thus interleaves 3269669SN/A // over the ranks 3279669SN/A rank = addr % ranksPerChannel; 3289669SN/A addr = addr / ranksPerChannel; 3299669SN/A 33011189Sandreas.hansson@arm.com // lastly, get the row bits, no need to remove them from addr 3319669SN/A row = addr % rowsPerBank; 33210136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 33310286Sandreas.hansson@arm.com // take out the lower-order column bits 33410286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 33510286Sandreas.hansson@arm.com 3369669SN/A // take out the channel part of the address 3379669SN/A addr = addr / channels; 3389669SN/A 33910286Sandreas.hansson@arm.com // next, the higher-order column bites 34010286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3419669SN/A 3429669SN/A // after the column bits, we get the bank bits to interleave 3439491SN/A // over the banks 3449243SN/A bank = addr % banksPerRank; 3459243SN/A addr = addr / banksPerRank; 3469243SN/A 3479491SN/A // after the bank, we get the rank bits which thus interleaves 3489491SN/A // over the ranks 3499243SN/A rank = addr % ranksPerChannel; 3509243SN/A addr = addr / ranksPerChannel; 3519243SN/A 35211189Sandreas.hansson@arm.com // lastly, get the row bits, no need to remove them from addr 3539243SN/A row = addr % rowsPerBank; 35410136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 3559491SN/A // optimise for closed page mode and utilise maximum 3569491SN/A // parallelism of the DRAM (at the cost of power) 3579491SN/A 35810286Sandreas.hansson@arm.com // take out the lower-order column bits 35910286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 36010286Sandreas.hansson@arm.com 3619566SN/A // take out the channel part of the address, not that this has 3629566SN/A // to match with how accesses are interleaved between the 3639566SN/A // controllers in the address mapping 3649566SN/A addr = addr / channels; 3659566SN/A 3669491SN/A // start with the bank bits, as this provides the maximum 3679491SN/A // opportunity for parallelism between requests 3689243SN/A bank = addr % banksPerRank; 3699243SN/A addr = addr / banksPerRank; 3709243SN/A 3719491SN/A // next get the rank bits 3729243SN/A rank = addr % ranksPerChannel; 3739243SN/A addr = addr / ranksPerChannel; 3749243SN/A 37510286Sandreas.hansson@arm.com // next, the higher-order column bites 37610286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3779243SN/A 37811189Sandreas.hansson@arm.com // lastly, get the row bits, no need to remove them from addr 3799243SN/A row = addr % rowsPerBank; 3809243SN/A } else 3819243SN/A panic("Unknown address mapping policy chosen!"); 3829243SN/A 3839243SN/A assert(rank < ranksPerChannel); 3849243SN/A assert(bank < banksPerRank); 3859243SN/A assert(row < rowsPerBank); 38610245Sandreas.hansson@arm.com assert(row < Bank::NO_ROW); 3879243SN/A 3889243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 3899831SN/A dramPktAddr, rank, bank, row); 3909243SN/A 3919243SN/A // create the corresponding DRAM packet with the entry time and 3929567SN/A // ready time set to the current tick, the latter will be updated 3939567SN/A // later 3949967SN/A uint16_t bank_id = banksPerRank * rank + bank; 3959967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 39610618SOmar.Naji@arm.com size, ranks[rank]->banks[bank], *ranks[rank]); 3979243SN/A} 3989243SN/A 3999243SN/Avoid 40010146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 4019243SN/A{ 4029243SN/A // only add to the read queue here. whenever the request is 4039243SN/A // eventually done, set the readyTime, and call schedule() 4049243SN/A assert(!pkt->isWrite()); 4059243SN/A 4069831SN/A assert(pktCount != 0); 4079831SN/A 4089831SN/A // if the request size is larger than burst size, the pkt is split into 4099831SN/A // multiple DRAM packets 4109831SN/A // Note if the pkt starting address is not aligened to burst size, the 4119831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 4129831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 4139831SN/A // check read packets against packets in write queue. 4149243SN/A Addr addr = pkt->getAddr(); 4159831SN/A unsigned pktsServicedByWrQ = 0; 4169831SN/A BurstHelper* burst_helper = NULL; 4179831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4189831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4199831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4209831SN/A readPktSize[ceilLog2(size)]++; 4219831SN/A readBursts++; 4229243SN/A 4239831SN/A // First check write buffer to see if the data is already at 4249831SN/A // the controller 4259831SN/A bool foundInWrQ = false; 42610889Sandreas.hansson@arm.com Addr burst_addr = burstAlign(addr); 42710889Sandreas.hansson@arm.com // if the burst address is not present then there is no need 42810889Sandreas.hansson@arm.com // looking any further 42910889Sandreas.hansson@arm.com if (isInWriteQueue.find(burst_addr) != isInWriteQueue.end()) { 43010889Sandreas.hansson@arm.com for (const auto& p : writeQueue) { 43110889Sandreas.hansson@arm.com // check if the read is subsumed in the write queue 43210889Sandreas.hansson@arm.com // packet we are looking at 43310889Sandreas.hansson@arm.com if (p->addr <= addr && (addr + size) <= (p->addr + p->size)) { 43410889Sandreas.hansson@arm.com foundInWrQ = true; 43510889Sandreas.hansson@arm.com servicedByWrQ++; 43610889Sandreas.hansson@arm.com pktsServicedByWrQ++; 43710889Sandreas.hansson@arm.com DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 43810889Sandreas.hansson@arm.com "write queue\n", addr, size); 43910889Sandreas.hansson@arm.com bytesReadWrQ += burstSize; 44010889Sandreas.hansson@arm.com break; 44110889Sandreas.hansson@arm.com } 4429831SN/A } 4439243SN/A } 4449831SN/A 4459831SN/A // If not found in the write q, make a DRAM packet and 4469831SN/A // push it onto the read queue 4479831SN/A if (!foundInWrQ) { 4489831SN/A 4499831SN/A // Make the burst helper for split packets 4509831SN/A if (pktCount > 1 && burst_helper == NULL) { 4519831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 4529831SN/A "dram requests\n", pkt->getAddr(), pktCount); 4539831SN/A burst_helper = new BurstHelper(pktCount); 4549831SN/A } 4559831SN/A 4569966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 4579831SN/A dram_pkt->burstHelper = burst_helper; 4589831SN/A 4599831SN/A assert(!readQueueFull(1)); 4609831SN/A rdQLenPdf[readQueue.size() + respQueue.size()]++; 4619831SN/A 4629831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 4639831SN/A 4649831SN/A readQueue.push_back(dram_pkt); 4659831SN/A 46611678Swendy.elsasser@arm.com // increment read entries of the rank 46711678Swendy.elsasser@arm.com ++dram_pkt->rankRef.readEntries; 46811678Swendy.elsasser@arm.com 4699831SN/A // Update stats 4709831SN/A avgRdQLen = readQueue.size() + respQueue.size(); 4719831SN/A } 4729831SN/A 4739831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 4749831SN/A addr = (addr | (burstSize - 1)) + 1; 4759243SN/A } 4769243SN/A 4779831SN/A // If all packets are serviced by write queue, we send the repsonse back 4789831SN/A if (pktsServicedByWrQ == pktCount) { 4799831SN/A accessAndRespond(pkt, frontendLatency); 4809831SN/A return; 4819831SN/A } 4829243SN/A 4839831SN/A // Update how many split packets are serviced by write queue 4849831SN/A if (burst_helper != NULL) 4859831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 4869243SN/A 48710206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 48810206Sandreas.hansson@arm.com // queue, do so now 48910206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 4909567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 4919567SN/A schedule(nextReqEvent, curTick()); 4929243SN/A } 4939243SN/A} 4949243SN/A 4959243SN/Avoid 49610146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 4979243SN/A{ 4989243SN/A // only add to the write queue here. whenever the request is 4999243SN/A // eventually done, set the readyTime, and call schedule() 5009243SN/A assert(pkt->isWrite()); 5019243SN/A 5029831SN/A // if the request size is larger than burst size, the pkt is split into 5039831SN/A // multiple DRAM packets 5049831SN/A Addr addr = pkt->getAddr(); 5059831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 5069831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 5079831SN/A pkt->getAddr() + pkt->getSize()) - addr; 5089831SN/A writePktSize[ceilLog2(size)]++; 5099831SN/A writeBursts++; 5109243SN/A 5119832SN/A // see if we can merge with an existing item in the write 51210889Sandreas.hansson@arm.com // queue and keep track of whether we have merged or not 51310889Sandreas.hansson@arm.com bool merged = isInWriteQueue.find(burstAlign(addr)) != 51410889Sandreas.hansson@arm.com isInWriteQueue.end(); 5159243SN/A 5169832SN/A // if the item was not merged we need to create a new write 5179832SN/A // and enqueue it 5189832SN/A if (!merged) { 5199966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 5209243SN/A 5219832SN/A assert(writeQueue.size() < writeBufferSize); 5229832SN/A wrQLenPdf[writeQueue.size()]++; 5239243SN/A 5249832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 5259831SN/A 5269832SN/A writeQueue.push_back(dram_pkt); 52710889Sandreas.hansson@arm.com isInWriteQueue.insert(burstAlign(addr)); 52810889Sandreas.hansson@arm.com assert(writeQueue.size() == isInWriteQueue.size()); 5299831SN/A 5309832SN/A // Update stats 5319832SN/A avgWrQLen = writeQueue.size(); 53211678Swendy.elsasser@arm.com 53311678Swendy.elsasser@arm.com // increment write entries of the rank 53411678Swendy.elsasser@arm.com ++dram_pkt->rankRef.writeEntries; 5359977SN/A } else { 53610889Sandreas.hansson@arm.com DPRINTF(DRAM, "Merging write burst with existing queue entry\n"); 53710889Sandreas.hansson@arm.com 5389977SN/A // keep track of the fact that this burst effectively 5399977SN/A // disappeared as it was merged with an existing one 5409977SN/A mergedWrBursts++; 5419832SN/A } 5429832SN/A 5439831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 5449831SN/A addr = (addr | (burstSize - 1)) + 1; 5459831SN/A } 5469243SN/A 5479243SN/A // we do not wait for the writes to be send to the actual memory, 5489243SN/A // but instead take responsibility for the consistency here and 5499243SN/A // snoop the write queue for any upcoming reads 5509831SN/A // @todo, if a pkt size is larger than burst size, we might need a 5519831SN/A // different front end latency 5529726SN/A accessAndRespond(pkt, frontendLatency); 5539243SN/A 55410206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 55510206Sandreas.hansson@arm.com // queue, do so now 55610206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 55710206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 55810206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 5599243SN/A } 5609243SN/A} 5619243SN/A 5629243SN/Avoid 56310146Sandreas.hansson@arm.comDRAMCtrl::printQs() const { 5649243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 5659833SN/A for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 5669243SN/A DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 5679243SN/A } 5689243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 5699833SN/A for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 5709243SN/A DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 5719243SN/A } 5729243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 5739833SN/A for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 5749243SN/A DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 5759243SN/A } 5769243SN/A} 5779243SN/A 5789243SN/Abool 57910146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 5809243SN/A{ 5819243SN/A // This is where we enter from the outside world 5829567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 5839831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 5849243SN/A 58511334Sandreas.hansson@arm.com panic_if(pkt->cacheResponding(), "Should not see packets where cache " 58611334Sandreas.hansson@arm.com "is responding"); 58711334Sandreas.hansson@arm.com 58811334Sandreas.hansson@arm.com panic_if(!(pkt->isRead() || pkt->isWrite()), 58911334Sandreas.hansson@arm.com "Should only see read and writes at memory controller\n"); 5909243SN/A 5919243SN/A // Calc avg gap between requests 5929243SN/A if (prevArrival != 0) { 5939243SN/A totGap += curTick() - prevArrival; 5949243SN/A } 5959243SN/A prevArrival = curTick(); 5969243SN/A 5979831SN/A 5989831SN/A // Find out how many dram packets a pkt translates to 5999831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 6009831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 6019831SN/A // multiple dram packets 6029243SN/A unsigned size = pkt->getSize(); 6039831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 6049831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 6059243SN/A 6069243SN/A // check local buffers and do not accept if full 6079243SN/A if (pkt->isRead()) { 6089567SN/A assert(size != 0); 6099831SN/A if (readQueueFull(dram_pkt_count)) { 6109567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 6119243SN/A // remember that we have to retry this port 6129243SN/A retryRdReq = true; 6139243SN/A numRdRetry++; 6149243SN/A return false; 6159243SN/A } else { 6169831SN/A addToReadQueue(pkt, dram_pkt_count); 6179243SN/A readReqs++; 6189977SN/A bytesReadSys += size; 6199243SN/A } 62011334Sandreas.hansson@arm.com } else { 62111334Sandreas.hansson@arm.com assert(pkt->isWrite()); 6229567SN/A assert(size != 0); 6239831SN/A if (writeQueueFull(dram_pkt_count)) { 6249567SN/A DPRINTF(DRAM, "Write queue full, not accepting\n"); 6259243SN/A // remember that we have to retry this port 6269243SN/A retryWrReq = true; 6279243SN/A numWrRetry++; 6289243SN/A return false; 6299243SN/A } else { 6309831SN/A addToWriteQueue(pkt, dram_pkt_count); 6319243SN/A writeReqs++; 6329977SN/A bytesWrittenSys += size; 6339243SN/A } 6349243SN/A } 6359243SN/A 6369243SN/A return true; 6379243SN/A} 6389243SN/A 6399243SN/Avoid 64010146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 6419243SN/A{ 6429243SN/A DPRINTF(DRAM, 6439243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 6449243SN/A 6459831SN/A DRAMPacket* dram_pkt = respQueue.front(); 6469243SN/A 64711678Swendy.elsasser@arm.com // if a read has reached its ready-time, decrement the number of reads 64811678Swendy.elsasser@arm.com // At this point the packet has been handled and there is a possibility 64911678Swendy.elsasser@arm.com // to switch to low-power mode if no other packet is available 65011678Swendy.elsasser@arm.com --dram_pkt->rankRef.readEntries; 65111678Swendy.elsasser@arm.com DPRINTF(DRAM, "number of read entries for rank %d is %d\n", 65211678Swendy.elsasser@arm.com dram_pkt->rank, dram_pkt->rankRef.readEntries); 65311678Swendy.elsasser@arm.com 65411678Swendy.elsasser@arm.com // counter should at least indicate one outstanding request 65511678Swendy.elsasser@arm.com // for this read 65611678Swendy.elsasser@arm.com assert(dram_pkt->rankRef.outstandingEvents > 0); 65711678Swendy.elsasser@arm.com // read response received, decrement count 65811678Swendy.elsasser@arm.com --dram_pkt->rankRef.outstandingEvents; 65911678Swendy.elsasser@arm.com 66011846Swendy.elsasser@arm.com // at this moment should not have transitioned to a low-power state 66111846Swendy.elsasser@arm.com assert((dram_pkt->rankRef.pwrState != PWR_SREF) && 66211846Swendy.elsasser@arm.com (dram_pkt->rankRef.pwrState != PWR_PRE_PDN) && 66311846Swendy.elsasser@arm.com (dram_pkt->rankRef.pwrState != PWR_ACT_PDN)); 66411678Swendy.elsasser@arm.com 66511678Swendy.elsasser@arm.com // track if this is the last packet before idling 66611678Swendy.elsasser@arm.com // and that there are no outstanding commands to this rank 66711846Swendy.elsasser@arm.com // if REF in progress, transition to LP state should not occur 66811846Swendy.elsasser@arm.com // until REF completes 66911846Swendy.elsasser@arm.com if ((dram_pkt->rankRef.refreshState == REF_IDLE) && 67011846Swendy.elsasser@arm.com (dram_pkt->rankRef.lowPowerEntryReady())) { 67111678Swendy.elsasser@arm.com // verify that there are no events scheduled 67211678Swendy.elsasser@arm.com assert(!dram_pkt->rankRef.activateEvent.scheduled()); 67311678Swendy.elsasser@arm.com assert(!dram_pkt->rankRef.prechargeEvent.scheduled()); 67411678Swendy.elsasser@arm.com 67511678Swendy.elsasser@arm.com // if coming from active state, schedule power event to 67611678Swendy.elsasser@arm.com // active power-down else go to precharge power-down 67711678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleep at tick %d; current power state is " 67811678Swendy.elsasser@arm.com "%d\n", dram_pkt->rank, curTick(), dram_pkt->rankRef.pwrState); 67911678Swendy.elsasser@arm.com 68011678Swendy.elsasser@arm.com // default to ACT power-down unless already in IDLE state 68111678Swendy.elsasser@arm.com // could be in IDLE if PRE issued before data returned 68211678Swendy.elsasser@arm.com PowerState next_pwr_state = PWR_ACT_PDN; 68311678Swendy.elsasser@arm.com if (dram_pkt->rankRef.pwrState == PWR_IDLE) { 68411678Swendy.elsasser@arm.com next_pwr_state = PWR_PRE_PDN; 68511678Swendy.elsasser@arm.com } 68611678Swendy.elsasser@arm.com 68711678Swendy.elsasser@arm.com dram_pkt->rankRef.powerDownSleep(next_pwr_state, curTick()); 68811678Swendy.elsasser@arm.com } 68911678Swendy.elsasser@arm.com 6909831SN/A if (dram_pkt->burstHelper) { 6919831SN/A // it is a split packet 6929831SN/A dram_pkt->burstHelper->burstsServiced++; 6939831SN/A if (dram_pkt->burstHelper->burstsServiced == 69410143SN/A dram_pkt->burstHelper->burstCount) { 6959831SN/A // we have now serviced all children packets of a system packet 6969831SN/A // so we can now respond to the requester 6979831SN/A // @todo we probably want to have a different front end and back 6989831SN/A // end latency for split packets 6999831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7009831SN/A delete dram_pkt->burstHelper; 7019831SN/A dram_pkt->burstHelper = NULL; 7029831SN/A } 7039831SN/A } else { 7049831SN/A // it is not a split packet 7059831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7069831SN/A } 7079243SN/A 7089831SN/A delete respQueue.front(); 7099831SN/A respQueue.pop_front(); 7109243SN/A 7119831SN/A if (!respQueue.empty()) { 7129831SN/A assert(respQueue.front()->readyTime >= curTick()); 7139831SN/A assert(!respondEvent.scheduled()); 7149831SN/A schedule(respondEvent, respQueue.front()->readyTime); 7159831SN/A } else { 7169831SN/A // if there is nothing left in any queue, signal a drain 71710913Sandreas.sandberg@arm.com if (drainState() == DrainState::Draining && 71811676Swendy.elsasser@arm.com writeQueue.empty() && readQueue.empty() && allRanksDrained()) { 71910913Sandreas.sandberg@arm.com 72010509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 72110913Sandreas.sandberg@arm.com signalDrainDone(); 7229831SN/A } 7239831SN/A } 7249567SN/A 7259831SN/A // We have made a location in the queue available at this point, 7269831SN/A // so if there is a read that was forced to wait, retry now 7279831SN/A if (retryRdReq) { 7289831SN/A retryRdReq = false; 72910713Sandreas.hansson@arm.com port.sendRetryReq(); 7309831SN/A } 7319243SN/A} 7329243SN/A 73310618SOmar.Naji@arm.combool 73410890Swendy.elsasser@arm.comDRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay) 7359243SN/A{ 73610206Sandreas.hansson@arm.com // This method does the arbitration between requests. The chosen 73710206Sandreas.hansson@arm.com // packet is simply moved to the head of the queue. The other 73810206Sandreas.hansson@arm.com // methods know that this is the place to look. For example, with 73910206Sandreas.hansson@arm.com // FCFS, this method does nothing 74010206Sandreas.hansson@arm.com assert(!queue.empty()); 7419243SN/A 74210618SOmar.Naji@arm.com // bool to indicate if a packet to an available rank is found 74310618SOmar.Naji@arm.com bool found_packet = false; 74410206Sandreas.hansson@arm.com if (queue.size() == 1) { 74510618SOmar.Naji@arm.com DRAMPacket* dram_pkt = queue.front(); 74610618SOmar.Naji@arm.com // available rank corresponds to state refresh idle 74712266Sradhika.jagtap@arm.com if (ranks[dram_pkt->rank]->inRefIdleState()) { 74810618SOmar.Naji@arm.com found_packet = true; 74910618SOmar.Naji@arm.com DPRINTF(DRAM, "Single request, going to a free rank\n"); 75010618SOmar.Naji@arm.com } else { 75110618SOmar.Naji@arm.com DPRINTF(DRAM, "Single request, going to a busy rank\n"); 75210618SOmar.Naji@arm.com } 75310618SOmar.Naji@arm.com return found_packet; 7549243SN/A } 7559243SN/A 7569243SN/A if (memSchedPolicy == Enums::fcfs) { 75710618SOmar.Naji@arm.com // check if there is a packet going to a free rank 75811321Ssteve.reinhardt@amd.com for (auto i = queue.begin(); i != queue.end() ; ++i) { 75910618SOmar.Naji@arm.com DRAMPacket* dram_pkt = *i; 76012266Sradhika.jagtap@arm.com if (ranks[dram_pkt->rank]->inRefIdleState()) { 76110618SOmar.Naji@arm.com queue.erase(i); 76210618SOmar.Naji@arm.com queue.push_front(dram_pkt); 76310618SOmar.Naji@arm.com found_packet = true; 76410618SOmar.Naji@arm.com break; 76510618SOmar.Naji@arm.com } 76610618SOmar.Naji@arm.com } 7679243SN/A } else if (memSchedPolicy == Enums::frfcfs) { 76810890Swendy.elsasser@arm.com found_packet = reorderQueue(queue, extra_col_delay); 7699243SN/A } else 7709243SN/A panic("No scheduling policy chosen\n"); 77110618SOmar.Naji@arm.com return found_packet; 7729243SN/A} 7739243SN/A 77410618SOmar.Naji@arm.combool 77510890Swendy.elsasser@arm.comDRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay) 7769974SN/A{ 77710890Swendy.elsasser@arm.com // Only determine this if needed 7789974SN/A uint64_t earliest_banks = 0; 77910890Swendy.elsasser@arm.com bool hidden_bank_prep = false; 7809974SN/A 78110890Swendy.elsasser@arm.com // search for seamless row hits first, if no seamless row hit is 78210890Swendy.elsasser@arm.com // found then determine if there are other packets that can be issued 78310890Swendy.elsasser@arm.com // without incurring additional bus delay due to bank timing 78410890Swendy.elsasser@arm.com // Will select closed rows first to enable more open row possibilies 78510890Swendy.elsasser@arm.com // in future selections 78610890Swendy.elsasser@arm.com bool found_hidden_bank = false; 78710890Swendy.elsasser@arm.com 78810890Swendy.elsasser@arm.com // remember if we found a row hit, not seamless, but bank prepped 78910890Swendy.elsasser@arm.com // and ready 79010890Swendy.elsasser@arm.com bool found_prepped_pkt = false; 79110890Swendy.elsasser@arm.com 79210890Swendy.elsasser@arm.com // if we have no row hit, prepped or not, and no seamless packet, 79310890Swendy.elsasser@arm.com // just go for the earliest possible 7949974SN/A bool found_earliest_pkt = false; 79510890Swendy.elsasser@arm.com 79610618SOmar.Naji@arm.com auto selected_pkt_it = queue.end(); 7979974SN/A 79810890Swendy.elsasser@arm.com // time we need to issue a column command to be seamless 79910890Swendy.elsasser@arm.com const Tick min_col_at = std::max(busBusyUntil - tCL + extra_col_delay, 80010890Swendy.elsasser@arm.com curTick()); 80110890Swendy.elsasser@arm.com 8029974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 8039974SN/A DRAMPacket* dram_pkt = *i; 8049974SN/A const Bank& bank = dram_pkt->bankRef; 80510890Swendy.elsasser@arm.com 80612266Sradhika.jagtap@arm.com // check if rank is not doing a refresh and thus is available, if not, 80712266Sradhika.jagtap@arm.com // jump to the next packet 80812266Sradhika.jagtap@arm.com if (dram_pkt->rankRef.inRefIdleState()) { 80910890Swendy.elsasser@arm.com // check if it is a row hit 81010618SOmar.Naji@arm.com if (bank.openRow == dram_pkt->row) { 81110890Swendy.elsasser@arm.com // no additional rank-to-rank or same bank-group 81210890Swendy.elsasser@arm.com // delays, or we switched read/write and might as well 81310890Swendy.elsasser@arm.com // go for the row hit 81410890Swendy.elsasser@arm.com if (bank.colAllowedAt <= min_col_at) { 81510890Swendy.elsasser@arm.com // FCFS within the hits, giving priority to 81610890Swendy.elsasser@arm.com // commands that can issue seamlessly, without 81710890Swendy.elsasser@arm.com // additional delay, such as same rank accesses 81810890Swendy.elsasser@arm.com // and/or different bank-group accesses 81910890Swendy.elsasser@arm.com DPRINTF(DRAM, "Seamless row buffer hit\n"); 82010618SOmar.Naji@arm.com selected_pkt_it = i; 82110890Swendy.elsasser@arm.com // no need to look through the remaining queue entries 82210618SOmar.Naji@arm.com break; 82310890Swendy.elsasser@arm.com } else if (!found_hidden_bank && !found_prepped_pkt) { 82410890Swendy.elsasser@arm.com // if we did not find a packet to a closed row that can 82510890Swendy.elsasser@arm.com // issue the bank commands without incurring delay, and 82610890Swendy.elsasser@arm.com // did not yet find a packet to a prepped row, remember 82710890Swendy.elsasser@arm.com // the current one 82810618SOmar.Naji@arm.com selected_pkt_it = i; 82910890Swendy.elsasser@arm.com found_prepped_pkt = true; 83010890Swendy.elsasser@arm.com DPRINTF(DRAM, "Prepped row buffer hit\n"); 83110618SOmar.Naji@arm.com } 83210890Swendy.elsasser@arm.com } else if (!found_earliest_pkt) { 83310890Swendy.elsasser@arm.com // if we have not initialised the bank status, do it 83410890Swendy.elsasser@arm.com // now, and only once per scheduling decisions 83510890Swendy.elsasser@arm.com if (earliest_banks == 0) { 83610890Swendy.elsasser@arm.com // determine entries with earliest bank delay 83710890Swendy.elsasser@arm.com pair<uint64_t, bool> bankStatus = 83810890Swendy.elsasser@arm.com minBankPrep(queue, min_col_at); 83910890Swendy.elsasser@arm.com earliest_banks = bankStatus.first; 84010890Swendy.elsasser@arm.com hidden_bank_prep = bankStatus.second; 84110890Swendy.elsasser@arm.com } 84210211Sandreas.hansson@arm.com 84310890Swendy.elsasser@arm.com // bank is amongst first available banks 84410890Swendy.elsasser@arm.com // minBankPrep will give priority to packets that can 84510890Swendy.elsasser@arm.com // issue seamlessly 84610890Swendy.elsasser@arm.com if (bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) { 84710618SOmar.Naji@arm.com found_earliest_pkt = true; 84810890Swendy.elsasser@arm.com found_hidden_bank = hidden_bank_prep; 84910890Swendy.elsasser@arm.com 85010890Swendy.elsasser@arm.com // give priority to packets that can issue 85110890Swendy.elsasser@arm.com // bank commands 'behind the scenes' 85210890Swendy.elsasser@arm.com // any additional delay if any will be due to 85310890Swendy.elsasser@arm.com // col-to-col command requirements 85410890Swendy.elsasser@arm.com if (hidden_bank_prep || !found_prepped_pkt) 85510890Swendy.elsasser@arm.com selected_pkt_it = i; 85610618SOmar.Naji@arm.com } 8579974SN/A } 8589974SN/A } 8599974SN/A } 8609974SN/A 86110618SOmar.Naji@arm.com if (selected_pkt_it != queue.end()) { 86210618SOmar.Naji@arm.com DRAMPacket* selected_pkt = *selected_pkt_it; 86310618SOmar.Naji@arm.com queue.erase(selected_pkt_it); 86410618SOmar.Naji@arm.com queue.push_front(selected_pkt); 86510890Swendy.elsasser@arm.com return true; 86610618SOmar.Naji@arm.com } 86710890Swendy.elsasser@arm.com 86810890Swendy.elsasser@arm.com return false; 8699974SN/A} 8709974SN/A 8719974SN/Avoid 87210146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 8739243SN/A{ 8749243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 8759243SN/A 8769243SN/A bool needsResponse = pkt->needsResponse(); 8779243SN/A // do the actual memory access which also turns the packet into a 8789243SN/A // response 8799243SN/A access(pkt); 8809243SN/A 8819243SN/A // turn packet around to go back to requester if response expected 8829243SN/A if (needsResponse) { 8839243SN/A // access already turned the packet into a response 8849243SN/A assert(pkt->isResponse()); 88510721SMarco.Balboni@ARM.com // response_time consumes the static latency and is charged also 88610721SMarco.Balboni@ARM.com // with headerDelay that takes into account the delay provided by 88710721SMarco.Balboni@ARM.com // the xbar and also the payloadDelay that takes into account the 88810721SMarco.Balboni@ARM.com // number of data beats. 88910721SMarco.Balboni@ARM.com Tick response_time = curTick() + static_latency + pkt->headerDelay + 89010721SMarco.Balboni@ARM.com pkt->payloadDelay; 89110721SMarco.Balboni@ARM.com // Here we reset the timing of the packet before sending it out. 89210694SMarco.Balboni@ARM.com pkt->headerDelay = pkt->payloadDelay = 0; 8939549SN/A 8949726SN/A // queue the packet in the response queue to be sent out after 8959726SN/A // the static latency has passed 89611194Sali.jafri@arm.com port.schedTimingResp(pkt, response_time, true); 8979243SN/A } else { 8989587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 8999587SN/A // is still having a pointer to it 90011190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 9019243SN/A } 9029243SN/A 9039243SN/A DPRINTF(DRAM, "Done\n"); 9049243SN/A 9059243SN/A return; 9069243SN/A} 9079243SN/A 9089243SN/Avoid 90910618SOmar.Naji@arm.comDRAMCtrl::activateBank(Rank& rank_ref, Bank& bank_ref, 91010618SOmar.Naji@arm.com Tick act_tick, uint32_t row) 9119488SN/A{ 91210618SOmar.Naji@arm.com assert(rank_ref.actTicks.size() == activationLimit); 9139488SN/A 9149488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 9159488SN/A 91610207Sandreas.hansson@arm.com // update the open row 91710618SOmar.Naji@arm.com assert(bank_ref.openRow == Bank::NO_ROW); 91810618SOmar.Naji@arm.com bank_ref.openRow = row; 91910207Sandreas.hansson@arm.com 92010207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 92110207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 92210207Sandreas.hansson@arm.com // precharge 92310618SOmar.Naji@arm.com bank_ref.bytesAccessed = 0; 92410618SOmar.Naji@arm.com bank_ref.rowAccesses = 0; 92510207Sandreas.hansson@arm.com 92610618SOmar.Naji@arm.com ++rank_ref.numBanksActive; 92710618SOmar.Naji@arm.com assert(rank_ref.numBanksActive <= banksPerRank); 92810207Sandreas.hansson@arm.com 92910247Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n", 93010618SOmar.Naji@arm.com bank_ref.bank, rank_ref.rank, act_tick, 93110618SOmar.Naji@arm.com ranks[rank_ref.rank]->numBanksActive); 93210247Sandreas.hansson@arm.com 93311675Swendy.elsasser@arm.com rank_ref.cmdList.push_back(Command(MemCommand::ACT, bank_ref.bank, 93411675Swendy.elsasser@arm.com act_tick)); 93510432SOmar.Naji@arm.com 93610432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK) - 93710618SOmar.Naji@arm.com timeStampOffset, bank_ref.bank, rank_ref.rank); 9389975SN/A 93910211Sandreas.hansson@arm.com // The next access has to respect tRAS for this bank 94010618SOmar.Naji@arm.com bank_ref.preAllowedAt = act_tick + tRAS; 94110211Sandreas.hansson@arm.com 94210211Sandreas.hansson@arm.com // Respect the row-to-column command delay 94310618SOmar.Naji@arm.com bank_ref.colAllowedAt = std::max(act_tick + tRCD, bank_ref.colAllowedAt); 94410211Sandreas.hansson@arm.com 9459971SN/A // start by enforcing tRRD 94611321Ssteve.reinhardt@amd.com for (int i = 0; i < banksPerRank; i++) { 94710210Sandreas.hansson@arm.com // next activate to any bank in this rank must not happen 94810210Sandreas.hansson@arm.com // before tRRD 94910618SOmar.Naji@arm.com if (bankGroupArch && (bank_ref.bankgr == rank_ref.banks[i].bankgr)) { 95010394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 95110394Swendy.elsasser@arm.com // ACT commands within the same bank group. Use tRRD_L 95210394Swendy.elsasser@arm.com // in this case 95310618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD_L, 95410618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt); 95510394Swendy.elsasser@arm.com } else { 95610394Swendy.elsasser@arm.com // use shorter tRRD value when either 95710394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 95810394Swendy.elsasser@arm.com // 2) bank is in a different bank group 95910618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD, 96010618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt); 96110394Swendy.elsasser@arm.com } 9629971SN/A } 96310208Sandreas.hansson@arm.com 9649971SN/A // next, we deal with tXAW, if the activation limit is disabled 96510492SOmar.Naji@arm.com // then we directly schedule an activate power event 96610618SOmar.Naji@arm.com if (!rank_ref.actTicks.empty()) { 96710492SOmar.Naji@arm.com // sanity check 96810618SOmar.Naji@arm.com if (rank_ref.actTicks.back() && 96910618SOmar.Naji@arm.com (act_tick - rank_ref.actTicks.back()) < tXAW) { 97010492SOmar.Naji@arm.com panic("Got %d activates in window %d (%llu - %llu) which " 97110492SOmar.Naji@arm.com "is smaller than %llu\n", activationLimit, act_tick - 97210618SOmar.Naji@arm.com rank_ref.actTicks.back(), act_tick, 97310618SOmar.Naji@arm.com rank_ref.actTicks.back(), tXAW); 97410492SOmar.Naji@arm.com } 9759824SN/A 97610492SOmar.Naji@arm.com // shift the times used for the book keeping, the last element 97710492SOmar.Naji@arm.com // (highest index) is the oldest one and hence the lowest value 97810618SOmar.Naji@arm.com rank_ref.actTicks.pop_back(); 9799488SN/A 98010492SOmar.Naji@arm.com // record an new activation (in the future) 98110618SOmar.Naji@arm.com rank_ref.actTicks.push_front(act_tick); 9829488SN/A 98310492SOmar.Naji@arm.com // cannot activate more than X times in time window tXAW, push the 98410492SOmar.Naji@arm.com // next one (the X + 1'st activate) to be tXAW away from the 98510492SOmar.Naji@arm.com // oldest in our window of X 98610618SOmar.Naji@arm.com if (rank_ref.actTicks.back() && 98710618SOmar.Naji@arm.com (act_tick - rank_ref.actTicks.back()) < tXAW) { 98810492SOmar.Naji@arm.com DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate " 98910492SOmar.Naji@arm.com "no earlier than %llu\n", activationLimit, 99010618SOmar.Naji@arm.com rank_ref.actTicks.back() + tXAW); 99111321Ssteve.reinhardt@amd.com for (int j = 0; j < banksPerRank; j++) 9929488SN/A // next activate must not happen before end of window 99310618SOmar.Naji@arm.com rank_ref.banks[j].actAllowedAt = 99410618SOmar.Naji@arm.com std::max(rank_ref.actTicks.back() + tXAW, 99510618SOmar.Naji@arm.com rank_ref.banks[j].actAllowedAt); 99610492SOmar.Naji@arm.com } 9979488SN/A } 99810208Sandreas.hansson@arm.com 99910208Sandreas.hansson@arm.com // at the point when this activate takes place, make sure we 100010208Sandreas.hansson@arm.com // transition to the active power state 100110618SOmar.Naji@arm.com if (!rank_ref.activateEvent.scheduled()) 100210618SOmar.Naji@arm.com schedule(rank_ref.activateEvent, act_tick); 100310618SOmar.Naji@arm.com else if (rank_ref.activateEvent.when() > act_tick) 100410208Sandreas.hansson@arm.com // move it sooner in time 100510618SOmar.Naji@arm.com reschedule(rank_ref.activateEvent, act_tick); 100610208Sandreas.hansson@arm.com} 100710208Sandreas.hansson@arm.com 100810208Sandreas.hansson@arm.comvoid 100910618SOmar.Naji@arm.comDRAMCtrl::prechargeBank(Rank& rank_ref, Bank& bank, Tick pre_at, bool trace) 101010207Sandreas.hansson@arm.com{ 101110207Sandreas.hansson@arm.com // make sure the bank has an open row 101210207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 101310207Sandreas.hansson@arm.com 101410207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 101510207Sandreas.hansson@arm.com // the page 101610207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 101710207Sandreas.hansson@arm.com 101810207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 101910207Sandreas.hansson@arm.com 102010214Sandreas.hansson@arm.com // no precharge allowed before this one 102110214Sandreas.hansson@arm.com bank.preAllowedAt = pre_at; 102210214Sandreas.hansson@arm.com 102310211Sandreas.hansson@arm.com Tick pre_done_at = pre_at + tRP; 102410211Sandreas.hansson@arm.com 102510211Sandreas.hansson@arm.com bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at); 102610207Sandreas.hansson@arm.com 102710618SOmar.Naji@arm.com assert(rank_ref.numBanksActive != 0); 102810618SOmar.Naji@arm.com --rank_ref.numBanksActive; 102910207Sandreas.hansson@arm.com 103010247Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got " 103110618SOmar.Naji@arm.com "%d active\n", bank.bank, rank_ref.rank, pre_at, 103210618SOmar.Naji@arm.com rank_ref.numBanksActive); 103310247Sandreas.hansson@arm.com 103410432SOmar.Naji@arm.com if (trace) { 103510207Sandreas.hansson@arm.com 103611675Swendy.elsasser@arm.com rank_ref.cmdList.push_back(Command(MemCommand::PRE, bank.bank, 103711675Swendy.elsasser@arm.com pre_at)); 103810432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK) - 103910618SOmar.Naji@arm.com timeStampOffset, bank.bank, rank_ref.rank); 104010432SOmar.Naji@arm.com } 104110208Sandreas.hansson@arm.com // if we look at the current number of active banks we might be 104210208Sandreas.hansson@arm.com // tempted to think the DRAM is now idle, however this can be 104310208Sandreas.hansson@arm.com // undone by an activate that is scheduled to happen before we 104410208Sandreas.hansson@arm.com // would have reached the idle state, so schedule an event and 104510208Sandreas.hansson@arm.com // rather check once we actually make it to the point in time when 104610208Sandreas.hansson@arm.com // the (last) precharge takes place 104711678Swendy.elsasser@arm.com if (!rank_ref.prechargeEvent.scheduled()) { 104810618SOmar.Naji@arm.com schedule(rank_ref.prechargeEvent, pre_done_at); 104911678Swendy.elsasser@arm.com // New event, increment count 105011678Swendy.elsasser@arm.com ++rank_ref.outstandingEvents; 105111678Swendy.elsasser@arm.com } else if (rank_ref.prechargeEvent.when() < pre_done_at) { 105210618SOmar.Naji@arm.com reschedule(rank_ref.prechargeEvent, pre_done_at); 105311678Swendy.elsasser@arm.com } 105410207Sandreas.hansson@arm.com} 105510207Sandreas.hansson@arm.com 105610207Sandreas.hansson@arm.comvoid 105710146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 10589243SN/A{ 10599243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 10609243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 10619243SN/A 106210618SOmar.Naji@arm.com // get the rank 106310618SOmar.Naji@arm.com Rank& rank = dram_pkt->rankRef; 106410618SOmar.Naji@arm.com 106511678Swendy.elsasser@arm.com // are we in or transitioning to a low-power state and have not scheduled 106611678Swendy.elsasser@arm.com // a power-up event? 106711678Swendy.elsasser@arm.com // if so, wake up from power down to issue RD/WR burst 106811678Swendy.elsasser@arm.com if (rank.inLowPowerState) { 106911678Swendy.elsasser@arm.com assert(rank.pwrState != PWR_SREF); 107011678Swendy.elsasser@arm.com rank.scheduleWakeUpEvent(tXP); 107111678Swendy.elsasser@arm.com } 107211678Swendy.elsasser@arm.com 107310211Sandreas.hansson@arm.com // get the bank 10749967SN/A Bank& bank = dram_pkt->bankRef; 10759243SN/A 107610211Sandreas.hansson@arm.com // for the state we need to track if it is a row hit or not 107710211Sandreas.hansson@arm.com bool row_hit = true; 107810211Sandreas.hansson@arm.com 107910211Sandreas.hansson@arm.com // respect any constraints on the command (e.g. tRCD or tCCD) 108010211Sandreas.hansson@arm.com Tick cmd_at = std::max(bank.colAllowedAt, curTick()); 108110211Sandreas.hansson@arm.com 108210211Sandreas.hansson@arm.com // Determine the access latency and update the bank state 108310211Sandreas.hansson@arm.com if (bank.openRow == dram_pkt->row) { 108410211Sandreas.hansson@arm.com // nothing to do 108510209Sandreas.hansson@arm.com } else { 108610211Sandreas.hansson@arm.com row_hit = false; 108710211Sandreas.hansson@arm.com 108810209Sandreas.hansson@arm.com // If there is a page open, precharge it. 108910209Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 109010618SOmar.Naji@arm.com prechargeBank(rank, bank, std::max(bank.preAllowedAt, curTick())); 10919488SN/A } 10929973SN/A 109310211Sandreas.hansson@arm.com // next we need to account for the delay in activating the 109410211Sandreas.hansson@arm.com // page 109510211Sandreas.hansson@arm.com Tick act_tick = std::max(bank.actAllowedAt, curTick()); 10969973SN/A 109710210Sandreas.hansson@arm.com // Record the activation and deal with all the global timing 109810210Sandreas.hansson@arm.com // constraints caused be a new activation (tRRD and tXAW) 109910618SOmar.Naji@arm.com activateBank(rank, bank, act_tick, dram_pkt->row); 110010210Sandreas.hansson@arm.com 110110211Sandreas.hansson@arm.com // issue the command as early as possible 110210211Sandreas.hansson@arm.com cmd_at = bank.colAllowedAt; 110310209Sandreas.hansson@arm.com } 110410209Sandreas.hansson@arm.com 110510211Sandreas.hansson@arm.com // we need to wait until the bus is available before we can issue 110610211Sandreas.hansson@arm.com // the command 110710211Sandreas.hansson@arm.com cmd_at = std::max(cmd_at, busBusyUntil - tCL); 110810211Sandreas.hansson@arm.com 110910211Sandreas.hansson@arm.com // update the packet ready time 111010211Sandreas.hansson@arm.com dram_pkt->readyTime = cmd_at + tCL + tBURST; 111110211Sandreas.hansson@arm.com 111210211Sandreas.hansson@arm.com // only one burst can use the bus at any one point in time 111310211Sandreas.hansson@arm.com assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 111410211Sandreas.hansson@arm.com 111510394Swendy.elsasser@arm.com // update the time for the next read/write burst for each 111610394Swendy.elsasser@arm.com // bank (add a max with tCCD/tCCD_L here) 111710394Swendy.elsasser@arm.com Tick cmd_dly; 111811321Ssteve.reinhardt@amd.com for (int j = 0; j < ranksPerChannel; j++) { 111911321Ssteve.reinhardt@amd.com for (int i = 0; i < banksPerRank; i++) { 112010394Swendy.elsasser@arm.com // next burst to same bank group in this rank must not happen 112110394Swendy.elsasser@arm.com // before tCCD_L. Different bank group timing requirement is 112210394Swendy.elsasser@arm.com // tBURST; Add tCS for different ranks 112310394Swendy.elsasser@arm.com if (dram_pkt->rank == j) { 112410618SOmar.Naji@arm.com if (bankGroupArch && 112510618SOmar.Naji@arm.com (bank.bankgr == ranks[j]->banks[i].bankgr)) { 112610394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 112710394Swendy.elsasser@arm.com // RD/WR burst commands to the same bank group. 112810394Swendy.elsasser@arm.com // Use tCCD_L in this case 112910394Swendy.elsasser@arm.com cmd_dly = tCCD_L; 113010394Swendy.elsasser@arm.com } else { 113110394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), the shorter 113210394Swendy.elsasser@arm.com // cas-to-cas delay value, when either: 113310394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 113410394Swendy.elsasser@arm.com // 2) bank is in a different bank group 113510394Swendy.elsasser@arm.com cmd_dly = tBURST; 113610394Swendy.elsasser@arm.com } 113710394Swendy.elsasser@arm.com } else { 113810394Swendy.elsasser@arm.com // different rank is by default in a different bank group 113910394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), which is the shorter 114010394Swendy.elsasser@arm.com // cas-to-cas delay in this case 114110394Swendy.elsasser@arm.com // Add tCS to account for rank-to-rank bus delay requirements 114210394Swendy.elsasser@arm.com cmd_dly = tBURST + tCS; 114310394Swendy.elsasser@arm.com } 114410618SOmar.Naji@arm.com ranks[j]->banks[i].colAllowedAt = std::max(cmd_at + cmd_dly, 114510618SOmar.Naji@arm.com ranks[j]->banks[i].colAllowedAt); 114610394Swendy.elsasser@arm.com } 114710394Swendy.elsasser@arm.com } 114810211Sandreas.hansson@arm.com 114910393Swendy.elsasser@arm.com // Save rank of current access 115010393Swendy.elsasser@arm.com activeRank = dram_pkt->rank; 115110393Swendy.elsasser@arm.com 115210212Sandreas.hansson@arm.com // If this is a write, we also need to respect the write recovery 115310212Sandreas.hansson@arm.com // time before a precharge, in the case of a read, respect the 115410212Sandreas.hansson@arm.com // read to precharge constraint 115510212Sandreas.hansson@arm.com bank.preAllowedAt = std::max(bank.preAllowedAt, 115610212Sandreas.hansson@arm.com dram_pkt->isRead ? cmd_at + tRTP : 115710212Sandreas.hansson@arm.com dram_pkt->readyTime + tWR); 115810210Sandreas.hansson@arm.com 115910209Sandreas.hansson@arm.com // increment the bytes accessed and the accesses per row 116010209Sandreas.hansson@arm.com bank.bytesAccessed += burstSize; 116110209Sandreas.hansson@arm.com ++bank.rowAccesses; 116210209Sandreas.hansson@arm.com 116310209Sandreas.hansson@arm.com // if we reached the max, then issue with an auto-precharge 116410209Sandreas.hansson@arm.com bool auto_precharge = pageMgmt == Enums::close || 116510209Sandreas.hansson@arm.com bank.rowAccesses == maxAccessesPerRow; 116610209Sandreas.hansson@arm.com 116710209Sandreas.hansson@arm.com // if we did not hit the limit, we might still want to 116810209Sandreas.hansson@arm.com // auto-precharge 116910209Sandreas.hansson@arm.com if (!auto_precharge && 117010209Sandreas.hansson@arm.com (pageMgmt == Enums::open_adaptive || 117110209Sandreas.hansson@arm.com pageMgmt == Enums::close_adaptive)) { 117210209Sandreas.hansson@arm.com // a twist on the open and close page policies: 117310209Sandreas.hansson@arm.com // 1) open_adaptive page policy does not blindly keep the 117410209Sandreas.hansson@arm.com // page open, but close it if there are no row hits, and there 117510209Sandreas.hansson@arm.com // are bank conflicts in the queue 117610209Sandreas.hansson@arm.com // 2) close_adaptive page policy does not blindly close the 117710209Sandreas.hansson@arm.com // page, but closes it only if there are no row hits in the queue. 117810209Sandreas.hansson@arm.com // In this case, only force an auto precharge when there 117910209Sandreas.hansson@arm.com // are no same page hits in the queue 118010209Sandreas.hansson@arm.com bool got_more_hits = false; 118110209Sandreas.hansson@arm.com bool got_bank_conflict = false; 118210209Sandreas.hansson@arm.com 118310209Sandreas.hansson@arm.com // either look at the read queue or write queue 118410209Sandreas.hansson@arm.com const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 118510209Sandreas.hansson@arm.com writeQueue; 118610209Sandreas.hansson@arm.com auto p = queue.begin(); 118710209Sandreas.hansson@arm.com // make sure we are not considering the packet that we are 118810209Sandreas.hansson@arm.com // currently dealing with (which is the head of the queue) 118910209Sandreas.hansson@arm.com ++p; 119010209Sandreas.hansson@arm.com 119110809Srb639@drexel.edu // keep on looking until we find a hit or reach the end of the queue 119210809Srb639@drexel.edu // 1) if a hit is found, then both open and close adaptive policies keep 119310809Srb639@drexel.edu // the page open 119410809Srb639@drexel.edu // 2) if no hit is found, got_bank_conflict is set to true if a bank 119510809Srb639@drexel.edu // conflict request is waiting in the queue 119610809Srb639@drexel.edu while (!got_more_hits && p != queue.end()) { 119710209Sandreas.hansson@arm.com bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 119810209Sandreas.hansson@arm.com (dram_pkt->bank == (*p)->bank); 119910209Sandreas.hansson@arm.com bool same_row = dram_pkt->row == (*p)->row; 120010209Sandreas.hansson@arm.com got_more_hits |= same_rank_bank && same_row; 120110209Sandreas.hansson@arm.com got_bank_conflict |= same_rank_bank && !same_row; 12029973SN/A ++p; 120310141SN/A } 120410141SN/A 120510209Sandreas.hansson@arm.com // auto pre-charge when either 120610209Sandreas.hansson@arm.com // 1) open_adaptive policy, we have not got any more hits, and 120710209Sandreas.hansson@arm.com // have a bank conflict 120810209Sandreas.hansson@arm.com // 2) close_adaptive policy and we have not got any more hits 120910209Sandreas.hansson@arm.com auto_precharge = !got_more_hits && 121010209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive); 121110209Sandreas.hansson@arm.com } 121210142SN/A 121310247Sandreas.hansson@arm.com // DRAMPower trace command to be written 121410247Sandreas.hansson@arm.com std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR"; 121510247Sandreas.hansson@arm.com 121610432SOmar.Naji@arm.com // MemCommand required for DRAMPower library 121710432SOmar.Naji@arm.com MemCommand::cmds command = (mem_cmd == "RD") ? MemCommand::RD : 121810432SOmar.Naji@arm.com MemCommand::WR; 121910432SOmar.Naji@arm.com 122011675Swendy.elsasser@arm.com // Update bus state 122111675Swendy.elsasser@arm.com busBusyUntil = dram_pkt->readyTime; 122211675Swendy.elsasser@arm.com 122311675Swendy.elsasser@arm.com DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n", 122411675Swendy.elsasser@arm.com dram_pkt->addr, dram_pkt->readyTime, busBusyUntil); 122511675Swendy.elsasser@arm.com 122611675Swendy.elsasser@arm.com dram_pkt->rankRef.cmdList.push_back(Command(command, dram_pkt->bank, 122711675Swendy.elsasser@arm.com cmd_at)); 122811675Swendy.elsasser@arm.com 122911675Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK) - 123011675Swendy.elsasser@arm.com timeStampOffset, mem_cmd, dram_pkt->bank, dram_pkt->rank); 123111675Swendy.elsasser@arm.com 123210209Sandreas.hansson@arm.com // if this access should use auto-precharge, then we are 123311675Swendy.elsasser@arm.com // closing the row after the read/write burst 123410209Sandreas.hansson@arm.com if (auto_precharge) { 123510432SOmar.Naji@arm.com // if auto-precharge push a PRE command at the correct tick to the 123610432SOmar.Naji@arm.com // list used by DRAMPower library to calculate power 123710618SOmar.Naji@arm.com prechargeBank(rank, bank, std::max(curTick(), bank.preAllowedAt)); 12389973SN/A 123910209Sandreas.hansson@arm.com DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 124010209Sandreas.hansson@arm.com } 12419963SN/A 124210206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 124310206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 124410206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 124510206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 124610206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 12479972SN/A 124810206Sandreas.hansson@arm.com // Update the stats and schedule the next request 12499977SN/A if (dram_pkt->isRead) { 125010147Sandreas.hansson@arm.com ++readsThisTime; 125110211Sandreas.hansson@arm.com if (row_hit) 12529977SN/A readRowHits++; 12539977SN/A bytesReadDRAM += burstSize; 12549977SN/A perBankRdBursts[dram_pkt->bankId]++; 125510206Sandreas.hansson@arm.com 125610206Sandreas.hansson@arm.com // Update latency stats 125710206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 125810206Sandreas.hansson@arm.com totBusLat += tBURST; 125910211Sandreas.hansson@arm.com totQLat += cmd_at - dram_pkt->entryTime; 12609977SN/A } else { 126110147Sandreas.hansson@arm.com ++writesThisTime; 126210211Sandreas.hansson@arm.com if (row_hit) 12639977SN/A writeRowHits++; 12649977SN/A bytesWritten += burstSize; 12659977SN/A perBankWrBursts[dram_pkt->bankId]++; 12669243SN/A } 12679243SN/A} 12689243SN/A 12699243SN/Avoid 127010206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 12719243SN/A{ 127210618SOmar.Naji@arm.com int busyRanks = 0; 127310618SOmar.Naji@arm.com for (auto r : ranks) { 127412266Sradhika.jagtap@arm.com if (!r->inRefIdleState()) { 127511678Swendy.elsasser@arm.com if (r->pwrState != PWR_SREF) { 127611678Swendy.elsasser@arm.com // rank is busy refreshing 127711678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d is not available\n", r->rank); 127811678Swendy.elsasser@arm.com busyRanks++; 127911678Swendy.elsasser@arm.com 128011678Swendy.elsasser@arm.com // let the rank know that if it was waiting to drain, it 128111678Swendy.elsasser@arm.com // is now done and ready to proceed 128211678Swendy.elsasser@arm.com r->checkDrainDone(); 128311678Swendy.elsasser@arm.com } 128411678Swendy.elsasser@arm.com 128511678Swendy.elsasser@arm.com // check if we were in self-refresh and haven't started 128611678Swendy.elsasser@arm.com // to transition out 128711678Swendy.elsasser@arm.com if ((r->pwrState == PWR_SREF) && r->inLowPowerState) { 128811678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d is in self-refresh\n", r->rank); 128911678Swendy.elsasser@arm.com // if we have commands queued to this rank and we don't have 129011678Swendy.elsasser@arm.com // a minimum number of active commands enqueued, 129111678Swendy.elsasser@arm.com // exit self-refresh 129211678Swendy.elsasser@arm.com if (r->forceSelfRefreshExit()) { 129311678Swendy.elsasser@arm.com DPRINTF(DRAMState, "rank %d was in self refresh and" 129411678Swendy.elsasser@arm.com " should wake up\n", r->rank); 129511678Swendy.elsasser@arm.com //wake up from self-refresh 129611678Swendy.elsasser@arm.com r->scheduleWakeUpEvent(tXS); 129711678Swendy.elsasser@arm.com // things are brought back into action once a refresh is 129811678Swendy.elsasser@arm.com // performed after self-refresh 129911678Swendy.elsasser@arm.com // continue with selection for other ranks 130011678Swendy.elsasser@arm.com } 130111678Swendy.elsasser@arm.com } 130210618SOmar.Naji@arm.com } 130310618SOmar.Naji@arm.com } 130410618SOmar.Naji@arm.com 130510618SOmar.Naji@arm.com if (busyRanks == ranksPerChannel) { 130610618SOmar.Naji@arm.com // if all ranks are refreshing wait for them to finish 130710618SOmar.Naji@arm.com // and stall this state machine without taking any further 130810618SOmar.Naji@arm.com // action, and do not schedule a new nextReqEvent 130910618SOmar.Naji@arm.com return; 131010618SOmar.Naji@arm.com } 131110618SOmar.Naji@arm.com 131211678Swendy.elsasser@arm.com // pre-emptively set to false. Overwrite if in transitioning to 131311678Swendy.elsasser@arm.com // a new state 131410393Swendy.elsasser@arm.com bool switched_cmd_type = false; 131511678Swendy.elsasser@arm.com if (busState != busStateNext) { 131611678Swendy.elsasser@arm.com if (busState == READ) { 131711678Swendy.elsasser@arm.com DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 131811678Swendy.elsasser@arm.com "waiting\n", readsThisTime, readQueue.size()); 131911678Swendy.elsasser@arm.com 132011678Swendy.elsasser@arm.com // sample and reset the read-related stats as we are now 132111678Swendy.elsasser@arm.com // transitioning to writes, and all reads are done 132211678Swendy.elsasser@arm.com rdPerTurnAround.sample(readsThisTime); 132311678Swendy.elsasser@arm.com readsThisTime = 0; 132411678Swendy.elsasser@arm.com 132511678Swendy.elsasser@arm.com // now proceed to do the actual writes 132611678Swendy.elsasser@arm.com switched_cmd_type = true; 132711678Swendy.elsasser@arm.com } else { 132811678Swendy.elsasser@arm.com DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 132911678Swendy.elsasser@arm.com "waiting\n", writesThisTime, writeQueue.size()); 133011678Swendy.elsasser@arm.com 133111678Swendy.elsasser@arm.com wrPerTurnAround.sample(writesThisTime); 133211678Swendy.elsasser@arm.com writesThisTime = 0; 133311678Swendy.elsasser@arm.com 133411678Swendy.elsasser@arm.com switched_cmd_type = true; 133511678Swendy.elsasser@arm.com } 133611678Swendy.elsasser@arm.com // update busState to match next state until next transition 133711678Swendy.elsasser@arm.com busState = busStateNext; 133810206Sandreas.hansson@arm.com } 133910206Sandreas.hansson@arm.com 134010206Sandreas.hansson@arm.com // when we get here it is either a read or a write 134110206Sandreas.hansson@arm.com if (busState == READ) { 134210206Sandreas.hansson@arm.com 134310206Sandreas.hansson@arm.com // track if we should switch or not 134410206Sandreas.hansson@arm.com bool switch_to_writes = false; 134510206Sandreas.hansson@arm.com 134610206Sandreas.hansson@arm.com if (readQueue.empty()) { 134710206Sandreas.hansson@arm.com // In the case there is no read request to go next, 134810206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 134910206Sandreas.hansson@arm.com // if we are draining) 135010206Sandreas.hansson@arm.com if (!writeQueue.empty() && 135110913Sandreas.sandberg@arm.com (drainState() == DrainState::Draining || 135210913Sandreas.sandberg@arm.com writeQueue.size() > writeLowThreshold)) { 135310206Sandreas.hansson@arm.com 135410206Sandreas.hansson@arm.com switch_to_writes = true; 135510206Sandreas.hansson@arm.com } else { 135610206Sandreas.hansson@arm.com // check if we are drained 135711676Swendy.elsasser@arm.com // not done draining until in PWR_IDLE state 135811676Swendy.elsasser@arm.com // ensuring all banks are closed and 135911676Swendy.elsasser@arm.com // have exited low power states 136010913Sandreas.sandberg@arm.com if (drainState() == DrainState::Draining && 136111676Swendy.elsasser@arm.com respQueue.empty() && allRanksDrained()) { 136210913Sandreas.sandberg@arm.com 136310509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 136410913Sandreas.sandberg@arm.com signalDrainDone(); 136510206Sandreas.hansson@arm.com } 136610206Sandreas.hansson@arm.com 136710206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 136810206Sandreas.hansson@arm.com // event for the next request 136910206Sandreas.hansson@arm.com return; 137010206Sandreas.hansson@arm.com } 137110206Sandreas.hansson@arm.com } else { 137210618SOmar.Naji@arm.com // bool to check if there is a read to a free rank 137310618SOmar.Naji@arm.com bool found_read = false; 137410618SOmar.Naji@arm.com 137510206Sandreas.hansson@arm.com // Figure out which read request goes next, and move it to the 137610206Sandreas.hansson@arm.com // front of the read queue 137710890Swendy.elsasser@arm.com // If we are changing command type, incorporate the minimum 137810890Swendy.elsasser@arm.com // bus turnaround delay which will be tCS (different rank) case 137910890Swendy.elsasser@arm.com found_read = chooseNext(readQueue, 138010890Swendy.elsasser@arm.com switched_cmd_type ? tCS : 0); 138110618SOmar.Naji@arm.com 138210618SOmar.Naji@arm.com // if no read to an available rank is found then return 138310618SOmar.Naji@arm.com // at this point. There could be writes to the available ranks 138410618SOmar.Naji@arm.com // which are above the required threshold. However, to 138510618SOmar.Naji@arm.com // avoid adding more complexity to the code, return and wait 138610618SOmar.Naji@arm.com // for a refresh event to kick things into action again. 138710618SOmar.Naji@arm.com if (!found_read) 138810618SOmar.Naji@arm.com return; 138910206Sandreas.hansson@arm.com 139010215Sandreas.hansson@arm.com DRAMPacket* dram_pkt = readQueue.front(); 139112266Sradhika.jagtap@arm.com assert(dram_pkt->rankRef.inRefIdleState()); 139211678Swendy.elsasser@arm.com 139310393Swendy.elsasser@arm.com // here we get a bit creative and shift the bus busy time not 139410393Swendy.elsasser@arm.com // just the tWTR, but also a CAS latency to capture the fact 139510393Swendy.elsasser@arm.com // that we are allowed to prepare a new bank, but not issue a 139610393Swendy.elsasser@arm.com // read command until after tWTR, in essence we capture a 139710393Swendy.elsasser@arm.com // bubble on the data bus that is tWTR + tCL 139810394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 139910394Swendy.elsasser@arm.com busBusyUntil += tWTR + tCL; 140010393Swendy.elsasser@arm.com } 140110393Swendy.elsasser@arm.com 140210215Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 140310206Sandreas.hansson@arm.com 140410206Sandreas.hansson@arm.com // At this point we're done dealing with the request 140510215Sandreas.hansson@arm.com readQueue.pop_front(); 140610215Sandreas.hansson@arm.com 140711678Swendy.elsasser@arm.com // Every respQueue which will generate an event, increment count 140811678Swendy.elsasser@arm.com ++dram_pkt->rankRef.outstandingEvents; 140911678Swendy.elsasser@arm.com 141010215Sandreas.hansson@arm.com // sanity check 141110215Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 141210215Sandreas.hansson@arm.com assert(dram_pkt->readyTime >= curTick()); 141310215Sandreas.hansson@arm.com 141410215Sandreas.hansson@arm.com // Insert into response queue. It will be sent back to the 141510215Sandreas.hansson@arm.com // requestor at its readyTime 141610215Sandreas.hansson@arm.com if (respQueue.empty()) { 141710215Sandreas.hansson@arm.com assert(!respondEvent.scheduled()); 141810215Sandreas.hansson@arm.com schedule(respondEvent, dram_pkt->readyTime); 141910215Sandreas.hansson@arm.com } else { 142010215Sandreas.hansson@arm.com assert(respQueue.back()->readyTime <= dram_pkt->readyTime); 142110215Sandreas.hansson@arm.com assert(respondEvent.scheduled()); 142210215Sandreas.hansson@arm.com } 142310215Sandreas.hansson@arm.com 142410215Sandreas.hansson@arm.com respQueue.push_back(dram_pkt); 142510206Sandreas.hansson@arm.com 142610206Sandreas.hansson@arm.com // we have so many writes that we have to transition 142710206Sandreas.hansson@arm.com if (writeQueue.size() > writeHighThreshold) { 142810206Sandreas.hansson@arm.com switch_to_writes = true; 142910206Sandreas.hansson@arm.com } 143010206Sandreas.hansson@arm.com } 143110206Sandreas.hansson@arm.com 143210206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 143310206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 143410206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 143510206Sandreas.hansson@arm.com if (switch_to_writes) { 143610206Sandreas.hansson@arm.com // transition to writing 143711678Swendy.elsasser@arm.com busStateNext = WRITE; 143810206Sandreas.hansson@arm.com } 14399352SN/A } else { 144010618SOmar.Naji@arm.com // bool to check if write to free rank is found 144110618SOmar.Naji@arm.com bool found_write = false; 144210618SOmar.Naji@arm.com 144310890Swendy.elsasser@arm.com // If we are changing command type, incorporate the minimum 144410890Swendy.elsasser@arm.com // bus turnaround delay 144510890Swendy.elsasser@arm.com found_write = chooseNext(writeQueue, 144610890Swendy.elsasser@arm.com switched_cmd_type ? std::min(tRTW, tCS) : 0); 144710618SOmar.Naji@arm.com 144812266Sradhika.jagtap@arm.com // if there are no writes to a rank that is available to service 144912266Sradhika.jagtap@arm.com // requests (i.e. rank is in refresh idle state) are found then 145012266Sradhika.jagtap@arm.com // return. There could be reads to the available ranks. However, to 145112266Sradhika.jagtap@arm.com // avoid adding more complexity to the code, return at this point and 145212266Sradhika.jagtap@arm.com // wait for a refresh event to kick things into action again. 145310618SOmar.Naji@arm.com if (!found_write) 145410618SOmar.Naji@arm.com return; 145510618SOmar.Naji@arm.com 145610206Sandreas.hansson@arm.com DRAMPacket* dram_pkt = writeQueue.front(); 145712266Sradhika.jagtap@arm.com assert(dram_pkt->rankRef.inRefIdleState()); 145810206Sandreas.hansson@arm.com // sanity check 145910206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 146010393Swendy.elsasser@arm.com 146110394Swendy.elsasser@arm.com // add a bubble to the data bus, as defined by the 146210394Swendy.elsasser@arm.com // tRTW when access is to the same rank as previous burst 146310394Swendy.elsasser@arm.com // Different rank timing is handled with tCS, which is 146410394Swendy.elsasser@arm.com // applied to colAllowedAt 146510394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 146610394Swendy.elsasser@arm.com busBusyUntil += tRTW; 146710393Swendy.elsasser@arm.com } 146810393Swendy.elsasser@arm.com 146910206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 147010206Sandreas.hansson@arm.com 147110206Sandreas.hansson@arm.com writeQueue.pop_front(); 147211678Swendy.elsasser@arm.com 147311678Swendy.elsasser@arm.com // removed write from queue, decrement count 147411678Swendy.elsasser@arm.com --dram_pkt->rankRef.writeEntries; 147511678Swendy.elsasser@arm.com 147611678Swendy.elsasser@arm.com // Schedule write done event to decrement event count 147711678Swendy.elsasser@arm.com // after the readyTime has been reached 147811678Swendy.elsasser@arm.com // Only schedule latest write event to minimize events 147911678Swendy.elsasser@arm.com // required; only need to ensure that final event scheduled covers 148011678Swendy.elsasser@arm.com // the time that writes are outstanding and bus is active 148111678Swendy.elsasser@arm.com // to holdoff power-down entry events 148211678Swendy.elsasser@arm.com if (!dram_pkt->rankRef.writeDoneEvent.scheduled()) { 148311678Swendy.elsasser@arm.com schedule(dram_pkt->rankRef.writeDoneEvent, dram_pkt->readyTime); 148411678Swendy.elsasser@arm.com // New event, increment count 148511678Swendy.elsasser@arm.com ++dram_pkt->rankRef.outstandingEvents; 148611678Swendy.elsasser@arm.com 148711678Swendy.elsasser@arm.com } else if (dram_pkt->rankRef.writeDoneEvent.when() < 148811678Swendy.elsasser@arm.com dram_pkt-> readyTime) { 148911678Swendy.elsasser@arm.com reschedule(dram_pkt->rankRef.writeDoneEvent, dram_pkt->readyTime); 149011678Swendy.elsasser@arm.com } 149111678Swendy.elsasser@arm.com 149210889Sandreas.hansson@arm.com isInWriteQueue.erase(burstAlign(dram_pkt->addr)); 149310206Sandreas.hansson@arm.com delete dram_pkt; 149410206Sandreas.hansson@arm.com 149510206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 149610206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 149710206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 149810206Sandreas.hansson@arm.com // writes, then switch to reads. 149910206Sandreas.hansson@arm.com if (writeQueue.empty() || 150010206Sandreas.hansson@arm.com (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 150110913Sandreas.sandberg@arm.com drainState() != DrainState::Draining) || 150210206Sandreas.hansson@arm.com (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 150310206Sandreas.hansson@arm.com // turn the bus back around for reads again 150411678Swendy.elsasser@arm.com busStateNext = READ; 150510206Sandreas.hansson@arm.com 150610206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 150710206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 150810206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 150910206Sandreas.hansson@arm.com // nothing to do 151010206Sandreas.hansson@arm.com } 151110206Sandreas.hansson@arm.com } 151210618SOmar.Naji@arm.com // It is possible that a refresh to another rank kicks things back into 151310618SOmar.Naji@arm.com // action before reaching this point. 151410618SOmar.Naji@arm.com if (!nextReqEvent.scheduled()) 151510618SOmar.Naji@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 151610206Sandreas.hansson@arm.com 151710206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 151810206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 151910206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 152010206Sandreas.hansson@arm.com // the next request processing 152110206Sandreas.hansson@arm.com if (retryWrReq && writeQueue.size() < writeBufferSize) { 152210206Sandreas.hansson@arm.com retryWrReq = false; 152310713Sandreas.hansson@arm.com port.sendRetryReq(); 15249352SN/A } 15259243SN/A} 15269243SN/A 152710890Swendy.elsasser@arm.compair<uint64_t, bool> 152810393Swendy.elsasser@arm.comDRAMCtrl::minBankPrep(const deque<DRAMPacket*>& queue, 152910890Swendy.elsasser@arm.com Tick min_col_at) const 15309967SN/A{ 15319967SN/A uint64_t bank_mask = 0; 153210211Sandreas.hansson@arm.com Tick min_act_at = MaxTick; 15339967SN/A 153410890Swendy.elsasser@arm.com // latest Tick for which ACT can occur without incurring additoinal 153510890Swendy.elsasser@arm.com // delay on the data bus 153610890Swendy.elsasser@arm.com const Tick hidden_act_max = std::max(min_col_at - tRCD, curTick()); 153710393Swendy.elsasser@arm.com 153810890Swendy.elsasser@arm.com // Flag condition when burst can issue back-to-back with previous burst 153910890Swendy.elsasser@arm.com bool found_seamless_bank = false; 154010890Swendy.elsasser@arm.com 154110890Swendy.elsasser@arm.com // Flag condition when bank can be opened without incurring additional 154210890Swendy.elsasser@arm.com // delay on the data bus 154310890Swendy.elsasser@arm.com bool hidden_bank_prep = false; 154410393Swendy.elsasser@arm.com 154510393Swendy.elsasser@arm.com // determine if we have queued transactions targetting the 15469967SN/A // bank in question 15479967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 154810618SOmar.Naji@arm.com for (const auto& p : queue) { 154912266Sradhika.jagtap@arm.com if (p->rankRef.inRefIdleState()) 155010618SOmar.Naji@arm.com got_waiting[p->bankId] = true; 15519967SN/A } 15529967SN/A 155310890Swendy.elsasser@arm.com // Find command with optimal bank timing 155410890Swendy.elsasser@arm.com // Will prioritize commands that can issue seamlessly. 15559967SN/A for (int i = 0; i < ranksPerChannel; i++) { 15569967SN/A for (int j = 0; j < banksPerRank; j++) { 155710618SOmar.Naji@arm.com uint16_t bank_id = i * banksPerRank + j; 155810211Sandreas.hansson@arm.com 15599967SN/A // if we have waiting requests for the bank, and it is 15609967SN/A // amongst the first available, update the mask 156110211Sandreas.hansson@arm.com if (got_waiting[bank_id]) { 156210618SOmar.Naji@arm.com // make sure this rank is not currently refreshing. 156312266Sradhika.jagtap@arm.com assert(ranks[i]->inRefIdleState()); 156410211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue 156510211Sandreas.hansson@arm.com // an activate, ignoring any rank-to-rank switching 156610393Swendy.elsasser@arm.com // cost in this calculation 156710618SOmar.Naji@arm.com Tick act_at = ranks[i]->banks[j].openRow == Bank::NO_ROW ? 156810890Swendy.elsasser@arm.com std::max(ranks[i]->banks[j].actAllowedAt, curTick()) : 156910618SOmar.Naji@arm.com std::max(ranks[i]->banks[j].preAllowedAt, curTick()) + tRP; 157010211Sandreas.hansson@arm.com 157110890Swendy.elsasser@arm.com // When is the earliest the R/W burst can issue? 157210890Swendy.elsasser@arm.com Tick col_at = std::max(ranks[i]->banks[j].colAllowedAt, 157310890Swendy.elsasser@arm.com act_at + tRCD); 157410393Swendy.elsasser@arm.com 157510890Swendy.elsasser@arm.com // bank can issue burst back-to-back (seamlessly) with 157610890Swendy.elsasser@arm.com // previous burst 157710890Swendy.elsasser@arm.com bool new_seamless_bank = col_at <= min_col_at; 157810393Swendy.elsasser@arm.com 157910890Swendy.elsasser@arm.com // if we found a new seamless bank or we have no 158010890Swendy.elsasser@arm.com // seamless banks, and got a bank with an earlier 158110890Swendy.elsasser@arm.com // activate time, it should be added to the bit mask 158210890Swendy.elsasser@arm.com if (new_seamless_bank || 158310890Swendy.elsasser@arm.com (!found_seamless_bank && act_at <= min_act_at)) { 158410890Swendy.elsasser@arm.com // if we did not have a seamless bank before, and 158510890Swendy.elsasser@arm.com // we do now, reset the bank mask, also reset it 158610890Swendy.elsasser@arm.com // if we have not yet found a seamless bank and 158710890Swendy.elsasser@arm.com // the activate time is smaller than what we have 158810890Swendy.elsasser@arm.com // seen so far 158910890Swendy.elsasser@arm.com if (!found_seamless_bank && 159010890Swendy.elsasser@arm.com (new_seamless_bank || act_at < min_act_at)) { 159110890Swendy.elsasser@arm.com bank_mask = 0; 159210393Swendy.elsasser@arm.com } 159310890Swendy.elsasser@arm.com 159410890Swendy.elsasser@arm.com found_seamless_bank |= new_seamless_bank; 159510890Swendy.elsasser@arm.com 159610890Swendy.elsasser@arm.com // ACT can occur 'behind the scenes' 159710890Swendy.elsasser@arm.com hidden_bank_prep = act_at <= hidden_act_max; 159810890Swendy.elsasser@arm.com 159910890Swendy.elsasser@arm.com // set the bit corresponding to the available bank 160010890Swendy.elsasser@arm.com replaceBits(bank_mask, bank_id, bank_id, 1); 160110890Swendy.elsasser@arm.com min_act_at = act_at; 160210211Sandreas.hansson@arm.com } 16039967SN/A } 16049967SN/A } 16059967SN/A } 160610211Sandreas.hansson@arm.com 160710890Swendy.elsasser@arm.com return make_pair(bank_mask, hidden_bank_prep); 16089967SN/A} 16099967SN/A 161012081Sspwilson2@wisc.eduDRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p, int rank) 161110618SOmar.Naji@arm.com : EventManager(&_memory), memory(_memory), 161211678Swendy.elsasser@arm.com pwrStateTrans(PWR_IDLE), pwrStatePostRefresh(PWR_IDLE), 161311678Swendy.elsasser@arm.com pwrStateTick(0), refreshDueAt(0), pwrState(PWR_IDLE), 161412081Sspwilson2@wisc.edu refreshState(REF_IDLE), inLowPowerState(false), rank(rank), 161511678Swendy.elsasser@arm.com readEntries(0), writeEntries(0), outstandingEvents(0), 161612081Sspwilson2@wisc.edu wakeUpAllowedAt(0), power(_p, false), banks(_p->banks_per_rank), 161712081Sspwilson2@wisc.edu numBanksActive(0), actTicks(_p->activation_limit, 0), 161812084Sspwilson2@wisc.edu writeDoneEvent([this]{ processWriteDoneEvent(); }, name()), 161912084Sspwilson2@wisc.edu activateEvent([this]{ processActivateEvent(); }, name()), 162012084Sspwilson2@wisc.edu prechargeEvent([this]{ processPrechargeEvent(); }, name()), 162112084Sspwilson2@wisc.edu refreshEvent([this]{ processRefreshEvent(); }, name()), 162212084Sspwilson2@wisc.edu powerEvent([this]{ processPowerEvent(); }, name()), 162312084Sspwilson2@wisc.edu wakeUpEvent([this]{ processWakeUpEvent(); }, name()) 162412081Sspwilson2@wisc.edu{ 162512081Sspwilson2@wisc.edu for (int b = 0; b < _p->banks_per_rank; b++) { 162612081Sspwilson2@wisc.edu banks[b].bank = b; 162712081Sspwilson2@wisc.edu // GDDR addressing of banks to BG is linear. 162812081Sspwilson2@wisc.edu // Here we assume that all DRAM generations address bank groups as 162912081Sspwilson2@wisc.edu // follows: 163012081Sspwilson2@wisc.edu if (_p->bank_groups_per_rank > 0) { 163112081Sspwilson2@wisc.edu // Simply assign lower bits to bank group in order to 163212081Sspwilson2@wisc.edu // rotate across bank groups as banks are incremented 163312081Sspwilson2@wisc.edu // e.g. with 4 banks per bank group and 16 banks total: 163412081Sspwilson2@wisc.edu // banks 0,4,8,12 are in bank group 0 163512081Sspwilson2@wisc.edu // banks 1,5,9,13 are in bank group 1 163612081Sspwilson2@wisc.edu // banks 2,6,10,14 are in bank group 2 163712081Sspwilson2@wisc.edu // banks 3,7,11,15 are in bank group 3 163812081Sspwilson2@wisc.edu banks[b].bankgr = b % _p->bank_groups_per_rank; 163912081Sspwilson2@wisc.edu } else { 164012081Sspwilson2@wisc.edu // No bank groups; simply assign to bank number 164112081Sspwilson2@wisc.edu banks[b].bankgr = b; 164212081Sspwilson2@wisc.edu } 164312081Sspwilson2@wisc.edu } 164412081Sspwilson2@wisc.edu} 164510618SOmar.Naji@arm.com 16469243SN/Avoid 164710618SOmar.Naji@arm.comDRAMCtrl::Rank::startup(Tick ref_tick) 164810618SOmar.Naji@arm.com{ 164910618SOmar.Naji@arm.com assert(ref_tick > curTick()); 165010618SOmar.Naji@arm.com 165110618SOmar.Naji@arm.com pwrStateTick = curTick(); 165210618SOmar.Naji@arm.com 165310618SOmar.Naji@arm.com // kick off the refresh, and give ourselves enough time to 165410618SOmar.Naji@arm.com // precharge 165510618SOmar.Naji@arm.com schedule(refreshEvent, ref_tick); 165610618SOmar.Naji@arm.com} 165710618SOmar.Naji@arm.com 165810618SOmar.Naji@arm.comvoid 165910619Sandreas.hansson@arm.comDRAMCtrl::Rank::suspend() 166010619Sandreas.hansson@arm.com{ 166110619Sandreas.hansson@arm.com deschedule(refreshEvent); 166211676Swendy.elsasser@arm.com 166311676Swendy.elsasser@arm.com // Update the stats 166411676Swendy.elsasser@arm.com updatePowerStats(); 166511678Swendy.elsasser@arm.com 166611678Swendy.elsasser@arm.com // don't automatically transition back to LP state after next REF 166711678Swendy.elsasser@arm.com pwrStatePostRefresh = PWR_IDLE; 166811678Swendy.elsasser@arm.com} 166911678Swendy.elsasser@arm.com 167011678Swendy.elsasser@arm.combool 167111678Swendy.elsasser@arm.comDRAMCtrl::Rank::lowPowerEntryReady() const 167211678Swendy.elsasser@arm.com{ 167311678Swendy.elsasser@arm.com bool no_queued_cmds = ((memory.busStateNext == READ) && (readEntries == 0)) 167411678Swendy.elsasser@arm.com || ((memory.busStateNext == WRITE) && 167511678Swendy.elsasser@arm.com (writeEntries == 0)); 167611678Swendy.elsasser@arm.com 167711678Swendy.elsasser@arm.com if (refreshState == REF_RUN) { 167811678Swendy.elsasser@arm.com // have not decremented outstandingEvents for refresh command 167911678Swendy.elsasser@arm.com // still check if there are no commands queued to force PD 168011678Swendy.elsasser@arm.com // entry after refresh completes 168111678Swendy.elsasser@arm.com return no_queued_cmds; 168211678Swendy.elsasser@arm.com } else { 168311678Swendy.elsasser@arm.com // ensure no commands in Q and no commands scheduled 168411678Swendy.elsasser@arm.com return (no_queued_cmds && (outstandingEvents == 0)); 168511678Swendy.elsasser@arm.com } 168610619Sandreas.hansson@arm.com} 168710619Sandreas.hansson@arm.com 168810619Sandreas.hansson@arm.comvoid 168910618SOmar.Naji@arm.comDRAMCtrl::Rank::checkDrainDone() 169010618SOmar.Naji@arm.com{ 169110618SOmar.Naji@arm.com // if this rank was waiting to drain it is now able to proceed to 169210618SOmar.Naji@arm.com // precharge 169310618SOmar.Naji@arm.com if (refreshState == REF_DRAIN) { 169410618SOmar.Naji@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 169510618SOmar.Naji@arm.com 169611678Swendy.elsasser@arm.com refreshState = REF_PD_EXIT; 169710618SOmar.Naji@arm.com 169810618SOmar.Naji@arm.com // hand control back to the refresh event loop 169910618SOmar.Naji@arm.com schedule(refreshEvent, curTick()); 170010618SOmar.Naji@arm.com } 170110618SOmar.Naji@arm.com} 170210618SOmar.Naji@arm.com 170310618SOmar.Naji@arm.comvoid 170411675Swendy.elsasser@arm.comDRAMCtrl::Rank::flushCmdList() 170511675Swendy.elsasser@arm.com{ 170611675Swendy.elsasser@arm.com // at the moment sort the list of commands and update the counters 170711675Swendy.elsasser@arm.com // for DRAMPower libray when doing a refresh 170811675Swendy.elsasser@arm.com sort(cmdList.begin(), cmdList.end(), DRAMCtrl::sortTime); 170911675Swendy.elsasser@arm.com 171011675Swendy.elsasser@arm.com auto next_iter = cmdList.begin(); 171111675Swendy.elsasser@arm.com // push to commands to DRAMPower 171211675Swendy.elsasser@arm.com for ( ; next_iter != cmdList.end() ; ++next_iter) { 171311675Swendy.elsasser@arm.com Command cmd = *next_iter; 171411675Swendy.elsasser@arm.com if (cmd.timeStamp <= curTick()) { 171511675Swendy.elsasser@arm.com // Move all commands at or before curTick to DRAMPower 171611675Swendy.elsasser@arm.com power.powerlib.doCommand(cmd.type, cmd.bank, 171711675Swendy.elsasser@arm.com divCeil(cmd.timeStamp, memory.tCK) - 171811675Swendy.elsasser@arm.com memory.timeStampOffset); 171911675Swendy.elsasser@arm.com } else { 172011675Swendy.elsasser@arm.com // done - found all commands at or before curTick() 172111675Swendy.elsasser@arm.com // next_iter references the 1st command after curTick 172211675Swendy.elsasser@arm.com break; 172311675Swendy.elsasser@arm.com } 172411675Swendy.elsasser@arm.com } 172511675Swendy.elsasser@arm.com // reset cmdList to only contain commands after curTick 172611675Swendy.elsasser@arm.com // if there are no commands after curTick, updated cmdList will be empty 172711675Swendy.elsasser@arm.com // in this case, next_iter is cmdList.end() 172811675Swendy.elsasser@arm.com cmdList.assign(next_iter, cmdList.end()); 172911675Swendy.elsasser@arm.com} 173011675Swendy.elsasser@arm.com 173111675Swendy.elsasser@arm.comvoid 173210618SOmar.Naji@arm.comDRAMCtrl::Rank::processActivateEvent() 173310618SOmar.Naji@arm.com{ 173410618SOmar.Naji@arm.com // we should transition to the active state as soon as any bank is active 173510618SOmar.Naji@arm.com if (pwrState != PWR_ACT) 173610618SOmar.Naji@arm.com // note that at this point numBanksActive could be back at 173710618SOmar.Naji@arm.com // zero again due to a precharge scheduled in the future 173810618SOmar.Naji@arm.com schedulePowerEvent(PWR_ACT, curTick()); 173910618SOmar.Naji@arm.com} 174010618SOmar.Naji@arm.com 174110618SOmar.Naji@arm.comvoid 174210618SOmar.Naji@arm.comDRAMCtrl::Rank::processPrechargeEvent() 174310618SOmar.Naji@arm.com{ 174411678Swendy.elsasser@arm.com // counter should at least indicate one outstanding request 174511678Swendy.elsasser@arm.com // for this precharge 174611678Swendy.elsasser@arm.com assert(outstandingEvents > 0); 174711678Swendy.elsasser@arm.com // precharge complete, decrement count 174811678Swendy.elsasser@arm.com --outstandingEvents; 174911678Swendy.elsasser@arm.com 175010618SOmar.Naji@arm.com // if we reached zero, then special conditions apply as we track 175110618SOmar.Naji@arm.com // if all banks are precharged for the power models 175210618SOmar.Naji@arm.com if (numBanksActive == 0) { 175311678Swendy.elsasser@arm.com // no reads to this rank in the Q and no pending 175411678Swendy.elsasser@arm.com // RD/WR or refresh commands 175511678Swendy.elsasser@arm.com if (lowPowerEntryReady()) { 175611678Swendy.elsasser@arm.com // should still be in ACT state since bank still open 175711678Swendy.elsasser@arm.com assert(pwrState == PWR_ACT); 175811678Swendy.elsasser@arm.com 175911678Swendy.elsasser@arm.com // All banks closed - switch to precharge power down state. 176011678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleep at tick %d\n", 176111678Swendy.elsasser@arm.com rank, curTick()); 176211678Swendy.elsasser@arm.com powerDownSleep(PWR_PRE_PDN, curTick()); 176311678Swendy.elsasser@arm.com } else { 176411678Swendy.elsasser@arm.com // we should transition to the idle state when the last bank 176511678Swendy.elsasser@arm.com // is precharged 176611678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 176711678Swendy.elsasser@arm.com } 176810618SOmar.Naji@arm.com } 176910618SOmar.Naji@arm.com} 177010618SOmar.Naji@arm.com 177110618SOmar.Naji@arm.comvoid 177211678Swendy.elsasser@arm.comDRAMCtrl::Rank::processWriteDoneEvent() 177311678Swendy.elsasser@arm.com{ 177411678Swendy.elsasser@arm.com // counter should at least indicate one outstanding request 177511678Swendy.elsasser@arm.com // for this write 177611678Swendy.elsasser@arm.com assert(outstandingEvents > 0); 177711678Swendy.elsasser@arm.com // Write transfer on bus has completed 177811678Swendy.elsasser@arm.com // decrement per rank counter 177911678Swendy.elsasser@arm.com --outstandingEvents; 178011678Swendy.elsasser@arm.com} 178111678Swendy.elsasser@arm.com 178211678Swendy.elsasser@arm.comvoid 178310618SOmar.Naji@arm.comDRAMCtrl::Rank::processRefreshEvent() 17849243SN/A{ 178510207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 178611678Swendy.elsasser@arm.com if ((refreshState == REF_IDLE) || (refreshState == REF_SREF_EXIT)) { 178710207Sandreas.hansson@arm.com // remember when the refresh is due 178810207Sandreas.hansson@arm.com refreshDueAt = curTick(); 17899243SN/A 179010207Sandreas.hansson@arm.com // proceed to drain 179110207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 17929243SN/A 179311678Swendy.elsasser@arm.com // make nonzero while refresh is pending to ensure 179411678Swendy.elsasser@arm.com // power down and self-refresh are not entered 179511678Swendy.elsasser@arm.com ++outstandingEvents; 179611678Swendy.elsasser@arm.com 179710207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 179810207Sandreas.hansson@arm.com } 179910207Sandreas.hansson@arm.com 180010618SOmar.Naji@arm.com // let any scheduled read or write to the same rank go ahead, 180110618SOmar.Naji@arm.com // after which it will 180210207Sandreas.hansson@arm.com // hand control back to this event loop 180310207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 180410618SOmar.Naji@arm.com // if a request is at the moment being handled and this request is 180510618SOmar.Naji@arm.com // accessing the current rank then wait for it to finish 180610618SOmar.Naji@arm.com if ((rank == memory.activeRank) 180710618SOmar.Naji@arm.com && (memory.nextReqEvent.scheduled())) { 180810207Sandreas.hansson@arm.com // hand control over to the request loop until it is 180910207Sandreas.hansson@arm.com // evaluated next 181010207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 181110207Sandreas.hansson@arm.com 181210207Sandreas.hansson@arm.com return; 181310207Sandreas.hansson@arm.com } else { 181411678Swendy.elsasser@arm.com refreshState = REF_PD_EXIT; 181511678Swendy.elsasser@arm.com } 181611678Swendy.elsasser@arm.com } 181711678Swendy.elsasser@arm.com 181811678Swendy.elsasser@arm.com // at this point, ensure that rank is not in a power-down state 181911678Swendy.elsasser@arm.com if (refreshState == REF_PD_EXIT) { 182011678Swendy.elsasser@arm.com // if rank was sleeping and we have't started exit process, 182111678Swendy.elsasser@arm.com // wake-up for refresh 182211678Swendy.elsasser@arm.com if (inLowPowerState) { 182311678Swendy.elsasser@arm.com DPRINTF(DRAM, "Wake Up for refresh\n"); 182411678Swendy.elsasser@arm.com // save state and return after refresh completes 182511678Swendy.elsasser@arm.com scheduleWakeUpEvent(memory.tXP); 182611678Swendy.elsasser@arm.com return; 182711678Swendy.elsasser@arm.com } else { 182810207Sandreas.hansson@arm.com refreshState = REF_PRE; 182910207Sandreas.hansson@arm.com } 183010207Sandreas.hansson@arm.com } 183110207Sandreas.hansson@arm.com 183210207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 183310207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 183411678Swendy.elsasser@arm.com // precharge any active bank 183511678Swendy.elsasser@arm.com if (numBanksActive != 0) { 183610214Sandreas.hansson@arm.com // at the moment, we use a precharge all even if there is 183710214Sandreas.hansson@arm.com // only a single bank open 183810208Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 183910214Sandreas.hansson@arm.com 184010214Sandreas.hansson@arm.com // first determine when we can precharge 184110214Sandreas.hansson@arm.com Tick pre_at = curTick(); 184210618SOmar.Naji@arm.com 184310618SOmar.Naji@arm.com for (auto &b : banks) { 184410618SOmar.Naji@arm.com // respect both causality and any existing bank 184510618SOmar.Naji@arm.com // constraints, some banks could already have a 184610618SOmar.Naji@arm.com // (auto) precharge scheduled 184710618SOmar.Naji@arm.com pre_at = std::max(b.preAllowedAt, pre_at); 184810618SOmar.Naji@arm.com } 184910618SOmar.Naji@arm.com 185010618SOmar.Naji@arm.com // make sure all banks per rank are precharged, and for those that 185110618SOmar.Naji@arm.com // already are, update their availability 185210618SOmar.Naji@arm.com Tick act_allowed_at = pre_at + memory.tRP; 185310618SOmar.Naji@arm.com 185410618SOmar.Naji@arm.com for (auto &b : banks) { 185510618SOmar.Naji@arm.com if (b.openRow != Bank::NO_ROW) { 185610618SOmar.Naji@arm.com memory.prechargeBank(*this, b, pre_at, false); 185710618SOmar.Naji@arm.com } else { 185810618SOmar.Naji@arm.com b.actAllowedAt = std::max(b.actAllowedAt, act_allowed_at); 185910618SOmar.Naji@arm.com b.preAllowedAt = std::max(b.preAllowedAt, pre_at); 186010214Sandreas.hansson@arm.com } 186110214Sandreas.hansson@arm.com } 186210214Sandreas.hansson@arm.com 186310618SOmar.Naji@arm.com // precharge all banks in rank 186411675Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PREA, 0, pre_at)); 186510214Sandreas.hansson@arm.com 186610618SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PREA,0,%d\n", 186710618SOmar.Naji@arm.com divCeil(pre_at, memory.tCK) - 186810618SOmar.Naji@arm.com memory.timeStampOffset, rank); 186911678Swendy.elsasser@arm.com } else if ((pwrState == PWR_IDLE) && (outstandingEvents == 1)) { 187011678Swendy.elsasser@arm.com // Banks are closed, have transitioned to IDLE state, and 187111678Swendy.elsasser@arm.com // no outstanding ACT,RD/WR,Auto-PRE sequence scheduled 187210208Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 187310208Sandreas.hansson@arm.com 187411678Swendy.elsasser@arm.com // go ahead and kick the power state machine into gear since 187510208Sandreas.hansson@arm.com // we are already idle 187610208Sandreas.hansson@arm.com schedulePowerEvent(PWR_REF, curTick()); 187711678Swendy.elsasser@arm.com } else { 187811678Swendy.elsasser@arm.com // banks state is closed but haven't transitioned pwrState to IDLE 187911678Swendy.elsasser@arm.com // or have outstanding ACT,RD/WR,Auto-PRE sequence scheduled 188011678Swendy.elsasser@arm.com // should have outstanding precharge event in this case 188111678Swendy.elsasser@arm.com assert(prechargeEvent.scheduled()); 188211678Swendy.elsasser@arm.com // will start refresh when pwrState transitions to IDLE 18839975SN/A } 18849975SN/A 188510208Sandreas.hansson@arm.com assert(numBanksActive == 0); 18869243SN/A 188710208Sandreas.hansson@arm.com // wait for all banks to be precharged, at which point the 188810208Sandreas.hansson@arm.com // power state machine will transition to the idle state, and 188910208Sandreas.hansson@arm.com // automatically move to a refresh, at that point it will also 189010208Sandreas.hansson@arm.com // call this method to get the refresh event loop going again 189110207Sandreas.hansson@arm.com return; 189210207Sandreas.hansson@arm.com } 189310207Sandreas.hansson@arm.com 189410207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 189511678Swendy.elsasser@arm.com if (refreshState == REF_START) { 189611678Swendy.elsasser@arm.com // should never get here with any banks active 189711678Swendy.elsasser@arm.com assert(numBanksActive == 0); 189811678Swendy.elsasser@arm.com assert(pwrState == PWR_REF); 189911678Swendy.elsasser@arm.com 190011678Swendy.elsasser@arm.com Tick ref_done_at = curTick() + memory.tRFC; 190111678Swendy.elsasser@arm.com 190211678Swendy.elsasser@arm.com for (auto &b : banks) { 190311678Swendy.elsasser@arm.com b.actAllowedAt = ref_done_at; 190411678Swendy.elsasser@arm.com } 190511678Swendy.elsasser@arm.com 190611678Swendy.elsasser@arm.com // at the moment this affects all ranks 190711678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::REF, 0, curTick())); 190811678Swendy.elsasser@arm.com 190911678Swendy.elsasser@arm.com // Update the stats 191011678Swendy.elsasser@arm.com updatePowerStats(); 191111678Swendy.elsasser@arm.com 191211678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), memory.tCK) - 191311678Swendy.elsasser@arm.com memory.timeStampOffset, rank); 191411678Swendy.elsasser@arm.com 191511678Swendy.elsasser@arm.com // Update for next refresh 191611678Swendy.elsasser@arm.com refreshDueAt += memory.tREFI; 191711678Swendy.elsasser@arm.com 191811678Swendy.elsasser@arm.com // make sure we did not wait so long that we cannot make up 191911678Swendy.elsasser@arm.com // for it 192011678Swendy.elsasser@arm.com if (refreshDueAt < ref_done_at) { 192111678Swendy.elsasser@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 192211678Swendy.elsasser@arm.com } 192311678Swendy.elsasser@arm.com 192411678Swendy.elsasser@arm.com // Run the refresh and schedule event to transition power states 192511678Swendy.elsasser@arm.com // when refresh completes 192611678Swendy.elsasser@arm.com refreshState = REF_RUN; 192711678Swendy.elsasser@arm.com schedule(refreshEvent, ref_done_at); 192811678Swendy.elsasser@arm.com return; 192911678Swendy.elsasser@arm.com } 193011678Swendy.elsasser@arm.com 193110207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 193210207Sandreas.hansson@arm.com // should never get here with any banks active 193310207Sandreas.hansson@arm.com assert(numBanksActive == 0); 193410208Sandreas.hansson@arm.com assert(pwrState == PWR_REF); 193510207Sandreas.hansson@arm.com 193611678Swendy.elsasser@arm.com assert(!powerEvent.scheduled()); 193711678Swendy.elsasser@arm.com 193811678Swendy.elsasser@arm.com if ((memory.drainState() == DrainState::Draining) || 193911678Swendy.elsasser@arm.com (memory.drainState() == DrainState::Drained)) { 194011678Swendy.elsasser@arm.com // if draining, do not re-enter low-power mode. 194111678Swendy.elsasser@arm.com // simply go to IDLE and wait 194211678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 194311678Swendy.elsasser@arm.com } else { 194411678Swendy.elsasser@arm.com // At the moment, we sleep when the refresh ends and wait to be 194511678Swendy.elsasser@arm.com // woken up again if previously in a low-power state. 194611678Swendy.elsasser@arm.com if (pwrStatePostRefresh != PWR_IDLE) { 194711678Swendy.elsasser@arm.com // power State should be power Refresh 194811678Swendy.elsasser@arm.com assert(pwrState == PWR_REF); 194911678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleeping after refresh and was in " 195011678Swendy.elsasser@arm.com "power state %d before refreshing\n", rank, 195111678Swendy.elsasser@arm.com pwrStatePostRefresh); 195211678Swendy.elsasser@arm.com powerDownSleep(pwrState, curTick()); 195311678Swendy.elsasser@arm.com 195411678Swendy.elsasser@arm.com // Force PRE power-down if there are no outstanding commands 195511678Swendy.elsasser@arm.com // in Q after refresh. 195611678Swendy.elsasser@arm.com } else if (lowPowerEntryReady()) { 195711678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleeping after refresh but was NOT" 195811678Swendy.elsasser@arm.com " in a low power state before refreshing\n", rank); 195911678Swendy.elsasser@arm.com powerDownSleep(PWR_PRE_PDN, curTick()); 196011678Swendy.elsasser@arm.com 196111678Swendy.elsasser@arm.com } else { 196211678Swendy.elsasser@arm.com // move to the idle power state once the refresh is done, this 196311678Swendy.elsasser@arm.com // will also move the refresh state machine to the refresh 196411678Swendy.elsasser@arm.com // idle state 196511678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 196611678Swendy.elsasser@arm.com } 196710618SOmar.Naji@arm.com } 196810247Sandreas.hansson@arm.com 196911678Swendy.elsasser@arm.com // if transitioning to self refresh do not schedule a new refresh; 197011678Swendy.elsasser@arm.com // when waking from self refresh, a refresh is scheduled again. 197111678Swendy.elsasser@arm.com if (pwrStateTrans != PWR_SREF) { 197211678Swendy.elsasser@arm.com // compensate for the delay in actually performing the refresh 197311678Swendy.elsasser@arm.com // when scheduling the next one 197411678Swendy.elsasser@arm.com schedule(refreshEvent, refreshDueAt - memory.tRP); 197511678Swendy.elsasser@arm.com 197611678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Refresh done at %llu and next refresh" 197711678Swendy.elsasser@arm.com " at %llu\n", curTick(), refreshDueAt); 197810207Sandreas.hansson@arm.com } 197910208Sandreas.hansson@arm.com } 198010208Sandreas.hansson@arm.com} 198110208Sandreas.hansson@arm.com 198210208Sandreas.hansson@arm.comvoid 198310618SOmar.Naji@arm.comDRAMCtrl::Rank::schedulePowerEvent(PowerState pwr_state, Tick tick) 198410208Sandreas.hansson@arm.com{ 198510208Sandreas.hansson@arm.com // respect causality 198610208Sandreas.hansson@arm.com assert(tick >= curTick()); 198710208Sandreas.hansson@arm.com 198810208Sandreas.hansson@arm.com if (!powerEvent.scheduled()) { 198910208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 199010208Sandreas.hansson@arm.com tick, pwr_state); 199110208Sandreas.hansson@arm.com 199210208Sandreas.hansson@arm.com // insert the new transition 199310208Sandreas.hansson@arm.com pwrStateTrans = pwr_state; 199410208Sandreas.hansson@arm.com 199510208Sandreas.hansson@arm.com schedule(powerEvent, tick); 199610208Sandreas.hansson@arm.com } else { 199710208Sandreas.hansson@arm.com panic("Scheduled power event at %llu to state %d, " 199810208Sandreas.hansson@arm.com "with scheduled event at %llu to %d\n", tick, pwr_state, 199910208Sandreas.hansson@arm.com powerEvent.when(), pwrStateTrans); 200010208Sandreas.hansson@arm.com } 200110208Sandreas.hansson@arm.com} 200210208Sandreas.hansson@arm.com 200310208Sandreas.hansson@arm.comvoid 200411678Swendy.elsasser@arm.comDRAMCtrl::Rank::powerDownSleep(PowerState pwr_state, Tick tick) 200511678Swendy.elsasser@arm.com{ 200611678Swendy.elsasser@arm.com // if low power state is active low, schedule to active low power state. 200711678Swendy.elsasser@arm.com // in reality tCKE is needed to enter active low power. This is neglected 200811678Swendy.elsasser@arm.com // here and could be added in the future. 200911678Swendy.elsasser@arm.com if (pwr_state == PWR_ACT_PDN) { 201011678Swendy.elsasser@arm.com schedulePowerEvent(pwr_state, tick); 201111678Swendy.elsasser@arm.com // push command to DRAMPower 201211678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PDN_F_ACT, 0, tick)); 201311678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PDN_F_ACT,0,%d\n", divCeil(tick, 201411678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 201511678Swendy.elsasser@arm.com } else if (pwr_state == PWR_PRE_PDN) { 201611678Swendy.elsasser@arm.com // if low power state is precharge low, schedule to precharge low 201711678Swendy.elsasser@arm.com // power state. In reality tCKE is needed to enter active low power. 201811678Swendy.elsasser@arm.com // This is neglected here. 201911678Swendy.elsasser@arm.com schedulePowerEvent(pwr_state, tick); 202011678Swendy.elsasser@arm.com //push Command to DRAMPower 202111678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PDN_F_PRE, 0, tick)); 202211678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PDN_F_PRE,0,%d\n", divCeil(tick, 202311678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 202411678Swendy.elsasser@arm.com } else if (pwr_state == PWR_REF) { 202511678Swendy.elsasser@arm.com // if a refresh just occured 202611678Swendy.elsasser@arm.com // transition to PRE_PDN now that all banks are closed 202711678Swendy.elsasser@arm.com // do not transition to SREF if commands are in Q; stay in PRE_PDN 202811678Swendy.elsasser@arm.com if (pwrStatePostRefresh == PWR_ACT_PDN || !lowPowerEntryReady()) { 202911678Swendy.elsasser@arm.com // prechage power down requires tCKE to enter. For simplicity 203011678Swendy.elsasser@arm.com // this is not considered. 203111678Swendy.elsasser@arm.com schedulePowerEvent(PWR_PRE_PDN, tick); 203211678Swendy.elsasser@arm.com //push Command to DRAMPower 203311678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PDN_F_PRE, 0, tick)); 203411678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PDN_F_PRE,0,%d\n", divCeil(tick, 203511678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 203611678Swendy.elsasser@arm.com } else { 203711678Swendy.elsasser@arm.com // last low power State was power precharge 203811678Swendy.elsasser@arm.com assert(pwrStatePostRefresh == PWR_PRE_PDN); 203911678Swendy.elsasser@arm.com // self refresh requires time tCKESR to enter. For simplicity, 204011678Swendy.elsasser@arm.com // this is not considered. 204111678Swendy.elsasser@arm.com schedulePowerEvent(PWR_SREF, tick); 204211678Swendy.elsasser@arm.com // push Command to DRAMPower 204311678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::SREN, 0, tick)); 204411678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,SREN,0,%d\n", divCeil(tick, 204511678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 204611678Swendy.elsasser@arm.com } 204711678Swendy.elsasser@arm.com } 204811678Swendy.elsasser@arm.com // Ensure that we don't power-down and back up in same tick 204911678Swendy.elsasser@arm.com // Once we commit to PD entry, do it and wait for at least 1tCK 205011678Swendy.elsasser@arm.com // This could be replaced with tCKE if/when that is added to the model 205111678Swendy.elsasser@arm.com wakeUpAllowedAt = tick + memory.tCK; 205211678Swendy.elsasser@arm.com 205311678Swendy.elsasser@arm.com // Transitioning to a low power state, set flag 205411678Swendy.elsasser@arm.com inLowPowerState = true; 205511678Swendy.elsasser@arm.com} 205611678Swendy.elsasser@arm.com 205711678Swendy.elsasser@arm.comvoid 205811678Swendy.elsasser@arm.comDRAMCtrl::Rank::scheduleWakeUpEvent(Tick exit_delay) 205911678Swendy.elsasser@arm.com{ 206011678Swendy.elsasser@arm.com Tick wake_up_tick = std::max(curTick(), wakeUpAllowedAt); 206111678Swendy.elsasser@arm.com 206211678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Scheduling wake-up for rank %d at tick %d\n", 206311678Swendy.elsasser@arm.com rank, wake_up_tick); 206411678Swendy.elsasser@arm.com 206511678Swendy.elsasser@arm.com // if waking for refresh, hold previous state 206611678Swendy.elsasser@arm.com // else reset state back to IDLE 206711678Swendy.elsasser@arm.com if (refreshState == REF_PD_EXIT) { 206811678Swendy.elsasser@arm.com pwrStatePostRefresh = pwrState; 206911678Swendy.elsasser@arm.com } else { 207011678Swendy.elsasser@arm.com // don't automatically transition back to LP state after next REF 207111678Swendy.elsasser@arm.com pwrStatePostRefresh = PWR_IDLE; 207211678Swendy.elsasser@arm.com } 207311678Swendy.elsasser@arm.com 207411678Swendy.elsasser@arm.com // schedule wake-up with event to ensure entry has completed before 207511678Swendy.elsasser@arm.com // we try to wake-up 207611678Swendy.elsasser@arm.com schedule(wakeUpEvent, wake_up_tick); 207711678Swendy.elsasser@arm.com 207811678Swendy.elsasser@arm.com for (auto &b : banks) { 207911678Swendy.elsasser@arm.com // respect both causality and any existing bank 208011678Swendy.elsasser@arm.com // constraints, some banks could already have a 208111678Swendy.elsasser@arm.com // (auto) precharge scheduled 208211678Swendy.elsasser@arm.com b.colAllowedAt = std::max(wake_up_tick + exit_delay, b.colAllowedAt); 208311678Swendy.elsasser@arm.com b.preAllowedAt = std::max(wake_up_tick + exit_delay, b.preAllowedAt); 208411678Swendy.elsasser@arm.com b.actAllowedAt = std::max(wake_up_tick + exit_delay, b.actAllowedAt); 208511678Swendy.elsasser@arm.com } 208611678Swendy.elsasser@arm.com // Transitioning out of low power state, clear flag 208711678Swendy.elsasser@arm.com inLowPowerState = false; 208811678Swendy.elsasser@arm.com 208911678Swendy.elsasser@arm.com // push to DRAMPower 209011678Swendy.elsasser@arm.com // use pwrStateTrans for cases where we have a power event scheduled 209111678Swendy.elsasser@arm.com // to enter low power that has not yet been processed 209211678Swendy.elsasser@arm.com if (pwrStateTrans == PWR_ACT_PDN) { 209311678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PUP_ACT, 0, wake_up_tick)); 209411678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PUP_ACT,0,%d\n", divCeil(wake_up_tick, 209511678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 209611678Swendy.elsasser@arm.com 209711678Swendy.elsasser@arm.com } else if (pwrStateTrans == PWR_PRE_PDN) { 209811678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PUP_PRE, 0, wake_up_tick)); 209911678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PUP_PRE,0,%d\n", divCeil(wake_up_tick, 210011678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 210111678Swendy.elsasser@arm.com } else if (pwrStateTrans == PWR_SREF) { 210211678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::SREX, 0, wake_up_tick)); 210311678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,SREX,0,%d\n", divCeil(wake_up_tick, 210411678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 210511678Swendy.elsasser@arm.com } 210611678Swendy.elsasser@arm.com} 210711678Swendy.elsasser@arm.com 210811678Swendy.elsasser@arm.comvoid 210911678Swendy.elsasser@arm.comDRAMCtrl::Rank::processWakeUpEvent() 211011678Swendy.elsasser@arm.com{ 211111678Swendy.elsasser@arm.com // Should be in a power-down or self-refresh state 211211678Swendy.elsasser@arm.com assert((pwrState == PWR_ACT_PDN) || (pwrState == PWR_PRE_PDN) || 211311678Swendy.elsasser@arm.com (pwrState == PWR_SREF)); 211411678Swendy.elsasser@arm.com 211511678Swendy.elsasser@arm.com // Check current state to determine transition state 211611678Swendy.elsasser@arm.com if (pwrState == PWR_ACT_PDN) { 211711678Swendy.elsasser@arm.com // banks still open, transition to PWR_ACT 211811678Swendy.elsasser@arm.com schedulePowerEvent(PWR_ACT, curTick()); 211911678Swendy.elsasser@arm.com } else { 212011678Swendy.elsasser@arm.com // transitioning from a precharge power-down or self-refresh state 212111678Swendy.elsasser@arm.com // banks are closed - transition to PWR_IDLE 212211678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 212311678Swendy.elsasser@arm.com } 212411678Swendy.elsasser@arm.com} 212511678Swendy.elsasser@arm.com 212611678Swendy.elsasser@arm.comvoid 212710618SOmar.Naji@arm.comDRAMCtrl::Rank::processPowerEvent() 212810208Sandreas.hansson@arm.com{ 212911678Swendy.elsasser@arm.com assert(curTick() >= pwrStateTick); 213010208Sandreas.hansson@arm.com // remember where we were, and for how long 213110208Sandreas.hansson@arm.com Tick duration = curTick() - pwrStateTick; 213210208Sandreas.hansson@arm.com PowerState prev_state = pwrState; 213310208Sandreas.hansson@arm.com 213410208Sandreas.hansson@arm.com // update the accounting 213510208Sandreas.hansson@arm.com pwrStateTime[prev_state] += duration; 213610208Sandreas.hansson@arm.com 213711678Swendy.elsasser@arm.com // track to total idle time 213811678Swendy.elsasser@arm.com if ((prev_state == PWR_PRE_PDN) || (prev_state == PWR_ACT_PDN) || 213911678Swendy.elsasser@arm.com (prev_state == PWR_SREF)) { 214011678Swendy.elsasser@arm.com totalIdleTime += duration; 214111678Swendy.elsasser@arm.com } 214211678Swendy.elsasser@arm.com 214310208Sandreas.hansson@arm.com pwrState = pwrStateTrans; 214410208Sandreas.hansson@arm.com pwrStateTick = curTick(); 214510208Sandreas.hansson@arm.com 214611678Swendy.elsasser@arm.com // if rank was refreshing, make sure to start scheduling requests again 214711678Swendy.elsasser@arm.com if (prev_state == PWR_REF) { 214811678Swendy.elsasser@arm.com // bus IDLED prior to REF 214911678Swendy.elsasser@arm.com // counter should be one for refresh command only 215011678Swendy.elsasser@arm.com assert(outstandingEvents == 1); 215111678Swendy.elsasser@arm.com // REF complete, decrement count 215211678Swendy.elsasser@arm.com --outstandingEvents; 215311678Swendy.elsasser@arm.com 215411678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 215511678Swendy.elsasser@arm.com // if sleeping after refresh 215611678Swendy.elsasser@arm.com if (pwrState != PWR_IDLE) { 215711678Swendy.elsasser@arm.com assert((pwrState == PWR_PRE_PDN) || (pwrState == PWR_SREF)); 215811678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Switching to power down state after refreshing" 215911678Swendy.elsasser@arm.com " rank %d at %llu tick\n", rank, curTick()); 216011678Swendy.elsasser@arm.com } 216111678Swendy.elsasser@arm.com if (pwrState != PWR_SREF) { 216211678Swendy.elsasser@arm.com // rank is not available in SREF 216311678Swendy.elsasser@arm.com // don't transition to IDLE in this case 216411678Swendy.elsasser@arm.com refreshState = REF_IDLE; 216511678Swendy.elsasser@arm.com } 216611678Swendy.elsasser@arm.com // a request event could be already scheduled by the state 216711678Swendy.elsasser@arm.com // machine of the other rank 216811678Swendy.elsasser@arm.com if (!memory.nextReqEvent.scheduled()) { 216911678Swendy.elsasser@arm.com DPRINTF(DRAM, "Scheduling next request after refreshing rank %d\n", 217011678Swendy.elsasser@arm.com rank); 217111678Swendy.elsasser@arm.com schedule(memory.nextReqEvent, curTick()); 217211678Swendy.elsasser@arm.com } 217311678Swendy.elsasser@arm.com } else if (pwrState == PWR_ACT) { 217411678Swendy.elsasser@arm.com if (refreshState == REF_PD_EXIT) { 217511678Swendy.elsasser@arm.com // kick the refresh event loop into action again 217611678Swendy.elsasser@arm.com assert(prev_state == PWR_ACT_PDN); 217711678Swendy.elsasser@arm.com 217811678Swendy.elsasser@arm.com // go back to REF event and close banks 217911678Swendy.elsasser@arm.com refreshState = REF_PRE; 218011678Swendy.elsasser@arm.com schedule(refreshEvent, curTick()); 218111678Swendy.elsasser@arm.com } 218211678Swendy.elsasser@arm.com } else if (pwrState == PWR_IDLE) { 218310208Sandreas.hansson@arm.com DPRINTF(DRAMState, "All banks precharged\n"); 218411678Swendy.elsasser@arm.com if (prev_state == PWR_SREF) { 218512266Sradhika.jagtap@arm.com // set refresh state to REF_SREF_EXIT, ensuring inRefIdleState 218611678Swendy.elsasser@arm.com // continues to return false during tXS after SREF exit 218711678Swendy.elsasser@arm.com // Schedule a refresh which kicks things back into action 218811678Swendy.elsasser@arm.com // when it finishes 218911678Swendy.elsasser@arm.com refreshState = REF_SREF_EXIT; 219011678Swendy.elsasser@arm.com schedule(refreshEvent, curTick() + memory.tXS); 219110208Sandreas.hansson@arm.com } else { 219210208Sandreas.hansson@arm.com // if we have a pending refresh, and are now moving to 219311678Swendy.elsasser@arm.com // the idle state, directly transition to a refresh 219411678Swendy.elsasser@arm.com if ((refreshState == REF_PRE) || (refreshState == REF_PD_EXIT)) { 219511678Swendy.elsasser@arm.com // ensure refresh is restarted only after final PRE command. 219611678Swendy.elsasser@arm.com // do not restart refresh if controller is in an intermediate 219711678Swendy.elsasser@arm.com // state, after PRE_PDN exit, when banks are IDLE but an 219811678Swendy.elsasser@arm.com // ACT is scheduled. 219911678Swendy.elsasser@arm.com if (!activateEvent.scheduled()) { 220011678Swendy.elsasser@arm.com // there should be nothing waiting at this point 220111678Swendy.elsasser@arm.com assert(!powerEvent.scheduled()); 220211678Swendy.elsasser@arm.com // update the state in zero time and proceed below 220311678Swendy.elsasser@arm.com pwrState = PWR_REF; 220411678Swendy.elsasser@arm.com } else { 220511678Swendy.elsasser@arm.com // must have PRE scheduled to transition back to IDLE 220611678Swendy.elsasser@arm.com // and re-kick off refresh 220711678Swendy.elsasser@arm.com assert(prechargeEvent.scheduled()); 220811678Swendy.elsasser@arm.com } 220910208Sandreas.hansson@arm.com } 221011678Swendy.elsasser@arm.com } 221110208Sandreas.hansson@arm.com } 221210208Sandreas.hansson@arm.com 221310208Sandreas.hansson@arm.com // we transition to the refresh state, let the refresh state 221410208Sandreas.hansson@arm.com // machine know of this state update and let it deal with the 221510208Sandreas.hansson@arm.com // scheduling of the next power state transition as well as the 221610208Sandreas.hansson@arm.com // following refresh 221710208Sandreas.hansson@arm.com if (pwrState == PWR_REF) { 221811678Swendy.elsasser@arm.com assert(refreshState == REF_PRE || refreshState == REF_PD_EXIT); 221910208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refreshing\n"); 222011678Swendy.elsasser@arm.com 222110208Sandreas.hansson@arm.com // kick the refresh event loop into action again, and that 222210208Sandreas.hansson@arm.com // in turn will schedule a transition to the idle power 222310208Sandreas.hansson@arm.com // state once the refresh is done 222411678Swendy.elsasser@arm.com if (refreshState == REF_PD_EXIT) { 222511678Swendy.elsasser@arm.com // Wait for PD exit timing to complete before issuing REF 222611678Swendy.elsasser@arm.com schedule(refreshEvent, curTick() + memory.tXP); 222711678Swendy.elsasser@arm.com } else { 222811678Swendy.elsasser@arm.com schedule(refreshEvent, curTick()); 222911678Swendy.elsasser@arm.com } 223011678Swendy.elsasser@arm.com // Banks transitioned to IDLE, start REF 223111678Swendy.elsasser@arm.com refreshState = REF_START; 223210207Sandreas.hansson@arm.com } 22339243SN/A} 22349243SN/A 22359243SN/Avoid 223610618SOmar.Naji@arm.comDRAMCtrl::Rank::updatePowerStats() 223710432SOmar.Naji@arm.com{ 223811676Swendy.elsasser@arm.com // All commands up to refresh have completed 223911676Swendy.elsasser@arm.com // flush cmdList to DRAMPower 224011676Swendy.elsasser@arm.com flushCmdList(); 224111676Swendy.elsasser@arm.com 224212266Sradhika.jagtap@arm.com // Call the function that calculates window energy at intermediate update 224312266Sradhika.jagtap@arm.com // events like at refresh, stats dump as well as at simulation exit. 224412266Sradhika.jagtap@arm.com // Window starts at the last time the calcWindowEnergy function was called 224512266Sradhika.jagtap@arm.com // and is upto current time. 224612266Sradhika.jagtap@arm.com power.powerlib.calcWindowEnergy(divCeil(curTick(), memory.tCK) - 224712266Sradhika.jagtap@arm.com memory.timeStampOffset); 224812266Sradhika.jagtap@arm.com 224912266Sradhika.jagtap@arm.com // Get the energy from DRAMPower 225012266Sradhika.jagtap@arm.com Data::MemoryPowerModel::Energy energy = power.powerlib.getEnergy(); 225112266Sradhika.jagtap@arm.com 225212266Sradhika.jagtap@arm.com // The energy components inside the power lib are calculated over 225312266Sradhika.jagtap@arm.com // the window so accumulate into the corresponding gem5 stat 225412266Sradhika.jagtap@arm.com actEnergy += energy.act_energy * memory.devicesPerRank; 225512266Sradhika.jagtap@arm.com preEnergy += energy.pre_energy * memory.devicesPerRank; 225612266Sradhika.jagtap@arm.com readEnergy += energy.read_energy * memory.devicesPerRank; 225712266Sradhika.jagtap@arm.com writeEnergy += energy.write_energy * memory.devicesPerRank; 225812266Sradhika.jagtap@arm.com refreshEnergy += energy.ref_energy * memory.devicesPerRank; 225912266Sradhika.jagtap@arm.com actBackEnergy += energy.act_stdby_energy * memory.devicesPerRank; 226012266Sradhika.jagtap@arm.com preBackEnergy += energy.pre_stdby_energy * memory.devicesPerRank; 226112266Sradhika.jagtap@arm.com actPowerDownEnergy += energy.f_act_pd_energy * memory.devicesPerRank; 226212266Sradhika.jagtap@arm.com prePowerDownEnergy += energy.f_pre_pd_energy * memory.devicesPerRank; 226312266Sradhika.jagtap@arm.com selfRefreshEnergy += energy.sref_energy * memory.devicesPerRank; 226412266Sradhika.jagtap@arm.com 226512266Sradhika.jagtap@arm.com // Accumulate window energy into the total energy. 226612266Sradhika.jagtap@arm.com totalEnergy += energy.window_energy * memory.devicesPerRank; 226712266Sradhika.jagtap@arm.com // Average power must not be accumulated but calculated over the time 226812266Sradhika.jagtap@arm.com // since last stats reset. SimClock::Frequency is tick period not tick 226912266Sradhika.jagtap@arm.com // frequency. 227012266Sradhika.jagtap@arm.com // energy (pJ) 1e-9 227112266Sradhika.jagtap@arm.com // power (mW) = ----------- * ---------- 227212266Sradhika.jagtap@arm.com // time (tick) tick_frequency 227312266Sradhika.jagtap@arm.com averagePower = (totalEnergy.value() / 227412266Sradhika.jagtap@arm.com (curTick() - memory.lastStatsResetTick)) * 227512266Sradhika.jagtap@arm.com (SimClock::Frequency / 1000000000.0); 227610432SOmar.Naji@arm.com} 227710432SOmar.Naji@arm.com 227810432SOmar.Naji@arm.comvoid 227911677Swendy.elsasser@arm.comDRAMCtrl::Rank::computeStats() 228011677Swendy.elsasser@arm.com{ 228112266Sradhika.jagtap@arm.com DPRINTF(DRAM,"Computing stats due to a dump callback\n"); 228211677Swendy.elsasser@arm.com 228311677Swendy.elsasser@arm.com // Update the stats 228411677Swendy.elsasser@arm.com updatePowerStats(); 228511677Swendy.elsasser@arm.com 228611677Swendy.elsasser@arm.com // final update of power state times 228711677Swendy.elsasser@arm.com pwrStateTime[pwrState] += (curTick() - pwrStateTick); 228811677Swendy.elsasser@arm.com pwrStateTick = curTick(); 228911677Swendy.elsasser@arm.com 229011677Swendy.elsasser@arm.com} 229111677Swendy.elsasser@arm.com 229211677Swendy.elsasser@arm.comvoid 229312266Sradhika.jagtap@arm.comDRAMCtrl::Rank::resetStats() { 229412266Sradhika.jagtap@arm.com // The only way to clear the counters in DRAMPower is to call 229512266Sradhika.jagtap@arm.com // calcWindowEnergy function as that then calls clearCounters. The 229612266Sradhika.jagtap@arm.com // clearCounters method itself is private. 229712266Sradhika.jagtap@arm.com power.powerlib.calcWindowEnergy(divCeil(curTick(), memory.tCK) - 229812266Sradhika.jagtap@arm.com memory.timeStampOffset); 229912266Sradhika.jagtap@arm.com 230012266Sradhika.jagtap@arm.com} 230112266Sradhika.jagtap@arm.com 230212266Sradhika.jagtap@arm.comvoid 230310618SOmar.Naji@arm.comDRAMCtrl::Rank::regStats() 230410618SOmar.Naji@arm.com{ 230510618SOmar.Naji@arm.com pwrStateTime 230611678Swendy.elsasser@arm.com .init(6) 230710618SOmar.Naji@arm.com .name(name() + ".memoryStateTime") 230810618SOmar.Naji@arm.com .desc("Time in different power states"); 230910618SOmar.Naji@arm.com pwrStateTime.subname(0, "IDLE"); 231010618SOmar.Naji@arm.com pwrStateTime.subname(1, "REF"); 231111678Swendy.elsasser@arm.com pwrStateTime.subname(2, "SREF"); 231211678Swendy.elsasser@arm.com pwrStateTime.subname(3, "PRE_PDN"); 231311678Swendy.elsasser@arm.com pwrStateTime.subname(4, "ACT"); 231411678Swendy.elsasser@arm.com pwrStateTime.subname(5, "ACT_PDN"); 231510618SOmar.Naji@arm.com 231610618SOmar.Naji@arm.com actEnergy 231710618SOmar.Naji@arm.com .name(name() + ".actEnergy") 231810618SOmar.Naji@arm.com .desc("Energy for activate commands per rank (pJ)"); 231910618SOmar.Naji@arm.com 232010618SOmar.Naji@arm.com preEnergy 232110618SOmar.Naji@arm.com .name(name() + ".preEnergy") 232210618SOmar.Naji@arm.com .desc("Energy for precharge commands per rank (pJ)"); 232310618SOmar.Naji@arm.com 232410618SOmar.Naji@arm.com readEnergy 232510618SOmar.Naji@arm.com .name(name() + ".readEnergy") 232610618SOmar.Naji@arm.com .desc("Energy for read commands per rank (pJ)"); 232710618SOmar.Naji@arm.com 232810618SOmar.Naji@arm.com writeEnergy 232910618SOmar.Naji@arm.com .name(name() + ".writeEnergy") 233010618SOmar.Naji@arm.com .desc("Energy for write commands per rank (pJ)"); 233110618SOmar.Naji@arm.com 233210618SOmar.Naji@arm.com refreshEnergy 233310618SOmar.Naji@arm.com .name(name() + ".refreshEnergy") 233410618SOmar.Naji@arm.com .desc("Energy for refresh commands per rank (pJ)"); 233510618SOmar.Naji@arm.com 233610618SOmar.Naji@arm.com actBackEnergy 233710618SOmar.Naji@arm.com .name(name() + ".actBackEnergy") 233810618SOmar.Naji@arm.com .desc("Energy for active background per rank (pJ)"); 233910618SOmar.Naji@arm.com 234010618SOmar.Naji@arm.com preBackEnergy 234110618SOmar.Naji@arm.com .name(name() + ".preBackEnergy") 234210618SOmar.Naji@arm.com .desc("Energy for precharge background per rank (pJ)"); 234310618SOmar.Naji@arm.com 234411678Swendy.elsasser@arm.com actPowerDownEnergy 234511678Swendy.elsasser@arm.com .name(name() + ".actPowerDownEnergy") 234611678Swendy.elsasser@arm.com .desc("Energy for active power-down per rank (pJ)"); 234711678Swendy.elsasser@arm.com 234811678Swendy.elsasser@arm.com prePowerDownEnergy 234911678Swendy.elsasser@arm.com .name(name() + ".prePowerDownEnergy") 235011678Swendy.elsasser@arm.com .desc("Energy for precharge power-down per rank (pJ)"); 235111678Swendy.elsasser@arm.com 235211678Swendy.elsasser@arm.com selfRefreshEnergy 235311678Swendy.elsasser@arm.com .name(name() + ".selfRefreshEnergy") 235411678Swendy.elsasser@arm.com .desc("Energy for self refresh per rank (pJ)"); 235511678Swendy.elsasser@arm.com 235610618SOmar.Naji@arm.com totalEnergy 235710618SOmar.Naji@arm.com .name(name() + ".totalEnergy") 235810618SOmar.Naji@arm.com .desc("Total energy per rank (pJ)"); 235910618SOmar.Naji@arm.com 236010618SOmar.Naji@arm.com averagePower 236110618SOmar.Naji@arm.com .name(name() + ".averagePower") 236210618SOmar.Naji@arm.com .desc("Core power per rank (mW)"); 236311677Swendy.elsasser@arm.com 236411678Swendy.elsasser@arm.com totalIdleTime 236511678Swendy.elsasser@arm.com .name(name() + ".totalIdleTime") 236611678Swendy.elsasser@arm.com .desc("Total Idle time Per DRAM Rank"); 236711678Swendy.elsasser@arm.com 236812637Sodanrc@yahoo.com.br Stats::registerDumpCallback(new RankDumpCallback(this)); 236912637Sodanrc@yahoo.com.br Stats::registerResetCallback(new RankResetCallback(this)); 237010618SOmar.Naji@arm.com} 237110618SOmar.Naji@arm.comvoid 237210146Sandreas.hansson@arm.comDRAMCtrl::regStats() 23739243SN/A{ 23749243SN/A using namespace Stats; 23759243SN/A 23769243SN/A AbstractMemory::regStats(); 23779243SN/A 237810618SOmar.Naji@arm.com for (auto r : ranks) { 237910618SOmar.Naji@arm.com r->regStats(); 238010618SOmar.Naji@arm.com } 238110618SOmar.Naji@arm.com 238212266Sradhika.jagtap@arm.com registerResetCallback(new MemResetCallback(this)); 238312266Sradhika.jagtap@arm.com 23849243SN/A readReqs 23859243SN/A .name(name() + ".readReqs") 23869977SN/A .desc("Number of read requests accepted"); 23879243SN/A 23889243SN/A writeReqs 23899243SN/A .name(name() + ".writeReqs") 23909977SN/A .desc("Number of write requests accepted"); 23919831SN/A 23929831SN/A readBursts 23939831SN/A .name(name() + ".readBursts") 23949977SN/A .desc("Number of DRAM read bursts, " 23959977SN/A "including those serviced by the write queue"); 23969831SN/A 23979831SN/A writeBursts 23989831SN/A .name(name() + ".writeBursts") 23999977SN/A .desc("Number of DRAM write bursts, " 24009977SN/A "including those merged in the write queue"); 24019243SN/A 24029243SN/A servicedByWrQ 24039243SN/A .name(name() + ".servicedByWrQ") 24049977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 24059977SN/A 24069977SN/A mergedWrBursts 24079977SN/A .name(name() + ".mergedWrBursts") 24089977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 24099243SN/A 24109243SN/A neitherReadNorWrite 24119977SN/A .name(name() + ".neitherReadNorWriteReqs") 24129977SN/A .desc("Number of requests that are neither read nor write"); 24139243SN/A 24149977SN/A perBankRdBursts 24159243SN/A .init(banksPerRank * ranksPerChannel) 24169977SN/A .name(name() + ".perBankRdBursts") 24179977SN/A .desc("Per bank write bursts"); 24189243SN/A 24199977SN/A perBankWrBursts 24209243SN/A .init(banksPerRank * ranksPerChannel) 24219977SN/A .name(name() + ".perBankWrBursts") 24229977SN/A .desc("Per bank write bursts"); 24239243SN/A 24249243SN/A avgRdQLen 24259243SN/A .name(name() + ".avgRdQLen") 24269977SN/A .desc("Average read queue length when enqueuing") 24279243SN/A .precision(2); 24289243SN/A 24299243SN/A avgWrQLen 24309243SN/A .name(name() + ".avgWrQLen") 24319977SN/A .desc("Average write queue length when enqueuing") 24329243SN/A .precision(2); 24339243SN/A 24349243SN/A totQLat 24359243SN/A .name(name() + ".totQLat") 24369977SN/A .desc("Total ticks spent queuing"); 24379243SN/A 24389243SN/A totBusLat 24399243SN/A .name(name() + ".totBusLat") 24409977SN/A .desc("Total ticks spent in databus transfers"); 24419243SN/A 24429243SN/A totMemAccLat 24439243SN/A .name(name() + ".totMemAccLat") 24449977SN/A .desc("Total ticks spent from burst creation until serviced " 24459977SN/A "by the DRAM"); 24469243SN/A 24479243SN/A avgQLat 24489243SN/A .name(name() + ".avgQLat") 24499977SN/A .desc("Average queueing delay per DRAM burst") 24509243SN/A .precision(2); 24519243SN/A 24529831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 24539243SN/A 24549243SN/A avgBusLat 24559243SN/A .name(name() + ".avgBusLat") 24569977SN/A .desc("Average bus latency per DRAM burst") 24579243SN/A .precision(2); 24589243SN/A 24599831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 24609243SN/A 24619243SN/A avgMemAccLat 24629243SN/A .name(name() + ".avgMemAccLat") 24639977SN/A .desc("Average memory access latency per DRAM burst") 24649243SN/A .precision(2); 24659243SN/A 24669831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 24679243SN/A 24689243SN/A numRdRetry 24699243SN/A .name(name() + ".numRdRetry") 24709977SN/A .desc("Number of times read queue was full causing retry"); 24719243SN/A 24729243SN/A numWrRetry 24739243SN/A .name(name() + ".numWrRetry") 24749977SN/A .desc("Number of times write queue was full causing retry"); 24759243SN/A 24769243SN/A readRowHits 24779243SN/A .name(name() + ".readRowHits") 24789243SN/A .desc("Number of row buffer hits during reads"); 24799243SN/A 24809243SN/A writeRowHits 24819243SN/A .name(name() + ".writeRowHits") 24829243SN/A .desc("Number of row buffer hits during writes"); 24839243SN/A 24849243SN/A readRowHitRate 24859243SN/A .name(name() + ".readRowHitRate") 24869243SN/A .desc("Row buffer hit rate for reads") 24879243SN/A .precision(2); 24889243SN/A 24899831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 24909243SN/A 24919243SN/A writeRowHitRate 24929243SN/A .name(name() + ".writeRowHitRate") 24939243SN/A .desc("Row buffer hit rate for writes") 24949243SN/A .precision(2); 24959243SN/A 24969977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 24979243SN/A 24989243SN/A readPktSize 24999831SN/A .init(ceilLog2(burstSize) + 1) 25009243SN/A .name(name() + ".readPktSize") 25019977SN/A .desc("Read request sizes (log2)"); 25029243SN/A 25039243SN/A writePktSize 25049831SN/A .init(ceilLog2(burstSize) + 1) 25059243SN/A .name(name() + ".writePktSize") 25069977SN/A .desc("Write request sizes (log2)"); 25079243SN/A 25089243SN/A rdQLenPdf 25099567SN/A .init(readBufferSize) 25109243SN/A .name(name() + ".rdQLenPdf") 25119243SN/A .desc("What read queue length does an incoming req see"); 25129243SN/A 25139243SN/A wrQLenPdf 25149567SN/A .init(writeBufferSize) 25159243SN/A .name(name() + ".wrQLenPdf") 25169243SN/A .desc("What write queue length does an incoming req see"); 25179243SN/A 25189727SN/A bytesPerActivate 251910141SN/A .init(maxAccessesPerRow) 25209727SN/A .name(name() + ".bytesPerActivate") 25219727SN/A .desc("Bytes accessed per row activation") 25229727SN/A .flags(nozero); 25239243SN/A 252410147Sandreas.hansson@arm.com rdPerTurnAround 252510147Sandreas.hansson@arm.com .init(readBufferSize) 252610147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 252710147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 252810147Sandreas.hansson@arm.com .flags(nozero); 252910147Sandreas.hansson@arm.com 253010147Sandreas.hansson@arm.com wrPerTurnAround 253110147Sandreas.hansson@arm.com .init(writeBufferSize) 253210147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 253310147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 253410147Sandreas.hansson@arm.com .flags(nozero); 253510147Sandreas.hansson@arm.com 25369975SN/A bytesReadDRAM 25379975SN/A .name(name() + ".bytesReadDRAM") 25389975SN/A .desc("Total number of bytes read from DRAM"); 25399975SN/A 25409975SN/A bytesReadWrQ 25419975SN/A .name(name() + ".bytesReadWrQ") 25429975SN/A .desc("Total number of bytes read from write queue"); 25439243SN/A 25449243SN/A bytesWritten 25459243SN/A .name(name() + ".bytesWritten") 25469977SN/A .desc("Total number of bytes written to DRAM"); 25479243SN/A 25489977SN/A bytesReadSys 25499977SN/A .name(name() + ".bytesReadSys") 25509977SN/A .desc("Total read bytes from the system interface side"); 25519243SN/A 25529977SN/A bytesWrittenSys 25539977SN/A .name(name() + ".bytesWrittenSys") 25549977SN/A .desc("Total written bytes from the system interface side"); 25559243SN/A 25569243SN/A avgRdBW 25579243SN/A .name(name() + ".avgRdBW") 25589977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 25599243SN/A .precision(2); 25609243SN/A 25619977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 25629243SN/A 25639243SN/A avgWrBW 25649243SN/A .name(name() + ".avgWrBW") 25659977SN/A .desc("Average achieved write bandwidth in MiByte/s") 25669243SN/A .precision(2); 25679243SN/A 25689243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 25699243SN/A 25709977SN/A avgRdBWSys 25719977SN/A .name(name() + ".avgRdBWSys") 25729977SN/A .desc("Average system read bandwidth in MiByte/s") 25739243SN/A .precision(2); 25749243SN/A 25759977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 25769243SN/A 25779977SN/A avgWrBWSys 25789977SN/A .name(name() + ".avgWrBWSys") 25799977SN/A .desc("Average system write bandwidth in MiByte/s") 25809243SN/A .precision(2); 25819243SN/A 25829977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 25839243SN/A 25849243SN/A peakBW 25859243SN/A .name(name() + ".peakBW") 25869977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 25879243SN/A .precision(2); 25889243SN/A 25899831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 25909243SN/A 25919243SN/A busUtil 25929243SN/A .name(name() + ".busUtil") 25939243SN/A .desc("Data bus utilization in percentage") 25949243SN/A .precision(2); 25959243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 25969243SN/A 25979243SN/A totGap 25989243SN/A .name(name() + ".totGap") 25999243SN/A .desc("Total gap between requests"); 26009243SN/A 26019243SN/A avgGap 26029243SN/A .name(name() + ".avgGap") 26039243SN/A .desc("Average gap between requests") 26049243SN/A .precision(2); 26059243SN/A 26069243SN/A avgGap = totGap / (readReqs + writeReqs); 26079975SN/A 26089975SN/A // Stats for DRAM Power calculation based on Micron datasheet 26099975SN/A busUtilRead 26109975SN/A .name(name() + ".busUtilRead") 26119975SN/A .desc("Data bus utilization in percentage for reads") 26129975SN/A .precision(2); 26139975SN/A 26149975SN/A busUtilRead = avgRdBW / peakBW * 100; 26159975SN/A 26169975SN/A busUtilWrite 26179975SN/A .name(name() + ".busUtilWrite") 26189975SN/A .desc("Data bus utilization in percentage for writes") 26199975SN/A .precision(2); 26209975SN/A 26219975SN/A busUtilWrite = avgWrBW / peakBW * 100; 26229975SN/A 26239975SN/A pageHitRate 26249975SN/A .name(name() + ".pageHitRate") 26259975SN/A .desc("Row buffer hit rate, read and write combined") 26269975SN/A .precision(2); 26279975SN/A 26289977SN/A pageHitRate = (writeRowHits + readRowHits) / 26299977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 26309243SN/A} 26319243SN/A 26329243SN/Avoid 263310146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 26349243SN/A{ 26359243SN/A // rely on the abstract memory 26369243SN/A functionalAccess(pkt); 26379243SN/A} 26389243SN/A 26399294SN/ABaseSlavePort& 264010146Sandreas.hansson@arm.comDRAMCtrl::getSlavePort(const string &if_name, PortID idx) 26419243SN/A{ 26429243SN/A if (if_name != "port") { 26439243SN/A return MemObject::getSlavePort(if_name, idx); 26449243SN/A } else { 26459243SN/A return port; 26469243SN/A } 26479243SN/A} 26489243SN/A 264910913Sandreas.sandberg@arm.comDrainState 265010913Sandreas.sandberg@arm.comDRAMCtrl::drain() 26519243SN/A{ 26529243SN/A // if there is anything in any of our internal queues, keep track 26539243SN/A // of that as well 265411676Swendy.elsasser@arm.com if (!(writeQueue.empty() && readQueue.empty() && respQueue.empty() && 265511676Swendy.elsasser@arm.com allRanksDrained())) { 265611676Swendy.elsasser@arm.com 26579352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 26589567SN/A " resp: %d\n", writeQueue.size(), readQueue.size(), 26599567SN/A respQueue.size()); 266010206Sandreas.hansson@arm.com 266111678Swendy.elsasser@arm.com // the only queue that is not drained automatically over time 266210206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 266310206Sandreas.hansson@arm.com if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 266410206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 266510206Sandreas.hansson@arm.com } 266611678Swendy.elsasser@arm.com 266711678Swendy.elsasser@arm.com // also need to kick off events to exit self-refresh 266811678Swendy.elsasser@arm.com for (auto r : ranks) { 266911678Swendy.elsasser@arm.com // force self-refresh exit, which in turn will issue auto-refresh 267011678Swendy.elsasser@arm.com if (r->pwrState == PWR_SREF) { 267111678Swendy.elsasser@arm.com DPRINTF(DRAM,"Rank%d: Forcing self-refresh wakeup in drain\n", 267211678Swendy.elsasser@arm.com r->rank); 267311678Swendy.elsasser@arm.com r->scheduleWakeUpEvent(tXS); 267411678Swendy.elsasser@arm.com } 267511678Swendy.elsasser@arm.com } 267611678Swendy.elsasser@arm.com 267710913Sandreas.sandberg@arm.com return DrainState::Draining; 267810912Sandreas.sandberg@arm.com } else { 267910913Sandreas.sandberg@arm.com return DrainState::Drained; 26809243SN/A } 26819243SN/A} 26829243SN/A 268311676Swendy.elsasser@arm.combool 268411676Swendy.elsasser@arm.comDRAMCtrl::allRanksDrained() const 268511676Swendy.elsasser@arm.com{ 268611676Swendy.elsasser@arm.com // true until proven false 268711676Swendy.elsasser@arm.com bool all_ranks_drained = true; 268811676Swendy.elsasser@arm.com for (auto r : ranks) { 268912266Sradhika.jagtap@arm.com // then verify that the power state is IDLE ensuring all banks are 269012266Sradhika.jagtap@arm.com // closed and rank is not in a low power state. Also verify that rank 269112266Sradhika.jagtap@arm.com // is idle from a refresh point of view. 269212266Sradhika.jagtap@arm.com all_ranks_drained = r->inPwrIdleState() && r->inRefIdleState() && 269312266Sradhika.jagtap@arm.com all_ranks_drained; 269411676Swendy.elsasser@arm.com } 269511676Swendy.elsasser@arm.com return all_ranks_drained; 269611676Swendy.elsasser@arm.com} 269711676Swendy.elsasser@arm.com 269810619Sandreas.hansson@arm.comvoid 269910619Sandreas.hansson@arm.comDRAMCtrl::drainResume() 270010619Sandreas.hansson@arm.com{ 270110619Sandreas.hansson@arm.com if (!isTimingMode && system()->isTimingMode()) { 270210619Sandreas.hansson@arm.com // if we switched to timing mode, kick things into action, 270310619Sandreas.hansson@arm.com // and behave as if we restored from a checkpoint 270410619Sandreas.hansson@arm.com startup(); 270510619Sandreas.hansson@arm.com } else if (isTimingMode && !system()->isTimingMode()) { 270610619Sandreas.hansson@arm.com // if we switch from timing mode, stop the refresh events to 270710619Sandreas.hansson@arm.com // not cause issues with KVM 270810619Sandreas.hansson@arm.com for (auto r : ranks) { 270910619Sandreas.hansson@arm.com r->suspend(); 271010619Sandreas.hansson@arm.com } 271110619Sandreas.hansson@arm.com } 271210619Sandreas.hansson@arm.com 271310619Sandreas.hansson@arm.com // update the mode 271410619Sandreas.hansson@arm.com isTimingMode = system()->isTimingMode(); 271510619Sandreas.hansson@arm.com} 271610619Sandreas.hansson@arm.com 271710146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 27189243SN/A : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 27199243SN/A memory(_memory) 27209243SN/A{ } 27219243SN/A 27229243SN/AAddrRangeList 272310146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 27249243SN/A{ 27259243SN/A AddrRangeList ranges; 27269243SN/A ranges.push_back(memory.getAddrRange()); 27279243SN/A return ranges; 27289243SN/A} 27299243SN/A 27309243SN/Avoid 273110146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 27329243SN/A{ 27339243SN/A pkt->pushLabel(memory.name()); 27349243SN/A 27359243SN/A if (!queue.checkFunctional(pkt)) { 27369243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 27379243SN/A // calls recvAtomic() and throws away the latency; we can save a 27389243SN/A // little here by just not calculating the latency. 27399243SN/A memory.recvFunctional(pkt); 27409243SN/A } 27419243SN/A 27429243SN/A pkt->popLabel(); 27439243SN/A} 27449243SN/A 27459243SN/ATick 274610146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 27479243SN/A{ 27489243SN/A return memory.recvAtomic(pkt); 27499243SN/A} 27509243SN/A 27519243SN/Abool 275210146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 27539243SN/A{ 27549243SN/A // pass it to the memory controller 27559243SN/A return memory.recvTimingReq(pkt); 27569243SN/A} 27579243SN/A 275810146Sandreas.hansson@arm.comDRAMCtrl* 275910146Sandreas.hansson@arm.comDRAMCtrlParams::create() 27609243SN/A{ 276110146Sandreas.hansson@arm.com return new DRAMCtrl(this); 27629243SN/A} 2763