dram_ctrl.cc revision 12084
19243SN/A/* 211846Swendy.elsasser@arm.com * Copyright (c) 2010-2017 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 4310618SOmar.Naji@arm.com * Omar Naji 4411678Swendy.elsasser@arm.com * Wendy Elsasser 459243SN/A */ 469243SN/A 4711793Sbrandon.potter@amd.com#include "mem/dram_ctrl.hh" 4811793Sbrandon.potter@amd.com 4910146Sandreas.hansson@arm.com#include "base/bitfield.hh" 509356SN/A#include "base/trace.hh" 5110146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 5210247Sandreas.hansson@arm.com#include "debug/DRAMPower.hh" 5310208Sandreas.hansson@arm.com#include "debug/DRAMState.hh" 549352SN/A#include "debug/Drain.hh" 559814SN/A#include "sim/system.hh" 569243SN/A 579243SN/Ausing namespace std; 5810432SOmar.Naji@arm.comusing namespace Data; 599243SN/A 6010146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 619243SN/A AbstractMemory(p), 6210619Sandreas.hansson@arm.com port(name() + ".port", *this), isTimingMode(false), 639243SN/A retryRdReq(false), retryWrReq(false), 6410211Sandreas.hansson@arm.com busState(READ), 6511678Swendy.elsasser@arm.com busStateNext(READ), 6612084Sspwilson2@wisc.edu nextReqEvent([this]{ processNextReqEvent(); }, name()), 6712084Sspwilson2@wisc.edu respondEvent([this]{ processRespondEvent(); }, name()), 6810489SOmar.Naji@arm.com deviceSize(p->device_size), 699831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 709831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 719831SN/A devicesPerRank(p->devices_per_rank), 729831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 739831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 7410140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 7510646Sandreas.hansson@arm.com columnsPerStripe(range.interleaved() ? range.granularity() / burstSize : 1), 769243SN/A ranksPerChannel(p->ranks_per_channel), 7710394Swendy.elsasser@arm.com bankGroupsPerRank(p->bank_groups_per_rank), 7810394Swendy.elsasser@arm.com bankGroupArch(p->bank_groups_per_rank > 0), 799566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 809243SN/A readBufferSize(p->read_buffer_size), 819243SN/A writeBufferSize(p->write_buffer_size), 8210140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 8310140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 8410147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 8510147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 8610393Swendy.elsasser@arm.com tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST), 8710394Swendy.elsasser@arm.com tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), 8810394Swendy.elsasser@arm.com tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 8911673SOmar.Naji@arm.com tRRD_L(p->tRRD_L), tXAW(p->tXAW), tXP(p->tXP), tXS(p->tXS), 9011673SOmar.Naji@arm.com activationLimit(p->activation_limit), 919243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 929243SN/A pageMgmt(p->page_policy), 9310141SN/A maxAccessesPerRow(p->max_accesses_per_row), 949726SN/A frontendLatency(p->static_frontend_latency), 959726SN/A backendLatency(p->static_backend_latency), 9610618SOmar.Naji@arm.com busBusyUntil(0), prevArrival(0), 9710618SOmar.Naji@arm.com nextReqTime(0), activeRank(0), timeStampOffset(0) 989243SN/A{ 9910620Sandreas.hansson@arm.com // sanity check the ranks since we rely on bit slicing for the 10010620Sandreas.hansson@arm.com // address decoding 10110620Sandreas.hansson@arm.com fatal_if(!isPowerOf2(ranksPerChannel), "DRAM rank count of %d is not " 10210620Sandreas.hansson@arm.com "allowed, must be a power of two\n", ranksPerChannel); 10310620Sandreas.hansson@arm.com 10410889Sandreas.hansson@arm.com fatal_if(!isPowerOf2(burstSize), "DRAM burst size %d is not allowed, " 10510889Sandreas.hansson@arm.com "must be a power of two\n", burstSize); 10610889Sandreas.hansson@arm.com 10710618SOmar.Naji@arm.com for (int i = 0; i < ranksPerChannel; i++) { 10812081Sspwilson2@wisc.edu Rank* rank = new Rank(*this, p, i); 10910618SOmar.Naji@arm.com ranks.push_back(rank); 11010246Sandreas.hansson@arm.com } 11110246Sandreas.hansson@arm.com 11210140SN/A // perform a basic check of the write thresholds 11310140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 11410140SN/A fatal("Write buffer low threshold %d must be smaller than the " 11510140SN/A "high threshold %d\n", p->write_low_thresh_perc, 11610140SN/A p->write_high_thresh_perc); 1179243SN/A 1189243SN/A // determine the rows per bank by looking at the total capacity 1199567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1209243SN/A 12110489SOmar.Naji@arm.com // determine the dram actual capacity from the DRAM config in Mbytes 12210489SOmar.Naji@arm.com uint64_t deviceCapacity = deviceSize / (1024 * 1024) * devicesPerRank * 12310489SOmar.Naji@arm.com ranksPerChannel; 12410489SOmar.Naji@arm.com 12510489SOmar.Naji@arm.com // if actual DRAM size does not match memory capacity in system warn! 12610489SOmar.Naji@arm.com if (deviceCapacity != capacity / (1024 * 1024)) 12710489SOmar.Naji@arm.com warn("DRAM device capacity (%d Mbytes) does not match the " 12810489SOmar.Naji@arm.com "address range assigned (%d Mbytes)\n", deviceCapacity, 12910489SOmar.Naji@arm.com capacity / (1024 * 1024)); 13010489SOmar.Naji@arm.com 1319243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1329243SN/A AbstractMemory::size()); 1339831SN/A 1349831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1359831SN/A rowBufferSize, columnsPerRowBuffer); 1369831SN/A 1379831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1389243SN/A 13910207Sandreas.hansson@arm.com // some basic sanity checks 14010207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 14110207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 14210207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 14310207Sandreas.hansson@arm.com } 14410394Swendy.elsasser@arm.com 14510394Swendy.elsasser@arm.com // basic bank group architecture checks -> 14610394Swendy.elsasser@arm.com if (bankGroupArch) { 14710394Swendy.elsasser@arm.com // must have at least one bank per bank group 14810394Swendy.elsasser@arm.com if (bankGroupsPerRank > banksPerRank) { 14910394Swendy.elsasser@arm.com fatal("banks per rank (%d) must be equal to or larger than " 15010394Swendy.elsasser@arm.com "banks groups per rank (%d)\n", 15110394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 15210394Swendy.elsasser@arm.com } 15310394Swendy.elsasser@arm.com // must have same number of banks in each bank group 15410394Swendy.elsasser@arm.com if ((banksPerRank % bankGroupsPerRank) != 0) { 15510394Swendy.elsasser@arm.com fatal("Banks per rank (%d) must be evenly divisible by bank groups " 15610394Swendy.elsasser@arm.com "per rank (%d) for equal banks per bank group\n", 15710394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 15810394Swendy.elsasser@arm.com } 15910394Swendy.elsasser@arm.com // tCCD_L should be greater than minimal, back-to-back burst delay 16010394Swendy.elsasser@arm.com if (tCCD_L <= tBURST) { 16110394Swendy.elsasser@arm.com fatal("tCCD_L (%d) should be larger than tBURST (%d) when " 16210394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 16310394Swendy.elsasser@arm.com tCCD_L, tBURST, bankGroupsPerRank); 16410394Swendy.elsasser@arm.com } 16510394Swendy.elsasser@arm.com // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay 16610561SOmar.Naji@arm.com // some datasheets might specify it equal to tRRD 16710561SOmar.Naji@arm.com if (tRRD_L < tRRD) { 16810394Swendy.elsasser@arm.com fatal("tRRD_L (%d) should be larger than tRRD (%d) when " 16910394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 17010394Swendy.elsasser@arm.com tRRD_L, tRRD, bankGroupsPerRank); 17110394Swendy.elsasser@arm.com } 17210394Swendy.elsasser@arm.com } 17310394Swendy.elsasser@arm.com 1749243SN/A} 1759243SN/A 1769243SN/Avoid 17710146Sandreas.hansson@arm.comDRAMCtrl::init() 17810140SN/A{ 17910466Sandreas.hansson@arm.com AbstractMemory::init(); 18010466Sandreas.hansson@arm.com 18110466Sandreas.hansson@arm.com if (!port.isConnected()) { 18210146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 18310140SN/A } else { 18410140SN/A port.sendRangeChange(); 18510140SN/A } 18610646Sandreas.hansson@arm.com 18710646Sandreas.hansson@arm.com // a bit of sanity checks on the interleaving, save it for here to 18810646Sandreas.hansson@arm.com // ensure that the system pointer is initialised 18910646Sandreas.hansson@arm.com if (range.interleaved()) { 19010646Sandreas.hansson@arm.com if (channels != range.stripes()) 19110646Sandreas.hansson@arm.com fatal("%s has %d interleaved address stripes but %d channel(s)\n", 19210646Sandreas.hansson@arm.com name(), range.stripes(), channels); 19310646Sandreas.hansson@arm.com 19410646Sandreas.hansson@arm.com if (addrMapping == Enums::RoRaBaChCo) { 19510646Sandreas.hansson@arm.com if (rowBufferSize != range.granularity()) { 19610646Sandreas.hansson@arm.com fatal("Channel interleaving of %s doesn't match RoRaBaChCo " 19710646Sandreas.hansson@arm.com "address map\n", name()); 19810646Sandreas.hansson@arm.com } 19910646Sandreas.hansson@arm.com } else if (addrMapping == Enums::RoRaBaCoCh || 20010646Sandreas.hansson@arm.com addrMapping == Enums::RoCoRaBaCh) { 20110646Sandreas.hansson@arm.com // for the interleavings with channel bits in the bottom, 20210646Sandreas.hansson@arm.com // if the system uses a channel striping granularity that 20310646Sandreas.hansson@arm.com // is larger than the DRAM burst size, then map the 20410646Sandreas.hansson@arm.com // sequential accesses within a stripe to a number of 20510646Sandreas.hansson@arm.com // columns in the DRAM, effectively placing some of the 20610646Sandreas.hansson@arm.com // lower-order column bits as the least-significant bits 20710646Sandreas.hansson@arm.com // of the address (above the ones denoting the burst size) 20810646Sandreas.hansson@arm.com assert(columnsPerStripe >= 1); 20910646Sandreas.hansson@arm.com 21010646Sandreas.hansson@arm.com // channel striping has to be done at a granularity that 21110646Sandreas.hansson@arm.com // is equal or larger to a cache line 21210646Sandreas.hansson@arm.com if (system()->cacheLineSize() > range.granularity()) { 21310646Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at least as large " 21410646Sandreas.hansson@arm.com "as the cache line size\n", name()); 21510646Sandreas.hansson@arm.com } 21610646Sandreas.hansson@arm.com 21710646Sandreas.hansson@arm.com // ...and equal or smaller than the row-buffer size 21810646Sandreas.hansson@arm.com if (rowBufferSize < range.granularity()) { 21910646Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at most as large " 22010646Sandreas.hansson@arm.com "as the row-buffer size\n", name()); 22110646Sandreas.hansson@arm.com } 22210646Sandreas.hansson@arm.com // this is essentially the check above, so just to be sure 22310646Sandreas.hansson@arm.com assert(columnsPerStripe <= columnsPerRowBuffer); 22410646Sandreas.hansson@arm.com } 22510646Sandreas.hansson@arm.com } 22610140SN/A} 22710140SN/A 22810140SN/Avoid 22910146Sandreas.hansson@arm.comDRAMCtrl::startup() 2309243SN/A{ 23110619Sandreas.hansson@arm.com // remember the memory system mode of operation 23210619Sandreas.hansson@arm.com isTimingMode = system()->isTimingMode(); 23310618SOmar.Naji@arm.com 23410619Sandreas.hansson@arm.com if (isTimingMode) { 23510619Sandreas.hansson@arm.com // timestamp offset should be in clock cycles for DRAMPower 23610619Sandreas.hansson@arm.com timeStampOffset = divCeil(curTick(), tCK); 23710619Sandreas.hansson@arm.com 23810619Sandreas.hansson@arm.com // update the start tick for the precharge accounting to the 23910619Sandreas.hansson@arm.com // current tick 24010619Sandreas.hansson@arm.com for (auto r : ranks) { 24110619Sandreas.hansson@arm.com r->startup(curTick() + tREFI - tRP); 24210619Sandreas.hansson@arm.com } 24310619Sandreas.hansson@arm.com 24410619Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 24510619Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 24610619Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 24710619Sandreas.hansson@arm.com // start of simulation 24810619Sandreas.hansson@arm.com busBusyUntil = curTick() + tRP + tRCD + tCL; 24910618SOmar.Naji@arm.com } 2509243SN/A} 2519243SN/A 2529243SN/ATick 25310146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 2549243SN/A{ 2559243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 2569243SN/A 25711334Sandreas.hansson@arm.com panic_if(pkt->cacheResponding(), "Should not see packets where cache " 25811334Sandreas.hansson@arm.com "is responding"); 25911334Sandreas.hansson@arm.com 2609243SN/A // do the actual memory access and turn the packet into a response 2619243SN/A access(pkt); 2629243SN/A 2639243SN/A Tick latency = 0; 26411334Sandreas.hansson@arm.com if (pkt->hasData()) { 2659243SN/A // this value is not supposed to be accurate, just enough to 2669243SN/A // keep things going, mimic a closed page 2679243SN/A latency = tRP + tRCD + tCL; 2689243SN/A } 2699243SN/A return latency; 2709243SN/A} 2719243SN/A 2729243SN/Abool 27310146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 2749243SN/A{ 2759831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 2769831SN/A readBufferSize, readQueue.size() + respQueue.size(), 2779831SN/A neededEntries); 2789243SN/A 2799831SN/A return 2809831SN/A (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 2819243SN/A} 2829243SN/A 2839243SN/Abool 28410146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 2859243SN/A{ 2869831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 2879831SN/A writeBufferSize, writeQueue.size(), neededEntries); 2889831SN/A return (writeQueue.size() + neededEntries) > writeBufferSize; 2899243SN/A} 2909243SN/A 29110146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 29210146Sandreas.hansson@arm.comDRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 29310143SN/A bool isRead) 2949243SN/A{ 2959669SN/A // decode the address based on the address mapping scheme, with 29610136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 29710136SN/A // channel, respectively 2989243SN/A uint8_t rank; 2999967SN/A uint8_t bank; 30010245Sandreas.hansson@arm.com // use a 64-bit unsigned during the computations as the row is 30110245Sandreas.hansson@arm.com // always the top bits, and check before creating the DRAMPacket 30210245Sandreas.hansson@arm.com uint64_t row; 3039243SN/A 30410286Sandreas.hansson@arm.com // truncate the address to a DRAM burst, which makes it unique to 30510286Sandreas.hansson@arm.com // a specific column, row, bank, rank and channel 3069831SN/A Addr addr = dramPktAddr / burstSize; 3079243SN/A 3089491SN/A // we have removed the lowest order address bits that denote the 3099831SN/A // position within the column 31010136SN/A if (addrMapping == Enums::RoRaBaChCo) { 3119491SN/A // the lowest order bits denote the column to ensure that 3129491SN/A // sequential cache lines occupy the same row 3139831SN/A addr = addr / columnsPerRowBuffer; 3149243SN/A 3159669SN/A // take out the channel part of the address 3169566SN/A addr = addr / channels; 3179566SN/A 3189669SN/A // after the channel bits, get the bank bits to interleave 3199669SN/A // over the banks 3209669SN/A bank = addr % banksPerRank; 3219669SN/A addr = addr / banksPerRank; 3229669SN/A 3239669SN/A // after the bank, we get the rank bits which thus interleaves 3249669SN/A // over the ranks 3259669SN/A rank = addr % ranksPerChannel; 3269669SN/A addr = addr / ranksPerChannel; 3279669SN/A 32811189Sandreas.hansson@arm.com // lastly, get the row bits, no need to remove them from addr 3299669SN/A row = addr % rowsPerBank; 33010136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 33110286Sandreas.hansson@arm.com // take out the lower-order column bits 33210286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 33310286Sandreas.hansson@arm.com 3349669SN/A // take out the channel part of the address 3359669SN/A addr = addr / channels; 3369669SN/A 33710286Sandreas.hansson@arm.com // next, the higher-order column bites 33810286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3399669SN/A 3409669SN/A // after the column bits, we get the bank bits to interleave 3419491SN/A // over the banks 3429243SN/A bank = addr % banksPerRank; 3439243SN/A addr = addr / banksPerRank; 3449243SN/A 3459491SN/A // after the bank, we get the rank bits which thus interleaves 3469491SN/A // over the ranks 3479243SN/A rank = addr % ranksPerChannel; 3489243SN/A addr = addr / ranksPerChannel; 3499243SN/A 35011189Sandreas.hansson@arm.com // lastly, get the row bits, no need to remove them from addr 3519243SN/A row = addr % rowsPerBank; 35210136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 3539491SN/A // optimise for closed page mode and utilise maximum 3549491SN/A // parallelism of the DRAM (at the cost of power) 3559491SN/A 35610286Sandreas.hansson@arm.com // take out the lower-order column bits 35710286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 35810286Sandreas.hansson@arm.com 3599566SN/A // take out the channel part of the address, not that this has 3609566SN/A // to match with how accesses are interleaved between the 3619566SN/A // controllers in the address mapping 3629566SN/A addr = addr / channels; 3639566SN/A 3649491SN/A // start with the bank bits, as this provides the maximum 3659491SN/A // opportunity for parallelism between requests 3669243SN/A bank = addr % banksPerRank; 3679243SN/A addr = addr / banksPerRank; 3689243SN/A 3699491SN/A // next get the rank bits 3709243SN/A rank = addr % ranksPerChannel; 3719243SN/A addr = addr / ranksPerChannel; 3729243SN/A 37310286Sandreas.hansson@arm.com // next, the higher-order column bites 37410286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3759243SN/A 37611189Sandreas.hansson@arm.com // lastly, get the row bits, no need to remove them from addr 3779243SN/A row = addr % rowsPerBank; 3789243SN/A } else 3799243SN/A panic("Unknown address mapping policy chosen!"); 3809243SN/A 3819243SN/A assert(rank < ranksPerChannel); 3829243SN/A assert(bank < banksPerRank); 3839243SN/A assert(row < rowsPerBank); 38410245Sandreas.hansson@arm.com assert(row < Bank::NO_ROW); 3859243SN/A 3869243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 3879831SN/A dramPktAddr, rank, bank, row); 3889243SN/A 3899243SN/A // create the corresponding DRAM packet with the entry time and 3909567SN/A // ready time set to the current tick, the latter will be updated 3919567SN/A // later 3929967SN/A uint16_t bank_id = banksPerRank * rank + bank; 3939967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 39410618SOmar.Naji@arm.com size, ranks[rank]->banks[bank], *ranks[rank]); 3959243SN/A} 3969243SN/A 3979243SN/Avoid 39810146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 3999243SN/A{ 4009243SN/A // only add to the read queue here. whenever the request is 4019243SN/A // eventually done, set the readyTime, and call schedule() 4029243SN/A assert(!pkt->isWrite()); 4039243SN/A 4049831SN/A assert(pktCount != 0); 4059831SN/A 4069831SN/A // if the request size is larger than burst size, the pkt is split into 4079831SN/A // multiple DRAM packets 4089831SN/A // Note if the pkt starting address is not aligened to burst size, the 4099831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 4109831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 4119831SN/A // check read packets against packets in write queue. 4129243SN/A Addr addr = pkt->getAddr(); 4139831SN/A unsigned pktsServicedByWrQ = 0; 4149831SN/A BurstHelper* burst_helper = NULL; 4159831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4169831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4179831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4189831SN/A readPktSize[ceilLog2(size)]++; 4199831SN/A readBursts++; 4209243SN/A 4219831SN/A // First check write buffer to see if the data is already at 4229831SN/A // the controller 4239831SN/A bool foundInWrQ = false; 42410889Sandreas.hansson@arm.com Addr burst_addr = burstAlign(addr); 42510889Sandreas.hansson@arm.com // if the burst address is not present then there is no need 42610889Sandreas.hansson@arm.com // looking any further 42710889Sandreas.hansson@arm.com if (isInWriteQueue.find(burst_addr) != isInWriteQueue.end()) { 42810889Sandreas.hansson@arm.com for (const auto& p : writeQueue) { 42910889Sandreas.hansson@arm.com // check if the read is subsumed in the write queue 43010889Sandreas.hansson@arm.com // packet we are looking at 43110889Sandreas.hansson@arm.com if (p->addr <= addr && (addr + size) <= (p->addr + p->size)) { 43210889Sandreas.hansson@arm.com foundInWrQ = true; 43310889Sandreas.hansson@arm.com servicedByWrQ++; 43410889Sandreas.hansson@arm.com pktsServicedByWrQ++; 43510889Sandreas.hansson@arm.com DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 43610889Sandreas.hansson@arm.com "write queue\n", addr, size); 43710889Sandreas.hansson@arm.com bytesReadWrQ += burstSize; 43810889Sandreas.hansson@arm.com break; 43910889Sandreas.hansson@arm.com } 4409831SN/A } 4419243SN/A } 4429831SN/A 4439831SN/A // If not found in the write q, make a DRAM packet and 4449831SN/A // push it onto the read queue 4459831SN/A if (!foundInWrQ) { 4469831SN/A 4479831SN/A // Make the burst helper for split packets 4489831SN/A if (pktCount > 1 && burst_helper == NULL) { 4499831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 4509831SN/A "dram requests\n", pkt->getAddr(), pktCount); 4519831SN/A burst_helper = new BurstHelper(pktCount); 4529831SN/A } 4539831SN/A 4549966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 4559831SN/A dram_pkt->burstHelper = burst_helper; 4569831SN/A 4579831SN/A assert(!readQueueFull(1)); 4589831SN/A rdQLenPdf[readQueue.size() + respQueue.size()]++; 4599831SN/A 4609831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 4619831SN/A 4629831SN/A readQueue.push_back(dram_pkt); 4639831SN/A 46411678Swendy.elsasser@arm.com // increment read entries of the rank 46511678Swendy.elsasser@arm.com ++dram_pkt->rankRef.readEntries; 46611678Swendy.elsasser@arm.com 4679831SN/A // Update stats 4689831SN/A avgRdQLen = readQueue.size() + respQueue.size(); 4699831SN/A } 4709831SN/A 4719831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 4729831SN/A addr = (addr | (burstSize - 1)) + 1; 4739243SN/A } 4749243SN/A 4759831SN/A // If all packets are serviced by write queue, we send the repsonse back 4769831SN/A if (pktsServicedByWrQ == pktCount) { 4779831SN/A accessAndRespond(pkt, frontendLatency); 4789831SN/A return; 4799831SN/A } 4809243SN/A 4819831SN/A // Update how many split packets are serviced by write queue 4829831SN/A if (burst_helper != NULL) 4839831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 4849243SN/A 48510206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 48610206Sandreas.hansson@arm.com // queue, do so now 48710206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 4889567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 4899567SN/A schedule(nextReqEvent, curTick()); 4909243SN/A } 4919243SN/A} 4929243SN/A 4939243SN/Avoid 49410146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 4959243SN/A{ 4969243SN/A // only add to the write queue here. whenever the request is 4979243SN/A // eventually done, set the readyTime, and call schedule() 4989243SN/A assert(pkt->isWrite()); 4999243SN/A 5009831SN/A // if the request size is larger than burst size, the pkt is split into 5019831SN/A // multiple DRAM packets 5029831SN/A Addr addr = pkt->getAddr(); 5039831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 5049831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 5059831SN/A pkt->getAddr() + pkt->getSize()) - addr; 5069831SN/A writePktSize[ceilLog2(size)]++; 5079831SN/A writeBursts++; 5089243SN/A 5099832SN/A // see if we can merge with an existing item in the write 51010889Sandreas.hansson@arm.com // queue and keep track of whether we have merged or not 51110889Sandreas.hansson@arm.com bool merged = isInWriteQueue.find(burstAlign(addr)) != 51210889Sandreas.hansson@arm.com isInWriteQueue.end(); 5139243SN/A 5149832SN/A // if the item was not merged we need to create a new write 5159832SN/A // and enqueue it 5169832SN/A if (!merged) { 5179966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 5189243SN/A 5199832SN/A assert(writeQueue.size() < writeBufferSize); 5209832SN/A wrQLenPdf[writeQueue.size()]++; 5219243SN/A 5229832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 5239831SN/A 5249832SN/A writeQueue.push_back(dram_pkt); 52510889Sandreas.hansson@arm.com isInWriteQueue.insert(burstAlign(addr)); 52610889Sandreas.hansson@arm.com assert(writeQueue.size() == isInWriteQueue.size()); 5279831SN/A 5289832SN/A // Update stats 5299832SN/A avgWrQLen = writeQueue.size(); 53011678Swendy.elsasser@arm.com 53111678Swendy.elsasser@arm.com // increment write entries of the rank 53211678Swendy.elsasser@arm.com ++dram_pkt->rankRef.writeEntries; 5339977SN/A } else { 53410889Sandreas.hansson@arm.com DPRINTF(DRAM, "Merging write burst with existing queue entry\n"); 53510889Sandreas.hansson@arm.com 5369977SN/A // keep track of the fact that this burst effectively 5379977SN/A // disappeared as it was merged with an existing one 5389977SN/A mergedWrBursts++; 5399832SN/A } 5409832SN/A 5419831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 5429831SN/A addr = (addr | (burstSize - 1)) + 1; 5439831SN/A } 5449243SN/A 5459243SN/A // we do not wait for the writes to be send to the actual memory, 5469243SN/A // but instead take responsibility for the consistency here and 5479243SN/A // snoop the write queue for any upcoming reads 5489831SN/A // @todo, if a pkt size is larger than burst size, we might need a 5499831SN/A // different front end latency 5509726SN/A accessAndRespond(pkt, frontendLatency); 5519243SN/A 55210206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 55310206Sandreas.hansson@arm.com // queue, do so now 55410206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 55510206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 55610206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 5579243SN/A } 5589243SN/A} 5599243SN/A 5609243SN/Avoid 56110146Sandreas.hansson@arm.comDRAMCtrl::printQs() const { 5629243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 5639833SN/A for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 5649243SN/A DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 5659243SN/A } 5669243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 5679833SN/A for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 5689243SN/A DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 5699243SN/A } 5709243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 5719833SN/A for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 5729243SN/A DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 5739243SN/A } 5749243SN/A} 5759243SN/A 5769243SN/Abool 57710146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 5789243SN/A{ 5799243SN/A // This is where we enter from the outside world 5809567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 5819831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 5829243SN/A 58311334Sandreas.hansson@arm.com panic_if(pkt->cacheResponding(), "Should not see packets where cache " 58411334Sandreas.hansson@arm.com "is responding"); 58511334Sandreas.hansson@arm.com 58611334Sandreas.hansson@arm.com panic_if(!(pkt->isRead() || pkt->isWrite()), 58711334Sandreas.hansson@arm.com "Should only see read and writes at memory controller\n"); 5889243SN/A 5899243SN/A // Calc avg gap between requests 5909243SN/A if (prevArrival != 0) { 5919243SN/A totGap += curTick() - prevArrival; 5929243SN/A } 5939243SN/A prevArrival = curTick(); 5949243SN/A 5959831SN/A 5969831SN/A // Find out how many dram packets a pkt translates to 5979831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 5989831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 5999831SN/A // multiple dram packets 6009243SN/A unsigned size = pkt->getSize(); 6019831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 6029831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 6039243SN/A 6049243SN/A // check local buffers and do not accept if full 6059243SN/A if (pkt->isRead()) { 6069567SN/A assert(size != 0); 6079831SN/A if (readQueueFull(dram_pkt_count)) { 6089567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 6099243SN/A // remember that we have to retry this port 6109243SN/A retryRdReq = true; 6119243SN/A numRdRetry++; 6129243SN/A return false; 6139243SN/A } else { 6149831SN/A addToReadQueue(pkt, dram_pkt_count); 6159243SN/A readReqs++; 6169977SN/A bytesReadSys += size; 6179243SN/A } 61811334Sandreas.hansson@arm.com } else { 61911334Sandreas.hansson@arm.com assert(pkt->isWrite()); 6209567SN/A assert(size != 0); 6219831SN/A if (writeQueueFull(dram_pkt_count)) { 6229567SN/A DPRINTF(DRAM, "Write queue full, not accepting\n"); 6239243SN/A // remember that we have to retry this port 6249243SN/A retryWrReq = true; 6259243SN/A numWrRetry++; 6269243SN/A return false; 6279243SN/A } else { 6289831SN/A addToWriteQueue(pkt, dram_pkt_count); 6299243SN/A writeReqs++; 6309977SN/A bytesWrittenSys += size; 6319243SN/A } 6329243SN/A } 6339243SN/A 6349243SN/A return true; 6359243SN/A} 6369243SN/A 6379243SN/Avoid 63810146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 6399243SN/A{ 6409243SN/A DPRINTF(DRAM, 6419243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 6429243SN/A 6439831SN/A DRAMPacket* dram_pkt = respQueue.front(); 6449243SN/A 64511678Swendy.elsasser@arm.com // if a read has reached its ready-time, decrement the number of reads 64611678Swendy.elsasser@arm.com // At this point the packet has been handled and there is a possibility 64711678Swendy.elsasser@arm.com // to switch to low-power mode if no other packet is available 64811678Swendy.elsasser@arm.com --dram_pkt->rankRef.readEntries; 64911678Swendy.elsasser@arm.com DPRINTF(DRAM, "number of read entries for rank %d is %d\n", 65011678Swendy.elsasser@arm.com dram_pkt->rank, dram_pkt->rankRef.readEntries); 65111678Swendy.elsasser@arm.com 65211678Swendy.elsasser@arm.com // counter should at least indicate one outstanding request 65311678Swendy.elsasser@arm.com // for this read 65411678Swendy.elsasser@arm.com assert(dram_pkt->rankRef.outstandingEvents > 0); 65511678Swendy.elsasser@arm.com // read response received, decrement count 65611678Swendy.elsasser@arm.com --dram_pkt->rankRef.outstandingEvents; 65711678Swendy.elsasser@arm.com 65811846Swendy.elsasser@arm.com // at this moment should not have transitioned to a low-power state 65911846Swendy.elsasser@arm.com assert((dram_pkt->rankRef.pwrState != PWR_SREF) && 66011846Swendy.elsasser@arm.com (dram_pkt->rankRef.pwrState != PWR_PRE_PDN) && 66111846Swendy.elsasser@arm.com (dram_pkt->rankRef.pwrState != PWR_ACT_PDN)); 66211678Swendy.elsasser@arm.com 66311678Swendy.elsasser@arm.com // track if this is the last packet before idling 66411678Swendy.elsasser@arm.com // and that there are no outstanding commands to this rank 66511846Swendy.elsasser@arm.com // if REF in progress, transition to LP state should not occur 66611846Swendy.elsasser@arm.com // until REF completes 66711846Swendy.elsasser@arm.com if ((dram_pkt->rankRef.refreshState == REF_IDLE) && 66811846Swendy.elsasser@arm.com (dram_pkt->rankRef.lowPowerEntryReady())) { 66911678Swendy.elsasser@arm.com // verify that there are no events scheduled 67011678Swendy.elsasser@arm.com assert(!dram_pkt->rankRef.activateEvent.scheduled()); 67111678Swendy.elsasser@arm.com assert(!dram_pkt->rankRef.prechargeEvent.scheduled()); 67211678Swendy.elsasser@arm.com 67311678Swendy.elsasser@arm.com // if coming from active state, schedule power event to 67411678Swendy.elsasser@arm.com // active power-down else go to precharge power-down 67511678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleep at tick %d; current power state is " 67611678Swendy.elsasser@arm.com "%d\n", dram_pkt->rank, curTick(), dram_pkt->rankRef.pwrState); 67711678Swendy.elsasser@arm.com 67811678Swendy.elsasser@arm.com // default to ACT power-down unless already in IDLE state 67911678Swendy.elsasser@arm.com // could be in IDLE if PRE issued before data returned 68011678Swendy.elsasser@arm.com PowerState next_pwr_state = PWR_ACT_PDN; 68111678Swendy.elsasser@arm.com if (dram_pkt->rankRef.pwrState == PWR_IDLE) { 68211678Swendy.elsasser@arm.com next_pwr_state = PWR_PRE_PDN; 68311678Swendy.elsasser@arm.com } 68411678Swendy.elsasser@arm.com 68511678Swendy.elsasser@arm.com dram_pkt->rankRef.powerDownSleep(next_pwr_state, curTick()); 68611678Swendy.elsasser@arm.com } 68711678Swendy.elsasser@arm.com 6889831SN/A if (dram_pkt->burstHelper) { 6899831SN/A // it is a split packet 6909831SN/A dram_pkt->burstHelper->burstsServiced++; 6919831SN/A if (dram_pkt->burstHelper->burstsServiced == 69210143SN/A dram_pkt->burstHelper->burstCount) { 6939831SN/A // we have now serviced all children packets of a system packet 6949831SN/A // so we can now respond to the requester 6959831SN/A // @todo we probably want to have a different front end and back 6969831SN/A // end latency for split packets 6979831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6989831SN/A delete dram_pkt->burstHelper; 6999831SN/A dram_pkt->burstHelper = NULL; 7009831SN/A } 7019831SN/A } else { 7029831SN/A // it is not a split packet 7039831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7049831SN/A } 7059243SN/A 7069831SN/A delete respQueue.front(); 7079831SN/A respQueue.pop_front(); 7089243SN/A 7099831SN/A if (!respQueue.empty()) { 7109831SN/A assert(respQueue.front()->readyTime >= curTick()); 7119831SN/A assert(!respondEvent.scheduled()); 7129831SN/A schedule(respondEvent, respQueue.front()->readyTime); 7139831SN/A } else { 7149831SN/A // if there is nothing left in any queue, signal a drain 71510913Sandreas.sandberg@arm.com if (drainState() == DrainState::Draining && 71611676Swendy.elsasser@arm.com writeQueue.empty() && readQueue.empty() && allRanksDrained()) { 71710913Sandreas.sandberg@arm.com 71810509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 71910913Sandreas.sandberg@arm.com signalDrainDone(); 7209831SN/A } 7219831SN/A } 7229567SN/A 7239831SN/A // We have made a location in the queue available at this point, 7249831SN/A // so if there is a read that was forced to wait, retry now 7259831SN/A if (retryRdReq) { 7269831SN/A retryRdReq = false; 72710713Sandreas.hansson@arm.com port.sendRetryReq(); 7289831SN/A } 7299243SN/A} 7309243SN/A 73110618SOmar.Naji@arm.combool 73210890Swendy.elsasser@arm.comDRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay) 7339243SN/A{ 73410206Sandreas.hansson@arm.com // This method does the arbitration between requests. The chosen 73510206Sandreas.hansson@arm.com // packet is simply moved to the head of the queue. The other 73610206Sandreas.hansson@arm.com // methods know that this is the place to look. For example, with 73710206Sandreas.hansson@arm.com // FCFS, this method does nothing 73810206Sandreas.hansson@arm.com assert(!queue.empty()); 7399243SN/A 74010618SOmar.Naji@arm.com // bool to indicate if a packet to an available rank is found 74110618SOmar.Naji@arm.com bool found_packet = false; 74210206Sandreas.hansson@arm.com if (queue.size() == 1) { 74310618SOmar.Naji@arm.com DRAMPacket* dram_pkt = queue.front(); 74410618SOmar.Naji@arm.com // available rank corresponds to state refresh idle 74510618SOmar.Naji@arm.com if (ranks[dram_pkt->rank]->isAvailable()) { 74610618SOmar.Naji@arm.com found_packet = true; 74710618SOmar.Naji@arm.com DPRINTF(DRAM, "Single request, going to a free rank\n"); 74810618SOmar.Naji@arm.com } else { 74910618SOmar.Naji@arm.com DPRINTF(DRAM, "Single request, going to a busy rank\n"); 75010618SOmar.Naji@arm.com } 75110618SOmar.Naji@arm.com return found_packet; 7529243SN/A } 7539243SN/A 7549243SN/A if (memSchedPolicy == Enums::fcfs) { 75510618SOmar.Naji@arm.com // check if there is a packet going to a free rank 75611321Ssteve.reinhardt@amd.com for (auto i = queue.begin(); i != queue.end() ; ++i) { 75710618SOmar.Naji@arm.com DRAMPacket* dram_pkt = *i; 75810618SOmar.Naji@arm.com if (ranks[dram_pkt->rank]->isAvailable()) { 75910618SOmar.Naji@arm.com queue.erase(i); 76010618SOmar.Naji@arm.com queue.push_front(dram_pkt); 76110618SOmar.Naji@arm.com found_packet = true; 76210618SOmar.Naji@arm.com break; 76310618SOmar.Naji@arm.com } 76410618SOmar.Naji@arm.com } 7659243SN/A } else if (memSchedPolicy == Enums::frfcfs) { 76610890Swendy.elsasser@arm.com found_packet = reorderQueue(queue, extra_col_delay); 7679243SN/A } else 7689243SN/A panic("No scheduling policy chosen\n"); 76910618SOmar.Naji@arm.com return found_packet; 7709243SN/A} 7719243SN/A 77210618SOmar.Naji@arm.combool 77310890Swendy.elsasser@arm.comDRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay) 7749974SN/A{ 77510890Swendy.elsasser@arm.com // Only determine this if needed 7769974SN/A uint64_t earliest_banks = 0; 77710890Swendy.elsasser@arm.com bool hidden_bank_prep = false; 7789974SN/A 77910890Swendy.elsasser@arm.com // search for seamless row hits first, if no seamless row hit is 78010890Swendy.elsasser@arm.com // found then determine if there are other packets that can be issued 78110890Swendy.elsasser@arm.com // without incurring additional bus delay due to bank timing 78210890Swendy.elsasser@arm.com // Will select closed rows first to enable more open row possibilies 78310890Swendy.elsasser@arm.com // in future selections 78410890Swendy.elsasser@arm.com bool found_hidden_bank = false; 78510890Swendy.elsasser@arm.com 78610890Swendy.elsasser@arm.com // remember if we found a row hit, not seamless, but bank prepped 78710890Swendy.elsasser@arm.com // and ready 78810890Swendy.elsasser@arm.com bool found_prepped_pkt = false; 78910890Swendy.elsasser@arm.com 79010890Swendy.elsasser@arm.com // if we have no row hit, prepped or not, and no seamless packet, 79110890Swendy.elsasser@arm.com // just go for the earliest possible 7929974SN/A bool found_earliest_pkt = false; 79310890Swendy.elsasser@arm.com 79410618SOmar.Naji@arm.com auto selected_pkt_it = queue.end(); 7959974SN/A 79610890Swendy.elsasser@arm.com // time we need to issue a column command to be seamless 79710890Swendy.elsasser@arm.com const Tick min_col_at = std::max(busBusyUntil - tCL + extra_col_delay, 79810890Swendy.elsasser@arm.com curTick()); 79910890Swendy.elsasser@arm.com 8009974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 8019974SN/A DRAMPacket* dram_pkt = *i; 8029974SN/A const Bank& bank = dram_pkt->bankRef; 80310890Swendy.elsasser@arm.com 80410890Swendy.elsasser@arm.com // check if rank is available, if not, jump to the next packet 80510618SOmar.Naji@arm.com if (dram_pkt->rankRef.isAvailable()) { 80610890Swendy.elsasser@arm.com // check if it is a row hit 80710618SOmar.Naji@arm.com if (bank.openRow == dram_pkt->row) { 80810890Swendy.elsasser@arm.com // no additional rank-to-rank or same bank-group 80910890Swendy.elsasser@arm.com // delays, or we switched read/write and might as well 81010890Swendy.elsasser@arm.com // go for the row hit 81110890Swendy.elsasser@arm.com if (bank.colAllowedAt <= min_col_at) { 81210890Swendy.elsasser@arm.com // FCFS within the hits, giving priority to 81310890Swendy.elsasser@arm.com // commands that can issue seamlessly, without 81410890Swendy.elsasser@arm.com // additional delay, such as same rank accesses 81510890Swendy.elsasser@arm.com // and/or different bank-group accesses 81610890Swendy.elsasser@arm.com DPRINTF(DRAM, "Seamless row buffer hit\n"); 81710618SOmar.Naji@arm.com selected_pkt_it = i; 81810890Swendy.elsasser@arm.com // no need to look through the remaining queue entries 81910618SOmar.Naji@arm.com break; 82010890Swendy.elsasser@arm.com } else if (!found_hidden_bank && !found_prepped_pkt) { 82110890Swendy.elsasser@arm.com // if we did not find a packet to a closed row that can 82210890Swendy.elsasser@arm.com // issue the bank commands without incurring delay, and 82310890Swendy.elsasser@arm.com // did not yet find a packet to a prepped row, remember 82410890Swendy.elsasser@arm.com // the current one 82510618SOmar.Naji@arm.com selected_pkt_it = i; 82610890Swendy.elsasser@arm.com found_prepped_pkt = true; 82710890Swendy.elsasser@arm.com DPRINTF(DRAM, "Prepped row buffer hit\n"); 82810618SOmar.Naji@arm.com } 82910890Swendy.elsasser@arm.com } else if (!found_earliest_pkt) { 83010890Swendy.elsasser@arm.com // if we have not initialised the bank status, do it 83110890Swendy.elsasser@arm.com // now, and only once per scheduling decisions 83210890Swendy.elsasser@arm.com if (earliest_banks == 0) { 83310890Swendy.elsasser@arm.com // determine entries with earliest bank delay 83410890Swendy.elsasser@arm.com pair<uint64_t, bool> bankStatus = 83510890Swendy.elsasser@arm.com minBankPrep(queue, min_col_at); 83610890Swendy.elsasser@arm.com earliest_banks = bankStatus.first; 83710890Swendy.elsasser@arm.com hidden_bank_prep = bankStatus.second; 83810890Swendy.elsasser@arm.com } 83910211Sandreas.hansson@arm.com 84010890Swendy.elsasser@arm.com // bank is amongst first available banks 84110890Swendy.elsasser@arm.com // minBankPrep will give priority to packets that can 84210890Swendy.elsasser@arm.com // issue seamlessly 84310890Swendy.elsasser@arm.com if (bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) { 84410618SOmar.Naji@arm.com found_earliest_pkt = true; 84510890Swendy.elsasser@arm.com found_hidden_bank = hidden_bank_prep; 84610890Swendy.elsasser@arm.com 84710890Swendy.elsasser@arm.com // give priority to packets that can issue 84810890Swendy.elsasser@arm.com // bank commands 'behind the scenes' 84910890Swendy.elsasser@arm.com // any additional delay if any will be due to 85010890Swendy.elsasser@arm.com // col-to-col command requirements 85110890Swendy.elsasser@arm.com if (hidden_bank_prep || !found_prepped_pkt) 85210890Swendy.elsasser@arm.com selected_pkt_it = i; 85310618SOmar.Naji@arm.com } 8549974SN/A } 8559974SN/A } 8569974SN/A } 8579974SN/A 85810618SOmar.Naji@arm.com if (selected_pkt_it != queue.end()) { 85910618SOmar.Naji@arm.com DRAMPacket* selected_pkt = *selected_pkt_it; 86010618SOmar.Naji@arm.com queue.erase(selected_pkt_it); 86110618SOmar.Naji@arm.com queue.push_front(selected_pkt); 86210890Swendy.elsasser@arm.com return true; 86310618SOmar.Naji@arm.com } 86410890Swendy.elsasser@arm.com 86510890Swendy.elsasser@arm.com return false; 8669974SN/A} 8679974SN/A 8689974SN/Avoid 86910146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 8709243SN/A{ 8719243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 8729243SN/A 8739243SN/A bool needsResponse = pkt->needsResponse(); 8749243SN/A // do the actual memory access which also turns the packet into a 8759243SN/A // response 8769243SN/A access(pkt); 8779243SN/A 8789243SN/A // turn packet around to go back to requester if response expected 8799243SN/A if (needsResponse) { 8809243SN/A // access already turned the packet into a response 8819243SN/A assert(pkt->isResponse()); 88210721SMarco.Balboni@ARM.com // response_time consumes the static latency and is charged also 88310721SMarco.Balboni@ARM.com // with headerDelay that takes into account the delay provided by 88410721SMarco.Balboni@ARM.com // the xbar and also the payloadDelay that takes into account the 88510721SMarco.Balboni@ARM.com // number of data beats. 88610721SMarco.Balboni@ARM.com Tick response_time = curTick() + static_latency + pkt->headerDelay + 88710721SMarco.Balboni@ARM.com pkt->payloadDelay; 88810721SMarco.Balboni@ARM.com // Here we reset the timing of the packet before sending it out. 88910694SMarco.Balboni@ARM.com pkt->headerDelay = pkt->payloadDelay = 0; 8909549SN/A 8919726SN/A // queue the packet in the response queue to be sent out after 8929726SN/A // the static latency has passed 89311194Sali.jafri@arm.com port.schedTimingResp(pkt, response_time, true); 8949243SN/A } else { 8959587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 8969587SN/A // is still having a pointer to it 89711190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 8989243SN/A } 8999243SN/A 9009243SN/A DPRINTF(DRAM, "Done\n"); 9019243SN/A 9029243SN/A return; 9039243SN/A} 9049243SN/A 9059243SN/Avoid 90610618SOmar.Naji@arm.comDRAMCtrl::activateBank(Rank& rank_ref, Bank& bank_ref, 90710618SOmar.Naji@arm.com Tick act_tick, uint32_t row) 9089488SN/A{ 90910618SOmar.Naji@arm.com assert(rank_ref.actTicks.size() == activationLimit); 9109488SN/A 9119488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 9129488SN/A 91310207Sandreas.hansson@arm.com // update the open row 91410618SOmar.Naji@arm.com assert(bank_ref.openRow == Bank::NO_ROW); 91510618SOmar.Naji@arm.com bank_ref.openRow = row; 91610207Sandreas.hansson@arm.com 91710207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 91810207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 91910207Sandreas.hansson@arm.com // precharge 92010618SOmar.Naji@arm.com bank_ref.bytesAccessed = 0; 92110618SOmar.Naji@arm.com bank_ref.rowAccesses = 0; 92210207Sandreas.hansson@arm.com 92310618SOmar.Naji@arm.com ++rank_ref.numBanksActive; 92410618SOmar.Naji@arm.com assert(rank_ref.numBanksActive <= banksPerRank); 92510207Sandreas.hansson@arm.com 92610247Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n", 92710618SOmar.Naji@arm.com bank_ref.bank, rank_ref.rank, act_tick, 92810618SOmar.Naji@arm.com ranks[rank_ref.rank]->numBanksActive); 92910247Sandreas.hansson@arm.com 93011675Swendy.elsasser@arm.com rank_ref.cmdList.push_back(Command(MemCommand::ACT, bank_ref.bank, 93111675Swendy.elsasser@arm.com act_tick)); 93210432SOmar.Naji@arm.com 93310432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK) - 93410618SOmar.Naji@arm.com timeStampOffset, bank_ref.bank, rank_ref.rank); 9359975SN/A 93610211Sandreas.hansson@arm.com // The next access has to respect tRAS for this bank 93710618SOmar.Naji@arm.com bank_ref.preAllowedAt = act_tick + tRAS; 93810211Sandreas.hansson@arm.com 93910211Sandreas.hansson@arm.com // Respect the row-to-column command delay 94010618SOmar.Naji@arm.com bank_ref.colAllowedAt = std::max(act_tick + tRCD, bank_ref.colAllowedAt); 94110211Sandreas.hansson@arm.com 9429971SN/A // start by enforcing tRRD 94311321Ssteve.reinhardt@amd.com for (int i = 0; i < banksPerRank; i++) { 94410210Sandreas.hansson@arm.com // next activate to any bank in this rank must not happen 94510210Sandreas.hansson@arm.com // before tRRD 94610618SOmar.Naji@arm.com if (bankGroupArch && (bank_ref.bankgr == rank_ref.banks[i].bankgr)) { 94710394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 94810394Swendy.elsasser@arm.com // ACT commands within the same bank group. Use tRRD_L 94910394Swendy.elsasser@arm.com // in this case 95010618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD_L, 95110618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt); 95210394Swendy.elsasser@arm.com } else { 95310394Swendy.elsasser@arm.com // use shorter tRRD value when either 95410394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 95510394Swendy.elsasser@arm.com // 2) bank is in a different bank group 95610618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD, 95710618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt); 95810394Swendy.elsasser@arm.com } 9599971SN/A } 96010208Sandreas.hansson@arm.com 9619971SN/A // next, we deal with tXAW, if the activation limit is disabled 96210492SOmar.Naji@arm.com // then we directly schedule an activate power event 96310618SOmar.Naji@arm.com if (!rank_ref.actTicks.empty()) { 96410492SOmar.Naji@arm.com // sanity check 96510618SOmar.Naji@arm.com if (rank_ref.actTicks.back() && 96610618SOmar.Naji@arm.com (act_tick - rank_ref.actTicks.back()) < tXAW) { 96710492SOmar.Naji@arm.com panic("Got %d activates in window %d (%llu - %llu) which " 96810492SOmar.Naji@arm.com "is smaller than %llu\n", activationLimit, act_tick - 96910618SOmar.Naji@arm.com rank_ref.actTicks.back(), act_tick, 97010618SOmar.Naji@arm.com rank_ref.actTicks.back(), tXAW); 97110492SOmar.Naji@arm.com } 9729824SN/A 97310492SOmar.Naji@arm.com // shift the times used for the book keeping, the last element 97410492SOmar.Naji@arm.com // (highest index) is the oldest one and hence the lowest value 97510618SOmar.Naji@arm.com rank_ref.actTicks.pop_back(); 9769488SN/A 97710492SOmar.Naji@arm.com // record an new activation (in the future) 97810618SOmar.Naji@arm.com rank_ref.actTicks.push_front(act_tick); 9799488SN/A 98010492SOmar.Naji@arm.com // cannot activate more than X times in time window tXAW, push the 98110492SOmar.Naji@arm.com // next one (the X + 1'st activate) to be tXAW away from the 98210492SOmar.Naji@arm.com // oldest in our window of X 98310618SOmar.Naji@arm.com if (rank_ref.actTicks.back() && 98410618SOmar.Naji@arm.com (act_tick - rank_ref.actTicks.back()) < tXAW) { 98510492SOmar.Naji@arm.com DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate " 98610492SOmar.Naji@arm.com "no earlier than %llu\n", activationLimit, 98710618SOmar.Naji@arm.com rank_ref.actTicks.back() + tXAW); 98811321Ssteve.reinhardt@amd.com for (int j = 0; j < banksPerRank; j++) 9899488SN/A // next activate must not happen before end of window 99010618SOmar.Naji@arm.com rank_ref.banks[j].actAllowedAt = 99110618SOmar.Naji@arm.com std::max(rank_ref.actTicks.back() + tXAW, 99210618SOmar.Naji@arm.com rank_ref.banks[j].actAllowedAt); 99310492SOmar.Naji@arm.com } 9949488SN/A } 99510208Sandreas.hansson@arm.com 99610208Sandreas.hansson@arm.com // at the point when this activate takes place, make sure we 99710208Sandreas.hansson@arm.com // transition to the active power state 99810618SOmar.Naji@arm.com if (!rank_ref.activateEvent.scheduled()) 99910618SOmar.Naji@arm.com schedule(rank_ref.activateEvent, act_tick); 100010618SOmar.Naji@arm.com else if (rank_ref.activateEvent.when() > act_tick) 100110208Sandreas.hansson@arm.com // move it sooner in time 100210618SOmar.Naji@arm.com reschedule(rank_ref.activateEvent, act_tick); 100310208Sandreas.hansson@arm.com} 100410208Sandreas.hansson@arm.com 100510208Sandreas.hansson@arm.comvoid 100610618SOmar.Naji@arm.comDRAMCtrl::prechargeBank(Rank& rank_ref, Bank& bank, Tick pre_at, bool trace) 100710207Sandreas.hansson@arm.com{ 100810207Sandreas.hansson@arm.com // make sure the bank has an open row 100910207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 101010207Sandreas.hansson@arm.com 101110207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 101210207Sandreas.hansson@arm.com // the page 101310207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 101410207Sandreas.hansson@arm.com 101510207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 101610207Sandreas.hansson@arm.com 101710214Sandreas.hansson@arm.com // no precharge allowed before this one 101810214Sandreas.hansson@arm.com bank.preAllowedAt = pre_at; 101910214Sandreas.hansson@arm.com 102010211Sandreas.hansson@arm.com Tick pre_done_at = pre_at + tRP; 102110211Sandreas.hansson@arm.com 102210211Sandreas.hansson@arm.com bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at); 102310207Sandreas.hansson@arm.com 102410618SOmar.Naji@arm.com assert(rank_ref.numBanksActive != 0); 102510618SOmar.Naji@arm.com --rank_ref.numBanksActive; 102610207Sandreas.hansson@arm.com 102710247Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got " 102810618SOmar.Naji@arm.com "%d active\n", bank.bank, rank_ref.rank, pre_at, 102910618SOmar.Naji@arm.com rank_ref.numBanksActive); 103010247Sandreas.hansson@arm.com 103110432SOmar.Naji@arm.com if (trace) { 103210207Sandreas.hansson@arm.com 103311675Swendy.elsasser@arm.com rank_ref.cmdList.push_back(Command(MemCommand::PRE, bank.bank, 103411675Swendy.elsasser@arm.com pre_at)); 103510432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK) - 103610618SOmar.Naji@arm.com timeStampOffset, bank.bank, rank_ref.rank); 103710432SOmar.Naji@arm.com } 103810208Sandreas.hansson@arm.com // if we look at the current number of active banks we might be 103910208Sandreas.hansson@arm.com // tempted to think the DRAM is now idle, however this can be 104010208Sandreas.hansson@arm.com // undone by an activate that is scheduled to happen before we 104110208Sandreas.hansson@arm.com // would have reached the idle state, so schedule an event and 104210208Sandreas.hansson@arm.com // rather check once we actually make it to the point in time when 104310208Sandreas.hansson@arm.com // the (last) precharge takes place 104411678Swendy.elsasser@arm.com if (!rank_ref.prechargeEvent.scheduled()) { 104510618SOmar.Naji@arm.com schedule(rank_ref.prechargeEvent, pre_done_at); 104611678Swendy.elsasser@arm.com // New event, increment count 104711678Swendy.elsasser@arm.com ++rank_ref.outstandingEvents; 104811678Swendy.elsasser@arm.com } else if (rank_ref.prechargeEvent.when() < pre_done_at) { 104910618SOmar.Naji@arm.com reschedule(rank_ref.prechargeEvent, pre_done_at); 105011678Swendy.elsasser@arm.com } 105110207Sandreas.hansson@arm.com} 105210207Sandreas.hansson@arm.com 105310207Sandreas.hansson@arm.comvoid 105410146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 10559243SN/A{ 10569243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 10579243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 10589243SN/A 105910618SOmar.Naji@arm.com // get the rank 106010618SOmar.Naji@arm.com Rank& rank = dram_pkt->rankRef; 106110618SOmar.Naji@arm.com 106211678Swendy.elsasser@arm.com // are we in or transitioning to a low-power state and have not scheduled 106311678Swendy.elsasser@arm.com // a power-up event? 106411678Swendy.elsasser@arm.com // if so, wake up from power down to issue RD/WR burst 106511678Swendy.elsasser@arm.com if (rank.inLowPowerState) { 106611678Swendy.elsasser@arm.com assert(rank.pwrState != PWR_SREF); 106711678Swendy.elsasser@arm.com rank.scheduleWakeUpEvent(tXP); 106811678Swendy.elsasser@arm.com } 106911678Swendy.elsasser@arm.com 107010211Sandreas.hansson@arm.com // get the bank 10719967SN/A Bank& bank = dram_pkt->bankRef; 10729243SN/A 107310211Sandreas.hansson@arm.com // for the state we need to track if it is a row hit or not 107410211Sandreas.hansson@arm.com bool row_hit = true; 107510211Sandreas.hansson@arm.com 107610211Sandreas.hansson@arm.com // respect any constraints on the command (e.g. tRCD or tCCD) 107710211Sandreas.hansson@arm.com Tick cmd_at = std::max(bank.colAllowedAt, curTick()); 107810211Sandreas.hansson@arm.com 107910211Sandreas.hansson@arm.com // Determine the access latency and update the bank state 108010211Sandreas.hansson@arm.com if (bank.openRow == dram_pkt->row) { 108110211Sandreas.hansson@arm.com // nothing to do 108210209Sandreas.hansson@arm.com } else { 108310211Sandreas.hansson@arm.com row_hit = false; 108410211Sandreas.hansson@arm.com 108510209Sandreas.hansson@arm.com // If there is a page open, precharge it. 108610209Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 108710618SOmar.Naji@arm.com prechargeBank(rank, bank, std::max(bank.preAllowedAt, curTick())); 10889488SN/A } 10899973SN/A 109010211Sandreas.hansson@arm.com // next we need to account for the delay in activating the 109110211Sandreas.hansson@arm.com // page 109210211Sandreas.hansson@arm.com Tick act_tick = std::max(bank.actAllowedAt, curTick()); 10939973SN/A 109410210Sandreas.hansson@arm.com // Record the activation and deal with all the global timing 109510210Sandreas.hansson@arm.com // constraints caused be a new activation (tRRD and tXAW) 109610618SOmar.Naji@arm.com activateBank(rank, bank, act_tick, dram_pkt->row); 109710210Sandreas.hansson@arm.com 109810211Sandreas.hansson@arm.com // issue the command as early as possible 109910211Sandreas.hansson@arm.com cmd_at = bank.colAllowedAt; 110010209Sandreas.hansson@arm.com } 110110209Sandreas.hansson@arm.com 110210211Sandreas.hansson@arm.com // we need to wait until the bus is available before we can issue 110310211Sandreas.hansson@arm.com // the command 110410211Sandreas.hansson@arm.com cmd_at = std::max(cmd_at, busBusyUntil - tCL); 110510211Sandreas.hansson@arm.com 110610211Sandreas.hansson@arm.com // update the packet ready time 110710211Sandreas.hansson@arm.com dram_pkt->readyTime = cmd_at + tCL + tBURST; 110810211Sandreas.hansson@arm.com 110910211Sandreas.hansson@arm.com // only one burst can use the bus at any one point in time 111010211Sandreas.hansson@arm.com assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 111110211Sandreas.hansson@arm.com 111210394Swendy.elsasser@arm.com // update the time for the next read/write burst for each 111310394Swendy.elsasser@arm.com // bank (add a max with tCCD/tCCD_L here) 111410394Swendy.elsasser@arm.com Tick cmd_dly; 111511321Ssteve.reinhardt@amd.com for (int j = 0; j < ranksPerChannel; j++) { 111611321Ssteve.reinhardt@amd.com for (int i = 0; i < banksPerRank; i++) { 111710394Swendy.elsasser@arm.com // next burst to same bank group in this rank must not happen 111810394Swendy.elsasser@arm.com // before tCCD_L. Different bank group timing requirement is 111910394Swendy.elsasser@arm.com // tBURST; Add tCS for different ranks 112010394Swendy.elsasser@arm.com if (dram_pkt->rank == j) { 112110618SOmar.Naji@arm.com if (bankGroupArch && 112210618SOmar.Naji@arm.com (bank.bankgr == ranks[j]->banks[i].bankgr)) { 112310394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 112410394Swendy.elsasser@arm.com // RD/WR burst commands to the same bank group. 112510394Swendy.elsasser@arm.com // Use tCCD_L in this case 112610394Swendy.elsasser@arm.com cmd_dly = tCCD_L; 112710394Swendy.elsasser@arm.com } else { 112810394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), the shorter 112910394Swendy.elsasser@arm.com // cas-to-cas delay value, when either: 113010394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 113110394Swendy.elsasser@arm.com // 2) bank is in a different bank group 113210394Swendy.elsasser@arm.com cmd_dly = tBURST; 113310394Swendy.elsasser@arm.com } 113410394Swendy.elsasser@arm.com } else { 113510394Swendy.elsasser@arm.com // different rank is by default in a different bank group 113610394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), which is the shorter 113710394Swendy.elsasser@arm.com // cas-to-cas delay in this case 113810394Swendy.elsasser@arm.com // Add tCS to account for rank-to-rank bus delay requirements 113910394Swendy.elsasser@arm.com cmd_dly = tBURST + tCS; 114010394Swendy.elsasser@arm.com } 114110618SOmar.Naji@arm.com ranks[j]->banks[i].colAllowedAt = std::max(cmd_at + cmd_dly, 114210618SOmar.Naji@arm.com ranks[j]->banks[i].colAllowedAt); 114310394Swendy.elsasser@arm.com } 114410394Swendy.elsasser@arm.com } 114510211Sandreas.hansson@arm.com 114610393Swendy.elsasser@arm.com // Save rank of current access 114710393Swendy.elsasser@arm.com activeRank = dram_pkt->rank; 114810393Swendy.elsasser@arm.com 114910212Sandreas.hansson@arm.com // If this is a write, we also need to respect the write recovery 115010212Sandreas.hansson@arm.com // time before a precharge, in the case of a read, respect the 115110212Sandreas.hansson@arm.com // read to precharge constraint 115210212Sandreas.hansson@arm.com bank.preAllowedAt = std::max(bank.preAllowedAt, 115310212Sandreas.hansson@arm.com dram_pkt->isRead ? cmd_at + tRTP : 115410212Sandreas.hansson@arm.com dram_pkt->readyTime + tWR); 115510210Sandreas.hansson@arm.com 115610209Sandreas.hansson@arm.com // increment the bytes accessed and the accesses per row 115710209Sandreas.hansson@arm.com bank.bytesAccessed += burstSize; 115810209Sandreas.hansson@arm.com ++bank.rowAccesses; 115910209Sandreas.hansson@arm.com 116010209Sandreas.hansson@arm.com // if we reached the max, then issue with an auto-precharge 116110209Sandreas.hansson@arm.com bool auto_precharge = pageMgmt == Enums::close || 116210209Sandreas.hansson@arm.com bank.rowAccesses == maxAccessesPerRow; 116310209Sandreas.hansson@arm.com 116410209Sandreas.hansson@arm.com // if we did not hit the limit, we might still want to 116510209Sandreas.hansson@arm.com // auto-precharge 116610209Sandreas.hansson@arm.com if (!auto_precharge && 116710209Sandreas.hansson@arm.com (pageMgmt == Enums::open_adaptive || 116810209Sandreas.hansson@arm.com pageMgmt == Enums::close_adaptive)) { 116910209Sandreas.hansson@arm.com // a twist on the open and close page policies: 117010209Sandreas.hansson@arm.com // 1) open_adaptive page policy does not blindly keep the 117110209Sandreas.hansson@arm.com // page open, but close it if there are no row hits, and there 117210209Sandreas.hansson@arm.com // are bank conflicts in the queue 117310209Sandreas.hansson@arm.com // 2) close_adaptive page policy does not blindly close the 117410209Sandreas.hansson@arm.com // page, but closes it only if there are no row hits in the queue. 117510209Sandreas.hansson@arm.com // In this case, only force an auto precharge when there 117610209Sandreas.hansson@arm.com // are no same page hits in the queue 117710209Sandreas.hansson@arm.com bool got_more_hits = false; 117810209Sandreas.hansson@arm.com bool got_bank_conflict = false; 117910209Sandreas.hansson@arm.com 118010209Sandreas.hansson@arm.com // either look at the read queue or write queue 118110209Sandreas.hansson@arm.com const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 118210209Sandreas.hansson@arm.com writeQueue; 118310209Sandreas.hansson@arm.com auto p = queue.begin(); 118410209Sandreas.hansson@arm.com // make sure we are not considering the packet that we are 118510209Sandreas.hansson@arm.com // currently dealing with (which is the head of the queue) 118610209Sandreas.hansson@arm.com ++p; 118710209Sandreas.hansson@arm.com 118810809Srb639@drexel.edu // keep on looking until we find a hit or reach the end of the queue 118910809Srb639@drexel.edu // 1) if a hit is found, then both open and close adaptive policies keep 119010809Srb639@drexel.edu // the page open 119110809Srb639@drexel.edu // 2) if no hit is found, got_bank_conflict is set to true if a bank 119210809Srb639@drexel.edu // conflict request is waiting in the queue 119310809Srb639@drexel.edu while (!got_more_hits && p != queue.end()) { 119410209Sandreas.hansson@arm.com bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 119510209Sandreas.hansson@arm.com (dram_pkt->bank == (*p)->bank); 119610209Sandreas.hansson@arm.com bool same_row = dram_pkt->row == (*p)->row; 119710209Sandreas.hansson@arm.com got_more_hits |= same_rank_bank && same_row; 119810209Sandreas.hansson@arm.com got_bank_conflict |= same_rank_bank && !same_row; 11999973SN/A ++p; 120010141SN/A } 120110141SN/A 120210209Sandreas.hansson@arm.com // auto pre-charge when either 120310209Sandreas.hansson@arm.com // 1) open_adaptive policy, we have not got any more hits, and 120410209Sandreas.hansson@arm.com // have a bank conflict 120510209Sandreas.hansson@arm.com // 2) close_adaptive policy and we have not got any more hits 120610209Sandreas.hansson@arm.com auto_precharge = !got_more_hits && 120710209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive); 120810209Sandreas.hansson@arm.com } 120910142SN/A 121010247Sandreas.hansson@arm.com // DRAMPower trace command to be written 121110247Sandreas.hansson@arm.com std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR"; 121210247Sandreas.hansson@arm.com 121310432SOmar.Naji@arm.com // MemCommand required for DRAMPower library 121410432SOmar.Naji@arm.com MemCommand::cmds command = (mem_cmd == "RD") ? MemCommand::RD : 121510432SOmar.Naji@arm.com MemCommand::WR; 121610432SOmar.Naji@arm.com 121711675Swendy.elsasser@arm.com // Update bus state 121811675Swendy.elsasser@arm.com busBusyUntil = dram_pkt->readyTime; 121911675Swendy.elsasser@arm.com 122011675Swendy.elsasser@arm.com DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n", 122111675Swendy.elsasser@arm.com dram_pkt->addr, dram_pkt->readyTime, busBusyUntil); 122211675Swendy.elsasser@arm.com 122311675Swendy.elsasser@arm.com dram_pkt->rankRef.cmdList.push_back(Command(command, dram_pkt->bank, 122411675Swendy.elsasser@arm.com cmd_at)); 122511675Swendy.elsasser@arm.com 122611675Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK) - 122711675Swendy.elsasser@arm.com timeStampOffset, mem_cmd, dram_pkt->bank, dram_pkt->rank); 122811675Swendy.elsasser@arm.com 122910209Sandreas.hansson@arm.com // if this access should use auto-precharge, then we are 123011675Swendy.elsasser@arm.com // closing the row after the read/write burst 123110209Sandreas.hansson@arm.com if (auto_precharge) { 123210432SOmar.Naji@arm.com // if auto-precharge push a PRE command at the correct tick to the 123310432SOmar.Naji@arm.com // list used by DRAMPower library to calculate power 123410618SOmar.Naji@arm.com prechargeBank(rank, bank, std::max(curTick(), bank.preAllowedAt)); 12359973SN/A 123610209Sandreas.hansson@arm.com DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 123710209Sandreas.hansson@arm.com } 12389963SN/A 123910206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 124010206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 124110206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 124210206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 124310206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 12449972SN/A 124510206Sandreas.hansson@arm.com // Update the stats and schedule the next request 12469977SN/A if (dram_pkt->isRead) { 124710147Sandreas.hansson@arm.com ++readsThisTime; 124810211Sandreas.hansson@arm.com if (row_hit) 12499977SN/A readRowHits++; 12509977SN/A bytesReadDRAM += burstSize; 12519977SN/A perBankRdBursts[dram_pkt->bankId]++; 125210206Sandreas.hansson@arm.com 125310206Sandreas.hansson@arm.com // Update latency stats 125410206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 125510206Sandreas.hansson@arm.com totBusLat += tBURST; 125610211Sandreas.hansson@arm.com totQLat += cmd_at - dram_pkt->entryTime; 12579977SN/A } else { 125810147Sandreas.hansson@arm.com ++writesThisTime; 125910211Sandreas.hansson@arm.com if (row_hit) 12609977SN/A writeRowHits++; 12619977SN/A bytesWritten += burstSize; 12629977SN/A perBankWrBursts[dram_pkt->bankId]++; 12639243SN/A } 12649243SN/A} 12659243SN/A 12669243SN/Avoid 126710206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 12689243SN/A{ 126910618SOmar.Naji@arm.com int busyRanks = 0; 127010618SOmar.Naji@arm.com for (auto r : ranks) { 127110618SOmar.Naji@arm.com if (!r->isAvailable()) { 127211678Swendy.elsasser@arm.com if (r->pwrState != PWR_SREF) { 127311678Swendy.elsasser@arm.com // rank is busy refreshing 127411678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d is not available\n", r->rank); 127511678Swendy.elsasser@arm.com busyRanks++; 127611678Swendy.elsasser@arm.com 127711678Swendy.elsasser@arm.com // let the rank know that if it was waiting to drain, it 127811678Swendy.elsasser@arm.com // is now done and ready to proceed 127911678Swendy.elsasser@arm.com r->checkDrainDone(); 128011678Swendy.elsasser@arm.com } 128111678Swendy.elsasser@arm.com 128211678Swendy.elsasser@arm.com // check if we were in self-refresh and haven't started 128311678Swendy.elsasser@arm.com // to transition out 128411678Swendy.elsasser@arm.com if ((r->pwrState == PWR_SREF) && r->inLowPowerState) { 128511678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d is in self-refresh\n", r->rank); 128611678Swendy.elsasser@arm.com // if we have commands queued to this rank and we don't have 128711678Swendy.elsasser@arm.com // a minimum number of active commands enqueued, 128811678Swendy.elsasser@arm.com // exit self-refresh 128911678Swendy.elsasser@arm.com if (r->forceSelfRefreshExit()) { 129011678Swendy.elsasser@arm.com DPRINTF(DRAMState, "rank %d was in self refresh and" 129111678Swendy.elsasser@arm.com " should wake up\n", r->rank); 129211678Swendy.elsasser@arm.com //wake up from self-refresh 129311678Swendy.elsasser@arm.com r->scheduleWakeUpEvent(tXS); 129411678Swendy.elsasser@arm.com // things are brought back into action once a refresh is 129511678Swendy.elsasser@arm.com // performed after self-refresh 129611678Swendy.elsasser@arm.com // continue with selection for other ranks 129711678Swendy.elsasser@arm.com } 129811678Swendy.elsasser@arm.com } 129910618SOmar.Naji@arm.com } 130010618SOmar.Naji@arm.com } 130110618SOmar.Naji@arm.com 130210618SOmar.Naji@arm.com if (busyRanks == ranksPerChannel) { 130310618SOmar.Naji@arm.com // if all ranks are refreshing wait for them to finish 130410618SOmar.Naji@arm.com // and stall this state machine without taking any further 130510618SOmar.Naji@arm.com // action, and do not schedule a new nextReqEvent 130610618SOmar.Naji@arm.com return; 130710618SOmar.Naji@arm.com } 130810618SOmar.Naji@arm.com 130911678Swendy.elsasser@arm.com // pre-emptively set to false. Overwrite if in transitioning to 131011678Swendy.elsasser@arm.com // a new state 131110393Swendy.elsasser@arm.com bool switched_cmd_type = false; 131211678Swendy.elsasser@arm.com if (busState != busStateNext) { 131311678Swendy.elsasser@arm.com if (busState == READ) { 131411678Swendy.elsasser@arm.com DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 131511678Swendy.elsasser@arm.com "waiting\n", readsThisTime, readQueue.size()); 131611678Swendy.elsasser@arm.com 131711678Swendy.elsasser@arm.com // sample and reset the read-related stats as we are now 131811678Swendy.elsasser@arm.com // transitioning to writes, and all reads are done 131911678Swendy.elsasser@arm.com rdPerTurnAround.sample(readsThisTime); 132011678Swendy.elsasser@arm.com readsThisTime = 0; 132111678Swendy.elsasser@arm.com 132211678Swendy.elsasser@arm.com // now proceed to do the actual writes 132311678Swendy.elsasser@arm.com switched_cmd_type = true; 132411678Swendy.elsasser@arm.com } else { 132511678Swendy.elsasser@arm.com DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 132611678Swendy.elsasser@arm.com "waiting\n", writesThisTime, writeQueue.size()); 132711678Swendy.elsasser@arm.com 132811678Swendy.elsasser@arm.com wrPerTurnAround.sample(writesThisTime); 132911678Swendy.elsasser@arm.com writesThisTime = 0; 133011678Swendy.elsasser@arm.com 133111678Swendy.elsasser@arm.com switched_cmd_type = true; 133211678Swendy.elsasser@arm.com } 133311678Swendy.elsasser@arm.com // update busState to match next state until next transition 133411678Swendy.elsasser@arm.com busState = busStateNext; 133510206Sandreas.hansson@arm.com } 133610206Sandreas.hansson@arm.com 133710206Sandreas.hansson@arm.com // when we get here it is either a read or a write 133810206Sandreas.hansson@arm.com if (busState == READ) { 133910206Sandreas.hansson@arm.com 134010206Sandreas.hansson@arm.com // track if we should switch or not 134110206Sandreas.hansson@arm.com bool switch_to_writes = false; 134210206Sandreas.hansson@arm.com 134310206Sandreas.hansson@arm.com if (readQueue.empty()) { 134410206Sandreas.hansson@arm.com // In the case there is no read request to go next, 134510206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 134610206Sandreas.hansson@arm.com // if we are draining) 134710206Sandreas.hansson@arm.com if (!writeQueue.empty() && 134810913Sandreas.sandberg@arm.com (drainState() == DrainState::Draining || 134910913Sandreas.sandberg@arm.com writeQueue.size() > writeLowThreshold)) { 135010206Sandreas.hansson@arm.com 135110206Sandreas.hansson@arm.com switch_to_writes = true; 135210206Sandreas.hansson@arm.com } else { 135310206Sandreas.hansson@arm.com // check if we are drained 135411676Swendy.elsasser@arm.com // not done draining until in PWR_IDLE state 135511676Swendy.elsasser@arm.com // ensuring all banks are closed and 135611676Swendy.elsasser@arm.com // have exited low power states 135710913Sandreas.sandberg@arm.com if (drainState() == DrainState::Draining && 135811676Swendy.elsasser@arm.com respQueue.empty() && allRanksDrained()) { 135910913Sandreas.sandberg@arm.com 136010509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 136110913Sandreas.sandberg@arm.com signalDrainDone(); 136210206Sandreas.hansson@arm.com } 136310206Sandreas.hansson@arm.com 136410206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 136510206Sandreas.hansson@arm.com // event for the next request 136610206Sandreas.hansson@arm.com return; 136710206Sandreas.hansson@arm.com } 136810206Sandreas.hansson@arm.com } else { 136910618SOmar.Naji@arm.com // bool to check if there is a read to a free rank 137010618SOmar.Naji@arm.com bool found_read = false; 137110618SOmar.Naji@arm.com 137210206Sandreas.hansson@arm.com // Figure out which read request goes next, and move it to the 137310206Sandreas.hansson@arm.com // front of the read queue 137410890Swendy.elsasser@arm.com // If we are changing command type, incorporate the minimum 137510890Swendy.elsasser@arm.com // bus turnaround delay which will be tCS (different rank) case 137610890Swendy.elsasser@arm.com found_read = chooseNext(readQueue, 137710890Swendy.elsasser@arm.com switched_cmd_type ? tCS : 0); 137810618SOmar.Naji@arm.com 137910618SOmar.Naji@arm.com // if no read to an available rank is found then return 138010618SOmar.Naji@arm.com // at this point. There could be writes to the available ranks 138110618SOmar.Naji@arm.com // which are above the required threshold. However, to 138210618SOmar.Naji@arm.com // avoid adding more complexity to the code, return and wait 138310618SOmar.Naji@arm.com // for a refresh event to kick things into action again. 138410618SOmar.Naji@arm.com if (!found_read) 138510618SOmar.Naji@arm.com return; 138610206Sandreas.hansson@arm.com 138710215Sandreas.hansson@arm.com DRAMPacket* dram_pkt = readQueue.front(); 138810618SOmar.Naji@arm.com assert(dram_pkt->rankRef.isAvailable()); 138911678Swendy.elsasser@arm.com 139010393Swendy.elsasser@arm.com // here we get a bit creative and shift the bus busy time not 139110393Swendy.elsasser@arm.com // just the tWTR, but also a CAS latency to capture the fact 139210393Swendy.elsasser@arm.com // that we are allowed to prepare a new bank, but not issue a 139310393Swendy.elsasser@arm.com // read command until after tWTR, in essence we capture a 139410393Swendy.elsasser@arm.com // bubble on the data bus that is tWTR + tCL 139510394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 139610394Swendy.elsasser@arm.com busBusyUntil += tWTR + tCL; 139710393Swendy.elsasser@arm.com } 139810393Swendy.elsasser@arm.com 139910215Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 140010206Sandreas.hansson@arm.com 140110206Sandreas.hansson@arm.com // At this point we're done dealing with the request 140210215Sandreas.hansson@arm.com readQueue.pop_front(); 140310215Sandreas.hansson@arm.com 140411678Swendy.elsasser@arm.com // Every respQueue which will generate an event, increment count 140511678Swendy.elsasser@arm.com ++dram_pkt->rankRef.outstandingEvents; 140611678Swendy.elsasser@arm.com 140710215Sandreas.hansson@arm.com // sanity check 140810215Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 140910215Sandreas.hansson@arm.com assert(dram_pkt->readyTime >= curTick()); 141010215Sandreas.hansson@arm.com 141110215Sandreas.hansson@arm.com // Insert into response queue. It will be sent back to the 141210215Sandreas.hansson@arm.com // requestor at its readyTime 141310215Sandreas.hansson@arm.com if (respQueue.empty()) { 141410215Sandreas.hansson@arm.com assert(!respondEvent.scheduled()); 141510215Sandreas.hansson@arm.com schedule(respondEvent, dram_pkt->readyTime); 141610215Sandreas.hansson@arm.com } else { 141710215Sandreas.hansson@arm.com assert(respQueue.back()->readyTime <= dram_pkt->readyTime); 141810215Sandreas.hansson@arm.com assert(respondEvent.scheduled()); 141910215Sandreas.hansson@arm.com } 142010215Sandreas.hansson@arm.com 142110215Sandreas.hansson@arm.com respQueue.push_back(dram_pkt); 142210206Sandreas.hansson@arm.com 142310206Sandreas.hansson@arm.com // we have so many writes that we have to transition 142410206Sandreas.hansson@arm.com if (writeQueue.size() > writeHighThreshold) { 142510206Sandreas.hansson@arm.com switch_to_writes = true; 142610206Sandreas.hansson@arm.com } 142710206Sandreas.hansson@arm.com } 142810206Sandreas.hansson@arm.com 142910206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 143010206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 143110206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 143210206Sandreas.hansson@arm.com if (switch_to_writes) { 143310206Sandreas.hansson@arm.com // transition to writing 143411678Swendy.elsasser@arm.com busStateNext = WRITE; 143510206Sandreas.hansson@arm.com } 14369352SN/A } else { 143710618SOmar.Naji@arm.com // bool to check if write to free rank is found 143810618SOmar.Naji@arm.com bool found_write = false; 143910618SOmar.Naji@arm.com 144010890Swendy.elsasser@arm.com // If we are changing command type, incorporate the minimum 144110890Swendy.elsasser@arm.com // bus turnaround delay 144210890Swendy.elsasser@arm.com found_write = chooseNext(writeQueue, 144310890Swendy.elsasser@arm.com switched_cmd_type ? std::min(tRTW, tCS) : 0); 144410618SOmar.Naji@arm.com 144510618SOmar.Naji@arm.com // if no writes to an available rank are found then return. 144610618SOmar.Naji@arm.com // There could be reads to the available ranks. However, to avoid 144710618SOmar.Naji@arm.com // adding more complexity to the code, return at this point and wait 144810618SOmar.Naji@arm.com // for a refresh event to kick things into action again. 144910618SOmar.Naji@arm.com if (!found_write) 145010618SOmar.Naji@arm.com return; 145110618SOmar.Naji@arm.com 145210206Sandreas.hansson@arm.com DRAMPacket* dram_pkt = writeQueue.front(); 145310618SOmar.Naji@arm.com assert(dram_pkt->rankRef.isAvailable()); 145410206Sandreas.hansson@arm.com // sanity check 145510206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 145610393Swendy.elsasser@arm.com 145710394Swendy.elsasser@arm.com // add a bubble to the data bus, as defined by the 145810394Swendy.elsasser@arm.com // tRTW when access is to the same rank as previous burst 145910394Swendy.elsasser@arm.com // Different rank timing is handled with tCS, which is 146010394Swendy.elsasser@arm.com // applied to colAllowedAt 146110394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 146210394Swendy.elsasser@arm.com busBusyUntil += tRTW; 146310393Swendy.elsasser@arm.com } 146410393Swendy.elsasser@arm.com 146510206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 146610206Sandreas.hansson@arm.com 146710206Sandreas.hansson@arm.com writeQueue.pop_front(); 146811678Swendy.elsasser@arm.com 146911678Swendy.elsasser@arm.com // removed write from queue, decrement count 147011678Swendy.elsasser@arm.com --dram_pkt->rankRef.writeEntries; 147111678Swendy.elsasser@arm.com 147211678Swendy.elsasser@arm.com // Schedule write done event to decrement event count 147311678Swendy.elsasser@arm.com // after the readyTime has been reached 147411678Swendy.elsasser@arm.com // Only schedule latest write event to minimize events 147511678Swendy.elsasser@arm.com // required; only need to ensure that final event scheduled covers 147611678Swendy.elsasser@arm.com // the time that writes are outstanding and bus is active 147711678Swendy.elsasser@arm.com // to holdoff power-down entry events 147811678Swendy.elsasser@arm.com if (!dram_pkt->rankRef.writeDoneEvent.scheduled()) { 147911678Swendy.elsasser@arm.com schedule(dram_pkt->rankRef.writeDoneEvent, dram_pkt->readyTime); 148011678Swendy.elsasser@arm.com // New event, increment count 148111678Swendy.elsasser@arm.com ++dram_pkt->rankRef.outstandingEvents; 148211678Swendy.elsasser@arm.com 148311678Swendy.elsasser@arm.com } else if (dram_pkt->rankRef.writeDoneEvent.when() < 148411678Swendy.elsasser@arm.com dram_pkt-> readyTime) { 148511678Swendy.elsasser@arm.com reschedule(dram_pkt->rankRef.writeDoneEvent, dram_pkt->readyTime); 148611678Swendy.elsasser@arm.com } 148711678Swendy.elsasser@arm.com 148810889Sandreas.hansson@arm.com isInWriteQueue.erase(burstAlign(dram_pkt->addr)); 148910206Sandreas.hansson@arm.com delete dram_pkt; 149010206Sandreas.hansson@arm.com 149110206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 149210206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 149310206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 149410206Sandreas.hansson@arm.com // writes, then switch to reads. 149510206Sandreas.hansson@arm.com if (writeQueue.empty() || 149610206Sandreas.hansson@arm.com (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 149710913Sandreas.sandberg@arm.com drainState() != DrainState::Draining) || 149810206Sandreas.hansson@arm.com (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 149910206Sandreas.hansson@arm.com // turn the bus back around for reads again 150011678Swendy.elsasser@arm.com busStateNext = READ; 150110206Sandreas.hansson@arm.com 150210206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 150310206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 150410206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 150510206Sandreas.hansson@arm.com // nothing to do 150610206Sandreas.hansson@arm.com } 150710206Sandreas.hansson@arm.com } 150810618SOmar.Naji@arm.com // It is possible that a refresh to another rank kicks things back into 150910618SOmar.Naji@arm.com // action before reaching this point. 151010618SOmar.Naji@arm.com if (!nextReqEvent.scheduled()) 151110618SOmar.Naji@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 151210206Sandreas.hansson@arm.com 151310206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 151410206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 151510206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 151610206Sandreas.hansson@arm.com // the next request processing 151710206Sandreas.hansson@arm.com if (retryWrReq && writeQueue.size() < writeBufferSize) { 151810206Sandreas.hansson@arm.com retryWrReq = false; 151910713Sandreas.hansson@arm.com port.sendRetryReq(); 15209352SN/A } 15219243SN/A} 15229243SN/A 152310890Swendy.elsasser@arm.compair<uint64_t, bool> 152410393Swendy.elsasser@arm.comDRAMCtrl::minBankPrep(const deque<DRAMPacket*>& queue, 152510890Swendy.elsasser@arm.com Tick min_col_at) const 15269967SN/A{ 15279967SN/A uint64_t bank_mask = 0; 152810211Sandreas.hansson@arm.com Tick min_act_at = MaxTick; 15299967SN/A 153010890Swendy.elsasser@arm.com // latest Tick for which ACT can occur without incurring additoinal 153110890Swendy.elsasser@arm.com // delay on the data bus 153210890Swendy.elsasser@arm.com const Tick hidden_act_max = std::max(min_col_at - tRCD, curTick()); 153310393Swendy.elsasser@arm.com 153410890Swendy.elsasser@arm.com // Flag condition when burst can issue back-to-back with previous burst 153510890Swendy.elsasser@arm.com bool found_seamless_bank = false; 153610890Swendy.elsasser@arm.com 153710890Swendy.elsasser@arm.com // Flag condition when bank can be opened without incurring additional 153810890Swendy.elsasser@arm.com // delay on the data bus 153910890Swendy.elsasser@arm.com bool hidden_bank_prep = false; 154010393Swendy.elsasser@arm.com 154110393Swendy.elsasser@arm.com // determine if we have queued transactions targetting the 15429967SN/A // bank in question 15439967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 154410618SOmar.Naji@arm.com for (const auto& p : queue) { 154511321Ssteve.reinhardt@amd.com if (p->rankRef.isAvailable()) 154610618SOmar.Naji@arm.com got_waiting[p->bankId] = true; 15479967SN/A } 15489967SN/A 154910890Swendy.elsasser@arm.com // Find command with optimal bank timing 155010890Swendy.elsasser@arm.com // Will prioritize commands that can issue seamlessly. 15519967SN/A for (int i = 0; i < ranksPerChannel; i++) { 15529967SN/A for (int j = 0; j < banksPerRank; j++) { 155310618SOmar.Naji@arm.com uint16_t bank_id = i * banksPerRank + j; 155410211Sandreas.hansson@arm.com 15559967SN/A // if we have waiting requests for the bank, and it is 15569967SN/A // amongst the first available, update the mask 155710211Sandreas.hansson@arm.com if (got_waiting[bank_id]) { 155810618SOmar.Naji@arm.com // make sure this rank is not currently refreshing. 155910618SOmar.Naji@arm.com assert(ranks[i]->isAvailable()); 156010211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue 156110211Sandreas.hansson@arm.com // an activate, ignoring any rank-to-rank switching 156210393Swendy.elsasser@arm.com // cost in this calculation 156310618SOmar.Naji@arm.com Tick act_at = ranks[i]->banks[j].openRow == Bank::NO_ROW ? 156410890Swendy.elsasser@arm.com std::max(ranks[i]->banks[j].actAllowedAt, curTick()) : 156510618SOmar.Naji@arm.com std::max(ranks[i]->banks[j].preAllowedAt, curTick()) + tRP; 156610211Sandreas.hansson@arm.com 156710890Swendy.elsasser@arm.com // When is the earliest the R/W burst can issue? 156810890Swendy.elsasser@arm.com Tick col_at = std::max(ranks[i]->banks[j].colAllowedAt, 156910890Swendy.elsasser@arm.com act_at + tRCD); 157010393Swendy.elsasser@arm.com 157110890Swendy.elsasser@arm.com // bank can issue burst back-to-back (seamlessly) with 157210890Swendy.elsasser@arm.com // previous burst 157310890Swendy.elsasser@arm.com bool new_seamless_bank = col_at <= min_col_at; 157410393Swendy.elsasser@arm.com 157510890Swendy.elsasser@arm.com // if we found a new seamless bank or we have no 157610890Swendy.elsasser@arm.com // seamless banks, and got a bank with an earlier 157710890Swendy.elsasser@arm.com // activate time, it should be added to the bit mask 157810890Swendy.elsasser@arm.com if (new_seamless_bank || 157910890Swendy.elsasser@arm.com (!found_seamless_bank && act_at <= min_act_at)) { 158010890Swendy.elsasser@arm.com // if we did not have a seamless bank before, and 158110890Swendy.elsasser@arm.com // we do now, reset the bank mask, also reset it 158210890Swendy.elsasser@arm.com // if we have not yet found a seamless bank and 158310890Swendy.elsasser@arm.com // the activate time is smaller than what we have 158410890Swendy.elsasser@arm.com // seen so far 158510890Swendy.elsasser@arm.com if (!found_seamless_bank && 158610890Swendy.elsasser@arm.com (new_seamless_bank || act_at < min_act_at)) { 158710890Swendy.elsasser@arm.com bank_mask = 0; 158810393Swendy.elsasser@arm.com } 158910890Swendy.elsasser@arm.com 159010890Swendy.elsasser@arm.com found_seamless_bank |= new_seamless_bank; 159110890Swendy.elsasser@arm.com 159210890Swendy.elsasser@arm.com // ACT can occur 'behind the scenes' 159310890Swendy.elsasser@arm.com hidden_bank_prep = act_at <= hidden_act_max; 159410890Swendy.elsasser@arm.com 159510890Swendy.elsasser@arm.com // set the bit corresponding to the available bank 159610890Swendy.elsasser@arm.com replaceBits(bank_mask, bank_id, bank_id, 1); 159710890Swendy.elsasser@arm.com min_act_at = act_at; 159810211Sandreas.hansson@arm.com } 15999967SN/A } 16009967SN/A } 16019967SN/A } 160210211Sandreas.hansson@arm.com 160310890Swendy.elsasser@arm.com return make_pair(bank_mask, hidden_bank_prep); 16049967SN/A} 16059967SN/A 160612081Sspwilson2@wisc.eduDRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p, int rank) 160710618SOmar.Naji@arm.com : EventManager(&_memory), memory(_memory), 160811678Swendy.elsasser@arm.com pwrStateTrans(PWR_IDLE), pwrStatePostRefresh(PWR_IDLE), 160911678Swendy.elsasser@arm.com pwrStateTick(0), refreshDueAt(0), pwrState(PWR_IDLE), 161012081Sspwilson2@wisc.edu refreshState(REF_IDLE), inLowPowerState(false), rank(rank), 161111678Swendy.elsasser@arm.com readEntries(0), writeEntries(0), outstandingEvents(0), 161212081Sspwilson2@wisc.edu wakeUpAllowedAt(0), power(_p, false), banks(_p->banks_per_rank), 161312081Sspwilson2@wisc.edu numBanksActive(0), actTicks(_p->activation_limit, 0), 161412084Sspwilson2@wisc.edu writeDoneEvent([this]{ processWriteDoneEvent(); }, name()), 161512084Sspwilson2@wisc.edu activateEvent([this]{ processActivateEvent(); }, name()), 161612084Sspwilson2@wisc.edu prechargeEvent([this]{ processPrechargeEvent(); }, name()), 161712084Sspwilson2@wisc.edu refreshEvent([this]{ processRefreshEvent(); }, name()), 161812084Sspwilson2@wisc.edu powerEvent([this]{ processPowerEvent(); }, name()), 161912084Sspwilson2@wisc.edu wakeUpEvent([this]{ processWakeUpEvent(); }, name()) 162012081Sspwilson2@wisc.edu{ 162112081Sspwilson2@wisc.edu for (int b = 0; b < _p->banks_per_rank; b++) { 162212081Sspwilson2@wisc.edu banks[b].bank = b; 162312081Sspwilson2@wisc.edu // GDDR addressing of banks to BG is linear. 162412081Sspwilson2@wisc.edu // Here we assume that all DRAM generations address bank groups as 162512081Sspwilson2@wisc.edu // follows: 162612081Sspwilson2@wisc.edu if (_p->bank_groups_per_rank > 0) { 162712081Sspwilson2@wisc.edu // Simply assign lower bits to bank group in order to 162812081Sspwilson2@wisc.edu // rotate across bank groups as banks are incremented 162912081Sspwilson2@wisc.edu // e.g. with 4 banks per bank group and 16 banks total: 163012081Sspwilson2@wisc.edu // banks 0,4,8,12 are in bank group 0 163112081Sspwilson2@wisc.edu // banks 1,5,9,13 are in bank group 1 163212081Sspwilson2@wisc.edu // banks 2,6,10,14 are in bank group 2 163312081Sspwilson2@wisc.edu // banks 3,7,11,15 are in bank group 3 163412081Sspwilson2@wisc.edu banks[b].bankgr = b % _p->bank_groups_per_rank; 163512081Sspwilson2@wisc.edu } else { 163612081Sspwilson2@wisc.edu // No bank groups; simply assign to bank number 163712081Sspwilson2@wisc.edu banks[b].bankgr = b; 163812081Sspwilson2@wisc.edu } 163912081Sspwilson2@wisc.edu } 164012081Sspwilson2@wisc.edu} 164110618SOmar.Naji@arm.com 16429243SN/Avoid 164310618SOmar.Naji@arm.comDRAMCtrl::Rank::startup(Tick ref_tick) 164410618SOmar.Naji@arm.com{ 164510618SOmar.Naji@arm.com assert(ref_tick > curTick()); 164610618SOmar.Naji@arm.com 164710618SOmar.Naji@arm.com pwrStateTick = curTick(); 164810618SOmar.Naji@arm.com 164910618SOmar.Naji@arm.com // kick off the refresh, and give ourselves enough time to 165010618SOmar.Naji@arm.com // precharge 165110618SOmar.Naji@arm.com schedule(refreshEvent, ref_tick); 165210618SOmar.Naji@arm.com} 165310618SOmar.Naji@arm.com 165410618SOmar.Naji@arm.comvoid 165510619Sandreas.hansson@arm.comDRAMCtrl::Rank::suspend() 165610619Sandreas.hansson@arm.com{ 165710619Sandreas.hansson@arm.com deschedule(refreshEvent); 165811676Swendy.elsasser@arm.com 165911676Swendy.elsasser@arm.com // Update the stats 166011676Swendy.elsasser@arm.com updatePowerStats(); 166111678Swendy.elsasser@arm.com 166211678Swendy.elsasser@arm.com // don't automatically transition back to LP state after next REF 166311678Swendy.elsasser@arm.com pwrStatePostRefresh = PWR_IDLE; 166411678Swendy.elsasser@arm.com} 166511678Swendy.elsasser@arm.com 166611678Swendy.elsasser@arm.combool 166711678Swendy.elsasser@arm.comDRAMCtrl::Rank::lowPowerEntryReady() const 166811678Swendy.elsasser@arm.com{ 166911678Swendy.elsasser@arm.com bool no_queued_cmds = ((memory.busStateNext == READ) && (readEntries == 0)) 167011678Swendy.elsasser@arm.com || ((memory.busStateNext == WRITE) && 167111678Swendy.elsasser@arm.com (writeEntries == 0)); 167211678Swendy.elsasser@arm.com 167311678Swendy.elsasser@arm.com if (refreshState == REF_RUN) { 167411678Swendy.elsasser@arm.com // have not decremented outstandingEvents for refresh command 167511678Swendy.elsasser@arm.com // still check if there are no commands queued to force PD 167611678Swendy.elsasser@arm.com // entry after refresh completes 167711678Swendy.elsasser@arm.com return no_queued_cmds; 167811678Swendy.elsasser@arm.com } else { 167911678Swendy.elsasser@arm.com // ensure no commands in Q and no commands scheduled 168011678Swendy.elsasser@arm.com return (no_queued_cmds && (outstandingEvents == 0)); 168111678Swendy.elsasser@arm.com } 168210619Sandreas.hansson@arm.com} 168310619Sandreas.hansson@arm.com 168410619Sandreas.hansson@arm.comvoid 168510618SOmar.Naji@arm.comDRAMCtrl::Rank::checkDrainDone() 168610618SOmar.Naji@arm.com{ 168710618SOmar.Naji@arm.com // if this rank was waiting to drain it is now able to proceed to 168810618SOmar.Naji@arm.com // precharge 168910618SOmar.Naji@arm.com if (refreshState == REF_DRAIN) { 169010618SOmar.Naji@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 169110618SOmar.Naji@arm.com 169211678Swendy.elsasser@arm.com refreshState = REF_PD_EXIT; 169310618SOmar.Naji@arm.com 169410618SOmar.Naji@arm.com // hand control back to the refresh event loop 169510618SOmar.Naji@arm.com schedule(refreshEvent, curTick()); 169610618SOmar.Naji@arm.com } 169710618SOmar.Naji@arm.com} 169810618SOmar.Naji@arm.com 169910618SOmar.Naji@arm.comvoid 170011675Swendy.elsasser@arm.comDRAMCtrl::Rank::flushCmdList() 170111675Swendy.elsasser@arm.com{ 170211675Swendy.elsasser@arm.com // at the moment sort the list of commands and update the counters 170311675Swendy.elsasser@arm.com // for DRAMPower libray when doing a refresh 170411675Swendy.elsasser@arm.com sort(cmdList.begin(), cmdList.end(), DRAMCtrl::sortTime); 170511675Swendy.elsasser@arm.com 170611675Swendy.elsasser@arm.com auto next_iter = cmdList.begin(); 170711675Swendy.elsasser@arm.com // push to commands to DRAMPower 170811675Swendy.elsasser@arm.com for ( ; next_iter != cmdList.end() ; ++next_iter) { 170911675Swendy.elsasser@arm.com Command cmd = *next_iter; 171011675Swendy.elsasser@arm.com if (cmd.timeStamp <= curTick()) { 171111675Swendy.elsasser@arm.com // Move all commands at or before curTick to DRAMPower 171211675Swendy.elsasser@arm.com power.powerlib.doCommand(cmd.type, cmd.bank, 171311675Swendy.elsasser@arm.com divCeil(cmd.timeStamp, memory.tCK) - 171411675Swendy.elsasser@arm.com memory.timeStampOffset); 171511675Swendy.elsasser@arm.com } else { 171611675Swendy.elsasser@arm.com // done - found all commands at or before curTick() 171711675Swendy.elsasser@arm.com // next_iter references the 1st command after curTick 171811675Swendy.elsasser@arm.com break; 171911675Swendy.elsasser@arm.com } 172011675Swendy.elsasser@arm.com } 172111675Swendy.elsasser@arm.com // reset cmdList to only contain commands after curTick 172211675Swendy.elsasser@arm.com // if there are no commands after curTick, updated cmdList will be empty 172311675Swendy.elsasser@arm.com // in this case, next_iter is cmdList.end() 172411675Swendy.elsasser@arm.com cmdList.assign(next_iter, cmdList.end()); 172511675Swendy.elsasser@arm.com} 172611675Swendy.elsasser@arm.com 172711675Swendy.elsasser@arm.comvoid 172810618SOmar.Naji@arm.comDRAMCtrl::Rank::processActivateEvent() 172910618SOmar.Naji@arm.com{ 173010618SOmar.Naji@arm.com // we should transition to the active state as soon as any bank is active 173110618SOmar.Naji@arm.com if (pwrState != PWR_ACT) 173210618SOmar.Naji@arm.com // note that at this point numBanksActive could be back at 173310618SOmar.Naji@arm.com // zero again due to a precharge scheduled in the future 173410618SOmar.Naji@arm.com schedulePowerEvent(PWR_ACT, curTick()); 173510618SOmar.Naji@arm.com} 173610618SOmar.Naji@arm.com 173710618SOmar.Naji@arm.comvoid 173810618SOmar.Naji@arm.comDRAMCtrl::Rank::processPrechargeEvent() 173910618SOmar.Naji@arm.com{ 174011678Swendy.elsasser@arm.com // counter should at least indicate one outstanding request 174111678Swendy.elsasser@arm.com // for this precharge 174211678Swendy.elsasser@arm.com assert(outstandingEvents > 0); 174311678Swendy.elsasser@arm.com // precharge complete, decrement count 174411678Swendy.elsasser@arm.com --outstandingEvents; 174511678Swendy.elsasser@arm.com 174610618SOmar.Naji@arm.com // if we reached zero, then special conditions apply as we track 174710618SOmar.Naji@arm.com // if all banks are precharged for the power models 174810618SOmar.Naji@arm.com if (numBanksActive == 0) { 174911678Swendy.elsasser@arm.com // no reads to this rank in the Q and no pending 175011678Swendy.elsasser@arm.com // RD/WR or refresh commands 175111678Swendy.elsasser@arm.com if (lowPowerEntryReady()) { 175211678Swendy.elsasser@arm.com // should still be in ACT state since bank still open 175311678Swendy.elsasser@arm.com assert(pwrState == PWR_ACT); 175411678Swendy.elsasser@arm.com 175511678Swendy.elsasser@arm.com // All banks closed - switch to precharge power down state. 175611678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleep at tick %d\n", 175711678Swendy.elsasser@arm.com rank, curTick()); 175811678Swendy.elsasser@arm.com powerDownSleep(PWR_PRE_PDN, curTick()); 175911678Swendy.elsasser@arm.com } else { 176011678Swendy.elsasser@arm.com // we should transition to the idle state when the last bank 176111678Swendy.elsasser@arm.com // is precharged 176211678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 176311678Swendy.elsasser@arm.com } 176410618SOmar.Naji@arm.com } 176510618SOmar.Naji@arm.com} 176610618SOmar.Naji@arm.com 176710618SOmar.Naji@arm.comvoid 176811678Swendy.elsasser@arm.comDRAMCtrl::Rank::processWriteDoneEvent() 176911678Swendy.elsasser@arm.com{ 177011678Swendy.elsasser@arm.com // counter should at least indicate one outstanding request 177111678Swendy.elsasser@arm.com // for this write 177211678Swendy.elsasser@arm.com assert(outstandingEvents > 0); 177311678Swendy.elsasser@arm.com // Write transfer on bus has completed 177411678Swendy.elsasser@arm.com // decrement per rank counter 177511678Swendy.elsasser@arm.com --outstandingEvents; 177611678Swendy.elsasser@arm.com} 177711678Swendy.elsasser@arm.com 177811678Swendy.elsasser@arm.comvoid 177910618SOmar.Naji@arm.comDRAMCtrl::Rank::processRefreshEvent() 17809243SN/A{ 178110207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 178211678Swendy.elsasser@arm.com if ((refreshState == REF_IDLE) || (refreshState == REF_SREF_EXIT)) { 178310207Sandreas.hansson@arm.com // remember when the refresh is due 178410207Sandreas.hansson@arm.com refreshDueAt = curTick(); 17859243SN/A 178610207Sandreas.hansson@arm.com // proceed to drain 178710207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 17889243SN/A 178911678Swendy.elsasser@arm.com // make nonzero while refresh is pending to ensure 179011678Swendy.elsasser@arm.com // power down and self-refresh are not entered 179111678Swendy.elsasser@arm.com ++outstandingEvents; 179211678Swendy.elsasser@arm.com 179310207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 179410207Sandreas.hansson@arm.com } 179510207Sandreas.hansson@arm.com 179610618SOmar.Naji@arm.com // let any scheduled read or write to the same rank go ahead, 179710618SOmar.Naji@arm.com // after which it will 179810207Sandreas.hansson@arm.com // hand control back to this event loop 179910207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 180010618SOmar.Naji@arm.com // if a request is at the moment being handled and this request is 180110618SOmar.Naji@arm.com // accessing the current rank then wait for it to finish 180210618SOmar.Naji@arm.com if ((rank == memory.activeRank) 180310618SOmar.Naji@arm.com && (memory.nextReqEvent.scheduled())) { 180410207Sandreas.hansson@arm.com // hand control over to the request loop until it is 180510207Sandreas.hansson@arm.com // evaluated next 180610207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 180710207Sandreas.hansson@arm.com 180810207Sandreas.hansson@arm.com return; 180910207Sandreas.hansson@arm.com } else { 181011678Swendy.elsasser@arm.com refreshState = REF_PD_EXIT; 181111678Swendy.elsasser@arm.com } 181211678Swendy.elsasser@arm.com } 181311678Swendy.elsasser@arm.com 181411678Swendy.elsasser@arm.com // at this point, ensure that rank is not in a power-down state 181511678Swendy.elsasser@arm.com if (refreshState == REF_PD_EXIT) { 181611678Swendy.elsasser@arm.com // if rank was sleeping and we have't started exit process, 181711678Swendy.elsasser@arm.com // wake-up for refresh 181811678Swendy.elsasser@arm.com if (inLowPowerState) { 181911678Swendy.elsasser@arm.com DPRINTF(DRAM, "Wake Up for refresh\n"); 182011678Swendy.elsasser@arm.com // save state and return after refresh completes 182111678Swendy.elsasser@arm.com scheduleWakeUpEvent(memory.tXP); 182211678Swendy.elsasser@arm.com return; 182311678Swendy.elsasser@arm.com } else { 182410207Sandreas.hansson@arm.com refreshState = REF_PRE; 182510207Sandreas.hansson@arm.com } 182610207Sandreas.hansson@arm.com } 182710207Sandreas.hansson@arm.com 182810207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 182910207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 183011678Swendy.elsasser@arm.com // precharge any active bank 183111678Swendy.elsasser@arm.com if (numBanksActive != 0) { 183210214Sandreas.hansson@arm.com // at the moment, we use a precharge all even if there is 183310214Sandreas.hansson@arm.com // only a single bank open 183410208Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 183510214Sandreas.hansson@arm.com 183610214Sandreas.hansson@arm.com // first determine when we can precharge 183710214Sandreas.hansson@arm.com Tick pre_at = curTick(); 183810618SOmar.Naji@arm.com 183910618SOmar.Naji@arm.com for (auto &b : banks) { 184010618SOmar.Naji@arm.com // respect both causality and any existing bank 184110618SOmar.Naji@arm.com // constraints, some banks could already have a 184210618SOmar.Naji@arm.com // (auto) precharge scheduled 184310618SOmar.Naji@arm.com pre_at = std::max(b.preAllowedAt, pre_at); 184410618SOmar.Naji@arm.com } 184510618SOmar.Naji@arm.com 184610618SOmar.Naji@arm.com // make sure all banks per rank are precharged, and for those that 184710618SOmar.Naji@arm.com // already are, update their availability 184810618SOmar.Naji@arm.com Tick act_allowed_at = pre_at + memory.tRP; 184910618SOmar.Naji@arm.com 185010618SOmar.Naji@arm.com for (auto &b : banks) { 185110618SOmar.Naji@arm.com if (b.openRow != Bank::NO_ROW) { 185210618SOmar.Naji@arm.com memory.prechargeBank(*this, b, pre_at, false); 185310618SOmar.Naji@arm.com } else { 185410618SOmar.Naji@arm.com b.actAllowedAt = std::max(b.actAllowedAt, act_allowed_at); 185510618SOmar.Naji@arm.com b.preAllowedAt = std::max(b.preAllowedAt, pre_at); 185610214Sandreas.hansson@arm.com } 185710214Sandreas.hansson@arm.com } 185810214Sandreas.hansson@arm.com 185910618SOmar.Naji@arm.com // precharge all banks in rank 186011675Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PREA, 0, pre_at)); 186110214Sandreas.hansson@arm.com 186210618SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PREA,0,%d\n", 186310618SOmar.Naji@arm.com divCeil(pre_at, memory.tCK) - 186410618SOmar.Naji@arm.com memory.timeStampOffset, rank); 186511678Swendy.elsasser@arm.com } else if ((pwrState == PWR_IDLE) && (outstandingEvents == 1)) { 186611678Swendy.elsasser@arm.com // Banks are closed, have transitioned to IDLE state, and 186711678Swendy.elsasser@arm.com // no outstanding ACT,RD/WR,Auto-PRE sequence scheduled 186810208Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 186910208Sandreas.hansson@arm.com 187011678Swendy.elsasser@arm.com // go ahead and kick the power state machine into gear since 187110208Sandreas.hansson@arm.com // we are already idle 187210208Sandreas.hansson@arm.com schedulePowerEvent(PWR_REF, curTick()); 187311678Swendy.elsasser@arm.com } else { 187411678Swendy.elsasser@arm.com // banks state is closed but haven't transitioned pwrState to IDLE 187511678Swendy.elsasser@arm.com // or have outstanding ACT,RD/WR,Auto-PRE sequence scheduled 187611678Swendy.elsasser@arm.com // should have outstanding precharge event in this case 187711678Swendy.elsasser@arm.com assert(prechargeEvent.scheduled()); 187811678Swendy.elsasser@arm.com // will start refresh when pwrState transitions to IDLE 18799975SN/A } 18809975SN/A 188110208Sandreas.hansson@arm.com assert(numBanksActive == 0); 18829243SN/A 188310208Sandreas.hansson@arm.com // wait for all banks to be precharged, at which point the 188410208Sandreas.hansson@arm.com // power state machine will transition to the idle state, and 188510208Sandreas.hansson@arm.com // automatically move to a refresh, at that point it will also 188610208Sandreas.hansson@arm.com // call this method to get the refresh event loop going again 188710207Sandreas.hansson@arm.com return; 188810207Sandreas.hansson@arm.com } 188910207Sandreas.hansson@arm.com 189010207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 189111678Swendy.elsasser@arm.com if (refreshState == REF_START) { 189211678Swendy.elsasser@arm.com // should never get here with any banks active 189311678Swendy.elsasser@arm.com assert(numBanksActive == 0); 189411678Swendy.elsasser@arm.com assert(pwrState == PWR_REF); 189511678Swendy.elsasser@arm.com 189611678Swendy.elsasser@arm.com Tick ref_done_at = curTick() + memory.tRFC; 189711678Swendy.elsasser@arm.com 189811678Swendy.elsasser@arm.com for (auto &b : banks) { 189911678Swendy.elsasser@arm.com b.actAllowedAt = ref_done_at; 190011678Swendy.elsasser@arm.com } 190111678Swendy.elsasser@arm.com 190211678Swendy.elsasser@arm.com // at the moment this affects all ranks 190311678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::REF, 0, curTick())); 190411678Swendy.elsasser@arm.com 190511678Swendy.elsasser@arm.com // Update the stats 190611678Swendy.elsasser@arm.com updatePowerStats(); 190711678Swendy.elsasser@arm.com 190811678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), memory.tCK) - 190911678Swendy.elsasser@arm.com memory.timeStampOffset, rank); 191011678Swendy.elsasser@arm.com 191111678Swendy.elsasser@arm.com // Update for next refresh 191211678Swendy.elsasser@arm.com refreshDueAt += memory.tREFI; 191311678Swendy.elsasser@arm.com 191411678Swendy.elsasser@arm.com // make sure we did not wait so long that we cannot make up 191511678Swendy.elsasser@arm.com // for it 191611678Swendy.elsasser@arm.com if (refreshDueAt < ref_done_at) { 191711678Swendy.elsasser@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 191811678Swendy.elsasser@arm.com } 191911678Swendy.elsasser@arm.com 192011678Swendy.elsasser@arm.com // Run the refresh and schedule event to transition power states 192111678Swendy.elsasser@arm.com // when refresh completes 192211678Swendy.elsasser@arm.com refreshState = REF_RUN; 192311678Swendy.elsasser@arm.com schedule(refreshEvent, ref_done_at); 192411678Swendy.elsasser@arm.com return; 192511678Swendy.elsasser@arm.com } 192611678Swendy.elsasser@arm.com 192710207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 192810207Sandreas.hansson@arm.com // should never get here with any banks active 192910207Sandreas.hansson@arm.com assert(numBanksActive == 0); 193010208Sandreas.hansson@arm.com assert(pwrState == PWR_REF); 193110207Sandreas.hansson@arm.com 193211678Swendy.elsasser@arm.com assert(!powerEvent.scheduled()); 193311678Swendy.elsasser@arm.com 193411678Swendy.elsasser@arm.com if ((memory.drainState() == DrainState::Draining) || 193511678Swendy.elsasser@arm.com (memory.drainState() == DrainState::Drained)) { 193611678Swendy.elsasser@arm.com // if draining, do not re-enter low-power mode. 193711678Swendy.elsasser@arm.com // simply go to IDLE and wait 193811678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 193911678Swendy.elsasser@arm.com } else { 194011678Swendy.elsasser@arm.com // At the moment, we sleep when the refresh ends and wait to be 194111678Swendy.elsasser@arm.com // woken up again if previously in a low-power state. 194211678Swendy.elsasser@arm.com if (pwrStatePostRefresh != PWR_IDLE) { 194311678Swendy.elsasser@arm.com // power State should be power Refresh 194411678Swendy.elsasser@arm.com assert(pwrState == PWR_REF); 194511678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleeping after refresh and was in " 194611678Swendy.elsasser@arm.com "power state %d before refreshing\n", rank, 194711678Swendy.elsasser@arm.com pwrStatePostRefresh); 194811678Swendy.elsasser@arm.com powerDownSleep(pwrState, curTick()); 194911678Swendy.elsasser@arm.com 195011678Swendy.elsasser@arm.com // Force PRE power-down if there are no outstanding commands 195111678Swendy.elsasser@arm.com // in Q after refresh. 195211678Swendy.elsasser@arm.com } else if (lowPowerEntryReady()) { 195311678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleeping after refresh but was NOT" 195411678Swendy.elsasser@arm.com " in a low power state before refreshing\n", rank); 195511678Swendy.elsasser@arm.com powerDownSleep(PWR_PRE_PDN, curTick()); 195611678Swendy.elsasser@arm.com 195711678Swendy.elsasser@arm.com } else { 195811678Swendy.elsasser@arm.com // move to the idle power state once the refresh is done, this 195911678Swendy.elsasser@arm.com // will also move the refresh state machine to the refresh 196011678Swendy.elsasser@arm.com // idle state 196111678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 196211678Swendy.elsasser@arm.com } 196310618SOmar.Naji@arm.com } 196410247Sandreas.hansson@arm.com 196511678Swendy.elsasser@arm.com // if transitioning to self refresh do not schedule a new refresh; 196611678Swendy.elsasser@arm.com // when waking from self refresh, a refresh is scheduled again. 196711678Swendy.elsasser@arm.com if (pwrStateTrans != PWR_SREF) { 196811678Swendy.elsasser@arm.com // compensate for the delay in actually performing the refresh 196911678Swendy.elsasser@arm.com // when scheduling the next one 197011678Swendy.elsasser@arm.com schedule(refreshEvent, refreshDueAt - memory.tRP); 197111678Swendy.elsasser@arm.com 197211678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Refresh done at %llu and next refresh" 197311678Swendy.elsasser@arm.com " at %llu\n", curTick(), refreshDueAt); 197410207Sandreas.hansson@arm.com } 197510208Sandreas.hansson@arm.com } 197610208Sandreas.hansson@arm.com} 197710208Sandreas.hansson@arm.com 197810208Sandreas.hansson@arm.comvoid 197910618SOmar.Naji@arm.comDRAMCtrl::Rank::schedulePowerEvent(PowerState pwr_state, Tick tick) 198010208Sandreas.hansson@arm.com{ 198110208Sandreas.hansson@arm.com // respect causality 198210208Sandreas.hansson@arm.com assert(tick >= curTick()); 198310208Sandreas.hansson@arm.com 198410208Sandreas.hansson@arm.com if (!powerEvent.scheduled()) { 198510208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 198610208Sandreas.hansson@arm.com tick, pwr_state); 198710208Sandreas.hansson@arm.com 198810208Sandreas.hansson@arm.com // insert the new transition 198910208Sandreas.hansson@arm.com pwrStateTrans = pwr_state; 199010208Sandreas.hansson@arm.com 199110208Sandreas.hansson@arm.com schedule(powerEvent, tick); 199210208Sandreas.hansson@arm.com } else { 199310208Sandreas.hansson@arm.com panic("Scheduled power event at %llu to state %d, " 199410208Sandreas.hansson@arm.com "with scheduled event at %llu to %d\n", tick, pwr_state, 199510208Sandreas.hansson@arm.com powerEvent.when(), pwrStateTrans); 199610208Sandreas.hansson@arm.com } 199710208Sandreas.hansson@arm.com} 199810208Sandreas.hansson@arm.com 199910208Sandreas.hansson@arm.comvoid 200011678Swendy.elsasser@arm.comDRAMCtrl::Rank::powerDownSleep(PowerState pwr_state, Tick tick) 200111678Swendy.elsasser@arm.com{ 200211678Swendy.elsasser@arm.com // if low power state is active low, schedule to active low power state. 200311678Swendy.elsasser@arm.com // in reality tCKE is needed to enter active low power. This is neglected 200411678Swendy.elsasser@arm.com // here and could be added in the future. 200511678Swendy.elsasser@arm.com if (pwr_state == PWR_ACT_PDN) { 200611678Swendy.elsasser@arm.com schedulePowerEvent(pwr_state, tick); 200711678Swendy.elsasser@arm.com // push command to DRAMPower 200811678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PDN_F_ACT, 0, tick)); 200911678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PDN_F_ACT,0,%d\n", divCeil(tick, 201011678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 201111678Swendy.elsasser@arm.com } else if (pwr_state == PWR_PRE_PDN) { 201211678Swendy.elsasser@arm.com // if low power state is precharge low, schedule to precharge low 201311678Swendy.elsasser@arm.com // power state. In reality tCKE is needed to enter active low power. 201411678Swendy.elsasser@arm.com // This is neglected here. 201511678Swendy.elsasser@arm.com schedulePowerEvent(pwr_state, tick); 201611678Swendy.elsasser@arm.com //push Command to DRAMPower 201711678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PDN_F_PRE, 0, tick)); 201811678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PDN_F_PRE,0,%d\n", divCeil(tick, 201911678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 202011678Swendy.elsasser@arm.com } else if (pwr_state == PWR_REF) { 202111678Swendy.elsasser@arm.com // if a refresh just occured 202211678Swendy.elsasser@arm.com // transition to PRE_PDN now that all banks are closed 202311678Swendy.elsasser@arm.com // do not transition to SREF if commands are in Q; stay in PRE_PDN 202411678Swendy.elsasser@arm.com if (pwrStatePostRefresh == PWR_ACT_PDN || !lowPowerEntryReady()) { 202511678Swendy.elsasser@arm.com // prechage power down requires tCKE to enter. For simplicity 202611678Swendy.elsasser@arm.com // this is not considered. 202711678Swendy.elsasser@arm.com schedulePowerEvent(PWR_PRE_PDN, tick); 202811678Swendy.elsasser@arm.com //push Command to DRAMPower 202911678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PDN_F_PRE, 0, tick)); 203011678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PDN_F_PRE,0,%d\n", divCeil(tick, 203111678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 203211678Swendy.elsasser@arm.com } else { 203311678Swendy.elsasser@arm.com // last low power State was power precharge 203411678Swendy.elsasser@arm.com assert(pwrStatePostRefresh == PWR_PRE_PDN); 203511678Swendy.elsasser@arm.com // self refresh requires time tCKESR to enter. For simplicity, 203611678Swendy.elsasser@arm.com // this is not considered. 203711678Swendy.elsasser@arm.com schedulePowerEvent(PWR_SREF, tick); 203811678Swendy.elsasser@arm.com // push Command to DRAMPower 203911678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::SREN, 0, tick)); 204011678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,SREN,0,%d\n", divCeil(tick, 204111678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 204211678Swendy.elsasser@arm.com } 204311678Swendy.elsasser@arm.com } 204411678Swendy.elsasser@arm.com // Ensure that we don't power-down and back up in same tick 204511678Swendy.elsasser@arm.com // Once we commit to PD entry, do it and wait for at least 1tCK 204611678Swendy.elsasser@arm.com // This could be replaced with tCKE if/when that is added to the model 204711678Swendy.elsasser@arm.com wakeUpAllowedAt = tick + memory.tCK; 204811678Swendy.elsasser@arm.com 204911678Swendy.elsasser@arm.com // Transitioning to a low power state, set flag 205011678Swendy.elsasser@arm.com inLowPowerState = true; 205111678Swendy.elsasser@arm.com} 205211678Swendy.elsasser@arm.com 205311678Swendy.elsasser@arm.comvoid 205411678Swendy.elsasser@arm.comDRAMCtrl::Rank::scheduleWakeUpEvent(Tick exit_delay) 205511678Swendy.elsasser@arm.com{ 205611678Swendy.elsasser@arm.com Tick wake_up_tick = std::max(curTick(), wakeUpAllowedAt); 205711678Swendy.elsasser@arm.com 205811678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Scheduling wake-up for rank %d at tick %d\n", 205911678Swendy.elsasser@arm.com rank, wake_up_tick); 206011678Swendy.elsasser@arm.com 206111678Swendy.elsasser@arm.com // if waking for refresh, hold previous state 206211678Swendy.elsasser@arm.com // else reset state back to IDLE 206311678Swendy.elsasser@arm.com if (refreshState == REF_PD_EXIT) { 206411678Swendy.elsasser@arm.com pwrStatePostRefresh = pwrState; 206511678Swendy.elsasser@arm.com } else { 206611678Swendy.elsasser@arm.com // don't automatically transition back to LP state after next REF 206711678Swendy.elsasser@arm.com pwrStatePostRefresh = PWR_IDLE; 206811678Swendy.elsasser@arm.com } 206911678Swendy.elsasser@arm.com 207011678Swendy.elsasser@arm.com // schedule wake-up with event to ensure entry has completed before 207111678Swendy.elsasser@arm.com // we try to wake-up 207211678Swendy.elsasser@arm.com schedule(wakeUpEvent, wake_up_tick); 207311678Swendy.elsasser@arm.com 207411678Swendy.elsasser@arm.com for (auto &b : banks) { 207511678Swendy.elsasser@arm.com // respect both causality and any existing bank 207611678Swendy.elsasser@arm.com // constraints, some banks could already have a 207711678Swendy.elsasser@arm.com // (auto) precharge scheduled 207811678Swendy.elsasser@arm.com b.colAllowedAt = std::max(wake_up_tick + exit_delay, b.colAllowedAt); 207911678Swendy.elsasser@arm.com b.preAllowedAt = std::max(wake_up_tick + exit_delay, b.preAllowedAt); 208011678Swendy.elsasser@arm.com b.actAllowedAt = std::max(wake_up_tick + exit_delay, b.actAllowedAt); 208111678Swendy.elsasser@arm.com } 208211678Swendy.elsasser@arm.com // Transitioning out of low power state, clear flag 208311678Swendy.elsasser@arm.com inLowPowerState = false; 208411678Swendy.elsasser@arm.com 208511678Swendy.elsasser@arm.com // push to DRAMPower 208611678Swendy.elsasser@arm.com // use pwrStateTrans for cases where we have a power event scheduled 208711678Swendy.elsasser@arm.com // to enter low power that has not yet been processed 208811678Swendy.elsasser@arm.com if (pwrStateTrans == PWR_ACT_PDN) { 208911678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PUP_ACT, 0, wake_up_tick)); 209011678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PUP_ACT,0,%d\n", divCeil(wake_up_tick, 209111678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 209211678Swendy.elsasser@arm.com 209311678Swendy.elsasser@arm.com } else if (pwrStateTrans == PWR_PRE_PDN) { 209411678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PUP_PRE, 0, wake_up_tick)); 209511678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PUP_PRE,0,%d\n", divCeil(wake_up_tick, 209611678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 209711678Swendy.elsasser@arm.com } else if (pwrStateTrans == PWR_SREF) { 209811678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::SREX, 0, wake_up_tick)); 209911678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,SREX,0,%d\n", divCeil(wake_up_tick, 210011678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 210111678Swendy.elsasser@arm.com } 210211678Swendy.elsasser@arm.com} 210311678Swendy.elsasser@arm.com 210411678Swendy.elsasser@arm.comvoid 210511678Swendy.elsasser@arm.comDRAMCtrl::Rank::processWakeUpEvent() 210611678Swendy.elsasser@arm.com{ 210711678Swendy.elsasser@arm.com // Should be in a power-down or self-refresh state 210811678Swendy.elsasser@arm.com assert((pwrState == PWR_ACT_PDN) || (pwrState == PWR_PRE_PDN) || 210911678Swendy.elsasser@arm.com (pwrState == PWR_SREF)); 211011678Swendy.elsasser@arm.com 211111678Swendy.elsasser@arm.com // Check current state to determine transition state 211211678Swendy.elsasser@arm.com if (pwrState == PWR_ACT_PDN) { 211311678Swendy.elsasser@arm.com // banks still open, transition to PWR_ACT 211411678Swendy.elsasser@arm.com schedulePowerEvent(PWR_ACT, curTick()); 211511678Swendy.elsasser@arm.com } else { 211611678Swendy.elsasser@arm.com // transitioning from a precharge power-down or self-refresh state 211711678Swendy.elsasser@arm.com // banks are closed - transition to PWR_IDLE 211811678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 211911678Swendy.elsasser@arm.com } 212011678Swendy.elsasser@arm.com} 212111678Swendy.elsasser@arm.com 212211678Swendy.elsasser@arm.comvoid 212310618SOmar.Naji@arm.comDRAMCtrl::Rank::processPowerEvent() 212410208Sandreas.hansson@arm.com{ 212511678Swendy.elsasser@arm.com assert(curTick() >= pwrStateTick); 212610208Sandreas.hansson@arm.com // remember where we were, and for how long 212710208Sandreas.hansson@arm.com Tick duration = curTick() - pwrStateTick; 212810208Sandreas.hansson@arm.com PowerState prev_state = pwrState; 212910208Sandreas.hansson@arm.com 213010208Sandreas.hansson@arm.com // update the accounting 213110208Sandreas.hansson@arm.com pwrStateTime[prev_state] += duration; 213210208Sandreas.hansson@arm.com 213311678Swendy.elsasser@arm.com // track to total idle time 213411678Swendy.elsasser@arm.com if ((prev_state == PWR_PRE_PDN) || (prev_state == PWR_ACT_PDN) || 213511678Swendy.elsasser@arm.com (prev_state == PWR_SREF)) { 213611678Swendy.elsasser@arm.com totalIdleTime += duration; 213711678Swendy.elsasser@arm.com } 213811678Swendy.elsasser@arm.com 213910208Sandreas.hansson@arm.com pwrState = pwrStateTrans; 214010208Sandreas.hansson@arm.com pwrStateTick = curTick(); 214110208Sandreas.hansson@arm.com 214211678Swendy.elsasser@arm.com // if rank was refreshing, make sure to start scheduling requests again 214311678Swendy.elsasser@arm.com if (prev_state == PWR_REF) { 214411678Swendy.elsasser@arm.com // bus IDLED prior to REF 214511678Swendy.elsasser@arm.com // counter should be one for refresh command only 214611678Swendy.elsasser@arm.com assert(outstandingEvents == 1); 214711678Swendy.elsasser@arm.com // REF complete, decrement count 214811678Swendy.elsasser@arm.com --outstandingEvents; 214911678Swendy.elsasser@arm.com 215011678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 215111678Swendy.elsasser@arm.com // if sleeping after refresh 215211678Swendy.elsasser@arm.com if (pwrState != PWR_IDLE) { 215311678Swendy.elsasser@arm.com assert((pwrState == PWR_PRE_PDN) || (pwrState == PWR_SREF)); 215411678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Switching to power down state after refreshing" 215511678Swendy.elsasser@arm.com " rank %d at %llu tick\n", rank, curTick()); 215611678Swendy.elsasser@arm.com } 215711678Swendy.elsasser@arm.com if (pwrState != PWR_SREF) { 215811678Swendy.elsasser@arm.com // rank is not available in SREF 215911678Swendy.elsasser@arm.com // don't transition to IDLE in this case 216011678Swendy.elsasser@arm.com refreshState = REF_IDLE; 216111678Swendy.elsasser@arm.com } 216211678Swendy.elsasser@arm.com // a request event could be already scheduled by the state 216311678Swendy.elsasser@arm.com // machine of the other rank 216411678Swendy.elsasser@arm.com if (!memory.nextReqEvent.scheduled()) { 216511678Swendy.elsasser@arm.com DPRINTF(DRAM, "Scheduling next request after refreshing rank %d\n", 216611678Swendy.elsasser@arm.com rank); 216711678Swendy.elsasser@arm.com schedule(memory.nextReqEvent, curTick()); 216811678Swendy.elsasser@arm.com } 216911678Swendy.elsasser@arm.com } else if (pwrState == PWR_ACT) { 217011678Swendy.elsasser@arm.com if (refreshState == REF_PD_EXIT) { 217111678Swendy.elsasser@arm.com // kick the refresh event loop into action again 217211678Swendy.elsasser@arm.com assert(prev_state == PWR_ACT_PDN); 217311678Swendy.elsasser@arm.com 217411678Swendy.elsasser@arm.com // go back to REF event and close banks 217511678Swendy.elsasser@arm.com refreshState = REF_PRE; 217611678Swendy.elsasser@arm.com schedule(refreshEvent, curTick()); 217711678Swendy.elsasser@arm.com } 217811678Swendy.elsasser@arm.com } else if (pwrState == PWR_IDLE) { 217910208Sandreas.hansson@arm.com DPRINTF(DRAMState, "All banks precharged\n"); 218011678Swendy.elsasser@arm.com if (prev_state == PWR_SREF) { 218111678Swendy.elsasser@arm.com // set refresh state to REF_SREF_EXIT, ensuring isAvailable 218211678Swendy.elsasser@arm.com // continues to return false during tXS after SREF exit 218311678Swendy.elsasser@arm.com // Schedule a refresh which kicks things back into action 218411678Swendy.elsasser@arm.com // when it finishes 218511678Swendy.elsasser@arm.com refreshState = REF_SREF_EXIT; 218611678Swendy.elsasser@arm.com schedule(refreshEvent, curTick() + memory.tXS); 218710208Sandreas.hansson@arm.com } else { 218810208Sandreas.hansson@arm.com // if we have a pending refresh, and are now moving to 218911678Swendy.elsasser@arm.com // the idle state, directly transition to a refresh 219011678Swendy.elsasser@arm.com if ((refreshState == REF_PRE) || (refreshState == REF_PD_EXIT)) { 219111678Swendy.elsasser@arm.com // ensure refresh is restarted only after final PRE command. 219211678Swendy.elsasser@arm.com // do not restart refresh if controller is in an intermediate 219311678Swendy.elsasser@arm.com // state, after PRE_PDN exit, when banks are IDLE but an 219411678Swendy.elsasser@arm.com // ACT is scheduled. 219511678Swendy.elsasser@arm.com if (!activateEvent.scheduled()) { 219611678Swendy.elsasser@arm.com // there should be nothing waiting at this point 219711678Swendy.elsasser@arm.com assert(!powerEvent.scheduled()); 219811678Swendy.elsasser@arm.com // update the state in zero time and proceed below 219911678Swendy.elsasser@arm.com pwrState = PWR_REF; 220011678Swendy.elsasser@arm.com } else { 220111678Swendy.elsasser@arm.com // must have PRE scheduled to transition back to IDLE 220211678Swendy.elsasser@arm.com // and re-kick off refresh 220311678Swendy.elsasser@arm.com assert(prechargeEvent.scheduled()); 220411678Swendy.elsasser@arm.com } 220510208Sandreas.hansson@arm.com } 220611678Swendy.elsasser@arm.com } 220710208Sandreas.hansson@arm.com } 220810208Sandreas.hansson@arm.com 220910208Sandreas.hansson@arm.com // we transition to the refresh state, let the refresh state 221010208Sandreas.hansson@arm.com // machine know of this state update and let it deal with the 221110208Sandreas.hansson@arm.com // scheduling of the next power state transition as well as the 221210208Sandreas.hansson@arm.com // following refresh 221310208Sandreas.hansson@arm.com if (pwrState == PWR_REF) { 221411678Swendy.elsasser@arm.com assert(refreshState == REF_PRE || refreshState == REF_PD_EXIT); 221510208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refreshing\n"); 221611678Swendy.elsasser@arm.com 221710208Sandreas.hansson@arm.com // kick the refresh event loop into action again, and that 221810208Sandreas.hansson@arm.com // in turn will schedule a transition to the idle power 221910208Sandreas.hansson@arm.com // state once the refresh is done 222011678Swendy.elsasser@arm.com if (refreshState == REF_PD_EXIT) { 222111678Swendy.elsasser@arm.com // Wait for PD exit timing to complete before issuing REF 222211678Swendy.elsasser@arm.com schedule(refreshEvent, curTick() + memory.tXP); 222311678Swendy.elsasser@arm.com } else { 222411678Swendy.elsasser@arm.com schedule(refreshEvent, curTick()); 222511678Swendy.elsasser@arm.com } 222611678Swendy.elsasser@arm.com // Banks transitioned to IDLE, start REF 222711678Swendy.elsasser@arm.com refreshState = REF_START; 222810207Sandreas.hansson@arm.com } 22299243SN/A} 22309243SN/A 22319243SN/Avoid 223210618SOmar.Naji@arm.comDRAMCtrl::Rank::updatePowerStats() 223310432SOmar.Naji@arm.com{ 223411676Swendy.elsasser@arm.com // All commands up to refresh have completed 223511676Swendy.elsasser@arm.com // flush cmdList to DRAMPower 223611676Swendy.elsasser@arm.com flushCmdList(); 223711676Swendy.elsasser@arm.com 223811676Swendy.elsasser@arm.com // update the counters for DRAMPower, passing false to 223911676Swendy.elsasser@arm.com // indicate that this is not the last command in the 224011676Swendy.elsasser@arm.com // list. DRAMPower requires this information for the 224111676Swendy.elsasser@arm.com // correct calculation of the background energy at the end 224211676Swendy.elsasser@arm.com // of the simulation. Ideally we would want to call this 224311676Swendy.elsasser@arm.com // function with true once at the end of the 224411676Swendy.elsasser@arm.com // simulation. However, the discarded energy is extremly 224511676Swendy.elsasser@arm.com // small and does not effect the final results. 224611676Swendy.elsasser@arm.com power.powerlib.updateCounters(false); 224711676Swendy.elsasser@arm.com 224811676Swendy.elsasser@arm.com // call the energy function 224911676Swendy.elsasser@arm.com power.powerlib.calcEnergy(); 225011676Swendy.elsasser@arm.com 225110432SOmar.Naji@arm.com // Get the energy and power from DRAMPower 225210432SOmar.Naji@arm.com Data::MemoryPowerModel::Energy energy = 225310618SOmar.Naji@arm.com power.powerlib.getEnergy(); 225410618SOmar.Naji@arm.com Data::MemoryPowerModel::Power rank_power = 225510618SOmar.Naji@arm.com power.powerlib.getPower(); 225610432SOmar.Naji@arm.com 225710618SOmar.Naji@arm.com actEnergy = energy.act_energy * memory.devicesPerRank; 225810618SOmar.Naji@arm.com preEnergy = energy.pre_energy * memory.devicesPerRank; 225910618SOmar.Naji@arm.com readEnergy = energy.read_energy * memory.devicesPerRank; 226010618SOmar.Naji@arm.com writeEnergy = energy.write_energy * memory.devicesPerRank; 226110618SOmar.Naji@arm.com refreshEnergy = energy.ref_energy * memory.devicesPerRank; 226210618SOmar.Naji@arm.com actBackEnergy = energy.act_stdby_energy * memory.devicesPerRank; 226310618SOmar.Naji@arm.com preBackEnergy = energy.pre_stdby_energy * memory.devicesPerRank; 226411678Swendy.elsasser@arm.com actPowerDownEnergy = energy.f_act_pd_energy * memory.devicesPerRank; 226511678Swendy.elsasser@arm.com prePowerDownEnergy = energy.f_pre_pd_energy * memory.devicesPerRank; 226611678Swendy.elsasser@arm.com selfRefreshEnergy = energy.sref_energy * memory.devicesPerRank; 226710618SOmar.Naji@arm.com totalEnergy = energy.total_energy * memory.devicesPerRank; 226810618SOmar.Naji@arm.com averagePower = rank_power.average_power * memory.devicesPerRank; 226910432SOmar.Naji@arm.com} 227010432SOmar.Naji@arm.com 227110432SOmar.Naji@arm.comvoid 227211677Swendy.elsasser@arm.comDRAMCtrl::Rank::computeStats() 227311677Swendy.elsasser@arm.com{ 227411677Swendy.elsasser@arm.com DPRINTF(DRAM,"Computing final stats\n"); 227511677Swendy.elsasser@arm.com 227611677Swendy.elsasser@arm.com // Force DRAM power to update counters based on time spent in 227711677Swendy.elsasser@arm.com // current state up to curTick() 227811677Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::NOP, 0, curTick())); 227911677Swendy.elsasser@arm.com 228011677Swendy.elsasser@arm.com // Update the stats 228111677Swendy.elsasser@arm.com updatePowerStats(); 228211677Swendy.elsasser@arm.com 228311677Swendy.elsasser@arm.com // final update of power state times 228411677Swendy.elsasser@arm.com pwrStateTime[pwrState] += (curTick() - pwrStateTick); 228511677Swendy.elsasser@arm.com pwrStateTick = curTick(); 228611677Swendy.elsasser@arm.com 228711677Swendy.elsasser@arm.com} 228811677Swendy.elsasser@arm.com 228911677Swendy.elsasser@arm.comvoid 229010618SOmar.Naji@arm.comDRAMCtrl::Rank::regStats() 229110618SOmar.Naji@arm.com{ 229210618SOmar.Naji@arm.com using namespace Stats; 229310618SOmar.Naji@arm.com 229410618SOmar.Naji@arm.com pwrStateTime 229511678Swendy.elsasser@arm.com .init(6) 229610618SOmar.Naji@arm.com .name(name() + ".memoryStateTime") 229710618SOmar.Naji@arm.com .desc("Time in different power states"); 229810618SOmar.Naji@arm.com pwrStateTime.subname(0, "IDLE"); 229910618SOmar.Naji@arm.com pwrStateTime.subname(1, "REF"); 230011678Swendy.elsasser@arm.com pwrStateTime.subname(2, "SREF"); 230111678Swendy.elsasser@arm.com pwrStateTime.subname(3, "PRE_PDN"); 230211678Swendy.elsasser@arm.com pwrStateTime.subname(4, "ACT"); 230311678Swendy.elsasser@arm.com pwrStateTime.subname(5, "ACT_PDN"); 230410618SOmar.Naji@arm.com 230510618SOmar.Naji@arm.com actEnergy 230610618SOmar.Naji@arm.com .name(name() + ".actEnergy") 230710618SOmar.Naji@arm.com .desc("Energy for activate commands per rank (pJ)"); 230810618SOmar.Naji@arm.com 230910618SOmar.Naji@arm.com preEnergy 231010618SOmar.Naji@arm.com .name(name() + ".preEnergy") 231110618SOmar.Naji@arm.com .desc("Energy for precharge commands per rank (pJ)"); 231210618SOmar.Naji@arm.com 231310618SOmar.Naji@arm.com readEnergy 231410618SOmar.Naji@arm.com .name(name() + ".readEnergy") 231510618SOmar.Naji@arm.com .desc("Energy for read commands per rank (pJ)"); 231610618SOmar.Naji@arm.com 231710618SOmar.Naji@arm.com writeEnergy 231810618SOmar.Naji@arm.com .name(name() + ".writeEnergy") 231910618SOmar.Naji@arm.com .desc("Energy for write commands per rank (pJ)"); 232010618SOmar.Naji@arm.com 232110618SOmar.Naji@arm.com refreshEnergy 232210618SOmar.Naji@arm.com .name(name() + ".refreshEnergy") 232310618SOmar.Naji@arm.com .desc("Energy for refresh commands per rank (pJ)"); 232410618SOmar.Naji@arm.com 232510618SOmar.Naji@arm.com actBackEnergy 232610618SOmar.Naji@arm.com .name(name() + ".actBackEnergy") 232710618SOmar.Naji@arm.com .desc("Energy for active background per rank (pJ)"); 232810618SOmar.Naji@arm.com 232910618SOmar.Naji@arm.com preBackEnergy 233010618SOmar.Naji@arm.com .name(name() + ".preBackEnergy") 233110618SOmar.Naji@arm.com .desc("Energy for precharge background per rank (pJ)"); 233210618SOmar.Naji@arm.com 233311678Swendy.elsasser@arm.com actPowerDownEnergy 233411678Swendy.elsasser@arm.com .name(name() + ".actPowerDownEnergy") 233511678Swendy.elsasser@arm.com .desc("Energy for active power-down per rank (pJ)"); 233611678Swendy.elsasser@arm.com 233711678Swendy.elsasser@arm.com prePowerDownEnergy 233811678Swendy.elsasser@arm.com .name(name() + ".prePowerDownEnergy") 233911678Swendy.elsasser@arm.com .desc("Energy for precharge power-down per rank (pJ)"); 234011678Swendy.elsasser@arm.com 234111678Swendy.elsasser@arm.com selfRefreshEnergy 234211678Swendy.elsasser@arm.com .name(name() + ".selfRefreshEnergy") 234311678Swendy.elsasser@arm.com .desc("Energy for self refresh per rank (pJ)"); 234411678Swendy.elsasser@arm.com 234510618SOmar.Naji@arm.com totalEnergy 234610618SOmar.Naji@arm.com .name(name() + ".totalEnergy") 234710618SOmar.Naji@arm.com .desc("Total energy per rank (pJ)"); 234810618SOmar.Naji@arm.com 234910618SOmar.Naji@arm.com averagePower 235010618SOmar.Naji@arm.com .name(name() + ".averagePower") 235110618SOmar.Naji@arm.com .desc("Core power per rank (mW)"); 235211677Swendy.elsasser@arm.com 235311678Swendy.elsasser@arm.com totalIdleTime 235411678Swendy.elsasser@arm.com .name(name() + ".totalIdleTime") 235511678Swendy.elsasser@arm.com .desc("Total Idle time Per DRAM Rank"); 235611678Swendy.elsasser@arm.com 235711677Swendy.elsasser@arm.com registerDumpCallback(new RankDumpCallback(this)); 235810618SOmar.Naji@arm.com} 235910618SOmar.Naji@arm.comvoid 236010146Sandreas.hansson@arm.comDRAMCtrl::regStats() 23619243SN/A{ 23629243SN/A using namespace Stats; 23639243SN/A 23649243SN/A AbstractMemory::regStats(); 23659243SN/A 236610618SOmar.Naji@arm.com for (auto r : ranks) { 236710618SOmar.Naji@arm.com r->regStats(); 236810618SOmar.Naji@arm.com } 236910618SOmar.Naji@arm.com 23709243SN/A readReqs 23719243SN/A .name(name() + ".readReqs") 23729977SN/A .desc("Number of read requests accepted"); 23739243SN/A 23749243SN/A writeReqs 23759243SN/A .name(name() + ".writeReqs") 23769977SN/A .desc("Number of write requests accepted"); 23779831SN/A 23789831SN/A readBursts 23799831SN/A .name(name() + ".readBursts") 23809977SN/A .desc("Number of DRAM read bursts, " 23819977SN/A "including those serviced by the write queue"); 23829831SN/A 23839831SN/A writeBursts 23849831SN/A .name(name() + ".writeBursts") 23859977SN/A .desc("Number of DRAM write bursts, " 23869977SN/A "including those merged in the write queue"); 23879243SN/A 23889243SN/A servicedByWrQ 23899243SN/A .name(name() + ".servicedByWrQ") 23909977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 23919977SN/A 23929977SN/A mergedWrBursts 23939977SN/A .name(name() + ".mergedWrBursts") 23949977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 23959243SN/A 23969243SN/A neitherReadNorWrite 23979977SN/A .name(name() + ".neitherReadNorWriteReqs") 23989977SN/A .desc("Number of requests that are neither read nor write"); 23999243SN/A 24009977SN/A perBankRdBursts 24019243SN/A .init(banksPerRank * ranksPerChannel) 24029977SN/A .name(name() + ".perBankRdBursts") 24039977SN/A .desc("Per bank write bursts"); 24049243SN/A 24059977SN/A perBankWrBursts 24069243SN/A .init(banksPerRank * ranksPerChannel) 24079977SN/A .name(name() + ".perBankWrBursts") 24089977SN/A .desc("Per bank write bursts"); 24099243SN/A 24109243SN/A avgRdQLen 24119243SN/A .name(name() + ".avgRdQLen") 24129977SN/A .desc("Average read queue length when enqueuing") 24139243SN/A .precision(2); 24149243SN/A 24159243SN/A avgWrQLen 24169243SN/A .name(name() + ".avgWrQLen") 24179977SN/A .desc("Average write queue length when enqueuing") 24189243SN/A .precision(2); 24199243SN/A 24209243SN/A totQLat 24219243SN/A .name(name() + ".totQLat") 24229977SN/A .desc("Total ticks spent queuing"); 24239243SN/A 24249243SN/A totBusLat 24259243SN/A .name(name() + ".totBusLat") 24269977SN/A .desc("Total ticks spent in databus transfers"); 24279243SN/A 24289243SN/A totMemAccLat 24299243SN/A .name(name() + ".totMemAccLat") 24309977SN/A .desc("Total ticks spent from burst creation until serviced " 24319977SN/A "by the DRAM"); 24329243SN/A 24339243SN/A avgQLat 24349243SN/A .name(name() + ".avgQLat") 24359977SN/A .desc("Average queueing delay per DRAM burst") 24369243SN/A .precision(2); 24379243SN/A 24389831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 24399243SN/A 24409243SN/A avgBusLat 24419243SN/A .name(name() + ".avgBusLat") 24429977SN/A .desc("Average bus latency per DRAM burst") 24439243SN/A .precision(2); 24449243SN/A 24459831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 24469243SN/A 24479243SN/A avgMemAccLat 24489243SN/A .name(name() + ".avgMemAccLat") 24499977SN/A .desc("Average memory access latency per DRAM burst") 24509243SN/A .precision(2); 24519243SN/A 24529831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 24539243SN/A 24549243SN/A numRdRetry 24559243SN/A .name(name() + ".numRdRetry") 24569977SN/A .desc("Number of times read queue was full causing retry"); 24579243SN/A 24589243SN/A numWrRetry 24599243SN/A .name(name() + ".numWrRetry") 24609977SN/A .desc("Number of times write queue was full causing retry"); 24619243SN/A 24629243SN/A readRowHits 24639243SN/A .name(name() + ".readRowHits") 24649243SN/A .desc("Number of row buffer hits during reads"); 24659243SN/A 24669243SN/A writeRowHits 24679243SN/A .name(name() + ".writeRowHits") 24689243SN/A .desc("Number of row buffer hits during writes"); 24699243SN/A 24709243SN/A readRowHitRate 24719243SN/A .name(name() + ".readRowHitRate") 24729243SN/A .desc("Row buffer hit rate for reads") 24739243SN/A .precision(2); 24749243SN/A 24759831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 24769243SN/A 24779243SN/A writeRowHitRate 24789243SN/A .name(name() + ".writeRowHitRate") 24799243SN/A .desc("Row buffer hit rate for writes") 24809243SN/A .precision(2); 24819243SN/A 24829977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 24839243SN/A 24849243SN/A readPktSize 24859831SN/A .init(ceilLog2(burstSize) + 1) 24869243SN/A .name(name() + ".readPktSize") 24879977SN/A .desc("Read request sizes (log2)"); 24889243SN/A 24899243SN/A writePktSize 24909831SN/A .init(ceilLog2(burstSize) + 1) 24919243SN/A .name(name() + ".writePktSize") 24929977SN/A .desc("Write request sizes (log2)"); 24939243SN/A 24949243SN/A rdQLenPdf 24959567SN/A .init(readBufferSize) 24969243SN/A .name(name() + ".rdQLenPdf") 24979243SN/A .desc("What read queue length does an incoming req see"); 24989243SN/A 24999243SN/A wrQLenPdf 25009567SN/A .init(writeBufferSize) 25019243SN/A .name(name() + ".wrQLenPdf") 25029243SN/A .desc("What write queue length does an incoming req see"); 25039243SN/A 25049727SN/A bytesPerActivate 250510141SN/A .init(maxAccessesPerRow) 25069727SN/A .name(name() + ".bytesPerActivate") 25079727SN/A .desc("Bytes accessed per row activation") 25089727SN/A .flags(nozero); 25099243SN/A 251010147Sandreas.hansson@arm.com rdPerTurnAround 251110147Sandreas.hansson@arm.com .init(readBufferSize) 251210147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 251310147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 251410147Sandreas.hansson@arm.com .flags(nozero); 251510147Sandreas.hansson@arm.com 251610147Sandreas.hansson@arm.com wrPerTurnAround 251710147Sandreas.hansson@arm.com .init(writeBufferSize) 251810147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 251910147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 252010147Sandreas.hansson@arm.com .flags(nozero); 252110147Sandreas.hansson@arm.com 25229975SN/A bytesReadDRAM 25239975SN/A .name(name() + ".bytesReadDRAM") 25249975SN/A .desc("Total number of bytes read from DRAM"); 25259975SN/A 25269975SN/A bytesReadWrQ 25279975SN/A .name(name() + ".bytesReadWrQ") 25289975SN/A .desc("Total number of bytes read from write queue"); 25299243SN/A 25309243SN/A bytesWritten 25319243SN/A .name(name() + ".bytesWritten") 25329977SN/A .desc("Total number of bytes written to DRAM"); 25339243SN/A 25349977SN/A bytesReadSys 25359977SN/A .name(name() + ".bytesReadSys") 25369977SN/A .desc("Total read bytes from the system interface side"); 25379243SN/A 25389977SN/A bytesWrittenSys 25399977SN/A .name(name() + ".bytesWrittenSys") 25409977SN/A .desc("Total written bytes from the system interface side"); 25419243SN/A 25429243SN/A avgRdBW 25439243SN/A .name(name() + ".avgRdBW") 25449977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 25459243SN/A .precision(2); 25469243SN/A 25479977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 25489243SN/A 25499243SN/A avgWrBW 25509243SN/A .name(name() + ".avgWrBW") 25519977SN/A .desc("Average achieved write bandwidth in MiByte/s") 25529243SN/A .precision(2); 25539243SN/A 25549243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 25559243SN/A 25569977SN/A avgRdBWSys 25579977SN/A .name(name() + ".avgRdBWSys") 25589977SN/A .desc("Average system read bandwidth in MiByte/s") 25599243SN/A .precision(2); 25609243SN/A 25619977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 25629243SN/A 25639977SN/A avgWrBWSys 25649977SN/A .name(name() + ".avgWrBWSys") 25659977SN/A .desc("Average system write bandwidth in MiByte/s") 25669243SN/A .precision(2); 25679243SN/A 25689977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 25699243SN/A 25709243SN/A peakBW 25719243SN/A .name(name() + ".peakBW") 25729977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 25739243SN/A .precision(2); 25749243SN/A 25759831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 25769243SN/A 25779243SN/A busUtil 25789243SN/A .name(name() + ".busUtil") 25799243SN/A .desc("Data bus utilization in percentage") 25809243SN/A .precision(2); 25819243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 25829243SN/A 25839243SN/A totGap 25849243SN/A .name(name() + ".totGap") 25859243SN/A .desc("Total gap between requests"); 25869243SN/A 25879243SN/A avgGap 25889243SN/A .name(name() + ".avgGap") 25899243SN/A .desc("Average gap between requests") 25909243SN/A .precision(2); 25919243SN/A 25929243SN/A avgGap = totGap / (readReqs + writeReqs); 25939975SN/A 25949975SN/A // Stats for DRAM Power calculation based on Micron datasheet 25959975SN/A busUtilRead 25969975SN/A .name(name() + ".busUtilRead") 25979975SN/A .desc("Data bus utilization in percentage for reads") 25989975SN/A .precision(2); 25999975SN/A 26009975SN/A busUtilRead = avgRdBW / peakBW * 100; 26019975SN/A 26029975SN/A busUtilWrite 26039975SN/A .name(name() + ".busUtilWrite") 26049975SN/A .desc("Data bus utilization in percentage for writes") 26059975SN/A .precision(2); 26069975SN/A 26079975SN/A busUtilWrite = avgWrBW / peakBW * 100; 26089975SN/A 26099975SN/A pageHitRate 26109975SN/A .name(name() + ".pageHitRate") 26119975SN/A .desc("Row buffer hit rate, read and write combined") 26129975SN/A .precision(2); 26139975SN/A 26149977SN/A pageHitRate = (writeRowHits + readRowHits) / 26159977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 26169243SN/A} 26179243SN/A 26189243SN/Avoid 261910146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 26209243SN/A{ 26219243SN/A // rely on the abstract memory 26229243SN/A functionalAccess(pkt); 26239243SN/A} 26249243SN/A 26259294SN/ABaseSlavePort& 262610146Sandreas.hansson@arm.comDRAMCtrl::getSlavePort(const string &if_name, PortID idx) 26279243SN/A{ 26289243SN/A if (if_name != "port") { 26299243SN/A return MemObject::getSlavePort(if_name, idx); 26309243SN/A } else { 26319243SN/A return port; 26329243SN/A } 26339243SN/A} 26349243SN/A 263510913Sandreas.sandberg@arm.comDrainState 263610913Sandreas.sandberg@arm.comDRAMCtrl::drain() 26379243SN/A{ 26389243SN/A // if there is anything in any of our internal queues, keep track 26399243SN/A // of that as well 264011676Swendy.elsasser@arm.com if (!(writeQueue.empty() && readQueue.empty() && respQueue.empty() && 264111676Swendy.elsasser@arm.com allRanksDrained())) { 264211676Swendy.elsasser@arm.com 26439352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 26449567SN/A " resp: %d\n", writeQueue.size(), readQueue.size(), 26459567SN/A respQueue.size()); 264610206Sandreas.hansson@arm.com 264711678Swendy.elsasser@arm.com // the only queue that is not drained automatically over time 264810206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 264910206Sandreas.hansson@arm.com if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 265010206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 265110206Sandreas.hansson@arm.com } 265211678Swendy.elsasser@arm.com 265311678Swendy.elsasser@arm.com // also need to kick off events to exit self-refresh 265411678Swendy.elsasser@arm.com for (auto r : ranks) { 265511678Swendy.elsasser@arm.com // force self-refresh exit, which in turn will issue auto-refresh 265611678Swendy.elsasser@arm.com if (r->pwrState == PWR_SREF) { 265711678Swendy.elsasser@arm.com DPRINTF(DRAM,"Rank%d: Forcing self-refresh wakeup in drain\n", 265811678Swendy.elsasser@arm.com r->rank); 265911678Swendy.elsasser@arm.com r->scheduleWakeUpEvent(tXS); 266011678Swendy.elsasser@arm.com } 266111678Swendy.elsasser@arm.com } 266211678Swendy.elsasser@arm.com 266310913Sandreas.sandberg@arm.com return DrainState::Draining; 266410912Sandreas.sandberg@arm.com } else { 266510913Sandreas.sandberg@arm.com return DrainState::Drained; 26669243SN/A } 26679243SN/A} 26689243SN/A 266911676Swendy.elsasser@arm.combool 267011676Swendy.elsasser@arm.comDRAMCtrl::allRanksDrained() const 267111676Swendy.elsasser@arm.com{ 267211676Swendy.elsasser@arm.com // true until proven false 267311676Swendy.elsasser@arm.com bool all_ranks_drained = true; 267411676Swendy.elsasser@arm.com for (auto r : ranks) { 267511676Swendy.elsasser@arm.com // then verify that the power state is IDLE 267611676Swendy.elsasser@arm.com // ensuring all banks are closed and rank is not in a low power state 267711676Swendy.elsasser@arm.com all_ranks_drained = r->inPwrIdleState() && all_ranks_drained; 267811676Swendy.elsasser@arm.com } 267911676Swendy.elsasser@arm.com return all_ranks_drained; 268011676Swendy.elsasser@arm.com} 268111676Swendy.elsasser@arm.com 268210619Sandreas.hansson@arm.comvoid 268310619Sandreas.hansson@arm.comDRAMCtrl::drainResume() 268410619Sandreas.hansson@arm.com{ 268510619Sandreas.hansson@arm.com if (!isTimingMode && system()->isTimingMode()) { 268610619Sandreas.hansson@arm.com // if we switched to timing mode, kick things into action, 268710619Sandreas.hansson@arm.com // and behave as if we restored from a checkpoint 268810619Sandreas.hansson@arm.com startup(); 268910619Sandreas.hansson@arm.com } else if (isTimingMode && !system()->isTimingMode()) { 269010619Sandreas.hansson@arm.com // if we switch from timing mode, stop the refresh events to 269110619Sandreas.hansson@arm.com // not cause issues with KVM 269210619Sandreas.hansson@arm.com for (auto r : ranks) { 269310619Sandreas.hansson@arm.com r->suspend(); 269410619Sandreas.hansson@arm.com } 269510619Sandreas.hansson@arm.com } 269610619Sandreas.hansson@arm.com 269710619Sandreas.hansson@arm.com // update the mode 269810619Sandreas.hansson@arm.com isTimingMode = system()->isTimingMode(); 269910619Sandreas.hansson@arm.com} 270010619Sandreas.hansson@arm.com 270110146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 27029243SN/A : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 27039243SN/A memory(_memory) 27049243SN/A{ } 27059243SN/A 27069243SN/AAddrRangeList 270710146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 27089243SN/A{ 27099243SN/A AddrRangeList ranges; 27109243SN/A ranges.push_back(memory.getAddrRange()); 27119243SN/A return ranges; 27129243SN/A} 27139243SN/A 27149243SN/Avoid 271510146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 27169243SN/A{ 27179243SN/A pkt->pushLabel(memory.name()); 27189243SN/A 27199243SN/A if (!queue.checkFunctional(pkt)) { 27209243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 27219243SN/A // calls recvAtomic() and throws away the latency; we can save a 27229243SN/A // little here by just not calculating the latency. 27239243SN/A memory.recvFunctional(pkt); 27249243SN/A } 27259243SN/A 27269243SN/A pkt->popLabel(); 27279243SN/A} 27289243SN/A 27299243SN/ATick 273010146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 27319243SN/A{ 27329243SN/A return memory.recvAtomic(pkt); 27339243SN/A} 27349243SN/A 27359243SN/Abool 273610146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 27379243SN/A{ 27389243SN/A // pass it to the memory controller 27399243SN/A return memory.recvTimingReq(pkt); 27409243SN/A} 27419243SN/A 274210146Sandreas.hansson@arm.comDRAMCtrl* 274310146Sandreas.hansson@arm.comDRAMCtrlParams::create() 27449243SN/A{ 274510146Sandreas.hansson@arm.com return new DRAMCtrl(this); 27469243SN/A} 2747