dram_ctrl.cc revision 11846
19243SN/A/* 211846Swendy.elsasser@arm.com * Copyright (c) 2010-2017 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 4310618SOmar.Naji@arm.com * Omar Naji 4411678Swendy.elsasser@arm.com * Wendy Elsasser 459243SN/A */ 469243SN/A 4711793Sbrandon.potter@amd.com#include "mem/dram_ctrl.hh" 4811793Sbrandon.potter@amd.com 4910146Sandreas.hansson@arm.com#include "base/bitfield.hh" 509356SN/A#include "base/trace.hh" 5110146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 5210247Sandreas.hansson@arm.com#include "debug/DRAMPower.hh" 5310208Sandreas.hansson@arm.com#include "debug/DRAMState.hh" 549352SN/A#include "debug/Drain.hh" 559814SN/A#include "sim/system.hh" 569243SN/A 579243SN/Ausing namespace std; 5810432SOmar.Naji@arm.comusing namespace Data; 599243SN/A 6010146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 619243SN/A AbstractMemory(p), 6210619Sandreas.hansson@arm.com port(name() + ".port", *this), isTimingMode(false), 639243SN/A retryRdReq(false), retryWrReq(false), 6410211Sandreas.hansson@arm.com busState(READ), 6511678Swendy.elsasser@arm.com busStateNext(READ), 6610618SOmar.Naji@arm.com nextReqEvent(this), respondEvent(this), 6710489SOmar.Naji@arm.com deviceSize(p->device_size), 689831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 699831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 709831SN/A devicesPerRank(p->devices_per_rank), 719831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 729831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 7310140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 7410646Sandreas.hansson@arm.com columnsPerStripe(range.interleaved() ? range.granularity() / burstSize : 1), 759243SN/A ranksPerChannel(p->ranks_per_channel), 7610394Swendy.elsasser@arm.com bankGroupsPerRank(p->bank_groups_per_rank), 7710394Swendy.elsasser@arm.com bankGroupArch(p->bank_groups_per_rank > 0), 789566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 799243SN/A readBufferSize(p->read_buffer_size), 809243SN/A writeBufferSize(p->write_buffer_size), 8110140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 8210140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 8310147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 8410147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 8510393Swendy.elsasser@arm.com tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST), 8610394Swendy.elsasser@arm.com tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), 8710394Swendy.elsasser@arm.com tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 8811673SOmar.Naji@arm.com tRRD_L(p->tRRD_L), tXAW(p->tXAW), tXP(p->tXP), tXS(p->tXS), 8911673SOmar.Naji@arm.com activationLimit(p->activation_limit), 909243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 919243SN/A pageMgmt(p->page_policy), 9210141SN/A maxAccessesPerRow(p->max_accesses_per_row), 939726SN/A frontendLatency(p->static_frontend_latency), 949726SN/A backendLatency(p->static_backend_latency), 9510618SOmar.Naji@arm.com busBusyUntil(0), prevArrival(0), 9610618SOmar.Naji@arm.com nextReqTime(0), activeRank(0), timeStampOffset(0) 979243SN/A{ 9810620Sandreas.hansson@arm.com // sanity check the ranks since we rely on bit slicing for the 9910620Sandreas.hansson@arm.com // address decoding 10010620Sandreas.hansson@arm.com fatal_if(!isPowerOf2(ranksPerChannel), "DRAM rank count of %d is not " 10110620Sandreas.hansson@arm.com "allowed, must be a power of two\n", ranksPerChannel); 10210620Sandreas.hansson@arm.com 10310889Sandreas.hansson@arm.com fatal_if(!isPowerOf2(burstSize), "DRAM burst size %d is not allowed, " 10410889Sandreas.hansson@arm.com "must be a power of two\n", burstSize); 10510889Sandreas.hansson@arm.com 10610618SOmar.Naji@arm.com for (int i = 0; i < ranksPerChannel; i++) { 10710618SOmar.Naji@arm.com Rank* rank = new Rank(*this, p); 10810618SOmar.Naji@arm.com ranks.push_back(rank); 10910432SOmar.Naji@arm.com 11010618SOmar.Naji@arm.com rank->actTicks.resize(activationLimit, 0); 11110618SOmar.Naji@arm.com rank->banks.resize(banksPerRank); 11210618SOmar.Naji@arm.com rank->rank = i; 11310432SOmar.Naji@arm.com 11410246Sandreas.hansson@arm.com for (int b = 0; b < banksPerRank; b++) { 11510618SOmar.Naji@arm.com rank->banks[b].bank = b; 11610561SOmar.Naji@arm.com // GDDR addressing of banks to BG is linear. 11710561SOmar.Naji@arm.com // Here we assume that all DRAM generations address bank groups as 11810561SOmar.Naji@arm.com // follows: 11910394Swendy.elsasser@arm.com if (bankGroupArch) { 12010394Swendy.elsasser@arm.com // Simply assign lower bits to bank group in order to 12110394Swendy.elsasser@arm.com // rotate across bank groups as banks are incremented 12210394Swendy.elsasser@arm.com // e.g. with 4 banks per bank group and 16 banks total: 12310394Swendy.elsasser@arm.com // banks 0,4,8,12 are in bank group 0 12410394Swendy.elsasser@arm.com // banks 1,5,9,13 are in bank group 1 12510394Swendy.elsasser@arm.com // banks 2,6,10,14 are in bank group 2 12610394Swendy.elsasser@arm.com // banks 3,7,11,15 are in bank group 3 12710618SOmar.Naji@arm.com rank->banks[b].bankgr = b % bankGroupsPerRank; 12810394Swendy.elsasser@arm.com } else { 12910394Swendy.elsasser@arm.com // No bank groups; simply assign to bank number 13010618SOmar.Naji@arm.com rank->banks[b].bankgr = b; 13110394Swendy.elsasser@arm.com } 13210246Sandreas.hansson@arm.com } 13310246Sandreas.hansson@arm.com } 13410246Sandreas.hansson@arm.com 13510140SN/A // perform a basic check of the write thresholds 13610140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 13710140SN/A fatal("Write buffer low threshold %d must be smaller than the " 13810140SN/A "high threshold %d\n", p->write_low_thresh_perc, 13910140SN/A p->write_high_thresh_perc); 1409243SN/A 1419243SN/A // determine the rows per bank by looking at the total capacity 1429567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1439243SN/A 14410489SOmar.Naji@arm.com // determine the dram actual capacity from the DRAM config in Mbytes 14510489SOmar.Naji@arm.com uint64_t deviceCapacity = deviceSize / (1024 * 1024) * devicesPerRank * 14610489SOmar.Naji@arm.com ranksPerChannel; 14710489SOmar.Naji@arm.com 14810489SOmar.Naji@arm.com // if actual DRAM size does not match memory capacity in system warn! 14910489SOmar.Naji@arm.com if (deviceCapacity != capacity / (1024 * 1024)) 15010489SOmar.Naji@arm.com warn("DRAM device capacity (%d Mbytes) does not match the " 15110489SOmar.Naji@arm.com "address range assigned (%d Mbytes)\n", deviceCapacity, 15210489SOmar.Naji@arm.com capacity / (1024 * 1024)); 15310489SOmar.Naji@arm.com 1549243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1559243SN/A AbstractMemory::size()); 1569831SN/A 1579831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1589831SN/A rowBufferSize, columnsPerRowBuffer); 1599831SN/A 1609831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1619243SN/A 16210207Sandreas.hansson@arm.com // some basic sanity checks 16310207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 16410207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 16510207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 16610207Sandreas.hansson@arm.com } 16710394Swendy.elsasser@arm.com 16810394Swendy.elsasser@arm.com // basic bank group architecture checks -> 16910394Swendy.elsasser@arm.com if (bankGroupArch) { 17010394Swendy.elsasser@arm.com // must have at least one bank per bank group 17110394Swendy.elsasser@arm.com if (bankGroupsPerRank > banksPerRank) { 17210394Swendy.elsasser@arm.com fatal("banks per rank (%d) must be equal to or larger than " 17310394Swendy.elsasser@arm.com "banks groups per rank (%d)\n", 17410394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 17510394Swendy.elsasser@arm.com } 17610394Swendy.elsasser@arm.com // must have same number of banks in each bank group 17710394Swendy.elsasser@arm.com if ((banksPerRank % bankGroupsPerRank) != 0) { 17810394Swendy.elsasser@arm.com fatal("Banks per rank (%d) must be evenly divisible by bank groups " 17910394Swendy.elsasser@arm.com "per rank (%d) for equal banks per bank group\n", 18010394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 18110394Swendy.elsasser@arm.com } 18210394Swendy.elsasser@arm.com // tCCD_L should be greater than minimal, back-to-back burst delay 18310394Swendy.elsasser@arm.com if (tCCD_L <= tBURST) { 18410394Swendy.elsasser@arm.com fatal("tCCD_L (%d) should be larger than tBURST (%d) when " 18510394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 18610394Swendy.elsasser@arm.com tCCD_L, tBURST, bankGroupsPerRank); 18710394Swendy.elsasser@arm.com } 18810394Swendy.elsasser@arm.com // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay 18910561SOmar.Naji@arm.com // some datasheets might specify it equal to tRRD 19010561SOmar.Naji@arm.com if (tRRD_L < tRRD) { 19110394Swendy.elsasser@arm.com fatal("tRRD_L (%d) should be larger than tRRD (%d) when " 19210394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 19310394Swendy.elsasser@arm.com tRRD_L, tRRD, bankGroupsPerRank); 19410394Swendy.elsasser@arm.com } 19510394Swendy.elsasser@arm.com } 19610394Swendy.elsasser@arm.com 1979243SN/A} 1989243SN/A 1999243SN/Avoid 20010146Sandreas.hansson@arm.comDRAMCtrl::init() 20110140SN/A{ 20210466Sandreas.hansson@arm.com AbstractMemory::init(); 20310466Sandreas.hansson@arm.com 20410466Sandreas.hansson@arm.com if (!port.isConnected()) { 20510146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 20610140SN/A } else { 20710140SN/A port.sendRangeChange(); 20810140SN/A } 20910646Sandreas.hansson@arm.com 21010646Sandreas.hansson@arm.com // a bit of sanity checks on the interleaving, save it for here to 21110646Sandreas.hansson@arm.com // ensure that the system pointer is initialised 21210646Sandreas.hansson@arm.com if (range.interleaved()) { 21310646Sandreas.hansson@arm.com if (channels != range.stripes()) 21410646Sandreas.hansson@arm.com fatal("%s has %d interleaved address stripes but %d channel(s)\n", 21510646Sandreas.hansson@arm.com name(), range.stripes(), channels); 21610646Sandreas.hansson@arm.com 21710646Sandreas.hansson@arm.com if (addrMapping == Enums::RoRaBaChCo) { 21810646Sandreas.hansson@arm.com if (rowBufferSize != range.granularity()) { 21910646Sandreas.hansson@arm.com fatal("Channel interleaving of %s doesn't match RoRaBaChCo " 22010646Sandreas.hansson@arm.com "address map\n", name()); 22110646Sandreas.hansson@arm.com } 22210646Sandreas.hansson@arm.com } else if (addrMapping == Enums::RoRaBaCoCh || 22310646Sandreas.hansson@arm.com addrMapping == Enums::RoCoRaBaCh) { 22410646Sandreas.hansson@arm.com // for the interleavings with channel bits in the bottom, 22510646Sandreas.hansson@arm.com // if the system uses a channel striping granularity that 22610646Sandreas.hansson@arm.com // is larger than the DRAM burst size, then map the 22710646Sandreas.hansson@arm.com // sequential accesses within a stripe to a number of 22810646Sandreas.hansson@arm.com // columns in the DRAM, effectively placing some of the 22910646Sandreas.hansson@arm.com // lower-order column bits as the least-significant bits 23010646Sandreas.hansson@arm.com // of the address (above the ones denoting the burst size) 23110646Sandreas.hansson@arm.com assert(columnsPerStripe >= 1); 23210646Sandreas.hansson@arm.com 23310646Sandreas.hansson@arm.com // channel striping has to be done at a granularity that 23410646Sandreas.hansson@arm.com // is equal or larger to a cache line 23510646Sandreas.hansson@arm.com if (system()->cacheLineSize() > range.granularity()) { 23610646Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at least as large " 23710646Sandreas.hansson@arm.com "as the cache line size\n", name()); 23810646Sandreas.hansson@arm.com } 23910646Sandreas.hansson@arm.com 24010646Sandreas.hansson@arm.com // ...and equal or smaller than the row-buffer size 24110646Sandreas.hansson@arm.com if (rowBufferSize < range.granularity()) { 24210646Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at most as large " 24310646Sandreas.hansson@arm.com "as the row-buffer size\n", name()); 24410646Sandreas.hansson@arm.com } 24510646Sandreas.hansson@arm.com // this is essentially the check above, so just to be sure 24610646Sandreas.hansson@arm.com assert(columnsPerStripe <= columnsPerRowBuffer); 24710646Sandreas.hansson@arm.com } 24810646Sandreas.hansson@arm.com } 24910140SN/A} 25010140SN/A 25110140SN/Avoid 25210146Sandreas.hansson@arm.comDRAMCtrl::startup() 2539243SN/A{ 25410619Sandreas.hansson@arm.com // remember the memory system mode of operation 25510619Sandreas.hansson@arm.com isTimingMode = system()->isTimingMode(); 25610618SOmar.Naji@arm.com 25710619Sandreas.hansson@arm.com if (isTimingMode) { 25810619Sandreas.hansson@arm.com // timestamp offset should be in clock cycles for DRAMPower 25910619Sandreas.hansson@arm.com timeStampOffset = divCeil(curTick(), tCK); 26010619Sandreas.hansson@arm.com 26110619Sandreas.hansson@arm.com // update the start tick for the precharge accounting to the 26210619Sandreas.hansson@arm.com // current tick 26310619Sandreas.hansson@arm.com for (auto r : ranks) { 26410619Sandreas.hansson@arm.com r->startup(curTick() + tREFI - tRP); 26510619Sandreas.hansson@arm.com } 26610619Sandreas.hansson@arm.com 26710619Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 26810619Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 26910619Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 27010619Sandreas.hansson@arm.com // start of simulation 27110619Sandreas.hansson@arm.com busBusyUntil = curTick() + tRP + tRCD + tCL; 27210618SOmar.Naji@arm.com } 2739243SN/A} 2749243SN/A 2759243SN/ATick 27610146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 2779243SN/A{ 2789243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 2799243SN/A 28011334Sandreas.hansson@arm.com panic_if(pkt->cacheResponding(), "Should not see packets where cache " 28111334Sandreas.hansson@arm.com "is responding"); 28211334Sandreas.hansson@arm.com 2839243SN/A // do the actual memory access and turn the packet into a response 2849243SN/A access(pkt); 2859243SN/A 2869243SN/A Tick latency = 0; 28711334Sandreas.hansson@arm.com if (pkt->hasData()) { 2889243SN/A // this value is not supposed to be accurate, just enough to 2899243SN/A // keep things going, mimic a closed page 2909243SN/A latency = tRP + tRCD + tCL; 2919243SN/A } 2929243SN/A return latency; 2939243SN/A} 2949243SN/A 2959243SN/Abool 29610146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 2979243SN/A{ 2989831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 2999831SN/A readBufferSize, readQueue.size() + respQueue.size(), 3009831SN/A neededEntries); 3019243SN/A 3029831SN/A return 3039831SN/A (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 3049243SN/A} 3059243SN/A 3069243SN/Abool 30710146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 3089243SN/A{ 3099831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 3109831SN/A writeBufferSize, writeQueue.size(), neededEntries); 3119831SN/A return (writeQueue.size() + neededEntries) > writeBufferSize; 3129243SN/A} 3139243SN/A 31410146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 31510146Sandreas.hansson@arm.comDRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 31610143SN/A bool isRead) 3179243SN/A{ 3189669SN/A // decode the address based on the address mapping scheme, with 31910136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 32010136SN/A // channel, respectively 3219243SN/A uint8_t rank; 3229967SN/A uint8_t bank; 32310245Sandreas.hansson@arm.com // use a 64-bit unsigned during the computations as the row is 32410245Sandreas.hansson@arm.com // always the top bits, and check before creating the DRAMPacket 32510245Sandreas.hansson@arm.com uint64_t row; 3269243SN/A 32710286Sandreas.hansson@arm.com // truncate the address to a DRAM burst, which makes it unique to 32810286Sandreas.hansson@arm.com // a specific column, row, bank, rank and channel 3299831SN/A Addr addr = dramPktAddr / burstSize; 3309243SN/A 3319491SN/A // we have removed the lowest order address bits that denote the 3329831SN/A // position within the column 33310136SN/A if (addrMapping == Enums::RoRaBaChCo) { 3349491SN/A // the lowest order bits denote the column to ensure that 3359491SN/A // sequential cache lines occupy the same row 3369831SN/A addr = addr / columnsPerRowBuffer; 3379243SN/A 3389669SN/A // take out the channel part of the address 3399566SN/A addr = addr / channels; 3409566SN/A 3419669SN/A // after the channel bits, get the bank bits to interleave 3429669SN/A // over the banks 3439669SN/A bank = addr % banksPerRank; 3449669SN/A addr = addr / banksPerRank; 3459669SN/A 3469669SN/A // after the bank, we get the rank bits which thus interleaves 3479669SN/A // over the ranks 3489669SN/A rank = addr % ranksPerChannel; 3499669SN/A addr = addr / ranksPerChannel; 3509669SN/A 35111189Sandreas.hansson@arm.com // lastly, get the row bits, no need to remove them from addr 3529669SN/A row = addr % rowsPerBank; 35310136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 35410286Sandreas.hansson@arm.com // take out the lower-order column bits 35510286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 35610286Sandreas.hansson@arm.com 3579669SN/A // take out the channel part of the address 3589669SN/A addr = addr / channels; 3599669SN/A 36010286Sandreas.hansson@arm.com // next, the higher-order column bites 36110286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3629669SN/A 3639669SN/A // after the column bits, we get the bank bits to interleave 3649491SN/A // over the banks 3659243SN/A bank = addr % banksPerRank; 3669243SN/A addr = addr / banksPerRank; 3679243SN/A 3689491SN/A // after the bank, we get the rank bits which thus interleaves 3699491SN/A // over the ranks 3709243SN/A rank = addr % ranksPerChannel; 3719243SN/A addr = addr / ranksPerChannel; 3729243SN/A 37311189Sandreas.hansson@arm.com // lastly, get the row bits, no need to remove them from addr 3749243SN/A row = addr % rowsPerBank; 37510136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 3769491SN/A // optimise for closed page mode and utilise maximum 3779491SN/A // parallelism of the DRAM (at the cost of power) 3789491SN/A 37910286Sandreas.hansson@arm.com // take out the lower-order column bits 38010286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 38110286Sandreas.hansson@arm.com 3829566SN/A // take out the channel part of the address, not that this has 3839566SN/A // to match with how accesses are interleaved between the 3849566SN/A // controllers in the address mapping 3859566SN/A addr = addr / channels; 3869566SN/A 3879491SN/A // start with the bank bits, as this provides the maximum 3889491SN/A // opportunity for parallelism between requests 3899243SN/A bank = addr % banksPerRank; 3909243SN/A addr = addr / banksPerRank; 3919243SN/A 3929491SN/A // next get the rank bits 3939243SN/A rank = addr % ranksPerChannel; 3949243SN/A addr = addr / ranksPerChannel; 3959243SN/A 39610286Sandreas.hansson@arm.com // next, the higher-order column bites 39710286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3989243SN/A 39911189Sandreas.hansson@arm.com // lastly, get the row bits, no need to remove them from addr 4009243SN/A row = addr % rowsPerBank; 4019243SN/A } else 4029243SN/A panic("Unknown address mapping policy chosen!"); 4039243SN/A 4049243SN/A assert(rank < ranksPerChannel); 4059243SN/A assert(bank < banksPerRank); 4069243SN/A assert(row < rowsPerBank); 40710245Sandreas.hansson@arm.com assert(row < Bank::NO_ROW); 4089243SN/A 4099243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 4109831SN/A dramPktAddr, rank, bank, row); 4119243SN/A 4129243SN/A // create the corresponding DRAM packet with the entry time and 4139567SN/A // ready time set to the current tick, the latter will be updated 4149567SN/A // later 4159967SN/A uint16_t bank_id = banksPerRank * rank + bank; 4169967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 41710618SOmar.Naji@arm.com size, ranks[rank]->banks[bank], *ranks[rank]); 4189243SN/A} 4199243SN/A 4209243SN/Avoid 42110146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 4229243SN/A{ 4239243SN/A // only add to the read queue here. whenever the request is 4249243SN/A // eventually done, set the readyTime, and call schedule() 4259243SN/A assert(!pkt->isWrite()); 4269243SN/A 4279831SN/A assert(pktCount != 0); 4289831SN/A 4299831SN/A // if the request size is larger than burst size, the pkt is split into 4309831SN/A // multiple DRAM packets 4319831SN/A // Note if the pkt starting address is not aligened to burst size, the 4329831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 4339831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 4349831SN/A // check read packets against packets in write queue. 4359243SN/A Addr addr = pkt->getAddr(); 4369831SN/A unsigned pktsServicedByWrQ = 0; 4379831SN/A BurstHelper* burst_helper = NULL; 4389831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4399831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4409831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4419831SN/A readPktSize[ceilLog2(size)]++; 4429831SN/A readBursts++; 4439243SN/A 4449831SN/A // First check write buffer to see if the data is already at 4459831SN/A // the controller 4469831SN/A bool foundInWrQ = false; 44710889Sandreas.hansson@arm.com Addr burst_addr = burstAlign(addr); 44810889Sandreas.hansson@arm.com // if the burst address is not present then there is no need 44910889Sandreas.hansson@arm.com // looking any further 45010889Sandreas.hansson@arm.com if (isInWriteQueue.find(burst_addr) != isInWriteQueue.end()) { 45110889Sandreas.hansson@arm.com for (const auto& p : writeQueue) { 45210889Sandreas.hansson@arm.com // check if the read is subsumed in the write queue 45310889Sandreas.hansson@arm.com // packet we are looking at 45410889Sandreas.hansson@arm.com if (p->addr <= addr && (addr + size) <= (p->addr + p->size)) { 45510889Sandreas.hansson@arm.com foundInWrQ = true; 45610889Sandreas.hansson@arm.com servicedByWrQ++; 45710889Sandreas.hansson@arm.com pktsServicedByWrQ++; 45810889Sandreas.hansson@arm.com DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 45910889Sandreas.hansson@arm.com "write queue\n", addr, size); 46010889Sandreas.hansson@arm.com bytesReadWrQ += burstSize; 46110889Sandreas.hansson@arm.com break; 46210889Sandreas.hansson@arm.com } 4639831SN/A } 4649243SN/A } 4659831SN/A 4669831SN/A // If not found in the write q, make a DRAM packet and 4679831SN/A // push it onto the read queue 4689831SN/A if (!foundInWrQ) { 4699831SN/A 4709831SN/A // Make the burst helper for split packets 4719831SN/A if (pktCount > 1 && burst_helper == NULL) { 4729831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 4739831SN/A "dram requests\n", pkt->getAddr(), pktCount); 4749831SN/A burst_helper = new BurstHelper(pktCount); 4759831SN/A } 4769831SN/A 4779966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 4789831SN/A dram_pkt->burstHelper = burst_helper; 4799831SN/A 4809831SN/A assert(!readQueueFull(1)); 4819831SN/A rdQLenPdf[readQueue.size() + respQueue.size()]++; 4829831SN/A 4839831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 4849831SN/A 4859831SN/A readQueue.push_back(dram_pkt); 4869831SN/A 48711678Swendy.elsasser@arm.com // increment read entries of the rank 48811678Swendy.elsasser@arm.com ++dram_pkt->rankRef.readEntries; 48911678Swendy.elsasser@arm.com 4909831SN/A // Update stats 4919831SN/A avgRdQLen = readQueue.size() + respQueue.size(); 4929831SN/A } 4939831SN/A 4949831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 4959831SN/A addr = (addr | (burstSize - 1)) + 1; 4969243SN/A } 4979243SN/A 4989831SN/A // If all packets are serviced by write queue, we send the repsonse back 4999831SN/A if (pktsServicedByWrQ == pktCount) { 5009831SN/A accessAndRespond(pkt, frontendLatency); 5019831SN/A return; 5029831SN/A } 5039243SN/A 5049831SN/A // Update how many split packets are serviced by write queue 5059831SN/A if (burst_helper != NULL) 5069831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 5079243SN/A 50810206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 50910206Sandreas.hansson@arm.com // queue, do so now 51010206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 5119567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 5129567SN/A schedule(nextReqEvent, curTick()); 5139243SN/A } 5149243SN/A} 5159243SN/A 5169243SN/Avoid 51710146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 5189243SN/A{ 5199243SN/A // only add to the write queue here. whenever the request is 5209243SN/A // eventually done, set the readyTime, and call schedule() 5219243SN/A assert(pkt->isWrite()); 5229243SN/A 5239831SN/A // if the request size is larger than burst size, the pkt is split into 5249831SN/A // multiple DRAM packets 5259831SN/A Addr addr = pkt->getAddr(); 5269831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 5279831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 5289831SN/A pkt->getAddr() + pkt->getSize()) - addr; 5299831SN/A writePktSize[ceilLog2(size)]++; 5309831SN/A writeBursts++; 5319243SN/A 5329832SN/A // see if we can merge with an existing item in the write 53310889Sandreas.hansson@arm.com // queue and keep track of whether we have merged or not 53410889Sandreas.hansson@arm.com bool merged = isInWriteQueue.find(burstAlign(addr)) != 53510889Sandreas.hansson@arm.com isInWriteQueue.end(); 5369243SN/A 5379832SN/A // if the item was not merged we need to create a new write 5389832SN/A // and enqueue it 5399832SN/A if (!merged) { 5409966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 5419243SN/A 5429832SN/A assert(writeQueue.size() < writeBufferSize); 5439832SN/A wrQLenPdf[writeQueue.size()]++; 5449243SN/A 5459832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 5469831SN/A 5479832SN/A writeQueue.push_back(dram_pkt); 54810889Sandreas.hansson@arm.com isInWriteQueue.insert(burstAlign(addr)); 54910889Sandreas.hansson@arm.com assert(writeQueue.size() == isInWriteQueue.size()); 5509831SN/A 5519832SN/A // Update stats 5529832SN/A avgWrQLen = writeQueue.size(); 55311678Swendy.elsasser@arm.com 55411678Swendy.elsasser@arm.com // increment write entries of the rank 55511678Swendy.elsasser@arm.com ++dram_pkt->rankRef.writeEntries; 5569977SN/A } else { 55710889Sandreas.hansson@arm.com DPRINTF(DRAM, "Merging write burst with existing queue entry\n"); 55810889Sandreas.hansson@arm.com 5599977SN/A // keep track of the fact that this burst effectively 5609977SN/A // disappeared as it was merged with an existing one 5619977SN/A mergedWrBursts++; 5629832SN/A } 5639832SN/A 5649831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 5659831SN/A addr = (addr | (burstSize - 1)) + 1; 5669831SN/A } 5679243SN/A 5689243SN/A // we do not wait for the writes to be send to the actual memory, 5699243SN/A // but instead take responsibility for the consistency here and 5709243SN/A // snoop the write queue for any upcoming reads 5719831SN/A // @todo, if a pkt size is larger than burst size, we might need a 5729831SN/A // different front end latency 5739726SN/A accessAndRespond(pkt, frontendLatency); 5749243SN/A 57510206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 57610206Sandreas.hansson@arm.com // queue, do so now 57710206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 57810206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 57910206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 5809243SN/A } 5819243SN/A} 5829243SN/A 5839243SN/Avoid 58410146Sandreas.hansson@arm.comDRAMCtrl::printQs() const { 5859243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 5869833SN/A for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 5879243SN/A DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 5889243SN/A } 5899243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 5909833SN/A for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 5919243SN/A DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 5929243SN/A } 5939243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 5949833SN/A for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 5959243SN/A DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 5969243SN/A } 5979243SN/A} 5989243SN/A 5999243SN/Abool 60010146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 6019243SN/A{ 6029243SN/A // This is where we enter from the outside world 6039567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 6049831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 6059243SN/A 60611334Sandreas.hansson@arm.com panic_if(pkt->cacheResponding(), "Should not see packets where cache " 60711334Sandreas.hansson@arm.com "is responding"); 60811334Sandreas.hansson@arm.com 60911334Sandreas.hansson@arm.com panic_if(!(pkt->isRead() || pkt->isWrite()), 61011334Sandreas.hansson@arm.com "Should only see read and writes at memory controller\n"); 6119243SN/A 6129243SN/A // Calc avg gap between requests 6139243SN/A if (prevArrival != 0) { 6149243SN/A totGap += curTick() - prevArrival; 6159243SN/A } 6169243SN/A prevArrival = curTick(); 6179243SN/A 6189831SN/A 6199831SN/A // Find out how many dram packets a pkt translates to 6209831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 6219831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 6229831SN/A // multiple dram packets 6239243SN/A unsigned size = pkt->getSize(); 6249831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 6259831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 6269243SN/A 6279243SN/A // check local buffers and do not accept if full 6289243SN/A if (pkt->isRead()) { 6299567SN/A assert(size != 0); 6309831SN/A if (readQueueFull(dram_pkt_count)) { 6319567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 6329243SN/A // remember that we have to retry this port 6339243SN/A retryRdReq = true; 6349243SN/A numRdRetry++; 6359243SN/A return false; 6369243SN/A } else { 6379831SN/A addToReadQueue(pkt, dram_pkt_count); 6389243SN/A readReqs++; 6399977SN/A bytesReadSys += size; 6409243SN/A } 64111334Sandreas.hansson@arm.com } else { 64211334Sandreas.hansson@arm.com assert(pkt->isWrite()); 6439567SN/A assert(size != 0); 6449831SN/A if (writeQueueFull(dram_pkt_count)) { 6459567SN/A DPRINTF(DRAM, "Write queue full, not accepting\n"); 6469243SN/A // remember that we have to retry this port 6479243SN/A retryWrReq = true; 6489243SN/A numWrRetry++; 6499243SN/A return false; 6509243SN/A } else { 6519831SN/A addToWriteQueue(pkt, dram_pkt_count); 6529243SN/A writeReqs++; 6539977SN/A bytesWrittenSys += size; 6549243SN/A } 6559243SN/A } 6569243SN/A 6579243SN/A return true; 6589243SN/A} 6599243SN/A 6609243SN/Avoid 66110146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 6629243SN/A{ 6639243SN/A DPRINTF(DRAM, 6649243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 6659243SN/A 6669831SN/A DRAMPacket* dram_pkt = respQueue.front(); 6679243SN/A 66811678Swendy.elsasser@arm.com // if a read has reached its ready-time, decrement the number of reads 66911678Swendy.elsasser@arm.com // At this point the packet has been handled and there is a possibility 67011678Swendy.elsasser@arm.com // to switch to low-power mode if no other packet is available 67111678Swendy.elsasser@arm.com --dram_pkt->rankRef.readEntries; 67211678Swendy.elsasser@arm.com DPRINTF(DRAM, "number of read entries for rank %d is %d\n", 67311678Swendy.elsasser@arm.com dram_pkt->rank, dram_pkt->rankRef.readEntries); 67411678Swendy.elsasser@arm.com 67511678Swendy.elsasser@arm.com // counter should at least indicate one outstanding request 67611678Swendy.elsasser@arm.com // for this read 67711678Swendy.elsasser@arm.com assert(dram_pkt->rankRef.outstandingEvents > 0); 67811678Swendy.elsasser@arm.com // read response received, decrement count 67911678Swendy.elsasser@arm.com --dram_pkt->rankRef.outstandingEvents; 68011678Swendy.elsasser@arm.com 68111846Swendy.elsasser@arm.com // at this moment should not have transitioned to a low-power state 68211846Swendy.elsasser@arm.com assert((dram_pkt->rankRef.pwrState != PWR_SREF) && 68311846Swendy.elsasser@arm.com (dram_pkt->rankRef.pwrState != PWR_PRE_PDN) && 68411846Swendy.elsasser@arm.com (dram_pkt->rankRef.pwrState != PWR_ACT_PDN)); 68511678Swendy.elsasser@arm.com 68611678Swendy.elsasser@arm.com // track if this is the last packet before idling 68711678Swendy.elsasser@arm.com // and that there are no outstanding commands to this rank 68811846Swendy.elsasser@arm.com // if REF in progress, transition to LP state should not occur 68911846Swendy.elsasser@arm.com // until REF completes 69011846Swendy.elsasser@arm.com if ((dram_pkt->rankRef.refreshState == REF_IDLE) && 69111846Swendy.elsasser@arm.com (dram_pkt->rankRef.lowPowerEntryReady())) { 69211678Swendy.elsasser@arm.com // verify that there are no events scheduled 69311678Swendy.elsasser@arm.com assert(!dram_pkt->rankRef.activateEvent.scheduled()); 69411678Swendy.elsasser@arm.com assert(!dram_pkt->rankRef.prechargeEvent.scheduled()); 69511678Swendy.elsasser@arm.com 69611678Swendy.elsasser@arm.com // if coming from active state, schedule power event to 69711678Swendy.elsasser@arm.com // active power-down else go to precharge power-down 69811678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleep at tick %d; current power state is " 69911678Swendy.elsasser@arm.com "%d\n", dram_pkt->rank, curTick(), dram_pkt->rankRef.pwrState); 70011678Swendy.elsasser@arm.com 70111678Swendy.elsasser@arm.com // default to ACT power-down unless already in IDLE state 70211678Swendy.elsasser@arm.com // could be in IDLE if PRE issued before data returned 70311678Swendy.elsasser@arm.com PowerState next_pwr_state = PWR_ACT_PDN; 70411678Swendy.elsasser@arm.com if (dram_pkt->rankRef.pwrState == PWR_IDLE) { 70511678Swendy.elsasser@arm.com next_pwr_state = PWR_PRE_PDN; 70611678Swendy.elsasser@arm.com } 70711678Swendy.elsasser@arm.com 70811678Swendy.elsasser@arm.com dram_pkt->rankRef.powerDownSleep(next_pwr_state, curTick()); 70911678Swendy.elsasser@arm.com } 71011678Swendy.elsasser@arm.com 7119831SN/A if (dram_pkt->burstHelper) { 7129831SN/A // it is a split packet 7139831SN/A dram_pkt->burstHelper->burstsServiced++; 7149831SN/A if (dram_pkt->burstHelper->burstsServiced == 71510143SN/A dram_pkt->burstHelper->burstCount) { 7169831SN/A // we have now serviced all children packets of a system packet 7179831SN/A // so we can now respond to the requester 7189831SN/A // @todo we probably want to have a different front end and back 7199831SN/A // end latency for split packets 7209831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7219831SN/A delete dram_pkt->burstHelper; 7229831SN/A dram_pkt->burstHelper = NULL; 7239831SN/A } 7249831SN/A } else { 7259831SN/A // it is not a split packet 7269831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7279831SN/A } 7289243SN/A 7299831SN/A delete respQueue.front(); 7309831SN/A respQueue.pop_front(); 7319243SN/A 7329831SN/A if (!respQueue.empty()) { 7339831SN/A assert(respQueue.front()->readyTime >= curTick()); 7349831SN/A assert(!respondEvent.scheduled()); 7359831SN/A schedule(respondEvent, respQueue.front()->readyTime); 7369831SN/A } else { 7379831SN/A // if there is nothing left in any queue, signal a drain 73810913Sandreas.sandberg@arm.com if (drainState() == DrainState::Draining && 73911676Swendy.elsasser@arm.com writeQueue.empty() && readQueue.empty() && allRanksDrained()) { 74010913Sandreas.sandberg@arm.com 74110509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 74210913Sandreas.sandberg@arm.com signalDrainDone(); 7439831SN/A } 7449831SN/A } 7459567SN/A 7469831SN/A // We have made a location in the queue available at this point, 7479831SN/A // so if there is a read that was forced to wait, retry now 7489831SN/A if (retryRdReq) { 7499831SN/A retryRdReq = false; 75010713Sandreas.hansson@arm.com port.sendRetryReq(); 7519831SN/A } 7529243SN/A} 7539243SN/A 75410618SOmar.Naji@arm.combool 75510890Swendy.elsasser@arm.comDRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay) 7569243SN/A{ 75710206Sandreas.hansson@arm.com // This method does the arbitration between requests. The chosen 75810206Sandreas.hansson@arm.com // packet is simply moved to the head of the queue. The other 75910206Sandreas.hansson@arm.com // methods know that this is the place to look. For example, with 76010206Sandreas.hansson@arm.com // FCFS, this method does nothing 76110206Sandreas.hansson@arm.com assert(!queue.empty()); 7629243SN/A 76310618SOmar.Naji@arm.com // bool to indicate if a packet to an available rank is found 76410618SOmar.Naji@arm.com bool found_packet = false; 76510206Sandreas.hansson@arm.com if (queue.size() == 1) { 76610618SOmar.Naji@arm.com DRAMPacket* dram_pkt = queue.front(); 76710618SOmar.Naji@arm.com // available rank corresponds to state refresh idle 76810618SOmar.Naji@arm.com if (ranks[dram_pkt->rank]->isAvailable()) { 76910618SOmar.Naji@arm.com found_packet = true; 77010618SOmar.Naji@arm.com DPRINTF(DRAM, "Single request, going to a free rank\n"); 77110618SOmar.Naji@arm.com } else { 77210618SOmar.Naji@arm.com DPRINTF(DRAM, "Single request, going to a busy rank\n"); 77310618SOmar.Naji@arm.com } 77410618SOmar.Naji@arm.com return found_packet; 7759243SN/A } 7769243SN/A 7779243SN/A if (memSchedPolicy == Enums::fcfs) { 77810618SOmar.Naji@arm.com // check if there is a packet going to a free rank 77911321Ssteve.reinhardt@amd.com for (auto i = queue.begin(); i != queue.end() ; ++i) { 78010618SOmar.Naji@arm.com DRAMPacket* dram_pkt = *i; 78110618SOmar.Naji@arm.com if (ranks[dram_pkt->rank]->isAvailable()) { 78210618SOmar.Naji@arm.com queue.erase(i); 78310618SOmar.Naji@arm.com queue.push_front(dram_pkt); 78410618SOmar.Naji@arm.com found_packet = true; 78510618SOmar.Naji@arm.com break; 78610618SOmar.Naji@arm.com } 78710618SOmar.Naji@arm.com } 7889243SN/A } else if (memSchedPolicy == Enums::frfcfs) { 78910890Swendy.elsasser@arm.com found_packet = reorderQueue(queue, extra_col_delay); 7909243SN/A } else 7919243SN/A panic("No scheduling policy chosen\n"); 79210618SOmar.Naji@arm.com return found_packet; 7939243SN/A} 7949243SN/A 79510618SOmar.Naji@arm.combool 79610890Swendy.elsasser@arm.comDRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay) 7979974SN/A{ 79810890Swendy.elsasser@arm.com // Only determine this if needed 7999974SN/A uint64_t earliest_banks = 0; 80010890Swendy.elsasser@arm.com bool hidden_bank_prep = false; 8019974SN/A 80210890Swendy.elsasser@arm.com // search for seamless row hits first, if no seamless row hit is 80310890Swendy.elsasser@arm.com // found then determine if there are other packets that can be issued 80410890Swendy.elsasser@arm.com // without incurring additional bus delay due to bank timing 80510890Swendy.elsasser@arm.com // Will select closed rows first to enable more open row possibilies 80610890Swendy.elsasser@arm.com // in future selections 80710890Swendy.elsasser@arm.com bool found_hidden_bank = false; 80810890Swendy.elsasser@arm.com 80910890Swendy.elsasser@arm.com // remember if we found a row hit, not seamless, but bank prepped 81010890Swendy.elsasser@arm.com // and ready 81110890Swendy.elsasser@arm.com bool found_prepped_pkt = false; 81210890Swendy.elsasser@arm.com 81310890Swendy.elsasser@arm.com // if we have no row hit, prepped or not, and no seamless packet, 81410890Swendy.elsasser@arm.com // just go for the earliest possible 8159974SN/A bool found_earliest_pkt = false; 81610890Swendy.elsasser@arm.com 81710618SOmar.Naji@arm.com auto selected_pkt_it = queue.end(); 8189974SN/A 81910890Swendy.elsasser@arm.com // time we need to issue a column command to be seamless 82010890Swendy.elsasser@arm.com const Tick min_col_at = std::max(busBusyUntil - tCL + extra_col_delay, 82110890Swendy.elsasser@arm.com curTick()); 82210890Swendy.elsasser@arm.com 8239974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 8249974SN/A DRAMPacket* dram_pkt = *i; 8259974SN/A const Bank& bank = dram_pkt->bankRef; 82610890Swendy.elsasser@arm.com 82710890Swendy.elsasser@arm.com // check if rank is available, if not, jump to the next packet 82810618SOmar.Naji@arm.com if (dram_pkt->rankRef.isAvailable()) { 82910890Swendy.elsasser@arm.com // check if it is a row hit 83010618SOmar.Naji@arm.com if (bank.openRow == dram_pkt->row) { 83110890Swendy.elsasser@arm.com // no additional rank-to-rank or same bank-group 83210890Swendy.elsasser@arm.com // delays, or we switched read/write and might as well 83310890Swendy.elsasser@arm.com // go for the row hit 83410890Swendy.elsasser@arm.com if (bank.colAllowedAt <= min_col_at) { 83510890Swendy.elsasser@arm.com // FCFS within the hits, giving priority to 83610890Swendy.elsasser@arm.com // commands that can issue seamlessly, without 83710890Swendy.elsasser@arm.com // additional delay, such as same rank accesses 83810890Swendy.elsasser@arm.com // and/or different bank-group accesses 83910890Swendy.elsasser@arm.com DPRINTF(DRAM, "Seamless row buffer hit\n"); 84010618SOmar.Naji@arm.com selected_pkt_it = i; 84110890Swendy.elsasser@arm.com // no need to look through the remaining queue entries 84210618SOmar.Naji@arm.com break; 84310890Swendy.elsasser@arm.com } else if (!found_hidden_bank && !found_prepped_pkt) { 84410890Swendy.elsasser@arm.com // if we did not find a packet to a closed row that can 84510890Swendy.elsasser@arm.com // issue the bank commands without incurring delay, and 84610890Swendy.elsasser@arm.com // did not yet find a packet to a prepped row, remember 84710890Swendy.elsasser@arm.com // the current one 84810618SOmar.Naji@arm.com selected_pkt_it = i; 84910890Swendy.elsasser@arm.com found_prepped_pkt = true; 85010890Swendy.elsasser@arm.com DPRINTF(DRAM, "Prepped row buffer hit\n"); 85110618SOmar.Naji@arm.com } 85210890Swendy.elsasser@arm.com } else if (!found_earliest_pkt) { 85310890Swendy.elsasser@arm.com // if we have not initialised the bank status, do it 85410890Swendy.elsasser@arm.com // now, and only once per scheduling decisions 85510890Swendy.elsasser@arm.com if (earliest_banks == 0) { 85610890Swendy.elsasser@arm.com // determine entries with earliest bank delay 85710890Swendy.elsasser@arm.com pair<uint64_t, bool> bankStatus = 85810890Swendy.elsasser@arm.com minBankPrep(queue, min_col_at); 85910890Swendy.elsasser@arm.com earliest_banks = bankStatus.first; 86010890Swendy.elsasser@arm.com hidden_bank_prep = bankStatus.second; 86110890Swendy.elsasser@arm.com } 86210211Sandreas.hansson@arm.com 86310890Swendy.elsasser@arm.com // bank is amongst first available banks 86410890Swendy.elsasser@arm.com // minBankPrep will give priority to packets that can 86510890Swendy.elsasser@arm.com // issue seamlessly 86610890Swendy.elsasser@arm.com if (bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) { 86710618SOmar.Naji@arm.com found_earliest_pkt = true; 86810890Swendy.elsasser@arm.com found_hidden_bank = hidden_bank_prep; 86910890Swendy.elsasser@arm.com 87010890Swendy.elsasser@arm.com // give priority to packets that can issue 87110890Swendy.elsasser@arm.com // bank commands 'behind the scenes' 87210890Swendy.elsasser@arm.com // any additional delay if any will be due to 87310890Swendy.elsasser@arm.com // col-to-col command requirements 87410890Swendy.elsasser@arm.com if (hidden_bank_prep || !found_prepped_pkt) 87510890Swendy.elsasser@arm.com selected_pkt_it = i; 87610618SOmar.Naji@arm.com } 8779974SN/A } 8789974SN/A } 8799974SN/A } 8809974SN/A 88110618SOmar.Naji@arm.com if (selected_pkt_it != queue.end()) { 88210618SOmar.Naji@arm.com DRAMPacket* selected_pkt = *selected_pkt_it; 88310618SOmar.Naji@arm.com queue.erase(selected_pkt_it); 88410618SOmar.Naji@arm.com queue.push_front(selected_pkt); 88510890Swendy.elsasser@arm.com return true; 88610618SOmar.Naji@arm.com } 88710890Swendy.elsasser@arm.com 88810890Swendy.elsasser@arm.com return false; 8899974SN/A} 8909974SN/A 8919974SN/Avoid 89210146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 8939243SN/A{ 8949243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 8959243SN/A 8969243SN/A bool needsResponse = pkt->needsResponse(); 8979243SN/A // do the actual memory access which also turns the packet into a 8989243SN/A // response 8999243SN/A access(pkt); 9009243SN/A 9019243SN/A // turn packet around to go back to requester if response expected 9029243SN/A if (needsResponse) { 9039243SN/A // access already turned the packet into a response 9049243SN/A assert(pkt->isResponse()); 90510721SMarco.Balboni@ARM.com // response_time consumes the static latency and is charged also 90610721SMarco.Balboni@ARM.com // with headerDelay that takes into account the delay provided by 90710721SMarco.Balboni@ARM.com // the xbar and also the payloadDelay that takes into account the 90810721SMarco.Balboni@ARM.com // number of data beats. 90910721SMarco.Balboni@ARM.com Tick response_time = curTick() + static_latency + pkt->headerDelay + 91010721SMarco.Balboni@ARM.com pkt->payloadDelay; 91110721SMarco.Balboni@ARM.com // Here we reset the timing of the packet before sending it out. 91210694SMarco.Balboni@ARM.com pkt->headerDelay = pkt->payloadDelay = 0; 9139549SN/A 9149726SN/A // queue the packet in the response queue to be sent out after 9159726SN/A // the static latency has passed 91611194Sali.jafri@arm.com port.schedTimingResp(pkt, response_time, true); 9179243SN/A } else { 9189587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 9199587SN/A // is still having a pointer to it 92011190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 9219243SN/A } 9229243SN/A 9239243SN/A DPRINTF(DRAM, "Done\n"); 9249243SN/A 9259243SN/A return; 9269243SN/A} 9279243SN/A 9289243SN/Avoid 92910618SOmar.Naji@arm.comDRAMCtrl::activateBank(Rank& rank_ref, Bank& bank_ref, 93010618SOmar.Naji@arm.com Tick act_tick, uint32_t row) 9319488SN/A{ 93210618SOmar.Naji@arm.com assert(rank_ref.actTicks.size() == activationLimit); 9339488SN/A 9349488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 9359488SN/A 93610207Sandreas.hansson@arm.com // update the open row 93710618SOmar.Naji@arm.com assert(bank_ref.openRow == Bank::NO_ROW); 93810618SOmar.Naji@arm.com bank_ref.openRow = row; 93910207Sandreas.hansson@arm.com 94010207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 94110207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 94210207Sandreas.hansson@arm.com // precharge 94310618SOmar.Naji@arm.com bank_ref.bytesAccessed = 0; 94410618SOmar.Naji@arm.com bank_ref.rowAccesses = 0; 94510207Sandreas.hansson@arm.com 94610618SOmar.Naji@arm.com ++rank_ref.numBanksActive; 94710618SOmar.Naji@arm.com assert(rank_ref.numBanksActive <= banksPerRank); 94810207Sandreas.hansson@arm.com 94910247Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n", 95010618SOmar.Naji@arm.com bank_ref.bank, rank_ref.rank, act_tick, 95110618SOmar.Naji@arm.com ranks[rank_ref.rank]->numBanksActive); 95210247Sandreas.hansson@arm.com 95311675Swendy.elsasser@arm.com rank_ref.cmdList.push_back(Command(MemCommand::ACT, bank_ref.bank, 95411675Swendy.elsasser@arm.com act_tick)); 95510432SOmar.Naji@arm.com 95610432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK) - 95710618SOmar.Naji@arm.com timeStampOffset, bank_ref.bank, rank_ref.rank); 9589975SN/A 95910211Sandreas.hansson@arm.com // The next access has to respect tRAS for this bank 96010618SOmar.Naji@arm.com bank_ref.preAllowedAt = act_tick + tRAS; 96110211Sandreas.hansson@arm.com 96210211Sandreas.hansson@arm.com // Respect the row-to-column command delay 96310618SOmar.Naji@arm.com bank_ref.colAllowedAt = std::max(act_tick + tRCD, bank_ref.colAllowedAt); 96410211Sandreas.hansson@arm.com 9659971SN/A // start by enforcing tRRD 96611321Ssteve.reinhardt@amd.com for (int i = 0; i < banksPerRank; i++) { 96710210Sandreas.hansson@arm.com // next activate to any bank in this rank must not happen 96810210Sandreas.hansson@arm.com // before tRRD 96910618SOmar.Naji@arm.com if (bankGroupArch && (bank_ref.bankgr == rank_ref.banks[i].bankgr)) { 97010394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 97110394Swendy.elsasser@arm.com // ACT commands within the same bank group. Use tRRD_L 97210394Swendy.elsasser@arm.com // in this case 97310618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD_L, 97410618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt); 97510394Swendy.elsasser@arm.com } else { 97610394Swendy.elsasser@arm.com // use shorter tRRD value when either 97710394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 97810394Swendy.elsasser@arm.com // 2) bank is in a different bank group 97910618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD, 98010618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt); 98110394Swendy.elsasser@arm.com } 9829971SN/A } 98310208Sandreas.hansson@arm.com 9849971SN/A // next, we deal with tXAW, if the activation limit is disabled 98510492SOmar.Naji@arm.com // then we directly schedule an activate power event 98610618SOmar.Naji@arm.com if (!rank_ref.actTicks.empty()) { 98710492SOmar.Naji@arm.com // sanity check 98810618SOmar.Naji@arm.com if (rank_ref.actTicks.back() && 98910618SOmar.Naji@arm.com (act_tick - rank_ref.actTicks.back()) < tXAW) { 99010492SOmar.Naji@arm.com panic("Got %d activates in window %d (%llu - %llu) which " 99110492SOmar.Naji@arm.com "is smaller than %llu\n", activationLimit, act_tick - 99210618SOmar.Naji@arm.com rank_ref.actTicks.back(), act_tick, 99310618SOmar.Naji@arm.com rank_ref.actTicks.back(), tXAW); 99410492SOmar.Naji@arm.com } 9959824SN/A 99610492SOmar.Naji@arm.com // shift the times used for the book keeping, the last element 99710492SOmar.Naji@arm.com // (highest index) is the oldest one and hence the lowest value 99810618SOmar.Naji@arm.com rank_ref.actTicks.pop_back(); 9999488SN/A 100010492SOmar.Naji@arm.com // record an new activation (in the future) 100110618SOmar.Naji@arm.com rank_ref.actTicks.push_front(act_tick); 10029488SN/A 100310492SOmar.Naji@arm.com // cannot activate more than X times in time window tXAW, push the 100410492SOmar.Naji@arm.com // next one (the X + 1'st activate) to be tXAW away from the 100510492SOmar.Naji@arm.com // oldest in our window of X 100610618SOmar.Naji@arm.com if (rank_ref.actTicks.back() && 100710618SOmar.Naji@arm.com (act_tick - rank_ref.actTicks.back()) < tXAW) { 100810492SOmar.Naji@arm.com DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate " 100910492SOmar.Naji@arm.com "no earlier than %llu\n", activationLimit, 101010618SOmar.Naji@arm.com rank_ref.actTicks.back() + tXAW); 101111321Ssteve.reinhardt@amd.com for (int j = 0; j < banksPerRank; j++) 10129488SN/A // next activate must not happen before end of window 101310618SOmar.Naji@arm.com rank_ref.banks[j].actAllowedAt = 101410618SOmar.Naji@arm.com std::max(rank_ref.actTicks.back() + tXAW, 101510618SOmar.Naji@arm.com rank_ref.banks[j].actAllowedAt); 101610492SOmar.Naji@arm.com } 10179488SN/A } 101810208Sandreas.hansson@arm.com 101910208Sandreas.hansson@arm.com // at the point when this activate takes place, make sure we 102010208Sandreas.hansson@arm.com // transition to the active power state 102110618SOmar.Naji@arm.com if (!rank_ref.activateEvent.scheduled()) 102210618SOmar.Naji@arm.com schedule(rank_ref.activateEvent, act_tick); 102310618SOmar.Naji@arm.com else if (rank_ref.activateEvent.when() > act_tick) 102410208Sandreas.hansson@arm.com // move it sooner in time 102510618SOmar.Naji@arm.com reschedule(rank_ref.activateEvent, act_tick); 102610208Sandreas.hansson@arm.com} 102710208Sandreas.hansson@arm.com 102810208Sandreas.hansson@arm.comvoid 102910618SOmar.Naji@arm.comDRAMCtrl::prechargeBank(Rank& rank_ref, Bank& bank, Tick pre_at, bool trace) 103010207Sandreas.hansson@arm.com{ 103110207Sandreas.hansson@arm.com // make sure the bank has an open row 103210207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 103310207Sandreas.hansson@arm.com 103410207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 103510207Sandreas.hansson@arm.com // the page 103610207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 103710207Sandreas.hansson@arm.com 103810207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 103910207Sandreas.hansson@arm.com 104010214Sandreas.hansson@arm.com // no precharge allowed before this one 104110214Sandreas.hansson@arm.com bank.preAllowedAt = pre_at; 104210214Sandreas.hansson@arm.com 104310211Sandreas.hansson@arm.com Tick pre_done_at = pre_at + tRP; 104410211Sandreas.hansson@arm.com 104510211Sandreas.hansson@arm.com bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at); 104610207Sandreas.hansson@arm.com 104710618SOmar.Naji@arm.com assert(rank_ref.numBanksActive != 0); 104810618SOmar.Naji@arm.com --rank_ref.numBanksActive; 104910207Sandreas.hansson@arm.com 105010247Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got " 105110618SOmar.Naji@arm.com "%d active\n", bank.bank, rank_ref.rank, pre_at, 105210618SOmar.Naji@arm.com rank_ref.numBanksActive); 105310247Sandreas.hansson@arm.com 105410432SOmar.Naji@arm.com if (trace) { 105510207Sandreas.hansson@arm.com 105611675Swendy.elsasser@arm.com rank_ref.cmdList.push_back(Command(MemCommand::PRE, bank.bank, 105711675Swendy.elsasser@arm.com pre_at)); 105810432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK) - 105910618SOmar.Naji@arm.com timeStampOffset, bank.bank, rank_ref.rank); 106010432SOmar.Naji@arm.com } 106110208Sandreas.hansson@arm.com // if we look at the current number of active banks we might be 106210208Sandreas.hansson@arm.com // tempted to think the DRAM is now idle, however this can be 106310208Sandreas.hansson@arm.com // undone by an activate that is scheduled to happen before we 106410208Sandreas.hansson@arm.com // would have reached the idle state, so schedule an event and 106510208Sandreas.hansson@arm.com // rather check once we actually make it to the point in time when 106610208Sandreas.hansson@arm.com // the (last) precharge takes place 106711678Swendy.elsasser@arm.com if (!rank_ref.prechargeEvent.scheduled()) { 106810618SOmar.Naji@arm.com schedule(rank_ref.prechargeEvent, pre_done_at); 106911678Swendy.elsasser@arm.com // New event, increment count 107011678Swendy.elsasser@arm.com ++rank_ref.outstandingEvents; 107111678Swendy.elsasser@arm.com } else if (rank_ref.prechargeEvent.when() < pre_done_at) { 107210618SOmar.Naji@arm.com reschedule(rank_ref.prechargeEvent, pre_done_at); 107311678Swendy.elsasser@arm.com } 107410207Sandreas.hansson@arm.com} 107510207Sandreas.hansson@arm.com 107610207Sandreas.hansson@arm.comvoid 107710146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 10789243SN/A{ 10799243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 10809243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 10819243SN/A 108210618SOmar.Naji@arm.com // get the rank 108310618SOmar.Naji@arm.com Rank& rank = dram_pkt->rankRef; 108410618SOmar.Naji@arm.com 108511678Swendy.elsasser@arm.com // are we in or transitioning to a low-power state and have not scheduled 108611678Swendy.elsasser@arm.com // a power-up event? 108711678Swendy.elsasser@arm.com // if so, wake up from power down to issue RD/WR burst 108811678Swendy.elsasser@arm.com if (rank.inLowPowerState) { 108911678Swendy.elsasser@arm.com assert(rank.pwrState != PWR_SREF); 109011678Swendy.elsasser@arm.com rank.scheduleWakeUpEvent(tXP); 109111678Swendy.elsasser@arm.com } 109211678Swendy.elsasser@arm.com 109310211Sandreas.hansson@arm.com // get the bank 10949967SN/A Bank& bank = dram_pkt->bankRef; 10959243SN/A 109610211Sandreas.hansson@arm.com // for the state we need to track if it is a row hit or not 109710211Sandreas.hansson@arm.com bool row_hit = true; 109810211Sandreas.hansson@arm.com 109910211Sandreas.hansson@arm.com // respect any constraints on the command (e.g. tRCD or tCCD) 110010211Sandreas.hansson@arm.com Tick cmd_at = std::max(bank.colAllowedAt, curTick()); 110110211Sandreas.hansson@arm.com 110210211Sandreas.hansson@arm.com // Determine the access latency and update the bank state 110310211Sandreas.hansson@arm.com if (bank.openRow == dram_pkt->row) { 110410211Sandreas.hansson@arm.com // nothing to do 110510209Sandreas.hansson@arm.com } else { 110610211Sandreas.hansson@arm.com row_hit = false; 110710211Sandreas.hansson@arm.com 110810209Sandreas.hansson@arm.com // If there is a page open, precharge it. 110910209Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 111010618SOmar.Naji@arm.com prechargeBank(rank, bank, std::max(bank.preAllowedAt, curTick())); 11119488SN/A } 11129973SN/A 111310211Sandreas.hansson@arm.com // next we need to account for the delay in activating the 111410211Sandreas.hansson@arm.com // page 111510211Sandreas.hansson@arm.com Tick act_tick = std::max(bank.actAllowedAt, curTick()); 11169973SN/A 111710210Sandreas.hansson@arm.com // Record the activation and deal with all the global timing 111810210Sandreas.hansson@arm.com // constraints caused be a new activation (tRRD and tXAW) 111910618SOmar.Naji@arm.com activateBank(rank, bank, act_tick, dram_pkt->row); 112010210Sandreas.hansson@arm.com 112110211Sandreas.hansson@arm.com // issue the command as early as possible 112210211Sandreas.hansson@arm.com cmd_at = bank.colAllowedAt; 112310209Sandreas.hansson@arm.com } 112410209Sandreas.hansson@arm.com 112510211Sandreas.hansson@arm.com // we need to wait until the bus is available before we can issue 112610211Sandreas.hansson@arm.com // the command 112710211Sandreas.hansson@arm.com cmd_at = std::max(cmd_at, busBusyUntil - tCL); 112810211Sandreas.hansson@arm.com 112910211Sandreas.hansson@arm.com // update the packet ready time 113010211Sandreas.hansson@arm.com dram_pkt->readyTime = cmd_at + tCL + tBURST; 113110211Sandreas.hansson@arm.com 113210211Sandreas.hansson@arm.com // only one burst can use the bus at any one point in time 113310211Sandreas.hansson@arm.com assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 113410211Sandreas.hansson@arm.com 113510394Swendy.elsasser@arm.com // update the time for the next read/write burst for each 113610394Swendy.elsasser@arm.com // bank (add a max with tCCD/tCCD_L here) 113710394Swendy.elsasser@arm.com Tick cmd_dly; 113811321Ssteve.reinhardt@amd.com for (int j = 0; j < ranksPerChannel; j++) { 113911321Ssteve.reinhardt@amd.com for (int i = 0; i < banksPerRank; i++) { 114010394Swendy.elsasser@arm.com // next burst to same bank group in this rank must not happen 114110394Swendy.elsasser@arm.com // before tCCD_L. Different bank group timing requirement is 114210394Swendy.elsasser@arm.com // tBURST; Add tCS for different ranks 114310394Swendy.elsasser@arm.com if (dram_pkt->rank == j) { 114410618SOmar.Naji@arm.com if (bankGroupArch && 114510618SOmar.Naji@arm.com (bank.bankgr == ranks[j]->banks[i].bankgr)) { 114610394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 114710394Swendy.elsasser@arm.com // RD/WR burst commands to the same bank group. 114810394Swendy.elsasser@arm.com // Use tCCD_L in this case 114910394Swendy.elsasser@arm.com cmd_dly = tCCD_L; 115010394Swendy.elsasser@arm.com } else { 115110394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), the shorter 115210394Swendy.elsasser@arm.com // cas-to-cas delay value, when either: 115310394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 115410394Swendy.elsasser@arm.com // 2) bank is in a different bank group 115510394Swendy.elsasser@arm.com cmd_dly = tBURST; 115610394Swendy.elsasser@arm.com } 115710394Swendy.elsasser@arm.com } else { 115810394Swendy.elsasser@arm.com // different rank is by default in a different bank group 115910394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), which is the shorter 116010394Swendy.elsasser@arm.com // cas-to-cas delay in this case 116110394Swendy.elsasser@arm.com // Add tCS to account for rank-to-rank bus delay requirements 116210394Swendy.elsasser@arm.com cmd_dly = tBURST + tCS; 116310394Swendy.elsasser@arm.com } 116410618SOmar.Naji@arm.com ranks[j]->banks[i].colAllowedAt = std::max(cmd_at + cmd_dly, 116510618SOmar.Naji@arm.com ranks[j]->banks[i].colAllowedAt); 116610394Swendy.elsasser@arm.com } 116710394Swendy.elsasser@arm.com } 116810211Sandreas.hansson@arm.com 116910393Swendy.elsasser@arm.com // Save rank of current access 117010393Swendy.elsasser@arm.com activeRank = dram_pkt->rank; 117110393Swendy.elsasser@arm.com 117210212Sandreas.hansson@arm.com // If this is a write, we also need to respect the write recovery 117310212Sandreas.hansson@arm.com // time before a precharge, in the case of a read, respect the 117410212Sandreas.hansson@arm.com // read to precharge constraint 117510212Sandreas.hansson@arm.com bank.preAllowedAt = std::max(bank.preAllowedAt, 117610212Sandreas.hansson@arm.com dram_pkt->isRead ? cmd_at + tRTP : 117710212Sandreas.hansson@arm.com dram_pkt->readyTime + tWR); 117810210Sandreas.hansson@arm.com 117910209Sandreas.hansson@arm.com // increment the bytes accessed and the accesses per row 118010209Sandreas.hansson@arm.com bank.bytesAccessed += burstSize; 118110209Sandreas.hansson@arm.com ++bank.rowAccesses; 118210209Sandreas.hansson@arm.com 118310209Sandreas.hansson@arm.com // if we reached the max, then issue with an auto-precharge 118410209Sandreas.hansson@arm.com bool auto_precharge = pageMgmt == Enums::close || 118510209Sandreas.hansson@arm.com bank.rowAccesses == maxAccessesPerRow; 118610209Sandreas.hansson@arm.com 118710209Sandreas.hansson@arm.com // if we did not hit the limit, we might still want to 118810209Sandreas.hansson@arm.com // auto-precharge 118910209Sandreas.hansson@arm.com if (!auto_precharge && 119010209Sandreas.hansson@arm.com (pageMgmt == Enums::open_adaptive || 119110209Sandreas.hansson@arm.com pageMgmt == Enums::close_adaptive)) { 119210209Sandreas.hansson@arm.com // a twist on the open and close page policies: 119310209Sandreas.hansson@arm.com // 1) open_adaptive page policy does not blindly keep the 119410209Sandreas.hansson@arm.com // page open, but close it if there are no row hits, and there 119510209Sandreas.hansson@arm.com // are bank conflicts in the queue 119610209Sandreas.hansson@arm.com // 2) close_adaptive page policy does not blindly close the 119710209Sandreas.hansson@arm.com // page, but closes it only if there are no row hits in the queue. 119810209Sandreas.hansson@arm.com // In this case, only force an auto precharge when there 119910209Sandreas.hansson@arm.com // are no same page hits in the queue 120010209Sandreas.hansson@arm.com bool got_more_hits = false; 120110209Sandreas.hansson@arm.com bool got_bank_conflict = false; 120210209Sandreas.hansson@arm.com 120310209Sandreas.hansson@arm.com // either look at the read queue or write queue 120410209Sandreas.hansson@arm.com const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 120510209Sandreas.hansson@arm.com writeQueue; 120610209Sandreas.hansson@arm.com auto p = queue.begin(); 120710209Sandreas.hansson@arm.com // make sure we are not considering the packet that we are 120810209Sandreas.hansson@arm.com // currently dealing with (which is the head of the queue) 120910209Sandreas.hansson@arm.com ++p; 121010209Sandreas.hansson@arm.com 121110809Srb639@drexel.edu // keep on looking until we find a hit or reach the end of the queue 121210809Srb639@drexel.edu // 1) if a hit is found, then both open and close adaptive policies keep 121310809Srb639@drexel.edu // the page open 121410809Srb639@drexel.edu // 2) if no hit is found, got_bank_conflict is set to true if a bank 121510809Srb639@drexel.edu // conflict request is waiting in the queue 121610809Srb639@drexel.edu while (!got_more_hits && p != queue.end()) { 121710209Sandreas.hansson@arm.com bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 121810209Sandreas.hansson@arm.com (dram_pkt->bank == (*p)->bank); 121910209Sandreas.hansson@arm.com bool same_row = dram_pkt->row == (*p)->row; 122010209Sandreas.hansson@arm.com got_more_hits |= same_rank_bank && same_row; 122110209Sandreas.hansson@arm.com got_bank_conflict |= same_rank_bank && !same_row; 12229973SN/A ++p; 122310141SN/A } 122410141SN/A 122510209Sandreas.hansson@arm.com // auto pre-charge when either 122610209Sandreas.hansson@arm.com // 1) open_adaptive policy, we have not got any more hits, and 122710209Sandreas.hansson@arm.com // have a bank conflict 122810209Sandreas.hansson@arm.com // 2) close_adaptive policy and we have not got any more hits 122910209Sandreas.hansson@arm.com auto_precharge = !got_more_hits && 123010209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive); 123110209Sandreas.hansson@arm.com } 123210142SN/A 123310247Sandreas.hansson@arm.com // DRAMPower trace command to be written 123410247Sandreas.hansson@arm.com std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR"; 123510247Sandreas.hansson@arm.com 123610432SOmar.Naji@arm.com // MemCommand required for DRAMPower library 123710432SOmar.Naji@arm.com MemCommand::cmds command = (mem_cmd == "RD") ? MemCommand::RD : 123810432SOmar.Naji@arm.com MemCommand::WR; 123910432SOmar.Naji@arm.com 124011675Swendy.elsasser@arm.com // Update bus state 124111675Swendy.elsasser@arm.com busBusyUntil = dram_pkt->readyTime; 124211675Swendy.elsasser@arm.com 124311675Swendy.elsasser@arm.com DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n", 124411675Swendy.elsasser@arm.com dram_pkt->addr, dram_pkt->readyTime, busBusyUntil); 124511675Swendy.elsasser@arm.com 124611675Swendy.elsasser@arm.com dram_pkt->rankRef.cmdList.push_back(Command(command, dram_pkt->bank, 124711675Swendy.elsasser@arm.com cmd_at)); 124811675Swendy.elsasser@arm.com 124911675Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK) - 125011675Swendy.elsasser@arm.com timeStampOffset, mem_cmd, dram_pkt->bank, dram_pkt->rank); 125111675Swendy.elsasser@arm.com 125210209Sandreas.hansson@arm.com // if this access should use auto-precharge, then we are 125311675Swendy.elsasser@arm.com // closing the row after the read/write burst 125410209Sandreas.hansson@arm.com if (auto_precharge) { 125510432SOmar.Naji@arm.com // if auto-precharge push a PRE command at the correct tick to the 125610432SOmar.Naji@arm.com // list used by DRAMPower library to calculate power 125710618SOmar.Naji@arm.com prechargeBank(rank, bank, std::max(curTick(), bank.preAllowedAt)); 12589973SN/A 125910209Sandreas.hansson@arm.com DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 126010209Sandreas.hansson@arm.com } 12619963SN/A 126210206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 126310206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 126410206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 126510206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 126610206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 12679972SN/A 126810206Sandreas.hansson@arm.com // Update the stats and schedule the next request 12699977SN/A if (dram_pkt->isRead) { 127010147Sandreas.hansson@arm.com ++readsThisTime; 127110211Sandreas.hansson@arm.com if (row_hit) 12729977SN/A readRowHits++; 12739977SN/A bytesReadDRAM += burstSize; 12749977SN/A perBankRdBursts[dram_pkt->bankId]++; 127510206Sandreas.hansson@arm.com 127610206Sandreas.hansson@arm.com // Update latency stats 127710206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 127810206Sandreas.hansson@arm.com totBusLat += tBURST; 127910211Sandreas.hansson@arm.com totQLat += cmd_at - dram_pkt->entryTime; 12809977SN/A } else { 128110147Sandreas.hansson@arm.com ++writesThisTime; 128210211Sandreas.hansson@arm.com if (row_hit) 12839977SN/A writeRowHits++; 12849977SN/A bytesWritten += burstSize; 12859977SN/A perBankWrBursts[dram_pkt->bankId]++; 12869243SN/A } 12879243SN/A} 12889243SN/A 12899243SN/Avoid 129010206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 12919243SN/A{ 129210618SOmar.Naji@arm.com int busyRanks = 0; 129310618SOmar.Naji@arm.com for (auto r : ranks) { 129410618SOmar.Naji@arm.com if (!r->isAvailable()) { 129511678Swendy.elsasser@arm.com if (r->pwrState != PWR_SREF) { 129611678Swendy.elsasser@arm.com // rank is busy refreshing 129711678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d is not available\n", r->rank); 129811678Swendy.elsasser@arm.com busyRanks++; 129911678Swendy.elsasser@arm.com 130011678Swendy.elsasser@arm.com // let the rank know that if it was waiting to drain, it 130111678Swendy.elsasser@arm.com // is now done and ready to proceed 130211678Swendy.elsasser@arm.com r->checkDrainDone(); 130311678Swendy.elsasser@arm.com } 130411678Swendy.elsasser@arm.com 130511678Swendy.elsasser@arm.com // check if we were in self-refresh and haven't started 130611678Swendy.elsasser@arm.com // to transition out 130711678Swendy.elsasser@arm.com if ((r->pwrState == PWR_SREF) && r->inLowPowerState) { 130811678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d is in self-refresh\n", r->rank); 130911678Swendy.elsasser@arm.com // if we have commands queued to this rank and we don't have 131011678Swendy.elsasser@arm.com // a minimum number of active commands enqueued, 131111678Swendy.elsasser@arm.com // exit self-refresh 131211678Swendy.elsasser@arm.com if (r->forceSelfRefreshExit()) { 131311678Swendy.elsasser@arm.com DPRINTF(DRAMState, "rank %d was in self refresh and" 131411678Swendy.elsasser@arm.com " should wake up\n", r->rank); 131511678Swendy.elsasser@arm.com //wake up from self-refresh 131611678Swendy.elsasser@arm.com r->scheduleWakeUpEvent(tXS); 131711678Swendy.elsasser@arm.com // things are brought back into action once a refresh is 131811678Swendy.elsasser@arm.com // performed after self-refresh 131911678Swendy.elsasser@arm.com // continue with selection for other ranks 132011678Swendy.elsasser@arm.com } 132111678Swendy.elsasser@arm.com } 132210618SOmar.Naji@arm.com } 132310618SOmar.Naji@arm.com } 132410618SOmar.Naji@arm.com 132510618SOmar.Naji@arm.com if (busyRanks == ranksPerChannel) { 132610618SOmar.Naji@arm.com // if all ranks are refreshing wait for them to finish 132710618SOmar.Naji@arm.com // and stall this state machine without taking any further 132810618SOmar.Naji@arm.com // action, and do not schedule a new nextReqEvent 132910618SOmar.Naji@arm.com return; 133010618SOmar.Naji@arm.com } 133110618SOmar.Naji@arm.com 133211678Swendy.elsasser@arm.com // pre-emptively set to false. Overwrite if in transitioning to 133311678Swendy.elsasser@arm.com // a new state 133410393Swendy.elsasser@arm.com bool switched_cmd_type = false; 133511678Swendy.elsasser@arm.com if (busState != busStateNext) { 133611678Swendy.elsasser@arm.com if (busState == READ) { 133711678Swendy.elsasser@arm.com DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 133811678Swendy.elsasser@arm.com "waiting\n", readsThisTime, readQueue.size()); 133911678Swendy.elsasser@arm.com 134011678Swendy.elsasser@arm.com // sample and reset the read-related stats as we are now 134111678Swendy.elsasser@arm.com // transitioning to writes, and all reads are done 134211678Swendy.elsasser@arm.com rdPerTurnAround.sample(readsThisTime); 134311678Swendy.elsasser@arm.com readsThisTime = 0; 134411678Swendy.elsasser@arm.com 134511678Swendy.elsasser@arm.com // now proceed to do the actual writes 134611678Swendy.elsasser@arm.com switched_cmd_type = true; 134711678Swendy.elsasser@arm.com } else { 134811678Swendy.elsasser@arm.com DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 134911678Swendy.elsasser@arm.com "waiting\n", writesThisTime, writeQueue.size()); 135011678Swendy.elsasser@arm.com 135111678Swendy.elsasser@arm.com wrPerTurnAround.sample(writesThisTime); 135211678Swendy.elsasser@arm.com writesThisTime = 0; 135311678Swendy.elsasser@arm.com 135411678Swendy.elsasser@arm.com switched_cmd_type = true; 135511678Swendy.elsasser@arm.com } 135611678Swendy.elsasser@arm.com // update busState to match next state until next transition 135711678Swendy.elsasser@arm.com busState = busStateNext; 135810206Sandreas.hansson@arm.com } 135910206Sandreas.hansson@arm.com 136010206Sandreas.hansson@arm.com // when we get here it is either a read or a write 136110206Sandreas.hansson@arm.com if (busState == READ) { 136210206Sandreas.hansson@arm.com 136310206Sandreas.hansson@arm.com // track if we should switch or not 136410206Sandreas.hansson@arm.com bool switch_to_writes = false; 136510206Sandreas.hansson@arm.com 136610206Sandreas.hansson@arm.com if (readQueue.empty()) { 136710206Sandreas.hansson@arm.com // In the case there is no read request to go next, 136810206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 136910206Sandreas.hansson@arm.com // if we are draining) 137010206Sandreas.hansson@arm.com if (!writeQueue.empty() && 137110913Sandreas.sandberg@arm.com (drainState() == DrainState::Draining || 137210913Sandreas.sandberg@arm.com writeQueue.size() > writeLowThreshold)) { 137310206Sandreas.hansson@arm.com 137410206Sandreas.hansson@arm.com switch_to_writes = true; 137510206Sandreas.hansson@arm.com } else { 137610206Sandreas.hansson@arm.com // check if we are drained 137711676Swendy.elsasser@arm.com // not done draining until in PWR_IDLE state 137811676Swendy.elsasser@arm.com // ensuring all banks are closed and 137911676Swendy.elsasser@arm.com // have exited low power states 138010913Sandreas.sandberg@arm.com if (drainState() == DrainState::Draining && 138111676Swendy.elsasser@arm.com respQueue.empty() && allRanksDrained()) { 138210913Sandreas.sandberg@arm.com 138310509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 138410913Sandreas.sandberg@arm.com signalDrainDone(); 138510206Sandreas.hansson@arm.com } 138610206Sandreas.hansson@arm.com 138710206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 138810206Sandreas.hansson@arm.com // event for the next request 138910206Sandreas.hansson@arm.com return; 139010206Sandreas.hansson@arm.com } 139110206Sandreas.hansson@arm.com } else { 139210618SOmar.Naji@arm.com // bool to check if there is a read to a free rank 139310618SOmar.Naji@arm.com bool found_read = false; 139410618SOmar.Naji@arm.com 139510206Sandreas.hansson@arm.com // Figure out which read request goes next, and move it to the 139610206Sandreas.hansson@arm.com // front of the read queue 139710890Swendy.elsasser@arm.com // If we are changing command type, incorporate the minimum 139810890Swendy.elsasser@arm.com // bus turnaround delay which will be tCS (different rank) case 139910890Swendy.elsasser@arm.com found_read = chooseNext(readQueue, 140010890Swendy.elsasser@arm.com switched_cmd_type ? tCS : 0); 140110618SOmar.Naji@arm.com 140210618SOmar.Naji@arm.com // if no read to an available rank is found then return 140310618SOmar.Naji@arm.com // at this point. There could be writes to the available ranks 140410618SOmar.Naji@arm.com // which are above the required threshold. However, to 140510618SOmar.Naji@arm.com // avoid adding more complexity to the code, return and wait 140610618SOmar.Naji@arm.com // for a refresh event to kick things into action again. 140710618SOmar.Naji@arm.com if (!found_read) 140810618SOmar.Naji@arm.com return; 140910206Sandreas.hansson@arm.com 141010215Sandreas.hansson@arm.com DRAMPacket* dram_pkt = readQueue.front(); 141110618SOmar.Naji@arm.com assert(dram_pkt->rankRef.isAvailable()); 141211678Swendy.elsasser@arm.com 141310393Swendy.elsasser@arm.com // here we get a bit creative and shift the bus busy time not 141410393Swendy.elsasser@arm.com // just the tWTR, but also a CAS latency to capture the fact 141510393Swendy.elsasser@arm.com // that we are allowed to prepare a new bank, but not issue a 141610393Swendy.elsasser@arm.com // read command until after tWTR, in essence we capture a 141710393Swendy.elsasser@arm.com // bubble on the data bus that is tWTR + tCL 141810394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 141910394Swendy.elsasser@arm.com busBusyUntil += tWTR + tCL; 142010393Swendy.elsasser@arm.com } 142110393Swendy.elsasser@arm.com 142210215Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 142310206Sandreas.hansson@arm.com 142410206Sandreas.hansson@arm.com // At this point we're done dealing with the request 142510215Sandreas.hansson@arm.com readQueue.pop_front(); 142610215Sandreas.hansson@arm.com 142711678Swendy.elsasser@arm.com // Every respQueue which will generate an event, increment count 142811678Swendy.elsasser@arm.com ++dram_pkt->rankRef.outstandingEvents; 142911678Swendy.elsasser@arm.com 143010215Sandreas.hansson@arm.com // sanity check 143110215Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 143210215Sandreas.hansson@arm.com assert(dram_pkt->readyTime >= curTick()); 143310215Sandreas.hansson@arm.com 143410215Sandreas.hansson@arm.com // Insert into response queue. It will be sent back to the 143510215Sandreas.hansson@arm.com // requestor at its readyTime 143610215Sandreas.hansson@arm.com if (respQueue.empty()) { 143710215Sandreas.hansson@arm.com assert(!respondEvent.scheduled()); 143810215Sandreas.hansson@arm.com schedule(respondEvent, dram_pkt->readyTime); 143910215Sandreas.hansson@arm.com } else { 144010215Sandreas.hansson@arm.com assert(respQueue.back()->readyTime <= dram_pkt->readyTime); 144110215Sandreas.hansson@arm.com assert(respondEvent.scheduled()); 144210215Sandreas.hansson@arm.com } 144310215Sandreas.hansson@arm.com 144410215Sandreas.hansson@arm.com respQueue.push_back(dram_pkt); 144510206Sandreas.hansson@arm.com 144610206Sandreas.hansson@arm.com // we have so many writes that we have to transition 144710206Sandreas.hansson@arm.com if (writeQueue.size() > writeHighThreshold) { 144810206Sandreas.hansson@arm.com switch_to_writes = true; 144910206Sandreas.hansson@arm.com } 145010206Sandreas.hansson@arm.com } 145110206Sandreas.hansson@arm.com 145210206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 145310206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 145410206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 145510206Sandreas.hansson@arm.com if (switch_to_writes) { 145610206Sandreas.hansson@arm.com // transition to writing 145711678Swendy.elsasser@arm.com busStateNext = WRITE; 145810206Sandreas.hansson@arm.com } 14599352SN/A } else { 146010618SOmar.Naji@arm.com // bool to check if write to free rank is found 146110618SOmar.Naji@arm.com bool found_write = false; 146210618SOmar.Naji@arm.com 146310890Swendy.elsasser@arm.com // If we are changing command type, incorporate the minimum 146410890Swendy.elsasser@arm.com // bus turnaround delay 146510890Swendy.elsasser@arm.com found_write = chooseNext(writeQueue, 146610890Swendy.elsasser@arm.com switched_cmd_type ? std::min(tRTW, tCS) : 0); 146710618SOmar.Naji@arm.com 146810618SOmar.Naji@arm.com // if no writes to an available rank are found then return. 146910618SOmar.Naji@arm.com // There could be reads to the available ranks. However, to avoid 147010618SOmar.Naji@arm.com // adding more complexity to the code, return at this point and wait 147110618SOmar.Naji@arm.com // for a refresh event to kick things into action again. 147210618SOmar.Naji@arm.com if (!found_write) 147310618SOmar.Naji@arm.com return; 147410618SOmar.Naji@arm.com 147510206Sandreas.hansson@arm.com DRAMPacket* dram_pkt = writeQueue.front(); 147610618SOmar.Naji@arm.com assert(dram_pkt->rankRef.isAvailable()); 147710206Sandreas.hansson@arm.com // sanity check 147810206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 147910393Swendy.elsasser@arm.com 148010394Swendy.elsasser@arm.com // add a bubble to the data bus, as defined by the 148110394Swendy.elsasser@arm.com // tRTW when access is to the same rank as previous burst 148210394Swendy.elsasser@arm.com // Different rank timing is handled with tCS, which is 148310394Swendy.elsasser@arm.com // applied to colAllowedAt 148410394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 148510394Swendy.elsasser@arm.com busBusyUntil += tRTW; 148610393Swendy.elsasser@arm.com } 148710393Swendy.elsasser@arm.com 148810206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 148910206Sandreas.hansson@arm.com 149010206Sandreas.hansson@arm.com writeQueue.pop_front(); 149111678Swendy.elsasser@arm.com 149211678Swendy.elsasser@arm.com // removed write from queue, decrement count 149311678Swendy.elsasser@arm.com --dram_pkt->rankRef.writeEntries; 149411678Swendy.elsasser@arm.com 149511678Swendy.elsasser@arm.com // Schedule write done event to decrement event count 149611678Swendy.elsasser@arm.com // after the readyTime has been reached 149711678Swendy.elsasser@arm.com // Only schedule latest write event to minimize events 149811678Swendy.elsasser@arm.com // required; only need to ensure that final event scheduled covers 149911678Swendy.elsasser@arm.com // the time that writes are outstanding and bus is active 150011678Swendy.elsasser@arm.com // to holdoff power-down entry events 150111678Swendy.elsasser@arm.com if (!dram_pkt->rankRef.writeDoneEvent.scheduled()) { 150211678Swendy.elsasser@arm.com schedule(dram_pkt->rankRef.writeDoneEvent, dram_pkt->readyTime); 150311678Swendy.elsasser@arm.com // New event, increment count 150411678Swendy.elsasser@arm.com ++dram_pkt->rankRef.outstandingEvents; 150511678Swendy.elsasser@arm.com 150611678Swendy.elsasser@arm.com } else if (dram_pkt->rankRef.writeDoneEvent.when() < 150711678Swendy.elsasser@arm.com dram_pkt-> readyTime) { 150811678Swendy.elsasser@arm.com reschedule(dram_pkt->rankRef.writeDoneEvent, dram_pkt->readyTime); 150911678Swendy.elsasser@arm.com } 151011678Swendy.elsasser@arm.com 151110889Sandreas.hansson@arm.com isInWriteQueue.erase(burstAlign(dram_pkt->addr)); 151210206Sandreas.hansson@arm.com delete dram_pkt; 151310206Sandreas.hansson@arm.com 151410206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 151510206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 151610206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 151710206Sandreas.hansson@arm.com // writes, then switch to reads. 151810206Sandreas.hansson@arm.com if (writeQueue.empty() || 151910206Sandreas.hansson@arm.com (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 152010913Sandreas.sandberg@arm.com drainState() != DrainState::Draining) || 152110206Sandreas.hansson@arm.com (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 152210206Sandreas.hansson@arm.com // turn the bus back around for reads again 152311678Swendy.elsasser@arm.com busStateNext = READ; 152410206Sandreas.hansson@arm.com 152510206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 152610206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 152710206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 152810206Sandreas.hansson@arm.com // nothing to do 152910206Sandreas.hansson@arm.com } 153010206Sandreas.hansson@arm.com } 153110618SOmar.Naji@arm.com // It is possible that a refresh to another rank kicks things back into 153210618SOmar.Naji@arm.com // action before reaching this point. 153310618SOmar.Naji@arm.com if (!nextReqEvent.scheduled()) 153410618SOmar.Naji@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 153510206Sandreas.hansson@arm.com 153610206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 153710206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 153810206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 153910206Sandreas.hansson@arm.com // the next request processing 154010206Sandreas.hansson@arm.com if (retryWrReq && writeQueue.size() < writeBufferSize) { 154110206Sandreas.hansson@arm.com retryWrReq = false; 154210713Sandreas.hansson@arm.com port.sendRetryReq(); 15439352SN/A } 15449243SN/A} 15459243SN/A 154610890Swendy.elsasser@arm.compair<uint64_t, bool> 154710393Swendy.elsasser@arm.comDRAMCtrl::minBankPrep(const deque<DRAMPacket*>& queue, 154810890Swendy.elsasser@arm.com Tick min_col_at) const 15499967SN/A{ 15509967SN/A uint64_t bank_mask = 0; 155110211Sandreas.hansson@arm.com Tick min_act_at = MaxTick; 15529967SN/A 155310890Swendy.elsasser@arm.com // latest Tick for which ACT can occur without incurring additoinal 155410890Swendy.elsasser@arm.com // delay on the data bus 155510890Swendy.elsasser@arm.com const Tick hidden_act_max = std::max(min_col_at - tRCD, curTick()); 155610393Swendy.elsasser@arm.com 155710890Swendy.elsasser@arm.com // Flag condition when burst can issue back-to-back with previous burst 155810890Swendy.elsasser@arm.com bool found_seamless_bank = false; 155910890Swendy.elsasser@arm.com 156010890Swendy.elsasser@arm.com // Flag condition when bank can be opened without incurring additional 156110890Swendy.elsasser@arm.com // delay on the data bus 156210890Swendy.elsasser@arm.com bool hidden_bank_prep = false; 156310393Swendy.elsasser@arm.com 156410393Swendy.elsasser@arm.com // determine if we have queued transactions targetting the 15659967SN/A // bank in question 15669967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 156710618SOmar.Naji@arm.com for (const auto& p : queue) { 156811321Ssteve.reinhardt@amd.com if (p->rankRef.isAvailable()) 156910618SOmar.Naji@arm.com got_waiting[p->bankId] = true; 15709967SN/A } 15719967SN/A 157210890Swendy.elsasser@arm.com // Find command with optimal bank timing 157310890Swendy.elsasser@arm.com // Will prioritize commands that can issue seamlessly. 15749967SN/A for (int i = 0; i < ranksPerChannel; i++) { 15759967SN/A for (int j = 0; j < banksPerRank; j++) { 157610618SOmar.Naji@arm.com uint16_t bank_id = i * banksPerRank + j; 157710211Sandreas.hansson@arm.com 15789967SN/A // if we have waiting requests for the bank, and it is 15799967SN/A // amongst the first available, update the mask 158010211Sandreas.hansson@arm.com if (got_waiting[bank_id]) { 158110618SOmar.Naji@arm.com // make sure this rank is not currently refreshing. 158210618SOmar.Naji@arm.com assert(ranks[i]->isAvailable()); 158310211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue 158410211Sandreas.hansson@arm.com // an activate, ignoring any rank-to-rank switching 158510393Swendy.elsasser@arm.com // cost in this calculation 158610618SOmar.Naji@arm.com Tick act_at = ranks[i]->banks[j].openRow == Bank::NO_ROW ? 158710890Swendy.elsasser@arm.com std::max(ranks[i]->banks[j].actAllowedAt, curTick()) : 158810618SOmar.Naji@arm.com std::max(ranks[i]->banks[j].preAllowedAt, curTick()) + tRP; 158910211Sandreas.hansson@arm.com 159010890Swendy.elsasser@arm.com // When is the earliest the R/W burst can issue? 159110890Swendy.elsasser@arm.com Tick col_at = std::max(ranks[i]->banks[j].colAllowedAt, 159210890Swendy.elsasser@arm.com act_at + tRCD); 159310393Swendy.elsasser@arm.com 159410890Swendy.elsasser@arm.com // bank can issue burst back-to-back (seamlessly) with 159510890Swendy.elsasser@arm.com // previous burst 159610890Swendy.elsasser@arm.com bool new_seamless_bank = col_at <= min_col_at; 159710393Swendy.elsasser@arm.com 159810890Swendy.elsasser@arm.com // if we found a new seamless bank or we have no 159910890Swendy.elsasser@arm.com // seamless banks, and got a bank with an earlier 160010890Swendy.elsasser@arm.com // activate time, it should be added to the bit mask 160110890Swendy.elsasser@arm.com if (new_seamless_bank || 160210890Swendy.elsasser@arm.com (!found_seamless_bank && act_at <= min_act_at)) { 160310890Swendy.elsasser@arm.com // if we did not have a seamless bank before, and 160410890Swendy.elsasser@arm.com // we do now, reset the bank mask, also reset it 160510890Swendy.elsasser@arm.com // if we have not yet found a seamless bank and 160610890Swendy.elsasser@arm.com // the activate time is smaller than what we have 160710890Swendy.elsasser@arm.com // seen so far 160810890Swendy.elsasser@arm.com if (!found_seamless_bank && 160910890Swendy.elsasser@arm.com (new_seamless_bank || act_at < min_act_at)) { 161010890Swendy.elsasser@arm.com bank_mask = 0; 161110393Swendy.elsasser@arm.com } 161210890Swendy.elsasser@arm.com 161310890Swendy.elsasser@arm.com found_seamless_bank |= new_seamless_bank; 161410890Swendy.elsasser@arm.com 161510890Swendy.elsasser@arm.com // ACT can occur 'behind the scenes' 161610890Swendy.elsasser@arm.com hidden_bank_prep = act_at <= hidden_act_max; 161710890Swendy.elsasser@arm.com 161810890Swendy.elsasser@arm.com // set the bit corresponding to the available bank 161910890Swendy.elsasser@arm.com replaceBits(bank_mask, bank_id, bank_id, 1); 162010890Swendy.elsasser@arm.com min_act_at = act_at; 162110211Sandreas.hansson@arm.com } 16229967SN/A } 16239967SN/A } 16249967SN/A } 162510211Sandreas.hansson@arm.com 162610890Swendy.elsasser@arm.com return make_pair(bank_mask, hidden_bank_prep); 16279967SN/A} 16289967SN/A 162910618SOmar.Naji@arm.comDRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p) 163010618SOmar.Naji@arm.com : EventManager(&_memory), memory(_memory), 163111678Swendy.elsasser@arm.com pwrStateTrans(PWR_IDLE), pwrStatePostRefresh(PWR_IDLE), 163211678Swendy.elsasser@arm.com pwrStateTick(0), refreshDueAt(0), pwrState(PWR_IDLE), 163311678Swendy.elsasser@arm.com refreshState(REF_IDLE), inLowPowerState(false), rank(0), 163411678Swendy.elsasser@arm.com readEntries(0), writeEntries(0), outstandingEvents(0), 163511678Swendy.elsasser@arm.com wakeUpAllowedAt(0), power(_p, false), numBanksActive(0), 163611678Swendy.elsasser@arm.com writeDoneEvent(*this), activateEvent(*this), prechargeEvent(*this), 163711678Swendy.elsasser@arm.com refreshEvent(*this), powerEvent(*this), wakeUpEvent(*this) 163810618SOmar.Naji@arm.com{ } 163910618SOmar.Naji@arm.com 16409243SN/Avoid 164110618SOmar.Naji@arm.comDRAMCtrl::Rank::startup(Tick ref_tick) 164210618SOmar.Naji@arm.com{ 164310618SOmar.Naji@arm.com assert(ref_tick > curTick()); 164410618SOmar.Naji@arm.com 164510618SOmar.Naji@arm.com pwrStateTick = curTick(); 164610618SOmar.Naji@arm.com 164710618SOmar.Naji@arm.com // kick off the refresh, and give ourselves enough time to 164810618SOmar.Naji@arm.com // precharge 164910618SOmar.Naji@arm.com schedule(refreshEvent, ref_tick); 165010618SOmar.Naji@arm.com} 165110618SOmar.Naji@arm.com 165210618SOmar.Naji@arm.comvoid 165310619Sandreas.hansson@arm.comDRAMCtrl::Rank::suspend() 165410619Sandreas.hansson@arm.com{ 165510619Sandreas.hansson@arm.com deschedule(refreshEvent); 165611676Swendy.elsasser@arm.com 165711676Swendy.elsasser@arm.com // Update the stats 165811676Swendy.elsasser@arm.com updatePowerStats(); 165911678Swendy.elsasser@arm.com 166011678Swendy.elsasser@arm.com // don't automatically transition back to LP state after next REF 166111678Swendy.elsasser@arm.com pwrStatePostRefresh = PWR_IDLE; 166211678Swendy.elsasser@arm.com} 166311678Swendy.elsasser@arm.com 166411678Swendy.elsasser@arm.combool 166511678Swendy.elsasser@arm.comDRAMCtrl::Rank::lowPowerEntryReady() const 166611678Swendy.elsasser@arm.com{ 166711678Swendy.elsasser@arm.com bool no_queued_cmds = ((memory.busStateNext == READ) && (readEntries == 0)) 166811678Swendy.elsasser@arm.com || ((memory.busStateNext == WRITE) && 166911678Swendy.elsasser@arm.com (writeEntries == 0)); 167011678Swendy.elsasser@arm.com 167111678Swendy.elsasser@arm.com if (refreshState == REF_RUN) { 167211678Swendy.elsasser@arm.com // have not decremented outstandingEvents for refresh command 167311678Swendy.elsasser@arm.com // still check if there are no commands queued to force PD 167411678Swendy.elsasser@arm.com // entry after refresh completes 167511678Swendy.elsasser@arm.com return no_queued_cmds; 167611678Swendy.elsasser@arm.com } else { 167711678Swendy.elsasser@arm.com // ensure no commands in Q and no commands scheduled 167811678Swendy.elsasser@arm.com return (no_queued_cmds && (outstandingEvents == 0)); 167911678Swendy.elsasser@arm.com } 168010619Sandreas.hansson@arm.com} 168110619Sandreas.hansson@arm.com 168210619Sandreas.hansson@arm.comvoid 168310618SOmar.Naji@arm.comDRAMCtrl::Rank::checkDrainDone() 168410618SOmar.Naji@arm.com{ 168510618SOmar.Naji@arm.com // if this rank was waiting to drain it is now able to proceed to 168610618SOmar.Naji@arm.com // precharge 168710618SOmar.Naji@arm.com if (refreshState == REF_DRAIN) { 168810618SOmar.Naji@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 168910618SOmar.Naji@arm.com 169011678Swendy.elsasser@arm.com refreshState = REF_PD_EXIT; 169110618SOmar.Naji@arm.com 169210618SOmar.Naji@arm.com // hand control back to the refresh event loop 169310618SOmar.Naji@arm.com schedule(refreshEvent, curTick()); 169410618SOmar.Naji@arm.com } 169510618SOmar.Naji@arm.com} 169610618SOmar.Naji@arm.com 169710618SOmar.Naji@arm.comvoid 169811675Swendy.elsasser@arm.comDRAMCtrl::Rank::flushCmdList() 169911675Swendy.elsasser@arm.com{ 170011675Swendy.elsasser@arm.com // at the moment sort the list of commands and update the counters 170111675Swendy.elsasser@arm.com // for DRAMPower libray when doing a refresh 170211675Swendy.elsasser@arm.com sort(cmdList.begin(), cmdList.end(), DRAMCtrl::sortTime); 170311675Swendy.elsasser@arm.com 170411675Swendy.elsasser@arm.com auto next_iter = cmdList.begin(); 170511675Swendy.elsasser@arm.com // push to commands to DRAMPower 170611675Swendy.elsasser@arm.com for ( ; next_iter != cmdList.end() ; ++next_iter) { 170711675Swendy.elsasser@arm.com Command cmd = *next_iter; 170811675Swendy.elsasser@arm.com if (cmd.timeStamp <= curTick()) { 170911675Swendy.elsasser@arm.com // Move all commands at or before curTick to DRAMPower 171011675Swendy.elsasser@arm.com power.powerlib.doCommand(cmd.type, cmd.bank, 171111675Swendy.elsasser@arm.com divCeil(cmd.timeStamp, memory.tCK) - 171211675Swendy.elsasser@arm.com memory.timeStampOffset); 171311675Swendy.elsasser@arm.com } else { 171411675Swendy.elsasser@arm.com // done - found all commands at or before curTick() 171511675Swendy.elsasser@arm.com // next_iter references the 1st command after curTick 171611675Swendy.elsasser@arm.com break; 171711675Swendy.elsasser@arm.com } 171811675Swendy.elsasser@arm.com } 171911675Swendy.elsasser@arm.com // reset cmdList to only contain commands after curTick 172011675Swendy.elsasser@arm.com // if there are no commands after curTick, updated cmdList will be empty 172111675Swendy.elsasser@arm.com // in this case, next_iter is cmdList.end() 172211675Swendy.elsasser@arm.com cmdList.assign(next_iter, cmdList.end()); 172311675Swendy.elsasser@arm.com} 172411675Swendy.elsasser@arm.com 172511675Swendy.elsasser@arm.comvoid 172610618SOmar.Naji@arm.comDRAMCtrl::Rank::processActivateEvent() 172710618SOmar.Naji@arm.com{ 172810618SOmar.Naji@arm.com // we should transition to the active state as soon as any bank is active 172910618SOmar.Naji@arm.com if (pwrState != PWR_ACT) 173010618SOmar.Naji@arm.com // note that at this point numBanksActive could be back at 173110618SOmar.Naji@arm.com // zero again due to a precharge scheduled in the future 173210618SOmar.Naji@arm.com schedulePowerEvent(PWR_ACT, curTick()); 173310618SOmar.Naji@arm.com} 173410618SOmar.Naji@arm.com 173510618SOmar.Naji@arm.comvoid 173610618SOmar.Naji@arm.comDRAMCtrl::Rank::processPrechargeEvent() 173710618SOmar.Naji@arm.com{ 173811678Swendy.elsasser@arm.com // counter should at least indicate one outstanding request 173911678Swendy.elsasser@arm.com // for this precharge 174011678Swendy.elsasser@arm.com assert(outstandingEvents > 0); 174111678Swendy.elsasser@arm.com // precharge complete, decrement count 174211678Swendy.elsasser@arm.com --outstandingEvents; 174311678Swendy.elsasser@arm.com 174410618SOmar.Naji@arm.com // if we reached zero, then special conditions apply as we track 174510618SOmar.Naji@arm.com // if all banks are precharged for the power models 174610618SOmar.Naji@arm.com if (numBanksActive == 0) { 174711678Swendy.elsasser@arm.com // no reads to this rank in the Q and no pending 174811678Swendy.elsasser@arm.com // RD/WR or refresh commands 174911678Swendy.elsasser@arm.com if (lowPowerEntryReady()) { 175011678Swendy.elsasser@arm.com // should still be in ACT state since bank still open 175111678Swendy.elsasser@arm.com assert(pwrState == PWR_ACT); 175211678Swendy.elsasser@arm.com 175311678Swendy.elsasser@arm.com // All banks closed - switch to precharge power down state. 175411678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleep at tick %d\n", 175511678Swendy.elsasser@arm.com rank, curTick()); 175611678Swendy.elsasser@arm.com powerDownSleep(PWR_PRE_PDN, curTick()); 175711678Swendy.elsasser@arm.com } else { 175811678Swendy.elsasser@arm.com // we should transition to the idle state when the last bank 175911678Swendy.elsasser@arm.com // is precharged 176011678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 176111678Swendy.elsasser@arm.com } 176210618SOmar.Naji@arm.com } 176310618SOmar.Naji@arm.com} 176410618SOmar.Naji@arm.com 176510618SOmar.Naji@arm.comvoid 176611678Swendy.elsasser@arm.comDRAMCtrl::Rank::processWriteDoneEvent() 176711678Swendy.elsasser@arm.com{ 176811678Swendy.elsasser@arm.com // counter should at least indicate one outstanding request 176911678Swendy.elsasser@arm.com // for this write 177011678Swendy.elsasser@arm.com assert(outstandingEvents > 0); 177111678Swendy.elsasser@arm.com // Write transfer on bus has completed 177211678Swendy.elsasser@arm.com // decrement per rank counter 177311678Swendy.elsasser@arm.com --outstandingEvents; 177411678Swendy.elsasser@arm.com} 177511678Swendy.elsasser@arm.com 177611678Swendy.elsasser@arm.comvoid 177710618SOmar.Naji@arm.comDRAMCtrl::Rank::processRefreshEvent() 17789243SN/A{ 177910207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 178011678Swendy.elsasser@arm.com if ((refreshState == REF_IDLE) || (refreshState == REF_SREF_EXIT)) { 178110207Sandreas.hansson@arm.com // remember when the refresh is due 178210207Sandreas.hansson@arm.com refreshDueAt = curTick(); 17839243SN/A 178410207Sandreas.hansson@arm.com // proceed to drain 178510207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 17869243SN/A 178711678Swendy.elsasser@arm.com // make nonzero while refresh is pending to ensure 178811678Swendy.elsasser@arm.com // power down and self-refresh are not entered 178911678Swendy.elsasser@arm.com ++outstandingEvents; 179011678Swendy.elsasser@arm.com 179110207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 179210207Sandreas.hansson@arm.com } 179310207Sandreas.hansson@arm.com 179410618SOmar.Naji@arm.com // let any scheduled read or write to the same rank go ahead, 179510618SOmar.Naji@arm.com // after which it will 179610207Sandreas.hansson@arm.com // hand control back to this event loop 179710207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 179810618SOmar.Naji@arm.com // if a request is at the moment being handled and this request is 179910618SOmar.Naji@arm.com // accessing the current rank then wait for it to finish 180010618SOmar.Naji@arm.com if ((rank == memory.activeRank) 180110618SOmar.Naji@arm.com && (memory.nextReqEvent.scheduled())) { 180210207Sandreas.hansson@arm.com // hand control over to the request loop until it is 180310207Sandreas.hansson@arm.com // evaluated next 180410207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 180510207Sandreas.hansson@arm.com 180610207Sandreas.hansson@arm.com return; 180710207Sandreas.hansson@arm.com } else { 180811678Swendy.elsasser@arm.com refreshState = REF_PD_EXIT; 180911678Swendy.elsasser@arm.com } 181011678Swendy.elsasser@arm.com } 181111678Swendy.elsasser@arm.com 181211678Swendy.elsasser@arm.com // at this point, ensure that rank is not in a power-down state 181311678Swendy.elsasser@arm.com if (refreshState == REF_PD_EXIT) { 181411678Swendy.elsasser@arm.com // if rank was sleeping and we have't started exit process, 181511678Swendy.elsasser@arm.com // wake-up for refresh 181611678Swendy.elsasser@arm.com if (inLowPowerState) { 181711678Swendy.elsasser@arm.com DPRINTF(DRAM, "Wake Up for refresh\n"); 181811678Swendy.elsasser@arm.com // save state and return after refresh completes 181911678Swendy.elsasser@arm.com scheduleWakeUpEvent(memory.tXP); 182011678Swendy.elsasser@arm.com return; 182111678Swendy.elsasser@arm.com } else { 182210207Sandreas.hansson@arm.com refreshState = REF_PRE; 182310207Sandreas.hansson@arm.com } 182410207Sandreas.hansson@arm.com } 182510207Sandreas.hansson@arm.com 182610207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 182710207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 182811678Swendy.elsasser@arm.com // precharge any active bank 182911678Swendy.elsasser@arm.com if (numBanksActive != 0) { 183010214Sandreas.hansson@arm.com // at the moment, we use a precharge all even if there is 183110214Sandreas.hansson@arm.com // only a single bank open 183210208Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 183310214Sandreas.hansson@arm.com 183410214Sandreas.hansson@arm.com // first determine when we can precharge 183510214Sandreas.hansson@arm.com Tick pre_at = curTick(); 183610618SOmar.Naji@arm.com 183710618SOmar.Naji@arm.com for (auto &b : banks) { 183810618SOmar.Naji@arm.com // respect both causality and any existing bank 183910618SOmar.Naji@arm.com // constraints, some banks could already have a 184010618SOmar.Naji@arm.com // (auto) precharge scheduled 184110618SOmar.Naji@arm.com pre_at = std::max(b.preAllowedAt, pre_at); 184210618SOmar.Naji@arm.com } 184310618SOmar.Naji@arm.com 184410618SOmar.Naji@arm.com // make sure all banks per rank are precharged, and for those that 184510618SOmar.Naji@arm.com // already are, update their availability 184610618SOmar.Naji@arm.com Tick act_allowed_at = pre_at + memory.tRP; 184710618SOmar.Naji@arm.com 184810618SOmar.Naji@arm.com for (auto &b : banks) { 184910618SOmar.Naji@arm.com if (b.openRow != Bank::NO_ROW) { 185010618SOmar.Naji@arm.com memory.prechargeBank(*this, b, pre_at, false); 185110618SOmar.Naji@arm.com } else { 185210618SOmar.Naji@arm.com b.actAllowedAt = std::max(b.actAllowedAt, act_allowed_at); 185310618SOmar.Naji@arm.com b.preAllowedAt = std::max(b.preAllowedAt, pre_at); 185410214Sandreas.hansson@arm.com } 185510214Sandreas.hansson@arm.com } 185610214Sandreas.hansson@arm.com 185710618SOmar.Naji@arm.com // precharge all banks in rank 185811675Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PREA, 0, pre_at)); 185910214Sandreas.hansson@arm.com 186010618SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PREA,0,%d\n", 186110618SOmar.Naji@arm.com divCeil(pre_at, memory.tCK) - 186210618SOmar.Naji@arm.com memory.timeStampOffset, rank); 186311678Swendy.elsasser@arm.com } else if ((pwrState == PWR_IDLE) && (outstandingEvents == 1)) { 186411678Swendy.elsasser@arm.com // Banks are closed, have transitioned to IDLE state, and 186511678Swendy.elsasser@arm.com // no outstanding ACT,RD/WR,Auto-PRE sequence scheduled 186610208Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 186710208Sandreas.hansson@arm.com 186811678Swendy.elsasser@arm.com // go ahead and kick the power state machine into gear since 186910208Sandreas.hansson@arm.com // we are already idle 187010208Sandreas.hansson@arm.com schedulePowerEvent(PWR_REF, curTick()); 187111678Swendy.elsasser@arm.com } else { 187211678Swendy.elsasser@arm.com // banks state is closed but haven't transitioned pwrState to IDLE 187311678Swendy.elsasser@arm.com // or have outstanding ACT,RD/WR,Auto-PRE sequence scheduled 187411678Swendy.elsasser@arm.com // should have outstanding precharge event in this case 187511678Swendy.elsasser@arm.com assert(prechargeEvent.scheduled()); 187611678Swendy.elsasser@arm.com // will start refresh when pwrState transitions to IDLE 18779975SN/A } 18789975SN/A 187910208Sandreas.hansson@arm.com assert(numBanksActive == 0); 18809243SN/A 188110208Sandreas.hansson@arm.com // wait for all banks to be precharged, at which point the 188210208Sandreas.hansson@arm.com // power state machine will transition to the idle state, and 188310208Sandreas.hansson@arm.com // automatically move to a refresh, at that point it will also 188410208Sandreas.hansson@arm.com // call this method to get the refresh event loop going again 188510207Sandreas.hansson@arm.com return; 188610207Sandreas.hansson@arm.com } 188710207Sandreas.hansson@arm.com 188810207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 188911678Swendy.elsasser@arm.com if (refreshState == REF_START) { 189011678Swendy.elsasser@arm.com // should never get here with any banks active 189111678Swendy.elsasser@arm.com assert(numBanksActive == 0); 189211678Swendy.elsasser@arm.com assert(pwrState == PWR_REF); 189311678Swendy.elsasser@arm.com 189411678Swendy.elsasser@arm.com Tick ref_done_at = curTick() + memory.tRFC; 189511678Swendy.elsasser@arm.com 189611678Swendy.elsasser@arm.com for (auto &b : banks) { 189711678Swendy.elsasser@arm.com b.actAllowedAt = ref_done_at; 189811678Swendy.elsasser@arm.com } 189911678Swendy.elsasser@arm.com 190011678Swendy.elsasser@arm.com // at the moment this affects all ranks 190111678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::REF, 0, curTick())); 190211678Swendy.elsasser@arm.com 190311678Swendy.elsasser@arm.com // Update the stats 190411678Swendy.elsasser@arm.com updatePowerStats(); 190511678Swendy.elsasser@arm.com 190611678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), memory.tCK) - 190711678Swendy.elsasser@arm.com memory.timeStampOffset, rank); 190811678Swendy.elsasser@arm.com 190911678Swendy.elsasser@arm.com // Update for next refresh 191011678Swendy.elsasser@arm.com refreshDueAt += memory.tREFI; 191111678Swendy.elsasser@arm.com 191211678Swendy.elsasser@arm.com // make sure we did not wait so long that we cannot make up 191311678Swendy.elsasser@arm.com // for it 191411678Swendy.elsasser@arm.com if (refreshDueAt < ref_done_at) { 191511678Swendy.elsasser@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 191611678Swendy.elsasser@arm.com } 191711678Swendy.elsasser@arm.com 191811678Swendy.elsasser@arm.com // Run the refresh and schedule event to transition power states 191911678Swendy.elsasser@arm.com // when refresh completes 192011678Swendy.elsasser@arm.com refreshState = REF_RUN; 192111678Swendy.elsasser@arm.com schedule(refreshEvent, ref_done_at); 192211678Swendy.elsasser@arm.com return; 192311678Swendy.elsasser@arm.com } 192411678Swendy.elsasser@arm.com 192510207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 192610207Sandreas.hansson@arm.com // should never get here with any banks active 192710207Sandreas.hansson@arm.com assert(numBanksActive == 0); 192810208Sandreas.hansson@arm.com assert(pwrState == PWR_REF); 192910207Sandreas.hansson@arm.com 193011678Swendy.elsasser@arm.com assert(!powerEvent.scheduled()); 193111678Swendy.elsasser@arm.com 193211678Swendy.elsasser@arm.com if ((memory.drainState() == DrainState::Draining) || 193311678Swendy.elsasser@arm.com (memory.drainState() == DrainState::Drained)) { 193411678Swendy.elsasser@arm.com // if draining, do not re-enter low-power mode. 193511678Swendy.elsasser@arm.com // simply go to IDLE and wait 193611678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 193711678Swendy.elsasser@arm.com } else { 193811678Swendy.elsasser@arm.com // At the moment, we sleep when the refresh ends and wait to be 193911678Swendy.elsasser@arm.com // woken up again if previously in a low-power state. 194011678Swendy.elsasser@arm.com if (pwrStatePostRefresh != PWR_IDLE) { 194111678Swendy.elsasser@arm.com // power State should be power Refresh 194211678Swendy.elsasser@arm.com assert(pwrState == PWR_REF); 194311678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleeping after refresh and was in " 194411678Swendy.elsasser@arm.com "power state %d before refreshing\n", rank, 194511678Swendy.elsasser@arm.com pwrStatePostRefresh); 194611678Swendy.elsasser@arm.com powerDownSleep(pwrState, curTick()); 194711678Swendy.elsasser@arm.com 194811678Swendy.elsasser@arm.com // Force PRE power-down if there are no outstanding commands 194911678Swendy.elsasser@arm.com // in Q after refresh. 195011678Swendy.elsasser@arm.com } else if (lowPowerEntryReady()) { 195111678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleeping after refresh but was NOT" 195211678Swendy.elsasser@arm.com " in a low power state before refreshing\n", rank); 195311678Swendy.elsasser@arm.com powerDownSleep(PWR_PRE_PDN, curTick()); 195411678Swendy.elsasser@arm.com 195511678Swendy.elsasser@arm.com } else { 195611678Swendy.elsasser@arm.com // move to the idle power state once the refresh is done, this 195711678Swendy.elsasser@arm.com // will also move the refresh state machine to the refresh 195811678Swendy.elsasser@arm.com // idle state 195911678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 196011678Swendy.elsasser@arm.com } 196110618SOmar.Naji@arm.com } 196210247Sandreas.hansson@arm.com 196311678Swendy.elsasser@arm.com // if transitioning to self refresh do not schedule a new refresh; 196411678Swendy.elsasser@arm.com // when waking from self refresh, a refresh is scheduled again. 196511678Swendy.elsasser@arm.com if (pwrStateTrans != PWR_SREF) { 196611678Swendy.elsasser@arm.com // compensate for the delay in actually performing the refresh 196711678Swendy.elsasser@arm.com // when scheduling the next one 196811678Swendy.elsasser@arm.com schedule(refreshEvent, refreshDueAt - memory.tRP); 196911678Swendy.elsasser@arm.com 197011678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Refresh done at %llu and next refresh" 197111678Swendy.elsasser@arm.com " at %llu\n", curTick(), refreshDueAt); 197210207Sandreas.hansson@arm.com } 197310208Sandreas.hansson@arm.com } 197410208Sandreas.hansson@arm.com} 197510208Sandreas.hansson@arm.com 197610208Sandreas.hansson@arm.comvoid 197710618SOmar.Naji@arm.comDRAMCtrl::Rank::schedulePowerEvent(PowerState pwr_state, Tick tick) 197810208Sandreas.hansson@arm.com{ 197910208Sandreas.hansson@arm.com // respect causality 198010208Sandreas.hansson@arm.com assert(tick >= curTick()); 198110208Sandreas.hansson@arm.com 198210208Sandreas.hansson@arm.com if (!powerEvent.scheduled()) { 198310208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 198410208Sandreas.hansson@arm.com tick, pwr_state); 198510208Sandreas.hansson@arm.com 198610208Sandreas.hansson@arm.com // insert the new transition 198710208Sandreas.hansson@arm.com pwrStateTrans = pwr_state; 198810208Sandreas.hansson@arm.com 198910208Sandreas.hansson@arm.com schedule(powerEvent, tick); 199010208Sandreas.hansson@arm.com } else { 199110208Sandreas.hansson@arm.com panic("Scheduled power event at %llu to state %d, " 199210208Sandreas.hansson@arm.com "with scheduled event at %llu to %d\n", tick, pwr_state, 199310208Sandreas.hansson@arm.com powerEvent.when(), pwrStateTrans); 199410208Sandreas.hansson@arm.com } 199510208Sandreas.hansson@arm.com} 199610208Sandreas.hansson@arm.com 199710208Sandreas.hansson@arm.comvoid 199811678Swendy.elsasser@arm.comDRAMCtrl::Rank::powerDownSleep(PowerState pwr_state, Tick tick) 199911678Swendy.elsasser@arm.com{ 200011678Swendy.elsasser@arm.com // if low power state is active low, schedule to active low power state. 200111678Swendy.elsasser@arm.com // in reality tCKE is needed to enter active low power. This is neglected 200211678Swendy.elsasser@arm.com // here and could be added in the future. 200311678Swendy.elsasser@arm.com if (pwr_state == PWR_ACT_PDN) { 200411678Swendy.elsasser@arm.com schedulePowerEvent(pwr_state, tick); 200511678Swendy.elsasser@arm.com // push command to DRAMPower 200611678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PDN_F_ACT, 0, tick)); 200711678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PDN_F_ACT,0,%d\n", divCeil(tick, 200811678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 200911678Swendy.elsasser@arm.com } else if (pwr_state == PWR_PRE_PDN) { 201011678Swendy.elsasser@arm.com // if low power state is precharge low, schedule to precharge low 201111678Swendy.elsasser@arm.com // power state. In reality tCKE is needed to enter active low power. 201211678Swendy.elsasser@arm.com // This is neglected here. 201311678Swendy.elsasser@arm.com schedulePowerEvent(pwr_state, tick); 201411678Swendy.elsasser@arm.com //push Command to DRAMPower 201511678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PDN_F_PRE, 0, tick)); 201611678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PDN_F_PRE,0,%d\n", divCeil(tick, 201711678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 201811678Swendy.elsasser@arm.com } else if (pwr_state == PWR_REF) { 201911678Swendy.elsasser@arm.com // if a refresh just occured 202011678Swendy.elsasser@arm.com // transition to PRE_PDN now that all banks are closed 202111678Swendy.elsasser@arm.com // do not transition to SREF if commands are in Q; stay in PRE_PDN 202211678Swendy.elsasser@arm.com if (pwrStatePostRefresh == PWR_ACT_PDN || !lowPowerEntryReady()) { 202311678Swendy.elsasser@arm.com // prechage power down requires tCKE to enter. For simplicity 202411678Swendy.elsasser@arm.com // this is not considered. 202511678Swendy.elsasser@arm.com schedulePowerEvent(PWR_PRE_PDN, tick); 202611678Swendy.elsasser@arm.com //push Command to DRAMPower 202711678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PDN_F_PRE, 0, tick)); 202811678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PDN_F_PRE,0,%d\n", divCeil(tick, 202911678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 203011678Swendy.elsasser@arm.com } else { 203111678Swendy.elsasser@arm.com // last low power State was power precharge 203211678Swendy.elsasser@arm.com assert(pwrStatePostRefresh == PWR_PRE_PDN); 203311678Swendy.elsasser@arm.com // self refresh requires time tCKESR to enter. For simplicity, 203411678Swendy.elsasser@arm.com // this is not considered. 203511678Swendy.elsasser@arm.com schedulePowerEvent(PWR_SREF, tick); 203611678Swendy.elsasser@arm.com // push Command to DRAMPower 203711678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::SREN, 0, tick)); 203811678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,SREN,0,%d\n", divCeil(tick, 203911678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 204011678Swendy.elsasser@arm.com } 204111678Swendy.elsasser@arm.com } 204211678Swendy.elsasser@arm.com // Ensure that we don't power-down and back up in same tick 204311678Swendy.elsasser@arm.com // Once we commit to PD entry, do it and wait for at least 1tCK 204411678Swendy.elsasser@arm.com // This could be replaced with tCKE if/when that is added to the model 204511678Swendy.elsasser@arm.com wakeUpAllowedAt = tick + memory.tCK; 204611678Swendy.elsasser@arm.com 204711678Swendy.elsasser@arm.com // Transitioning to a low power state, set flag 204811678Swendy.elsasser@arm.com inLowPowerState = true; 204911678Swendy.elsasser@arm.com} 205011678Swendy.elsasser@arm.com 205111678Swendy.elsasser@arm.comvoid 205211678Swendy.elsasser@arm.comDRAMCtrl::Rank::scheduleWakeUpEvent(Tick exit_delay) 205311678Swendy.elsasser@arm.com{ 205411678Swendy.elsasser@arm.com Tick wake_up_tick = std::max(curTick(), wakeUpAllowedAt); 205511678Swendy.elsasser@arm.com 205611678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Scheduling wake-up for rank %d at tick %d\n", 205711678Swendy.elsasser@arm.com rank, wake_up_tick); 205811678Swendy.elsasser@arm.com 205911678Swendy.elsasser@arm.com // if waking for refresh, hold previous state 206011678Swendy.elsasser@arm.com // else reset state back to IDLE 206111678Swendy.elsasser@arm.com if (refreshState == REF_PD_EXIT) { 206211678Swendy.elsasser@arm.com pwrStatePostRefresh = pwrState; 206311678Swendy.elsasser@arm.com } else { 206411678Swendy.elsasser@arm.com // don't automatically transition back to LP state after next REF 206511678Swendy.elsasser@arm.com pwrStatePostRefresh = PWR_IDLE; 206611678Swendy.elsasser@arm.com } 206711678Swendy.elsasser@arm.com 206811678Swendy.elsasser@arm.com // schedule wake-up with event to ensure entry has completed before 206911678Swendy.elsasser@arm.com // we try to wake-up 207011678Swendy.elsasser@arm.com schedule(wakeUpEvent, wake_up_tick); 207111678Swendy.elsasser@arm.com 207211678Swendy.elsasser@arm.com for (auto &b : banks) { 207311678Swendy.elsasser@arm.com // respect both causality and any existing bank 207411678Swendy.elsasser@arm.com // constraints, some banks could already have a 207511678Swendy.elsasser@arm.com // (auto) precharge scheduled 207611678Swendy.elsasser@arm.com b.colAllowedAt = std::max(wake_up_tick + exit_delay, b.colAllowedAt); 207711678Swendy.elsasser@arm.com b.preAllowedAt = std::max(wake_up_tick + exit_delay, b.preAllowedAt); 207811678Swendy.elsasser@arm.com b.actAllowedAt = std::max(wake_up_tick + exit_delay, b.actAllowedAt); 207911678Swendy.elsasser@arm.com } 208011678Swendy.elsasser@arm.com // Transitioning out of low power state, clear flag 208111678Swendy.elsasser@arm.com inLowPowerState = false; 208211678Swendy.elsasser@arm.com 208311678Swendy.elsasser@arm.com // push to DRAMPower 208411678Swendy.elsasser@arm.com // use pwrStateTrans for cases where we have a power event scheduled 208511678Swendy.elsasser@arm.com // to enter low power that has not yet been processed 208611678Swendy.elsasser@arm.com if (pwrStateTrans == PWR_ACT_PDN) { 208711678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PUP_ACT, 0, wake_up_tick)); 208811678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PUP_ACT,0,%d\n", divCeil(wake_up_tick, 208911678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 209011678Swendy.elsasser@arm.com 209111678Swendy.elsasser@arm.com } else if (pwrStateTrans == PWR_PRE_PDN) { 209211678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PUP_PRE, 0, wake_up_tick)); 209311678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PUP_PRE,0,%d\n", divCeil(wake_up_tick, 209411678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 209511678Swendy.elsasser@arm.com } else if (pwrStateTrans == PWR_SREF) { 209611678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::SREX, 0, wake_up_tick)); 209711678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,SREX,0,%d\n", divCeil(wake_up_tick, 209811678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 209911678Swendy.elsasser@arm.com } 210011678Swendy.elsasser@arm.com} 210111678Swendy.elsasser@arm.com 210211678Swendy.elsasser@arm.comvoid 210311678Swendy.elsasser@arm.comDRAMCtrl::Rank::processWakeUpEvent() 210411678Swendy.elsasser@arm.com{ 210511678Swendy.elsasser@arm.com // Should be in a power-down or self-refresh state 210611678Swendy.elsasser@arm.com assert((pwrState == PWR_ACT_PDN) || (pwrState == PWR_PRE_PDN) || 210711678Swendy.elsasser@arm.com (pwrState == PWR_SREF)); 210811678Swendy.elsasser@arm.com 210911678Swendy.elsasser@arm.com // Check current state to determine transition state 211011678Swendy.elsasser@arm.com if (pwrState == PWR_ACT_PDN) { 211111678Swendy.elsasser@arm.com // banks still open, transition to PWR_ACT 211211678Swendy.elsasser@arm.com schedulePowerEvent(PWR_ACT, curTick()); 211311678Swendy.elsasser@arm.com } else { 211411678Swendy.elsasser@arm.com // transitioning from a precharge power-down or self-refresh state 211511678Swendy.elsasser@arm.com // banks are closed - transition to PWR_IDLE 211611678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 211711678Swendy.elsasser@arm.com } 211811678Swendy.elsasser@arm.com} 211911678Swendy.elsasser@arm.com 212011678Swendy.elsasser@arm.comvoid 212110618SOmar.Naji@arm.comDRAMCtrl::Rank::processPowerEvent() 212210208Sandreas.hansson@arm.com{ 212311678Swendy.elsasser@arm.com assert(curTick() >= pwrStateTick); 212410208Sandreas.hansson@arm.com // remember where we were, and for how long 212510208Sandreas.hansson@arm.com Tick duration = curTick() - pwrStateTick; 212610208Sandreas.hansson@arm.com PowerState prev_state = pwrState; 212710208Sandreas.hansson@arm.com 212810208Sandreas.hansson@arm.com // update the accounting 212910208Sandreas.hansson@arm.com pwrStateTime[prev_state] += duration; 213010208Sandreas.hansson@arm.com 213111678Swendy.elsasser@arm.com // track to total idle time 213211678Swendy.elsasser@arm.com if ((prev_state == PWR_PRE_PDN) || (prev_state == PWR_ACT_PDN) || 213311678Swendy.elsasser@arm.com (prev_state == PWR_SREF)) { 213411678Swendy.elsasser@arm.com totalIdleTime += duration; 213511678Swendy.elsasser@arm.com } 213611678Swendy.elsasser@arm.com 213710208Sandreas.hansson@arm.com pwrState = pwrStateTrans; 213810208Sandreas.hansson@arm.com pwrStateTick = curTick(); 213910208Sandreas.hansson@arm.com 214011678Swendy.elsasser@arm.com // if rank was refreshing, make sure to start scheduling requests again 214111678Swendy.elsasser@arm.com if (prev_state == PWR_REF) { 214211678Swendy.elsasser@arm.com // bus IDLED prior to REF 214311678Swendy.elsasser@arm.com // counter should be one for refresh command only 214411678Swendy.elsasser@arm.com assert(outstandingEvents == 1); 214511678Swendy.elsasser@arm.com // REF complete, decrement count 214611678Swendy.elsasser@arm.com --outstandingEvents; 214711678Swendy.elsasser@arm.com 214811678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 214911678Swendy.elsasser@arm.com // if sleeping after refresh 215011678Swendy.elsasser@arm.com if (pwrState != PWR_IDLE) { 215111678Swendy.elsasser@arm.com assert((pwrState == PWR_PRE_PDN) || (pwrState == PWR_SREF)); 215211678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Switching to power down state after refreshing" 215311678Swendy.elsasser@arm.com " rank %d at %llu tick\n", rank, curTick()); 215411678Swendy.elsasser@arm.com } 215511678Swendy.elsasser@arm.com if (pwrState != PWR_SREF) { 215611678Swendy.elsasser@arm.com // rank is not available in SREF 215711678Swendy.elsasser@arm.com // don't transition to IDLE in this case 215811678Swendy.elsasser@arm.com refreshState = REF_IDLE; 215911678Swendy.elsasser@arm.com } 216011678Swendy.elsasser@arm.com // a request event could be already scheduled by the state 216111678Swendy.elsasser@arm.com // machine of the other rank 216211678Swendy.elsasser@arm.com if (!memory.nextReqEvent.scheduled()) { 216311678Swendy.elsasser@arm.com DPRINTF(DRAM, "Scheduling next request after refreshing rank %d\n", 216411678Swendy.elsasser@arm.com rank); 216511678Swendy.elsasser@arm.com schedule(memory.nextReqEvent, curTick()); 216611678Swendy.elsasser@arm.com } 216711678Swendy.elsasser@arm.com } else if (pwrState == PWR_ACT) { 216811678Swendy.elsasser@arm.com if (refreshState == REF_PD_EXIT) { 216911678Swendy.elsasser@arm.com // kick the refresh event loop into action again 217011678Swendy.elsasser@arm.com assert(prev_state == PWR_ACT_PDN); 217111678Swendy.elsasser@arm.com 217211678Swendy.elsasser@arm.com // go back to REF event and close banks 217311678Swendy.elsasser@arm.com refreshState = REF_PRE; 217411678Swendy.elsasser@arm.com schedule(refreshEvent, curTick()); 217511678Swendy.elsasser@arm.com } 217611678Swendy.elsasser@arm.com } else if (pwrState == PWR_IDLE) { 217710208Sandreas.hansson@arm.com DPRINTF(DRAMState, "All banks precharged\n"); 217811678Swendy.elsasser@arm.com if (prev_state == PWR_SREF) { 217911678Swendy.elsasser@arm.com // set refresh state to REF_SREF_EXIT, ensuring isAvailable 218011678Swendy.elsasser@arm.com // continues to return false during tXS after SREF exit 218111678Swendy.elsasser@arm.com // Schedule a refresh which kicks things back into action 218211678Swendy.elsasser@arm.com // when it finishes 218311678Swendy.elsasser@arm.com refreshState = REF_SREF_EXIT; 218411678Swendy.elsasser@arm.com schedule(refreshEvent, curTick() + memory.tXS); 218510208Sandreas.hansson@arm.com } else { 218610208Sandreas.hansson@arm.com // if we have a pending refresh, and are now moving to 218711678Swendy.elsasser@arm.com // the idle state, directly transition to a refresh 218811678Swendy.elsasser@arm.com if ((refreshState == REF_PRE) || (refreshState == REF_PD_EXIT)) { 218911678Swendy.elsasser@arm.com // ensure refresh is restarted only after final PRE command. 219011678Swendy.elsasser@arm.com // do not restart refresh if controller is in an intermediate 219111678Swendy.elsasser@arm.com // state, after PRE_PDN exit, when banks are IDLE but an 219211678Swendy.elsasser@arm.com // ACT is scheduled. 219311678Swendy.elsasser@arm.com if (!activateEvent.scheduled()) { 219411678Swendy.elsasser@arm.com // there should be nothing waiting at this point 219511678Swendy.elsasser@arm.com assert(!powerEvent.scheduled()); 219611678Swendy.elsasser@arm.com // update the state in zero time and proceed below 219711678Swendy.elsasser@arm.com pwrState = PWR_REF; 219811678Swendy.elsasser@arm.com } else { 219911678Swendy.elsasser@arm.com // must have PRE scheduled to transition back to IDLE 220011678Swendy.elsasser@arm.com // and re-kick off refresh 220111678Swendy.elsasser@arm.com assert(prechargeEvent.scheduled()); 220211678Swendy.elsasser@arm.com } 220310208Sandreas.hansson@arm.com } 220411678Swendy.elsasser@arm.com } 220510208Sandreas.hansson@arm.com } 220610208Sandreas.hansson@arm.com 220710208Sandreas.hansson@arm.com // we transition to the refresh state, let the refresh state 220810208Sandreas.hansson@arm.com // machine know of this state update and let it deal with the 220910208Sandreas.hansson@arm.com // scheduling of the next power state transition as well as the 221010208Sandreas.hansson@arm.com // following refresh 221110208Sandreas.hansson@arm.com if (pwrState == PWR_REF) { 221211678Swendy.elsasser@arm.com assert(refreshState == REF_PRE || refreshState == REF_PD_EXIT); 221310208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refreshing\n"); 221411678Swendy.elsasser@arm.com 221510208Sandreas.hansson@arm.com // kick the refresh event loop into action again, and that 221610208Sandreas.hansson@arm.com // in turn will schedule a transition to the idle power 221710208Sandreas.hansson@arm.com // state once the refresh is done 221811678Swendy.elsasser@arm.com if (refreshState == REF_PD_EXIT) { 221911678Swendy.elsasser@arm.com // Wait for PD exit timing to complete before issuing REF 222011678Swendy.elsasser@arm.com schedule(refreshEvent, curTick() + memory.tXP); 222111678Swendy.elsasser@arm.com } else { 222211678Swendy.elsasser@arm.com schedule(refreshEvent, curTick()); 222311678Swendy.elsasser@arm.com } 222411678Swendy.elsasser@arm.com // Banks transitioned to IDLE, start REF 222511678Swendy.elsasser@arm.com refreshState = REF_START; 222610207Sandreas.hansson@arm.com } 22279243SN/A} 22289243SN/A 22299243SN/Avoid 223010618SOmar.Naji@arm.comDRAMCtrl::Rank::updatePowerStats() 223110432SOmar.Naji@arm.com{ 223211676Swendy.elsasser@arm.com // All commands up to refresh have completed 223311676Swendy.elsasser@arm.com // flush cmdList to DRAMPower 223411676Swendy.elsasser@arm.com flushCmdList(); 223511676Swendy.elsasser@arm.com 223611676Swendy.elsasser@arm.com // update the counters for DRAMPower, passing false to 223711676Swendy.elsasser@arm.com // indicate that this is not the last command in the 223811676Swendy.elsasser@arm.com // list. DRAMPower requires this information for the 223911676Swendy.elsasser@arm.com // correct calculation of the background energy at the end 224011676Swendy.elsasser@arm.com // of the simulation. Ideally we would want to call this 224111676Swendy.elsasser@arm.com // function with true once at the end of the 224211676Swendy.elsasser@arm.com // simulation. However, the discarded energy is extremly 224311676Swendy.elsasser@arm.com // small and does not effect the final results. 224411676Swendy.elsasser@arm.com power.powerlib.updateCounters(false); 224511676Swendy.elsasser@arm.com 224611676Swendy.elsasser@arm.com // call the energy function 224711676Swendy.elsasser@arm.com power.powerlib.calcEnergy(); 224811676Swendy.elsasser@arm.com 224910432SOmar.Naji@arm.com // Get the energy and power from DRAMPower 225010432SOmar.Naji@arm.com Data::MemoryPowerModel::Energy energy = 225110618SOmar.Naji@arm.com power.powerlib.getEnergy(); 225210618SOmar.Naji@arm.com Data::MemoryPowerModel::Power rank_power = 225310618SOmar.Naji@arm.com power.powerlib.getPower(); 225410432SOmar.Naji@arm.com 225510618SOmar.Naji@arm.com actEnergy = energy.act_energy * memory.devicesPerRank; 225610618SOmar.Naji@arm.com preEnergy = energy.pre_energy * memory.devicesPerRank; 225710618SOmar.Naji@arm.com readEnergy = energy.read_energy * memory.devicesPerRank; 225810618SOmar.Naji@arm.com writeEnergy = energy.write_energy * memory.devicesPerRank; 225910618SOmar.Naji@arm.com refreshEnergy = energy.ref_energy * memory.devicesPerRank; 226010618SOmar.Naji@arm.com actBackEnergy = energy.act_stdby_energy * memory.devicesPerRank; 226110618SOmar.Naji@arm.com preBackEnergy = energy.pre_stdby_energy * memory.devicesPerRank; 226211678Swendy.elsasser@arm.com actPowerDownEnergy = energy.f_act_pd_energy * memory.devicesPerRank; 226311678Swendy.elsasser@arm.com prePowerDownEnergy = energy.f_pre_pd_energy * memory.devicesPerRank; 226411678Swendy.elsasser@arm.com selfRefreshEnergy = energy.sref_energy * memory.devicesPerRank; 226510618SOmar.Naji@arm.com totalEnergy = energy.total_energy * memory.devicesPerRank; 226610618SOmar.Naji@arm.com averagePower = rank_power.average_power * memory.devicesPerRank; 226710432SOmar.Naji@arm.com} 226810432SOmar.Naji@arm.com 226910432SOmar.Naji@arm.comvoid 227011677Swendy.elsasser@arm.comDRAMCtrl::Rank::computeStats() 227111677Swendy.elsasser@arm.com{ 227211677Swendy.elsasser@arm.com DPRINTF(DRAM,"Computing final stats\n"); 227311677Swendy.elsasser@arm.com 227411677Swendy.elsasser@arm.com // Force DRAM power to update counters based on time spent in 227511677Swendy.elsasser@arm.com // current state up to curTick() 227611677Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::NOP, 0, curTick())); 227711677Swendy.elsasser@arm.com 227811677Swendy.elsasser@arm.com // Update the stats 227911677Swendy.elsasser@arm.com updatePowerStats(); 228011677Swendy.elsasser@arm.com 228111677Swendy.elsasser@arm.com // final update of power state times 228211677Swendy.elsasser@arm.com pwrStateTime[pwrState] += (curTick() - pwrStateTick); 228311677Swendy.elsasser@arm.com pwrStateTick = curTick(); 228411677Swendy.elsasser@arm.com 228511677Swendy.elsasser@arm.com} 228611677Swendy.elsasser@arm.com 228711677Swendy.elsasser@arm.comvoid 228810618SOmar.Naji@arm.comDRAMCtrl::Rank::regStats() 228910618SOmar.Naji@arm.com{ 229010618SOmar.Naji@arm.com using namespace Stats; 229110618SOmar.Naji@arm.com 229210618SOmar.Naji@arm.com pwrStateTime 229311678Swendy.elsasser@arm.com .init(6) 229410618SOmar.Naji@arm.com .name(name() + ".memoryStateTime") 229510618SOmar.Naji@arm.com .desc("Time in different power states"); 229610618SOmar.Naji@arm.com pwrStateTime.subname(0, "IDLE"); 229710618SOmar.Naji@arm.com pwrStateTime.subname(1, "REF"); 229811678Swendy.elsasser@arm.com pwrStateTime.subname(2, "SREF"); 229911678Swendy.elsasser@arm.com pwrStateTime.subname(3, "PRE_PDN"); 230011678Swendy.elsasser@arm.com pwrStateTime.subname(4, "ACT"); 230111678Swendy.elsasser@arm.com pwrStateTime.subname(5, "ACT_PDN"); 230210618SOmar.Naji@arm.com 230310618SOmar.Naji@arm.com actEnergy 230410618SOmar.Naji@arm.com .name(name() + ".actEnergy") 230510618SOmar.Naji@arm.com .desc("Energy for activate commands per rank (pJ)"); 230610618SOmar.Naji@arm.com 230710618SOmar.Naji@arm.com preEnergy 230810618SOmar.Naji@arm.com .name(name() + ".preEnergy") 230910618SOmar.Naji@arm.com .desc("Energy for precharge commands per rank (pJ)"); 231010618SOmar.Naji@arm.com 231110618SOmar.Naji@arm.com readEnergy 231210618SOmar.Naji@arm.com .name(name() + ".readEnergy") 231310618SOmar.Naji@arm.com .desc("Energy for read commands per rank (pJ)"); 231410618SOmar.Naji@arm.com 231510618SOmar.Naji@arm.com writeEnergy 231610618SOmar.Naji@arm.com .name(name() + ".writeEnergy") 231710618SOmar.Naji@arm.com .desc("Energy for write commands per rank (pJ)"); 231810618SOmar.Naji@arm.com 231910618SOmar.Naji@arm.com refreshEnergy 232010618SOmar.Naji@arm.com .name(name() + ".refreshEnergy") 232110618SOmar.Naji@arm.com .desc("Energy for refresh commands per rank (pJ)"); 232210618SOmar.Naji@arm.com 232310618SOmar.Naji@arm.com actBackEnergy 232410618SOmar.Naji@arm.com .name(name() + ".actBackEnergy") 232510618SOmar.Naji@arm.com .desc("Energy for active background per rank (pJ)"); 232610618SOmar.Naji@arm.com 232710618SOmar.Naji@arm.com preBackEnergy 232810618SOmar.Naji@arm.com .name(name() + ".preBackEnergy") 232910618SOmar.Naji@arm.com .desc("Energy for precharge background per rank (pJ)"); 233010618SOmar.Naji@arm.com 233111678Swendy.elsasser@arm.com actPowerDownEnergy 233211678Swendy.elsasser@arm.com .name(name() + ".actPowerDownEnergy") 233311678Swendy.elsasser@arm.com .desc("Energy for active power-down per rank (pJ)"); 233411678Swendy.elsasser@arm.com 233511678Swendy.elsasser@arm.com prePowerDownEnergy 233611678Swendy.elsasser@arm.com .name(name() + ".prePowerDownEnergy") 233711678Swendy.elsasser@arm.com .desc("Energy for precharge power-down per rank (pJ)"); 233811678Swendy.elsasser@arm.com 233911678Swendy.elsasser@arm.com selfRefreshEnergy 234011678Swendy.elsasser@arm.com .name(name() + ".selfRefreshEnergy") 234111678Swendy.elsasser@arm.com .desc("Energy for self refresh per rank (pJ)"); 234211678Swendy.elsasser@arm.com 234310618SOmar.Naji@arm.com totalEnergy 234410618SOmar.Naji@arm.com .name(name() + ".totalEnergy") 234510618SOmar.Naji@arm.com .desc("Total energy per rank (pJ)"); 234610618SOmar.Naji@arm.com 234710618SOmar.Naji@arm.com averagePower 234810618SOmar.Naji@arm.com .name(name() + ".averagePower") 234910618SOmar.Naji@arm.com .desc("Core power per rank (mW)"); 235011677Swendy.elsasser@arm.com 235111678Swendy.elsasser@arm.com totalIdleTime 235211678Swendy.elsasser@arm.com .name(name() + ".totalIdleTime") 235311678Swendy.elsasser@arm.com .desc("Total Idle time Per DRAM Rank"); 235411678Swendy.elsasser@arm.com 235511677Swendy.elsasser@arm.com registerDumpCallback(new RankDumpCallback(this)); 235610618SOmar.Naji@arm.com} 235710618SOmar.Naji@arm.comvoid 235810146Sandreas.hansson@arm.comDRAMCtrl::regStats() 23599243SN/A{ 23609243SN/A using namespace Stats; 23619243SN/A 23629243SN/A AbstractMemory::regStats(); 23639243SN/A 236410618SOmar.Naji@arm.com for (auto r : ranks) { 236510618SOmar.Naji@arm.com r->regStats(); 236610618SOmar.Naji@arm.com } 236710618SOmar.Naji@arm.com 23689243SN/A readReqs 23699243SN/A .name(name() + ".readReqs") 23709977SN/A .desc("Number of read requests accepted"); 23719243SN/A 23729243SN/A writeReqs 23739243SN/A .name(name() + ".writeReqs") 23749977SN/A .desc("Number of write requests accepted"); 23759831SN/A 23769831SN/A readBursts 23779831SN/A .name(name() + ".readBursts") 23789977SN/A .desc("Number of DRAM read bursts, " 23799977SN/A "including those serviced by the write queue"); 23809831SN/A 23819831SN/A writeBursts 23829831SN/A .name(name() + ".writeBursts") 23839977SN/A .desc("Number of DRAM write bursts, " 23849977SN/A "including those merged in the write queue"); 23859243SN/A 23869243SN/A servicedByWrQ 23879243SN/A .name(name() + ".servicedByWrQ") 23889977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 23899977SN/A 23909977SN/A mergedWrBursts 23919977SN/A .name(name() + ".mergedWrBursts") 23929977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 23939243SN/A 23949243SN/A neitherReadNorWrite 23959977SN/A .name(name() + ".neitherReadNorWriteReqs") 23969977SN/A .desc("Number of requests that are neither read nor write"); 23979243SN/A 23989977SN/A perBankRdBursts 23999243SN/A .init(banksPerRank * ranksPerChannel) 24009977SN/A .name(name() + ".perBankRdBursts") 24019977SN/A .desc("Per bank write bursts"); 24029243SN/A 24039977SN/A perBankWrBursts 24049243SN/A .init(banksPerRank * ranksPerChannel) 24059977SN/A .name(name() + ".perBankWrBursts") 24069977SN/A .desc("Per bank write bursts"); 24079243SN/A 24089243SN/A avgRdQLen 24099243SN/A .name(name() + ".avgRdQLen") 24109977SN/A .desc("Average read queue length when enqueuing") 24119243SN/A .precision(2); 24129243SN/A 24139243SN/A avgWrQLen 24149243SN/A .name(name() + ".avgWrQLen") 24159977SN/A .desc("Average write queue length when enqueuing") 24169243SN/A .precision(2); 24179243SN/A 24189243SN/A totQLat 24199243SN/A .name(name() + ".totQLat") 24209977SN/A .desc("Total ticks spent queuing"); 24219243SN/A 24229243SN/A totBusLat 24239243SN/A .name(name() + ".totBusLat") 24249977SN/A .desc("Total ticks spent in databus transfers"); 24259243SN/A 24269243SN/A totMemAccLat 24279243SN/A .name(name() + ".totMemAccLat") 24289977SN/A .desc("Total ticks spent from burst creation until serviced " 24299977SN/A "by the DRAM"); 24309243SN/A 24319243SN/A avgQLat 24329243SN/A .name(name() + ".avgQLat") 24339977SN/A .desc("Average queueing delay per DRAM burst") 24349243SN/A .precision(2); 24359243SN/A 24369831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 24379243SN/A 24389243SN/A avgBusLat 24399243SN/A .name(name() + ".avgBusLat") 24409977SN/A .desc("Average bus latency per DRAM burst") 24419243SN/A .precision(2); 24429243SN/A 24439831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 24449243SN/A 24459243SN/A avgMemAccLat 24469243SN/A .name(name() + ".avgMemAccLat") 24479977SN/A .desc("Average memory access latency per DRAM burst") 24489243SN/A .precision(2); 24499243SN/A 24509831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 24519243SN/A 24529243SN/A numRdRetry 24539243SN/A .name(name() + ".numRdRetry") 24549977SN/A .desc("Number of times read queue was full causing retry"); 24559243SN/A 24569243SN/A numWrRetry 24579243SN/A .name(name() + ".numWrRetry") 24589977SN/A .desc("Number of times write queue was full causing retry"); 24599243SN/A 24609243SN/A readRowHits 24619243SN/A .name(name() + ".readRowHits") 24629243SN/A .desc("Number of row buffer hits during reads"); 24639243SN/A 24649243SN/A writeRowHits 24659243SN/A .name(name() + ".writeRowHits") 24669243SN/A .desc("Number of row buffer hits during writes"); 24679243SN/A 24689243SN/A readRowHitRate 24699243SN/A .name(name() + ".readRowHitRate") 24709243SN/A .desc("Row buffer hit rate for reads") 24719243SN/A .precision(2); 24729243SN/A 24739831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 24749243SN/A 24759243SN/A writeRowHitRate 24769243SN/A .name(name() + ".writeRowHitRate") 24779243SN/A .desc("Row buffer hit rate for writes") 24789243SN/A .precision(2); 24799243SN/A 24809977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 24819243SN/A 24829243SN/A readPktSize 24839831SN/A .init(ceilLog2(burstSize) + 1) 24849243SN/A .name(name() + ".readPktSize") 24859977SN/A .desc("Read request sizes (log2)"); 24869243SN/A 24879243SN/A writePktSize 24889831SN/A .init(ceilLog2(burstSize) + 1) 24899243SN/A .name(name() + ".writePktSize") 24909977SN/A .desc("Write request sizes (log2)"); 24919243SN/A 24929243SN/A rdQLenPdf 24939567SN/A .init(readBufferSize) 24949243SN/A .name(name() + ".rdQLenPdf") 24959243SN/A .desc("What read queue length does an incoming req see"); 24969243SN/A 24979243SN/A wrQLenPdf 24989567SN/A .init(writeBufferSize) 24999243SN/A .name(name() + ".wrQLenPdf") 25009243SN/A .desc("What write queue length does an incoming req see"); 25019243SN/A 25029727SN/A bytesPerActivate 250310141SN/A .init(maxAccessesPerRow) 25049727SN/A .name(name() + ".bytesPerActivate") 25059727SN/A .desc("Bytes accessed per row activation") 25069727SN/A .flags(nozero); 25079243SN/A 250810147Sandreas.hansson@arm.com rdPerTurnAround 250910147Sandreas.hansson@arm.com .init(readBufferSize) 251010147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 251110147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 251210147Sandreas.hansson@arm.com .flags(nozero); 251310147Sandreas.hansson@arm.com 251410147Sandreas.hansson@arm.com wrPerTurnAround 251510147Sandreas.hansson@arm.com .init(writeBufferSize) 251610147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 251710147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 251810147Sandreas.hansson@arm.com .flags(nozero); 251910147Sandreas.hansson@arm.com 25209975SN/A bytesReadDRAM 25219975SN/A .name(name() + ".bytesReadDRAM") 25229975SN/A .desc("Total number of bytes read from DRAM"); 25239975SN/A 25249975SN/A bytesReadWrQ 25259975SN/A .name(name() + ".bytesReadWrQ") 25269975SN/A .desc("Total number of bytes read from write queue"); 25279243SN/A 25289243SN/A bytesWritten 25299243SN/A .name(name() + ".bytesWritten") 25309977SN/A .desc("Total number of bytes written to DRAM"); 25319243SN/A 25329977SN/A bytesReadSys 25339977SN/A .name(name() + ".bytesReadSys") 25349977SN/A .desc("Total read bytes from the system interface side"); 25359243SN/A 25369977SN/A bytesWrittenSys 25379977SN/A .name(name() + ".bytesWrittenSys") 25389977SN/A .desc("Total written bytes from the system interface side"); 25399243SN/A 25409243SN/A avgRdBW 25419243SN/A .name(name() + ".avgRdBW") 25429977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 25439243SN/A .precision(2); 25449243SN/A 25459977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 25469243SN/A 25479243SN/A avgWrBW 25489243SN/A .name(name() + ".avgWrBW") 25499977SN/A .desc("Average achieved write bandwidth in MiByte/s") 25509243SN/A .precision(2); 25519243SN/A 25529243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 25539243SN/A 25549977SN/A avgRdBWSys 25559977SN/A .name(name() + ".avgRdBWSys") 25569977SN/A .desc("Average system read bandwidth in MiByte/s") 25579243SN/A .precision(2); 25589243SN/A 25599977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 25609243SN/A 25619977SN/A avgWrBWSys 25629977SN/A .name(name() + ".avgWrBWSys") 25639977SN/A .desc("Average system write bandwidth in MiByte/s") 25649243SN/A .precision(2); 25659243SN/A 25669977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 25679243SN/A 25689243SN/A peakBW 25699243SN/A .name(name() + ".peakBW") 25709977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 25719243SN/A .precision(2); 25729243SN/A 25739831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 25749243SN/A 25759243SN/A busUtil 25769243SN/A .name(name() + ".busUtil") 25779243SN/A .desc("Data bus utilization in percentage") 25789243SN/A .precision(2); 25799243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 25809243SN/A 25819243SN/A totGap 25829243SN/A .name(name() + ".totGap") 25839243SN/A .desc("Total gap between requests"); 25849243SN/A 25859243SN/A avgGap 25869243SN/A .name(name() + ".avgGap") 25879243SN/A .desc("Average gap between requests") 25889243SN/A .precision(2); 25899243SN/A 25909243SN/A avgGap = totGap / (readReqs + writeReqs); 25919975SN/A 25929975SN/A // Stats for DRAM Power calculation based on Micron datasheet 25939975SN/A busUtilRead 25949975SN/A .name(name() + ".busUtilRead") 25959975SN/A .desc("Data bus utilization in percentage for reads") 25969975SN/A .precision(2); 25979975SN/A 25989975SN/A busUtilRead = avgRdBW / peakBW * 100; 25999975SN/A 26009975SN/A busUtilWrite 26019975SN/A .name(name() + ".busUtilWrite") 26029975SN/A .desc("Data bus utilization in percentage for writes") 26039975SN/A .precision(2); 26049975SN/A 26059975SN/A busUtilWrite = avgWrBW / peakBW * 100; 26069975SN/A 26079975SN/A pageHitRate 26089975SN/A .name(name() + ".pageHitRate") 26099975SN/A .desc("Row buffer hit rate, read and write combined") 26109975SN/A .precision(2); 26119975SN/A 26129977SN/A pageHitRate = (writeRowHits + readRowHits) / 26139977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 26149243SN/A} 26159243SN/A 26169243SN/Avoid 261710146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 26189243SN/A{ 26199243SN/A // rely on the abstract memory 26209243SN/A functionalAccess(pkt); 26219243SN/A} 26229243SN/A 26239294SN/ABaseSlavePort& 262410146Sandreas.hansson@arm.comDRAMCtrl::getSlavePort(const string &if_name, PortID idx) 26259243SN/A{ 26269243SN/A if (if_name != "port") { 26279243SN/A return MemObject::getSlavePort(if_name, idx); 26289243SN/A } else { 26299243SN/A return port; 26309243SN/A } 26319243SN/A} 26329243SN/A 263310913Sandreas.sandberg@arm.comDrainState 263410913Sandreas.sandberg@arm.comDRAMCtrl::drain() 26359243SN/A{ 26369243SN/A // if there is anything in any of our internal queues, keep track 26379243SN/A // of that as well 263811676Swendy.elsasser@arm.com if (!(writeQueue.empty() && readQueue.empty() && respQueue.empty() && 263911676Swendy.elsasser@arm.com allRanksDrained())) { 264011676Swendy.elsasser@arm.com 26419352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 26429567SN/A " resp: %d\n", writeQueue.size(), readQueue.size(), 26439567SN/A respQueue.size()); 264410206Sandreas.hansson@arm.com 264511678Swendy.elsasser@arm.com // the only queue that is not drained automatically over time 264610206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 264710206Sandreas.hansson@arm.com if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 264810206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 264910206Sandreas.hansson@arm.com } 265011678Swendy.elsasser@arm.com 265111678Swendy.elsasser@arm.com // also need to kick off events to exit self-refresh 265211678Swendy.elsasser@arm.com for (auto r : ranks) { 265311678Swendy.elsasser@arm.com // force self-refresh exit, which in turn will issue auto-refresh 265411678Swendy.elsasser@arm.com if (r->pwrState == PWR_SREF) { 265511678Swendy.elsasser@arm.com DPRINTF(DRAM,"Rank%d: Forcing self-refresh wakeup in drain\n", 265611678Swendy.elsasser@arm.com r->rank); 265711678Swendy.elsasser@arm.com r->scheduleWakeUpEvent(tXS); 265811678Swendy.elsasser@arm.com } 265911678Swendy.elsasser@arm.com } 266011678Swendy.elsasser@arm.com 266110913Sandreas.sandberg@arm.com return DrainState::Draining; 266210912Sandreas.sandberg@arm.com } else { 266310913Sandreas.sandberg@arm.com return DrainState::Drained; 26649243SN/A } 26659243SN/A} 26669243SN/A 266711676Swendy.elsasser@arm.combool 266811676Swendy.elsasser@arm.comDRAMCtrl::allRanksDrained() const 266911676Swendy.elsasser@arm.com{ 267011676Swendy.elsasser@arm.com // true until proven false 267111676Swendy.elsasser@arm.com bool all_ranks_drained = true; 267211676Swendy.elsasser@arm.com for (auto r : ranks) { 267311676Swendy.elsasser@arm.com // then verify that the power state is IDLE 267411676Swendy.elsasser@arm.com // ensuring all banks are closed and rank is not in a low power state 267511676Swendy.elsasser@arm.com all_ranks_drained = r->inPwrIdleState() && all_ranks_drained; 267611676Swendy.elsasser@arm.com } 267711676Swendy.elsasser@arm.com return all_ranks_drained; 267811676Swendy.elsasser@arm.com} 267911676Swendy.elsasser@arm.com 268010619Sandreas.hansson@arm.comvoid 268110619Sandreas.hansson@arm.comDRAMCtrl::drainResume() 268210619Sandreas.hansson@arm.com{ 268310619Sandreas.hansson@arm.com if (!isTimingMode && system()->isTimingMode()) { 268410619Sandreas.hansson@arm.com // if we switched to timing mode, kick things into action, 268510619Sandreas.hansson@arm.com // and behave as if we restored from a checkpoint 268610619Sandreas.hansson@arm.com startup(); 268710619Sandreas.hansson@arm.com } else if (isTimingMode && !system()->isTimingMode()) { 268810619Sandreas.hansson@arm.com // if we switch from timing mode, stop the refresh events to 268910619Sandreas.hansson@arm.com // not cause issues with KVM 269010619Sandreas.hansson@arm.com for (auto r : ranks) { 269110619Sandreas.hansson@arm.com r->suspend(); 269210619Sandreas.hansson@arm.com } 269310619Sandreas.hansson@arm.com } 269410619Sandreas.hansson@arm.com 269510619Sandreas.hansson@arm.com // update the mode 269610619Sandreas.hansson@arm.com isTimingMode = system()->isTimingMode(); 269710619Sandreas.hansson@arm.com} 269810619Sandreas.hansson@arm.com 269910146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 27009243SN/A : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 27019243SN/A memory(_memory) 27029243SN/A{ } 27039243SN/A 27049243SN/AAddrRangeList 270510146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 27069243SN/A{ 27079243SN/A AddrRangeList ranges; 27089243SN/A ranges.push_back(memory.getAddrRange()); 27099243SN/A return ranges; 27109243SN/A} 27119243SN/A 27129243SN/Avoid 271310146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 27149243SN/A{ 27159243SN/A pkt->pushLabel(memory.name()); 27169243SN/A 27179243SN/A if (!queue.checkFunctional(pkt)) { 27189243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 27199243SN/A // calls recvAtomic() and throws away the latency; we can save a 27209243SN/A // little here by just not calculating the latency. 27219243SN/A memory.recvFunctional(pkt); 27229243SN/A } 27239243SN/A 27249243SN/A pkt->popLabel(); 27259243SN/A} 27269243SN/A 27279243SN/ATick 272810146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 27299243SN/A{ 27309243SN/A return memory.recvAtomic(pkt); 27319243SN/A} 27329243SN/A 27339243SN/Abool 273410146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 27359243SN/A{ 27369243SN/A // pass it to the memory controller 27379243SN/A return memory.recvTimingReq(pkt); 27389243SN/A} 27399243SN/A 274010146Sandreas.hansson@arm.comDRAMCtrl* 274110146Sandreas.hansson@arm.comDRAMCtrlParams::create() 27429243SN/A{ 274310146Sandreas.hansson@arm.com return new DRAMCtrl(this); 27449243SN/A} 2745