dram_ctrl.cc revision 11673
19243SN/A/* 210889Sandreas.hansson@arm.com * Copyright (c) 2010-2015 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 4310618SOmar.Naji@arm.com * Omar Naji 449243SN/A */ 459243SN/A 4610146Sandreas.hansson@arm.com#include "base/bitfield.hh" 479356SN/A#include "base/trace.hh" 4810146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 4910247Sandreas.hansson@arm.com#include "debug/DRAMPower.hh" 5010208Sandreas.hansson@arm.com#include "debug/DRAMState.hh" 519352SN/A#include "debug/Drain.hh" 5210146Sandreas.hansson@arm.com#include "mem/dram_ctrl.hh" 539814SN/A#include "sim/system.hh" 549243SN/A 559243SN/Ausing namespace std; 5610432SOmar.Naji@arm.comusing namespace Data; 579243SN/A 5810146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 599243SN/A AbstractMemory(p), 6010619Sandreas.hansson@arm.com port(name() + ".port", *this), isTimingMode(false), 619243SN/A retryRdReq(false), retryWrReq(false), 6210211Sandreas.hansson@arm.com busState(READ), 6310618SOmar.Naji@arm.com nextReqEvent(this), respondEvent(this), 6410489SOmar.Naji@arm.com deviceSize(p->device_size), 659831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 669831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 679831SN/A devicesPerRank(p->devices_per_rank), 689831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 699831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 7010140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 7110646Sandreas.hansson@arm.com columnsPerStripe(range.interleaved() ? range.granularity() / burstSize : 1), 729243SN/A ranksPerChannel(p->ranks_per_channel), 7310394Swendy.elsasser@arm.com bankGroupsPerRank(p->bank_groups_per_rank), 7410394Swendy.elsasser@arm.com bankGroupArch(p->bank_groups_per_rank > 0), 759566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 769243SN/A readBufferSize(p->read_buffer_size), 779243SN/A writeBufferSize(p->write_buffer_size), 7810140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 7910140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 8010147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 8110147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 8210393Swendy.elsasser@arm.com tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST), 8310394Swendy.elsasser@arm.com tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), 8410394Swendy.elsasser@arm.com tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 8511673SOmar.Naji@arm.com tRRD_L(p->tRRD_L), tXAW(p->tXAW), tXP(p->tXP), tXS(p->tXS), 8611673SOmar.Naji@arm.com activationLimit(p->activation_limit), 879243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 889243SN/A pageMgmt(p->page_policy), 8910141SN/A maxAccessesPerRow(p->max_accesses_per_row), 909726SN/A frontendLatency(p->static_frontend_latency), 919726SN/A backendLatency(p->static_backend_latency), 9210618SOmar.Naji@arm.com busBusyUntil(0), prevArrival(0), 9310618SOmar.Naji@arm.com nextReqTime(0), activeRank(0), timeStampOffset(0) 949243SN/A{ 9510620Sandreas.hansson@arm.com // sanity check the ranks since we rely on bit slicing for the 9610620Sandreas.hansson@arm.com // address decoding 9710620Sandreas.hansson@arm.com fatal_if(!isPowerOf2(ranksPerChannel), "DRAM rank count of %d is not " 9810620Sandreas.hansson@arm.com "allowed, must be a power of two\n", ranksPerChannel); 9910620Sandreas.hansson@arm.com 10010889Sandreas.hansson@arm.com fatal_if(!isPowerOf2(burstSize), "DRAM burst size %d is not allowed, " 10110889Sandreas.hansson@arm.com "must be a power of two\n", burstSize); 10210889Sandreas.hansson@arm.com 10310618SOmar.Naji@arm.com for (int i = 0; i < ranksPerChannel; i++) { 10410618SOmar.Naji@arm.com Rank* rank = new Rank(*this, p); 10510618SOmar.Naji@arm.com ranks.push_back(rank); 10610432SOmar.Naji@arm.com 10710618SOmar.Naji@arm.com rank->actTicks.resize(activationLimit, 0); 10810618SOmar.Naji@arm.com rank->banks.resize(banksPerRank); 10910618SOmar.Naji@arm.com rank->rank = i; 11010432SOmar.Naji@arm.com 11110246Sandreas.hansson@arm.com for (int b = 0; b < banksPerRank; b++) { 11210618SOmar.Naji@arm.com rank->banks[b].bank = b; 11310561SOmar.Naji@arm.com // GDDR addressing of banks to BG is linear. 11410561SOmar.Naji@arm.com // Here we assume that all DRAM generations address bank groups as 11510561SOmar.Naji@arm.com // follows: 11610394Swendy.elsasser@arm.com if (bankGroupArch) { 11710394Swendy.elsasser@arm.com // Simply assign lower bits to bank group in order to 11810394Swendy.elsasser@arm.com // rotate across bank groups as banks are incremented 11910394Swendy.elsasser@arm.com // e.g. with 4 banks per bank group and 16 banks total: 12010394Swendy.elsasser@arm.com // banks 0,4,8,12 are in bank group 0 12110394Swendy.elsasser@arm.com // banks 1,5,9,13 are in bank group 1 12210394Swendy.elsasser@arm.com // banks 2,6,10,14 are in bank group 2 12310394Swendy.elsasser@arm.com // banks 3,7,11,15 are in bank group 3 12410618SOmar.Naji@arm.com rank->banks[b].bankgr = b % bankGroupsPerRank; 12510394Swendy.elsasser@arm.com } else { 12610394Swendy.elsasser@arm.com // No bank groups; simply assign to bank number 12710618SOmar.Naji@arm.com rank->banks[b].bankgr = b; 12810394Swendy.elsasser@arm.com } 12910246Sandreas.hansson@arm.com } 13010246Sandreas.hansson@arm.com } 13110246Sandreas.hansson@arm.com 13210140SN/A // perform a basic check of the write thresholds 13310140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 13410140SN/A fatal("Write buffer low threshold %d must be smaller than the " 13510140SN/A "high threshold %d\n", p->write_low_thresh_perc, 13610140SN/A p->write_high_thresh_perc); 1379243SN/A 1389243SN/A // determine the rows per bank by looking at the total capacity 1399567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1409243SN/A 14110489SOmar.Naji@arm.com // determine the dram actual capacity from the DRAM config in Mbytes 14210489SOmar.Naji@arm.com uint64_t deviceCapacity = deviceSize / (1024 * 1024) * devicesPerRank * 14310489SOmar.Naji@arm.com ranksPerChannel; 14410489SOmar.Naji@arm.com 14510489SOmar.Naji@arm.com // if actual DRAM size does not match memory capacity in system warn! 14610489SOmar.Naji@arm.com if (deviceCapacity != capacity / (1024 * 1024)) 14710489SOmar.Naji@arm.com warn("DRAM device capacity (%d Mbytes) does not match the " 14810489SOmar.Naji@arm.com "address range assigned (%d Mbytes)\n", deviceCapacity, 14910489SOmar.Naji@arm.com capacity / (1024 * 1024)); 15010489SOmar.Naji@arm.com 1519243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1529243SN/A AbstractMemory::size()); 1539831SN/A 1549831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1559831SN/A rowBufferSize, columnsPerRowBuffer); 1569831SN/A 1579831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1589243SN/A 15910207Sandreas.hansson@arm.com // some basic sanity checks 16010207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 16110207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 16210207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 16310207Sandreas.hansson@arm.com } 16410394Swendy.elsasser@arm.com 16510394Swendy.elsasser@arm.com // basic bank group architecture checks -> 16610394Swendy.elsasser@arm.com if (bankGroupArch) { 16710394Swendy.elsasser@arm.com // must have at least one bank per bank group 16810394Swendy.elsasser@arm.com if (bankGroupsPerRank > banksPerRank) { 16910394Swendy.elsasser@arm.com fatal("banks per rank (%d) must be equal to or larger than " 17010394Swendy.elsasser@arm.com "banks groups per rank (%d)\n", 17110394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 17210394Swendy.elsasser@arm.com } 17310394Swendy.elsasser@arm.com // must have same number of banks in each bank group 17410394Swendy.elsasser@arm.com if ((banksPerRank % bankGroupsPerRank) != 0) { 17510394Swendy.elsasser@arm.com fatal("Banks per rank (%d) must be evenly divisible by bank groups " 17610394Swendy.elsasser@arm.com "per rank (%d) for equal banks per bank group\n", 17710394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 17810394Swendy.elsasser@arm.com } 17910394Swendy.elsasser@arm.com // tCCD_L should be greater than minimal, back-to-back burst delay 18010394Swendy.elsasser@arm.com if (tCCD_L <= tBURST) { 18110394Swendy.elsasser@arm.com fatal("tCCD_L (%d) should be larger than tBURST (%d) when " 18210394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 18310394Swendy.elsasser@arm.com tCCD_L, tBURST, bankGroupsPerRank); 18410394Swendy.elsasser@arm.com } 18510394Swendy.elsasser@arm.com // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay 18610561SOmar.Naji@arm.com // some datasheets might specify it equal to tRRD 18710561SOmar.Naji@arm.com if (tRRD_L < tRRD) { 18810394Swendy.elsasser@arm.com fatal("tRRD_L (%d) should be larger than tRRD (%d) when " 18910394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 19010394Swendy.elsasser@arm.com tRRD_L, tRRD, bankGroupsPerRank); 19110394Swendy.elsasser@arm.com } 19210394Swendy.elsasser@arm.com } 19310394Swendy.elsasser@arm.com 1949243SN/A} 1959243SN/A 1969243SN/Avoid 19710146Sandreas.hansson@arm.comDRAMCtrl::init() 19810140SN/A{ 19910466Sandreas.hansson@arm.com AbstractMemory::init(); 20010466Sandreas.hansson@arm.com 20110466Sandreas.hansson@arm.com if (!port.isConnected()) { 20210146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 20310140SN/A } else { 20410140SN/A port.sendRangeChange(); 20510140SN/A } 20610646Sandreas.hansson@arm.com 20710646Sandreas.hansson@arm.com // a bit of sanity checks on the interleaving, save it for here to 20810646Sandreas.hansson@arm.com // ensure that the system pointer is initialised 20910646Sandreas.hansson@arm.com if (range.interleaved()) { 21010646Sandreas.hansson@arm.com if (channels != range.stripes()) 21110646Sandreas.hansson@arm.com fatal("%s has %d interleaved address stripes but %d channel(s)\n", 21210646Sandreas.hansson@arm.com name(), range.stripes(), channels); 21310646Sandreas.hansson@arm.com 21410646Sandreas.hansson@arm.com if (addrMapping == Enums::RoRaBaChCo) { 21510646Sandreas.hansson@arm.com if (rowBufferSize != range.granularity()) { 21610646Sandreas.hansson@arm.com fatal("Channel interleaving of %s doesn't match RoRaBaChCo " 21710646Sandreas.hansson@arm.com "address map\n", name()); 21810646Sandreas.hansson@arm.com } 21910646Sandreas.hansson@arm.com } else if (addrMapping == Enums::RoRaBaCoCh || 22010646Sandreas.hansson@arm.com addrMapping == Enums::RoCoRaBaCh) { 22110646Sandreas.hansson@arm.com // for the interleavings with channel bits in the bottom, 22210646Sandreas.hansson@arm.com // if the system uses a channel striping granularity that 22310646Sandreas.hansson@arm.com // is larger than the DRAM burst size, then map the 22410646Sandreas.hansson@arm.com // sequential accesses within a stripe to a number of 22510646Sandreas.hansson@arm.com // columns in the DRAM, effectively placing some of the 22610646Sandreas.hansson@arm.com // lower-order column bits as the least-significant bits 22710646Sandreas.hansson@arm.com // of the address (above the ones denoting the burst size) 22810646Sandreas.hansson@arm.com assert(columnsPerStripe >= 1); 22910646Sandreas.hansson@arm.com 23010646Sandreas.hansson@arm.com // channel striping has to be done at a granularity that 23110646Sandreas.hansson@arm.com // is equal or larger to a cache line 23210646Sandreas.hansson@arm.com if (system()->cacheLineSize() > range.granularity()) { 23310646Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at least as large " 23410646Sandreas.hansson@arm.com "as the cache line size\n", name()); 23510646Sandreas.hansson@arm.com } 23610646Sandreas.hansson@arm.com 23710646Sandreas.hansson@arm.com // ...and equal or smaller than the row-buffer size 23810646Sandreas.hansson@arm.com if (rowBufferSize < range.granularity()) { 23910646Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at most as large " 24010646Sandreas.hansson@arm.com "as the row-buffer size\n", name()); 24110646Sandreas.hansson@arm.com } 24210646Sandreas.hansson@arm.com // this is essentially the check above, so just to be sure 24310646Sandreas.hansson@arm.com assert(columnsPerStripe <= columnsPerRowBuffer); 24410646Sandreas.hansson@arm.com } 24510646Sandreas.hansson@arm.com } 24610140SN/A} 24710140SN/A 24810140SN/Avoid 24910146Sandreas.hansson@arm.comDRAMCtrl::startup() 2509243SN/A{ 25110619Sandreas.hansson@arm.com // remember the memory system mode of operation 25210619Sandreas.hansson@arm.com isTimingMode = system()->isTimingMode(); 25310618SOmar.Naji@arm.com 25410619Sandreas.hansson@arm.com if (isTimingMode) { 25510619Sandreas.hansson@arm.com // timestamp offset should be in clock cycles for DRAMPower 25610619Sandreas.hansson@arm.com timeStampOffset = divCeil(curTick(), tCK); 25710619Sandreas.hansson@arm.com 25810619Sandreas.hansson@arm.com // update the start tick for the precharge accounting to the 25910619Sandreas.hansson@arm.com // current tick 26010619Sandreas.hansson@arm.com for (auto r : ranks) { 26110619Sandreas.hansson@arm.com r->startup(curTick() + tREFI - tRP); 26210619Sandreas.hansson@arm.com } 26310619Sandreas.hansson@arm.com 26410619Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 26510619Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 26610619Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 26710619Sandreas.hansson@arm.com // start of simulation 26810619Sandreas.hansson@arm.com busBusyUntil = curTick() + tRP + tRCD + tCL; 26910618SOmar.Naji@arm.com } 2709243SN/A} 2719243SN/A 2729243SN/ATick 27310146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 2749243SN/A{ 2759243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 2769243SN/A 27711334Sandreas.hansson@arm.com panic_if(pkt->cacheResponding(), "Should not see packets where cache " 27811334Sandreas.hansson@arm.com "is responding"); 27911334Sandreas.hansson@arm.com 2809243SN/A // do the actual memory access and turn the packet into a response 2819243SN/A access(pkt); 2829243SN/A 2839243SN/A Tick latency = 0; 28411334Sandreas.hansson@arm.com if (pkt->hasData()) { 2859243SN/A // this value is not supposed to be accurate, just enough to 2869243SN/A // keep things going, mimic a closed page 2879243SN/A latency = tRP + tRCD + tCL; 2889243SN/A } 2899243SN/A return latency; 2909243SN/A} 2919243SN/A 2929243SN/Abool 29310146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 2949243SN/A{ 2959831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 2969831SN/A readBufferSize, readQueue.size() + respQueue.size(), 2979831SN/A neededEntries); 2989243SN/A 2999831SN/A return 3009831SN/A (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 3019243SN/A} 3029243SN/A 3039243SN/Abool 30410146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 3059243SN/A{ 3069831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 3079831SN/A writeBufferSize, writeQueue.size(), neededEntries); 3089831SN/A return (writeQueue.size() + neededEntries) > writeBufferSize; 3099243SN/A} 3109243SN/A 31110146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 31210146Sandreas.hansson@arm.comDRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 31310143SN/A bool isRead) 3149243SN/A{ 3159669SN/A // decode the address based on the address mapping scheme, with 31610136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 31710136SN/A // channel, respectively 3189243SN/A uint8_t rank; 3199967SN/A uint8_t bank; 32010245Sandreas.hansson@arm.com // use a 64-bit unsigned during the computations as the row is 32110245Sandreas.hansson@arm.com // always the top bits, and check before creating the DRAMPacket 32210245Sandreas.hansson@arm.com uint64_t row; 3239243SN/A 32410286Sandreas.hansson@arm.com // truncate the address to a DRAM burst, which makes it unique to 32510286Sandreas.hansson@arm.com // a specific column, row, bank, rank and channel 3269831SN/A Addr addr = dramPktAddr / burstSize; 3279243SN/A 3289491SN/A // we have removed the lowest order address bits that denote the 3299831SN/A // position within the column 33010136SN/A if (addrMapping == Enums::RoRaBaChCo) { 3319491SN/A // the lowest order bits denote the column to ensure that 3329491SN/A // sequential cache lines occupy the same row 3339831SN/A addr = addr / columnsPerRowBuffer; 3349243SN/A 3359669SN/A // take out the channel part of the address 3369566SN/A addr = addr / channels; 3379566SN/A 3389669SN/A // after the channel bits, get the bank bits to interleave 3399669SN/A // over the banks 3409669SN/A bank = addr % banksPerRank; 3419669SN/A addr = addr / banksPerRank; 3429669SN/A 3439669SN/A // after the bank, we get the rank bits which thus interleaves 3449669SN/A // over the ranks 3459669SN/A rank = addr % ranksPerChannel; 3469669SN/A addr = addr / ranksPerChannel; 3479669SN/A 34811189Sandreas.hansson@arm.com // lastly, get the row bits, no need to remove them from addr 3499669SN/A row = addr % rowsPerBank; 35010136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 35110286Sandreas.hansson@arm.com // take out the lower-order column bits 35210286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 35310286Sandreas.hansson@arm.com 3549669SN/A // take out the channel part of the address 3559669SN/A addr = addr / channels; 3569669SN/A 35710286Sandreas.hansson@arm.com // next, the higher-order column bites 35810286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3599669SN/A 3609669SN/A // after the column bits, we get the bank bits to interleave 3619491SN/A // over the banks 3629243SN/A bank = addr % banksPerRank; 3639243SN/A addr = addr / banksPerRank; 3649243SN/A 3659491SN/A // after the bank, we get the rank bits which thus interleaves 3669491SN/A // over the ranks 3679243SN/A rank = addr % ranksPerChannel; 3689243SN/A addr = addr / ranksPerChannel; 3699243SN/A 37011189Sandreas.hansson@arm.com // lastly, get the row bits, no need to remove them from addr 3719243SN/A row = addr % rowsPerBank; 37210136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 3739491SN/A // optimise for closed page mode and utilise maximum 3749491SN/A // parallelism of the DRAM (at the cost of power) 3759491SN/A 37610286Sandreas.hansson@arm.com // take out the lower-order column bits 37710286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 37810286Sandreas.hansson@arm.com 3799566SN/A // take out the channel part of the address, not that this has 3809566SN/A // to match with how accesses are interleaved between the 3819566SN/A // controllers in the address mapping 3829566SN/A addr = addr / channels; 3839566SN/A 3849491SN/A // start with the bank bits, as this provides the maximum 3859491SN/A // opportunity for parallelism between requests 3869243SN/A bank = addr % banksPerRank; 3879243SN/A addr = addr / banksPerRank; 3889243SN/A 3899491SN/A // next get the rank bits 3909243SN/A rank = addr % ranksPerChannel; 3919243SN/A addr = addr / ranksPerChannel; 3929243SN/A 39310286Sandreas.hansson@arm.com // next, the higher-order column bites 39410286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3959243SN/A 39611189Sandreas.hansson@arm.com // lastly, get the row bits, no need to remove them from addr 3979243SN/A row = addr % rowsPerBank; 3989243SN/A } else 3999243SN/A panic("Unknown address mapping policy chosen!"); 4009243SN/A 4019243SN/A assert(rank < ranksPerChannel); 4029243SN/A assert(bank < banksPerRank); 4039243SN/A assert(row < rowsPerBank); 40410245Sandreas.hansson@arm.com assert(row < Bank::NO_ROW); 4059243SN/A 4069243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 4079831SN/A dramPktAddr, rank, bank, row); 4089243SN/A 4099243SN/A // create the corresponding DRAM packet with the entry time and 4109567SN/A // ready time set to the current tick, the latter will be updated 4119567SN/A // later 4129967SN/A uint16_t bank_id = banksPerRank * rank + bank; 4139967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 41410618SOmar.Naji@arm.com size, ranks[rank]->banks[bank], *ranks[rank]); 4159243SN/A} 4169243SN/A 4179243SN/Avoid 41810146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 4199243SN/A{ 4209243SN/A // only add to the read queue here. whenever the request is 4219243SN/A // eventually done, set the readyTime, and call schedule() 4229243SN/A assert(!pkt->isWrite()); 4239243SN/A 4249831SN/A assert(pktCount != 0); 4259831SN/A 4269831SN/A // if the request size is larger than burst size, the pkt is split into 4279831SN/A // multiple DRAM packets 4289831SN/A // Note if the pkt starting address is not aligened to burst size, the 4299831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 4309831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 4319831SN/A // check read packets against packets in write queue. 4329243SN/A Addr addr = pkt->getAddr(); 4339831SN/A unsigned pktsServicedByWrQ = 0; 4349831SN/A BurstHelper* burst_helper = NULL; 4359831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4369831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4379831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4389831SN/A readPktSize[ceilLog2(size)]++; 4399831SN/A readBursts++; 4409243SN/A 4419831SN/A // First check write buffer to see if the data is already at 4429831SN/A // the controller 4439831SN/A bool foundInWrQ = false; 44410889Sandreas.hansson@arm.com Addr burst_addr = burstAlign(addr); 44510889Sandreas.hansson@arm.com // if the burst address is not present then there is no need 44610889Sandreas.hansson@arm.com // looking any further 44710889Sandreas.hansson@arm.com if (isInWriteQueue.find(burst_addr) != isInWriteQueue.end()) { 44810889Sandreas.hansson@arm.com for (const auto& p : writeQueue) { 44910889Sandreas.hansson@arm.com // check if the read is subsumed in the write queue 45010889Sandreas.hansson@arm.com // packet we are looking at 45110889Sandreas.hansson@arm.com if (p->addr <= addr && (addr + size) <= (p->addr + p->size)) { 45210889Sandreas.hansson@arm.com foundInWrQ = true; 45310889Sandreas.hansson@arm.com servicedByWrQ++; 45410889Sandreas.hansson@arm.com pktsServicedByWrQ++; 45510889Sandreas.hansson@arm.com DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 45610889Sandreas.hansson@arm.com "write queue\n", addr, size); 45710889Sandreas.hansson@arm.com bytesReadWrQ += burstSize; 45810889Sandreas.hansson@arm.com break; 45910889Sandreas.hansson@arm.com } 4609831SN/A } 4619243SN/A } 4629831SN/A 4639831SN/A // If not found in the write q, make a DRAM packet and 4649831SN/A // push it onto the read queue 4659831SN/A if (!foundInWrQ) { 4669831SN/A 4679831SN/A // Make the burst helper for split packets 4689831SN/A if (pktCount > 1 && burst_helper == NULL) { 4699831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 4709831SN/A "dram requests\n", pkt->getAddr(), pktCount); 4719831SN/A burst_helper = new BurstHelper(pktCount); 4729831SN/A } 4739831SN/A 4749966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 4759831SN/A dram_pkt->burstHelper = burst_helper; 4769831SN/A 4779831SN/A assert(!readQueueFull(1)); 4789831SN/A rdQLenPdf[readQueue.size() + respQueue.size()]++; 4799831SN/A 4809831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 4819831SN/A 4829831SN/A readQueue.push_back(dram_pkt); 4839831SN/A 4849831SN/A // Update stats 4859831SN/A avgRdQLen = readQueue.size() + respQueue.size(); 4869831SN/A } 4879831SN/A 4889831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 4899831SN/A addr = (addr | (burstSize - 1)) + 1; 4909243SN/A } 4919243SN/A 4929831SN/A // If all packets are serviced by write queue, we send the repsonse back 4939831SN/A if (pktsServicedByWrQ == pktCount) { 4949831SN/A accessAndRespond(pkt, frontendLatency); 4959831SN/A return; 4969831SN/A } 4979243SN/A 4989831SN/A // Update how many split packets are serviced by write queue 4999831SN/A if (burst_helper != NULL) 5009831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 5019243SN/A 50210206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 50310206Sandreas.hansson@arm.com // queue, do so now 50410206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 5059567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 5069567SN/A schedule(nextReqEvent, curTick()); 5079243SN/A } 5089243SN/A} 5099243SN/A 5109243SN/Avoid 51110146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 5129243SN/A{ 5139243SN/A // only add to the write queue here. whenever the request is 5149243SN/A // eventually done, set the readyTime, and call schedule() 5159243SN/A assert(pkt->isWrite()); 5169243SN/A 5179831SN/A // if the request size is larger than burst size, the pkt is split into 5189831SN/A // multiple DRAM packets 5199831SN/A Addr addr = pkt->getAddr(); 5209831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 5219831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 5229831SN/A pkt->getAddr() + pkt->getSize()) - addr; 5239831SN/A writePktSize[ceilLog2(size)]++; 5249831SN/A writeBursts++; 5259243SN/A 5269832SN/A // see if we can merge with an existing item in the write 52710889Sandreas.hansson@arm.com // queue and keep track of whether we have merged or not 52810889Sandreas.hansson@arm.com bool merged = isInWriteQueue.find(burstAlign(addr)) != 52910889Sandreas.hansson@arm.com isInWriteQueue.end(); 5309243SN/A 5319832SN/A // if the item was not merged we need to create a new write 5329832SN/A // and enqueue it 5339832SN/A if (!merged) { 5349966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 5359243SN/A 5369832SN/A assert(writeQueue.size() < writeBufferSize); 5379832SN/A wrQLenPdf[writeQueue.size()]++; 5389243SN/A 5399832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 5409831SN/A 5419832SN/A writeQueue.push_back(dram_pkt); 54210889Sandreas.hansson@arm.com isInWriteQueue.insert(burstAlign(addr)); 54310889Sandreas.hansson@arm.com assert(writeQueue.size() == isInWriteQueue.size()); 5449831SN/A 5459832SN/A // Update stats 5469832SN/A avgWrQLen = writeQueue.size(); 5479977SN/A } else { 54810889Sandreas.hansson@arm.com DPRINTF(DRAM, "Merging write burst with existing queue entry\n"); 54910889Sandreas.hansson@arm.com 5509977SN/A // keep track of the fact that this burst effectively 5519977SN/A // disappeared as it was merged with an existing one 5529977SN/A mergedWrBursts++; 5539832SN/A } 5549832SN/A 5559831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 5569831SN/A addr = (addr | (burstSize - 1)) + 1; 5579831SN/A } 5589243SN/A 5599243SN/A // we do not wait for the writes to be send to the actual memory, 5609243SN/A // but instead take responsibility for the consistency here and 5619243SN/A // snoop the write queue for any upcoming reads 5629831SN/A // @todo, if a pkt size is larger than burst size, we might need a 5639831SN/A // different front end latency 5649726SN/A accessAndRespond(pkt, frontendLatency); 5659243SN/A 56610206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 56710206Sandreas.hansson@arm.com // queue, do so now 56810206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 56910206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 57010206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 5719243SN/A } 5729243SN/A} 5739243SN/A 5749243SN/Avoid 57510146Sandreas.hansson@arm.comDRAMCtrl::printQs() const { 5769243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 5779833SN/A for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 5789243SN/A DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 5799243SN/A } 5809243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 5819833SN/A for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 5829243SN/A DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 5839243SN/A } 5849243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 5859833SN/A for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 5869243SN/A DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 5879243SN/A } 5889243SN/A} 5899243SN/A 5909243SN/Abool 59110146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 5929243SN/A{ 5939243SN/A // This is where we enter from the outside world 5949567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 5959831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 5969243SN/A 59711334Sandreas.hansson@arm.com panic_if(pkt->cacheResponding(), "Should not see packets where cache " 59811334Sandreas.hansson@arm.com "is responding"); 59911334Sandreas.hansson@arm.com 60011334Sandreas.hansson@arm.com panic_if(!(pkt->isRead() || pkt->isWrite()), 60111334Sandreas.hansson@arm.com "Should only see read and writes at memory controller\n"); 6029243SN/A 6039243SN/A // Calc avg gap between requests 6049243SN/A if (prevArrival != 0) { 6059243SN/A totGap += curTick() - prevArrival; 6069243SN/A } 6079243SN/A prevArrival = curTick(); 6089243SN/A 6099831SN/A 6109831SN/A // Find out how many dram packets a pkt translates to 6119831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 6129831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 6139831SN/A // multiple dram packets 6149243SN/A unsigned size = pkt->getSize(); 6159831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 6169831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 6179243SN/A 6189243SN/A // check local buffers and do not accept if full 6199243SN/A if (pkt->isRead()) { 6209567SN/A assert(size != 0); 6219831SN/A if (readQueueFull(dram_pkt_count)) { 6229567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 6239243SN/A // remember that we have to retry this port 6249243SN/A retryRdReq = true; 6259243SN/A numRdRetry++; 6269243SN/A return false; 6279243SN/A } else { 6289831SN/A addToReadQueue(pkt, dram_pkt_count); 6299243SN/A readReqs++; 6309977SN/A bytesReadSys += size; 6319243SN/A } 63211334Sandreas.hansson@arm.com } else { 63311334Sandreas.hansson@arm.com assert(pkt->isWrite()); 6349567SN/A assert(size != 0); 6359831SN/A if (writeQueueFull(dram_pkt_count)) { 6369567SN/A DPRINTF(DRAM, "Write queue full, not accepting\n"); 6379243SN/A // remember that we have to retry this port 6389243SN/A retryWrReq = true; 6399243SN/A numWrRetry++; 6409243SN/A return false; 6419243SN/A } else { 6429831SN/A addToWriteQueue(pkt, dram_pkt_count); 6439243SN/A writeReqs++; 6449977SN/A bytesWrittenSys += size; 6459243SN/A } 6469243SN/A } 6479243SN/A 6489243SN/A return true; 6499243SN/A} 6509243SN/A 6519243SN/Avoid 65210146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 6539243SN/A{ 6549243SN/A DPRINTF(DRAM, 6559243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 6569243SN/A 6579831SN/A DRAMPacket* dram_pkt = respQueue.front(); 6589243SN/A 6599831SN/A if (dram_pkt->burstHelper) { 6609831SN/A // it is a split packet 6619831SN/A dram_pkt->burstHelper->burstsServiced++; 6629831SN/A if (dram_pkt->burstHelper->burstsServiced == 66310143SN/A dram_pkt->burstHelper->burstCount) { 6649831SN/A // we have now serviced all children packets of a system packet 6659831SN/A // so we can now respond to the requester 6669831SN/A // @todo we probably want to have a different front end and back 6679831SN/A // end latency for split packets 6689831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6699831SN/A delete dram_pkt->burstHelper; 6709831SN/A dram_pkt->burstHelper = NULL; 6719831SN/A } 6729831SN/A } else { 6739831SN/A // it is not a split packet 6749831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6759831SN/A } 6769243SN/A 6779831SN/A delete respQueue.front(); 6789831SN/A respQueue.pop_front(); 6799243SN/A 6809831SN/A if (!respQueue.empty()) { 6819831SN/A assert(respQueue.front()->readyTime >= curTick()); 6829831SN/A assert(!respondEvent.scheduled()); 6839831SN/A schedule(respondEvent, respQueue.front()->readyTime); 6849831SN/A } else { 6859831SN/A // if there is nothing left in any queue, signal a drain 68610913Sandreas.sandberg@arm.com if (drainState() == DrainState::Draining && 68710913Sandreas.sandberg@arm.com writeQueue.empty() && readQueue.empty()) { 68810913Sandreas.sandberg@arm.com 68910509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 69010913Sandreas.sandberg@arm.com signalDrainDone(); 6919831SN/A } 6929831SN/A } 6939567SN/A 6949831SN/A // We have made a location in the queue available at this point, 6959831SN/A // so if there is a read that was forced to wait, retry now 6969831SN/A if (retryRdReq) { 6979831SN/A retryRdReq = false; 69810713Sandreas.hansson@arm.com port.sendRetryReq(); 6999831SN/A } 7009243SN/A} 7019243SN/A 70210618SOmar.Naji@arm.combool 70310890Swendy.elsasser@arm.comDRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay) 7049243SN/A{ 70510206Sandreas.hansson@arm.com // This method does the arbitration between requests. The chosen 70610206Sandreas.hansson@arm.com // packet is simply moved to the head of the queue. The other 70710206Sandreas.hansson@arm.com // methods know that this is the place to look. For example, with 70810206Sandreas.hansson@arm.com // FCFS, this method does nothing 70910206Sandreas.hansson@arm.com assert(!queue.empty()); 7109243SN/A 71110618SOmar.Naji@arm.com // bool to indicate if a packet to an available rank is found 71210618SOmar.Naji@arm.com bool found_packet = false; 71310206Sandreas.hansson@arm.com if (queue.size() == 1) { 71410618SOmar.Naji@arm.com DRAMPacket* dram_pkt = queue.front(); 71510618SOmar.Naji@arm.com // available rank corresponds to state refresh idle 71610618SOmar.Naji@arm.com if (ranks[dram_pkt->rank]->isAvailable()) { 71710618SOmar.Naji@arm.com found_packet = true; 71810618SOmar.Naji@arm.com DPRINTF(DRAM, "Single request, going to a free rank\n"); 71910618SOmar.Naji@arm.com } else { 72010618SOmar.Naji@arm.com DPRINTF(DRAM, "Single request, going to a busy rank\n"); 72110618SOmar.Naji@arm.com } 72210618SOmar.Naji@arm.com return found_packet; 7239243SN/A } 7249243SN/A 7259243SN/A if (memSchedPolicy == Enums::fcfs) { 72610618SOmar.Naji@arm.com // check if there is a packet going to a free rank 72711321Ssteve.reinhardt@amd.com for (auto i = queue.begin(); i != queue.end() ; ++i) { 72810618SOmar.Naji@arm.com DRAMPacket* dram_pkt = *i; 72910618SOmar.Naji@arm.com if (ranks[dram_pkt->rank]->isAvailable()) { 73010618SOmar.Naji@arm.com queue.erase(i); 73110618SOmar.Naji@arm.com queue.push_front(dram_pkt); 73210618SOmar.Naji@arm.com found_packet = true; 73310618SOmar.Naji@arm.com break; 73410618SOmar.Naji@arm.com } 73510618SOmar.Naji@arm.com } 7369243SN/A } else if (memSchedPolicy == Enums::frfcfs) { 73710890Swendy.elsasser@arm.com found_packet = reorderQueue(queue, extra_col_delay); 7389243SN/A } else 7399243SN/A panic("No scheduling policy chosen\n"); 74010618SOmar.Naji@arm.com return found_packet; 7419243SN/A} 7429243SN/A 74310618SOmar.Naji@arm.combool 74410890Swendy.elsasser@arm.comDRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay) 7459974SN/A{ 74610890Swendy.elsasser@arm.com // Only determine this if needed 7479974SN/A uint64_t earliest_banks = 0; 74810890Swendy.elsasser@arm.com bool hidden_bank_prep = false; 7499974SN/A 75010890Swendy.elsasser@arm.com // search for seamless row hits first, if no seamless row hit is 75110890Swendy.elsasser@arm.com // found then determine if there are other packets that can be issued 75210890Swendy.elsasser@arm.com // without incurring additional bus delay due to bank timing 75310890Swendy.elsasser@arm.com // Will select closed rows first to enable more open row possibilies 75410890Swendy.elsasser@arm.com // in future selections 75510890Swendy.elsasser@arm.com bool found_hidden_bank = false; 75610890Swendy.elsasser@arm.com 75710890Swendy.elsasser@arm.com // remember if we found a row hit, not seamless, but bank prepped 75810890Swendy.elsasser@arm.com // and ready 75910890Swendy.elsasser@arm.com bool found_prepped_pkt = false; 76010890Swendy.elsasser@arm.com 76110890Swendy.elsasser@arm.com // if we have no row hit, prepped or not, and no seamless packet, 76210890Swendy.elsasser@arm.com // just go for the earliest possible 7639974SN/A bool found_earliest_pkt = false; 76410890Swendy.elsasser@arm.com 76510618SOmar.Naji@arm.com auto selected_pkt_it = queue.end(); 7669974SN/A 76710890Swendy.elsasser@arm.com // time we need to issue a column command to be seamless 76810890Swendy.elsasser@arm.com const Tick min_col_at = std::max(busBusyUntil - tCL + extra_col_delay, 76910890Swendy.elsasser@arm.com curTick()); 77010890Swendy.elsasser@arm.com 7719974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 7729974SN/A DRAMPacket* dram_pkt = *i; 7739974SN/A const Bank& bank = dram_pkt->bankRef; 77410890Swendy.elsasser@arm.com 77510890Swendy.elsasser@arm.com // check if rank is available, if not, jump to the next packet 77610618SOmar.Naji@arm.com if (dram_pkt->rankRef.isAvailable()) { 77710890Swendy.elsasser@arm.com // check if it is a row hit 77810618SOmar.Naji@arm.com if (bank.openRow == dram_pkt->row) { 77910890Swendy.elsasser@arm.com // no additional rank-to-rank or same bank-group 78010890Swendy.elsasser@arm.com // delays, or we switched read/write and might as well 78110890Swendy.elsasser@arm.com // go for the row hit 78210890Swendy.elsasser@arm.com if (bank.colAllowedAt <= min_col_at) { 78310890Swendy.elsasser@arm.com // FCFS within the hits, giving priority to 78410890Swendy.elsasser@arm.com // commands that can issue seamlessly, without 78510890Swendy.elsasser@arm.com // additional delay, such as same rank accesses 78610890Swendy.elsasser@arm.com // and/or different bank-group accesses 78710890Swendy.elsasser@arm.com DPRINTF(DRAM, "Seamless row buffer hit\n"); 78810618SOmar.Naji@arm.com selected_pkt_it = i; 78910890Swendy.elsasser@arm.com // no need to look through the remaining queue entries 79010618SOmar.Naji@arm.com break; 79110890Swendy.elsasser@arm.com } else if (!found_hidden_bank && !found_prepped_pkt) { 79210890Swendy.elsasser@arm.com // if we did not find a packet to a closed row that can 79310890Swendy.elsasser@arm.com // issue the bank commands without incurring delay, and 79410890Swendy.elsasser@arm.com // did not yet find a packet to a prepped row, remember 79510890Swendy.elsasser@arm.com // the current one 79610618SOmar.Naji@arm.com selected_pkt_it = i; 79710890Swendy.elsasser@arm.com found_prepped_pkt = true; 79810890Swendy.elsasser@arm.com DPRINTF(DRAM, "Prepped row buffer hit\n"); 79910618SOmar.Naji@arm.com } 80010890Swendy.elsasser@arm.com } else if (!found_earliest_pkt) { 80110890Swendy.elsasser@arm.com // if we have not initialised the bank status, do it 80210890Swendy.elsasser@arm.com // now, and only once per scheduling decisions 80310890Swendy.elsasser@arm.com if (earliest_banks == 0) { 80410890Swendy.elsasser@arm.com // determine entries with earliest bank delay 80510890Swendy.elsasser@arm.com pair<uint64_t, bool> bankStatus = 80610890Swendy.elsasser@arm.com minBankPrep(queue, min_col_at); 80710890Swendy.elsasser@arm.com earliest_banks = bankStatus.first; 80810890Swendy.elsasser@arm.com hidden_bank_prep = bankStatus.second; 80910890Swendy.elsasser@arm.com } 81010211Sandreas.hansson@arm.com 81110890Swendy.elsasser@arm.com // bank is amongst first available banks 81210890Swendy.elsasser@arm.com // minBankPrep will give priority to packets that can 81310890Swendy.elsasser@arm.com // issue seamlessly 81410890Swendy.elsasser@arm.com if (bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) { 81510618SOmar.Naji@arm.com found_earliest_pkt = true; 81610890Swendy.elsasser@arm.com found_hidden_bank = hidden_bank_prep; 81710890Swendy.elsasser@arm.com 81810890Swendy.elsasser@arm.com // give priority to packets that can issue 81910890Swendy.elsasser@arm.com // bank commands 'behind the scenes' 82010890Swendy.elsasser@arm.com // any additional delay if any will be due to 82110890Swendy.elsasser@arm.com // col-to-col command requirements 82210890Swendy.elsasser@arm.com if (hidden_bank_prep || !found_prepped_pkt) 82310890Swendy.elsasser@arm.com selected_pkt_it = i; 82410618SOmar.Naji@arm.com } 8259974SN/A } 8269974SN/A } 8279974SN/A } 8289974SN/A 82910618SOmar.Naji@arm.com if (selected_pkt_it != queue.end()) { 83010618SOmar.Naji@arm.com DRAMPacket* selected_pkt = *selected_pkt_it; 83110618SOmar.Naji@arm.com queue.erase(selected_pkt_it); 83210618SOmar.Naji@arm.com queue.push_front(selected_pkt); 83310890Swendy.elsasser@arm.com return true; 83410618SOmar.Naji@arm.com } 83510890Swendy.elsasser@arm.com 83610890Swendy.elsasser@arm.com return false; 8379974SN/A} 8389974SN/A 8399974SN/Avoid 84010146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 8419243SN/A{ 8429243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 8439243SN/A 8449243SN/A bool needsResponse = pkt->needsResponse(); 8459243SN/A // do the actual memory access which also turns the packet into a 8469243SN/A // response 8479243SN/A access(pkt); 8489243SN/A 8499243SN/A // turn packet around to go back to requester if response expected 8509243SN/A if (needsResponse) { 8519243SN/A // access already turned the packet into a response 8529243SN/A assert(pkt->isResponse()); 85310721SMarco.Balboni@ARM.com // response_time consumes the static latency and is charged also 85410721SMarco.Balboni@ARM.com // with headerDelay that takes into account the delay provided by 85510721SMarco.Balboni@ARM.com // the xbar and also the payloadDelay that takes into account the 85610721SMarco.Balboni@ARM.com // number of data beats. 85710721SMarco.Balboni@ARM.com Tick response_time = curTick() + static_latency + pkt->headerDelay + 85810721SMarco.Balboni@ARM.com pkt->payloadDelay; 85910721SMarco.Balboni@ARM.com // Here we reset the timing of the packet before sending it out. 86010694SMarco.Balboni@ARM.com pkt->headerDelay = pkt->payloadDelay = 0; 8619549SN/A 8629726SN/A // queue the packet in the response queue to be sent out after 8639726SN/A // the static latency has passed 86411194Sali.jafri@arm.com port.schedTimingResp(pkt, response_time, true); 8659243SN/A } else { 8669587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 8679587SN/A // is still having a pointer to it 86811190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 8699243SN/A } 8709243SN/A 8719243SN/A DPRINTF(DRAM, "Done\n"); 8729243SN/A 8739243SN/A return; 8749243SN/A} 8759243SN/A 8769243SN/Avoid 87710618SOmar.Naji@arm.comDRAMCtrl::activateBank(Rank& rank_ref, Bank& bank_ref, 87810618SOmar.Naji@arm.com Tick act_tick, uint32_t row) 8799488SN/A{ 88010618SOmar.Naji@arm.com assert(rank_ref.actTicks.size() == activationLimit); 8819488SN/A 8829488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 8839488SN/A 88410207Sandreas.hansson@arm.com // update the open row 88510618SOmar.Naji@arm.com assert(bank_ref.openRow == Bank::NO_ROW); 88610618SOmar.Naji@arm.com bank_ref.openRow = row; 88710207Sandreas.hansson@arm.com 88810207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 88910207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 89010207Sandreas.hansson@arm.com // precharge 89110618SOmar.Naji@arm.com bank_ref.bytesAccessed = 0; 89210618SOmar.Naji@arm.com bank_ref.rowAccesses = 0; 89310207Sandreas.hansson@arm.com 89410618SOmar.Naji@arm.com ++rank_ref.numBanksActive; 89510618SOmar.Naji@arm.com assert(rank_ref.numBanksActive <= banksPerRank); 89610207Sandreas.hansson@arm.com 89710247Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n", 89810618SOmar.Naji@arm.com bank_ref.bank, rank_ref.rank, act_tick, 89910618SOmar.Naji@arm.com ranks[rank_ref.rank]->numBanksActive); 90010247Sandreas.hansson@arm.com 90110618SOmar.Naji@arm.com rank_ref.power.powerlib.doCommand(MemCommand::ACT, bank_ref.bank, 90210618SOmar.Naji@arm.com divCeil(act_tick, tCK) - 90310618SOmar.Naji@arm.com timeStampOffset); 90410432SOmar.Naji@arm.com 90510432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK) - 90610618SOmar.Naji@arm.com timeStampOffset, bank_ref.bank, rank_ref.rank); 9079975SN/A 90810211Sandreas.hansson@arm.com // The next access has to respect tRAS for this bank 90910618SOmar.Naji@arm.com bank_ref.preAllowedAt = act_tick + tRAS; 91010211Sandreas.hansson@arm.com 91110211Sandreas.hansson@arm.com // Respect the row-to-column command delay 91210618SOmar.Naji@arm.com bank_ref.colAllowedAt = std::max(act_tick + tRCD, bank_ref.colAllowedAt); 91310211Sandreas.hansson@arm.com 9149971SN/A // start by enforcing tRRD 91511321Ssteve.reinhardt@amd.com for (int i = 0; i < banksPerRank; i++) { 91610210Sandreas.hansson@arm.com // next activate to any bank in this rank must not happen 91710210Sandreas.hansson@arm.com // before tRRD 91810618SOmar.Naji@arm.com if (bankGroupArch && (bank_ref.bankgr == rank_ref.banks[i].bankgr)) { 91910394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 92010394Swendy.elsasser@arm.com // ACT commands within the same bank group. Use tRRD_L 92110394Swendy.elsasser@arm.com // in this case 92210618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD_L, 92310618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt); 92410394Swendy.elsasser@arm.com } else { 92510394Swendy.elsasser@arm.com // use shorter tRRD value when either 92610394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 92710394Swendy.elsasser@arm.com // 2) bank is in a different bank group 92810618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD, 92910618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt); 93010394Swendy.elsasser@arm.com } 9319971SN/A } 93210208Sandreas.hansson@arm.com 9339971SN/A // next, we deal with tXAW, if the activation limit is disabled 93410492SOmar.Naji@arm.com // then we directly schedule an activate power event 93510618SOmar.Naji@arm.com if (!rank_ref.actTicks.empty()) { 93610492SOmar.Naji@arm.com // sanity check 93710618SOmar.Naji@arm.com if (rank_ref.actTicks.back() && 93810618SOmar.Naji@arm.com (act_tick - rank_ref.actTicks.back()) < tXAW) { 93910492SOmar.Naji@arm.com panic("Got %d activates in window %d (%llu - %llu) which " 94010492SOmar.Naji@arm.com "is smaller than %llu\n", activationLimit, act_tick - 94110618SOmar.Naji@arm.com rank_ref.actTicks.back(), act_tick, 94210618SOmar.Naji@arm.com rank_ref.actTicks.back(), tXAW); 94310492SOmar.Naji@arm.com } 9449824SN/A 94510492SOmar.Naji@arm.com // shift the times used for the book keeping, the last element 94610492SOmar.Naji@arm.com // (highest index) is the oldest one and hence the lowest value 94710618SOmar.Naji@arm.com rank_ref.actTicks.pop_back(); 9489488SN/A 94910492SOmar.Naji@arm.com // record an new activation (in the future) 95010618SOmar.Naji@arm.com rank_ref.actTicks.push_front(act_tick); 9519488SN/A 95210492SOmar.Naji@arm.com // cannot activate more than X times in time window tXAW, push the 95310492SOmar.Naji@arm.com // next one (the X + 1'st activate) to be tXAW away from the 95410492SOmar.Naji@arm.com // oldest in our window of X 95510618SOmar.Naji@arm.com if (rank_ref.actTicks.back() && 95610618SOmar.Naji@arm.com (act_tick - rank_ref.actTicks.back()) < tXAW) { 95710492SOmar.Naji@arm.com DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate " 95810492SOmar.Naji@arm.com "no earlier than %llu\n", activationLimit, 95910618SOmar.Naji@arm.com rank_ref.actTicks.back() + tXAW); 96011321Ssteve.reinhardt@amd.com for (int j = 0; j < banksPerRank; j++) 9619488SN/A // next activate must not happen before end of window 96210618SOmar.Naji@arm.com rank_ref.banks[j].actAllowedAt = 96310618SOmar.Naji@arm.com std::max(rank_ref.actTicks.back() + tXAW, 96410618SOmar.Naji@arm.com rank_ref.banks[j].actAllowedAt); 96510492SOmar.Naji@arm.com } 9669488SN/A } 96710208Sandreas.hansson@arm.com 96810208Sandreas.hansson@arm.com // at the point when this activate takes place, make sure we 96910208Sandreas.hansson@arm.com // transition to the active power state 97010618SOmar.Naji@arm.com if (!rank_ref.activateEvent.scheduled()) 97110618SOmar.Naji@arm.com schedule(rank_ref.activateEvent, act_tick); 97210618SOmar.Naji@arm.com else if (rank_ref.activateEvent.when() > act_tick) 97310208Sandreas.hansson@arm.com // move it sooner in time 97410618SOmar.Naji@arm.com reschedule(rank_ref.activateEvent, act_tick); 97510208Sandreas.hansson@arm.com} 97610208Sandreas.hansson@arm.com 97710208Sandreas.hansson@arm.comvoid 97810618SOmar.Naji@arm.comDRAMCtrl::prechargeBank(Rank& rank_ref, Bank& bank, Tick pre_at, bool trace) 97910207Sandreas.hansson@arm.com{ 98010207Sandreas.hansson@arm.com // make sure the bank has an open row 98110207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 98210207Sandreas.hansson@arm.com 98310207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 98410207Sandreas.hansson@arm.com // the page 98510207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 98610207Sandreas.hansson@arm.com 98710207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 98810207Sandreas.hansson@arm.com 98910214Sandreas.hansson@arm.com // no precharge allowed before this one 99010214Sandreas.hansson@arm.com bank.preAllowedAt = pre_at; 99110214Sandreas.hansson@arm.com 99210211Sandreas.hansson@arm.com Tick pre_done_at = pre_at + tRP; 99310211Sandreas.hansson@arm.com 99410211Sandreas.hansson@arm.com bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at); 99510207Sandreas.hansson@arm.com 99610618SOmar.Naji@arm.com assert(rank_ref.numBanksActive != 0); 99710618SOmar.Naji@arm.com --rank_ref.numBanksActive; 99810207Sandreas.hansson@arm.com 99910247Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got " 100010618SOmar.Naji@arm.com "%d active\n", bank.bank, rank_ref.rank, pre_at, 100110618SOmar.Naji@arm.com rank_ref.numBanksActive); 100210247Sandreas.hansson@arm.com 100310432SOmar.Naji@arm.com if (trace) { 100410207Sandreas.hansson@arm.com 100510618SOmar.Naji@arm.com rank_ref.power.powerlib.doCommand(MemCommand::PRE, bank.bank, 100610432SOmar.Naji@arm.com divCeil(pre_at, tCK) - 100710432SOmar.Naji@arm.com timeStampOffset); 100810432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK) - 100910618SOmar.Naji@arm.com timeStampOffset, bank.bank, rank_ref.rank); 101010432SOmar.Naji@arm.com } 101110208Sandreas.hansson@arm.com // if we look at the current number of active banks we might be 101210208Sandreas.hansson@arm.com // tempted to think the DRAM is now idle, however this can be 101310208Sandreas.hansson@arm.com // undone by an activate that is scheduled to happen before we 101410208Sandreas.hansson@arm.com // would have reached the idle state, so schedule an event and 101510208Sandreas.hansson@arm.com // rather check once we actually make it to the point in time when 101610208Sandreas.hansson@arm.com // the (last) precharge takes place 101710618SOmar.Naji@arm.com if (!rank_ref.prechargeEvent.scheduled()) 101810618SOmar.Naji@arm.com schedule(rank_ref.prechargeEvent, pre_done_at); 101910618SOmar.Naji@arm.com else if (rank_ref.prechargeEvent.when() < pre_done_at) 102010618SOmar.Naji@arm.com reschedule(rank_ref.prechargeEvent, pre_done_at); 102110207Sandreas.hansson@arm.com} 102210207Sandreas.hansson@arm.com 102310207Sandreas.hansson@arm.comvoid 102410146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 10259243SN/A{ 10269243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 10279243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 10289243SN/A 102910618SOmar.Naji@arm.com // get the rank 103010618SOmar.Naji@arm.com Rank& rank = dram_pkt->rankRef; 103110618SOmar.Naji@arm.com 103210211Sandreas.hansson@arm.com // get the bank 10339967SN/A Bank& bank = dram_pkt->bankRef; 10349243SN/A 103510211Sandreas.hansson@arm.com // for the state we need to track if it is a row hit or not 103610211Sandreas.hansson@arm.com bool row_hit = true; 103710211Sandreas.hansson@arm.com 103810211Sandreas.hansson@arm.com // respect any constraints on the command (e.g. tRCD or tCCD) 103910211Sandreas.hansson@arm.com Tick cmd_at = std::max(bank.colAllowedAt, curTick()); 104010211Sandreas.hansson@arm.com 104110211Sandreas.hansson@arm.com // Determine the access latency and update the bank state 104210211Sandreas.hansson@arm.com if (bank.openRow == dram_pkt->row) { 104310211Sandreas.hansson@arm.com // nothing to do 104410209Sandreas.hansson@arm.com } else { 104510211Sandreas.hansson@arm.com row_hit = false; 104610211Sandreas.hansson@arm.com 104710209Sandreas.hansson@arm.com // If there is a page open, precharge it. 104810209Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 104910618SOmar.Naji@arm.com prechargeBank(rank, bank, std::max(bank.preAllowedAt, curTick())); 10509488SN/A } 10519973SN/A 105210211Sandreas.hansson@arm.com // next we need to account for the delay in activating the 105310211Sandreas.hansson@arm.com // page 105410211Sandreas.hansson@arm.com Tick act_tick = std::max(bank.actAllowedAt, curTick()); 10559973SN/A 105610210Sandreas.hansson@arm.com // Record the activation and deal with all the global timing 105710210Sandreas.hansson@arm.com // constraints caused be a new activation (tRRD and tXAW) 105810618SOmar.Naji@arm.com activateBank(rank, bank, act_tick, dram_pkt->row); 105910210Sandreas.hansson@arm.com 106010211Sandreas.hansson@arm.com // issue the command as early as possible 106110211Sandreas.hansson@arm.com cmd_at = bank.colAllowedAt; 106210209Sandreas.hansson@arm.com } 106310209Sandreas.hansson@arm.com 106410211Sandreas.hansson@arm.com // we need to wait until the bus is available before we can issue 106510211Sandreas.hansson@arm.com // the command 106610211Sandreas.hansson@arm.com cmd_at = std::max(cmd_at, busBusyUntil - tCL); 106710211Sandreas.hansson@arm.com 106810211Sandreas.hansson@arm.com // update the packet ready time 106910211Sandreas.hansson@arm.com dram_pkt->readyTime = cmd_at + tCL + tBURST; 107010211Sandreas.hansson@arm.com 107110211Sandreas.hansson@arm.com // only one burst can use the bus at any one point in time 107210211Sandreas.hansson@arm.com assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 107310211Sandreas.hansson@arm.com 107410394Swendy.elsasser@arm.com // update the time for the next read/write burst for each 107510394Swendy.elsasser@arm.com // bank (add a max with tCCD/tCCD_L here) 107610394Swendy.elsasser@arm.com Tick cmd_dly; 107711321Ssteve.reinhardt@amd.com for (int j = 0; j < ranksPerChannel; j++) { 107811321Ssteve.reinhardt@amd.com for (int i = 0; i < banksPerRank; i++) { 107910394Swendy.elsasser@arm.com // next burst to same bank group in this rank must not happen 108010394Swendy.elsasser@arm.com // before tCCD_L. Different bank group timing requirement is 108110394Swendy.elsasser@arm.com // tBURST; Add tCS for different ranks 108210394Swendy.elsasser@arm.com if (dram_pkt->rank == j) { 108310618SOmar.Naji@arm.com if (bankGroupArch && 108410618SOmar.Naji@arm.com (bank.bankgr == ranks[j]->banks[i].bankgr)) { 108510394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 108610394Swendy.elsasser@arm.com // RD/WR burst commands to the same bank group. 108710394Swendy.elsasser@arm.com // Use tCCD_L in this case 108810394Swendy.elsasser@arm.com cmd_dly = tCCD_L; 108910394Swendy.elsasser@arm.com } else { 109010394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), the shorter 109110394Swendy.elsasser@arm.com // cas-to-cas delay value, when either: 109210394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 109310394Swendy.elsasser@arm.com // 2) bank is in a different bank group 109410394Swendy.elsasser@arm.com cmd_dly = tBURST; 109510394Swendy.elsasser@arm.com } 109610394Swendy.elsasser@arm.com } else { 109710394Swendy.elsasser@arm.com // different rank is by default in a different bank group 109810394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), which is the shorter 109910394Swendy.elsasser@arm.com // cas-to-cas delay in this case 110010394Swendy.elsasser@arm.com // Add tCS to account for rank-to-rank bus delay requirements 110110394Swendy.elsasser@arm.com cmd_dly = tBURST + tCS; 110210394Swendy.elsasser@arm.com } 110310618SOmar.Naji@arm.com ranks[j]->banks[i].colAllowedAt = std::max(cmd_at + cmd_dly, 110410618SOmar.Naji@arm.com ranks[j]->banks[i].colAllowedAt); 110510394Swendy.elsasser@arm.com } 110610394Swendy.elsasser@arm.com } 110710211Sandreas.hansson@arm.com 110810393Swendy.elsasser@arm.com // Save rank of current access 110910393Swendy.elsasser@arm.com activeRank = dram_pkt->rank; 111010393Swendy.elsasser@arm.com 111110212Sandreas.hansson@arm.com // If this is a write, we also need to respect the write recovery 111210212Sandreas.hansson@arm.com // time before a precharge, in the case of a read, respect the 111310212Sandreas.hansson@arm.com // read to precharge constraint 111410212Sandreas.hansson@arm.com bank.preAllowedAt = std::max(bank.preAllowedAt, 111510212Sandreas.hansson@arm.com dram_pkt->isRead ? cmd_at + tRTP : 111610212Sandreas.hansson@arm.com dram_pkt->readyTime + tWR); 111710210Sandreas.hansson@arm.com 111810209Sandreas.hansson@arm.com // increment the bytes accessed and the accesses per row 111910209Sandreas.hansson@arm.com bank.bytesAccessed += burstSize; 112010209Sandreas.hansson@arm.com ++bank.rowAccesses; 112110209Sandreas.hansson@arm.com 112210209Sandreas.hansson@arm.com // if we reached the max, then issue with an auto-precharge 112310209Sandreas.hansson@arm.com bool auto_precharge = pageMgmt == Enums::close || 112410209Sandreas.hansson@arm.com bank.rowAccesses == maxAccessesPerRow; 112510209Sandreas.hansson@arm.com 112610209Sandreas.hansson@arm.com // if we did not hit the limit, we might still want to 112710209Sandreas.hansson@arm.com // auto-precharge 112810209Sandreas.hansson@arm.com if (!auto_precharge && 112910209Sandreas.hansson@arm.com (pageMgmt == Enums::open_adaptive || 113010209Sandreas.hansson@arm.com pageMgmt == Enums::close_adaptive)) { 113110209Sandreas.hansson@arm.com // a twist on the open and close page policies: 113210209Sandreas.hansson@arm.com // 1) open_adaptive page policy does not blindly keep the 113310209Sandreas.hansson@arm.com // page open, but close it if there are no row hits, and there 113410209Sandreas.hansson@arm.com // are bank conflicts in the queue 113510209Sandreas.hansson@arm.com // 2) close_adaptive page policy does not blindly close the 113610209Sandreas.hansson@arm.com // page, but closes it only if there are no row hits in the queue. 113710209Sandreas.hansson@arm.com // In this case, only force an auto precharge when there 113810209Sandreas.hansson@arm.com // are no same page hits in the queue 113910209Sandreas.hansson@arm.com bool got_more_hits = false; 114010209Sandreas.hansson@arm.com bool got_bank_conflict = false; 114110209Sandreas.hansson@arm.com 114210209Sandreas.hansson@arm.com // either look at the read queue or write queue 114310209Sandreas.hansson@arm.com const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 114410209Sandreas.hansson@arm.com writeQueue; 114510209Sandreas.hansson@arm.com auto p = queue.begin(); 114610209Sandreas.hansson@arm.com // make sure we are not considering the packet that we are 114710209Sandreas.hansson@arm.com // currently dealing with (which is the head of the queue) 114810209Sandreas.hansson@arm.com ++p; 114910209Sandreas.hansson@arm.com 115010809Srb639@drexel.edu // keep on looking until we find a hit or reach the end of the queue 115110809Srb639@drexel.edu // 1) if a hit is found, then both open and close adaptive policies keep 115210809Srb639@drexel.edu // the page open 115310809Srb639@drexel.edu // 2) if no hit is found, got_bank_conflict is set to true if a bank 115410809Srb639@drexel.edu // conflict request is waiting in the queue 115510809Srb639@drexel.edu while (!got_more_hits && p != queue.end()) { 115610209Sandreas.hansson@arm.com bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 115710209Sandreas.hansson@arm.com (dram_pkt->bank == (*p)->bank); 115810209Sandreas.hansson@arm.com bool same_row = dram_pkt->row == (*p)->row; 115910209Sandreas.hansson@arm.com got_more_hits |= same_rank_bank && same_row; 116010209Sandreas.hansson@arm.com got_bank_conflict |= same_rank_bank && !same_row; 11619973SN/A ++p; 116210141SN/A } 116310141SN/A 116410209Sandreas.hansson@arm.com // auto pre-charge when either 116510209Sandreas.hansson@arm.com // 1) open_adaptive policy, we have not got any more hits, and 116610209Sandreas.hansson@arm.com // have a bank conflict 116710209Sandreas.hansson@arm.com // 2) close_adaptive policy and we have not got any more hits 116810209Sandreas.hansson@arm.com auto_precharge = !got_more_hits && 116910209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive); 117010209Sandreas.hansson@arm.com } 117110142SN/A 117210247Sandreas.hansson@arm.com // DRAMPower trace command to be written 117310247Sandreas.hansson@arm.com std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR"; 117410247Sandreas.hansson@arm.com 117510432SOmar.Naji@arm.com // MemCommand required for DRAMPower library 117610432SOmar.Naji@arm.com MemCommand::cmds command = (mem_cmd == "RD") ? MemCommand::RD : 117710432SOmar.Naji@arm.com MemCommand::WR; 117810432SOmar.Naji@arm.com 117910209Sandreas.hansson@arm.com // if this access should use auto-precharge, then we are 118010209Sandreas.hansson@arm.com // closing the row 118110209Sandreas.hansson@arm.com if (auto_precharge) { 118210432SOmar.Naji@arm.com // if auto-precharge push a PRE command at the correct tick to the 118310432SOmar.Naji@arm.com // list used by DRAMPower library to calculate power 118410618SOmar.Naji@arm.com prechargeBank(rank, bank, std::max(curTick(), bank.preAllowedAt)); 11859973SN/A 118610209Sandreas.hansson@arm.com DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 118710209Sandreas.hansson@arm.com } 11889963SN/A 11899243SN/A // Update bus state 11909243SN/A busBusyUntil = dram_pkt->readyTime; 11919243SN/A 119210211Sandreas.hansson@arm.com DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n", 119310211Sandreas.hansson@arm.com dram_pkt->addr, dram_pkt->readyTime, busBusyUntil); 11949243SN/A 119510618SOmar.Naji@arm.com dram_pkt->rankRef.power.powerlib.doCommand(command, dram_pkt->bank, 119610432SOmar.Naji@arm.com divCeil(cmd_at, tCK) - 119710432SOmar.Naji@arm.com timeStampOffset); 119810432SOmar.Naji@arm.com 119910432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK) - 120010432SOmar.Naji@arm.com timeStampOffset, mem_cmd, dram_pkt->bank, dram_pkt->rank); 120110247Sandreas.hansson@arm.com 120210206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 120310206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 120410206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 120510206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 120610206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 12079972SN/A 120810206Sandreas.hansson@arm.com // Update the stats and schedule the next request 12099977SN/A if (dram_pkt->isRead) { 121010147Sandreas.hansson@arm.com ++readsThisTime; 121110211Sandreas.hansson@arm.com if (row_hit) 12129977SN/A readRowHits++; 12139977SN/A bytesReadDRAM += burstSize; 12149977SN/A perBankRdBursts[dram_pkt->bankId]++; 121510206Sandreas.hansson@arm.com 121610206Sandreas.hansson@arm.com // Update latency stats 121710206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 121810206Sandreas.hansson@arm.com totBusLat += tBURST; 121910211Sandreas.hansson@arm.com totQLat += cmd_at - dram_pkt->entryTime; 12209977SN/A } else { 122110147Sandreas.hansson@arm.com ++writesThisTime; 122210211Sandreas.hansson@arm.com if (row_hit) 12239977SN/A writeRowHits++; 12249977SN/A bytesWritten += burstSize; 12259977SN/A perBankWrBursts[dram_pkt->bankId]++; 12269243SN/A } 12279243SN/A} 12289243SN/A 12299243SN/Avoid 123010206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 12319243SN/A{ 123210618SOmar.Naji@arm.com int busyRanks = 0; 123310618SOmar.Naji@arm.com for (auto r : ranks) { 123410618SOmar.Naji@arm.com if (!r->isAvailable()) { 123510618SOmar.Naji@arm.com // rank is busy refreshing 123610618SOmar.Naji@arm.com busyRanks++; 123710618SOmar.Naji@arm.com 123810618SOmar.Naji@arm.com // let the rank know that if it was waiting to drain, it 123910618SOmar.Naji@arm.com // is now done and ready to proceed 124010618SOmar.Naji@arm.com r->checkDrainDone(); 124110618SOmar.Naji@arm.com } 124210618SOmar.Naji@arm.com } 124310618SOmar.Naji@arm.com 124410618SOmar.Naji@arm.com if (busyRanks == ranksPerChannel) { 124510618SOmar.Naji@arm.com // if all ranks are refreshing wait for them to finish 124610618SOmar.Naji@arm.com // and stall this state machine without taking any further 124710618SOmar.Naji@arm.com // action, and do not schedule a new nextReqEvent 124810618SOmar.Naji@arm.com return; 124910618SOmar.Naji@arm.com } 125010618SOmar.Naji@arm.com 125110393Swendy.elsasser@arm.com // pre-emptively set to false. Overwrite if in READ_TO_WRITE 125210393Swendy.elsasser@arm.com // or WRITE_TO_READ state 125310393Swendy.elsasser@arm.com bool switched_cmd_type = false; 125410206Sandreas.hansson@arm.com if (busState == READ_TO_WRITE) { 125510206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 125610206Sandreas.hansson@arm.com "waiting\n", readsThisTime, readQueue.size()); 12579243SN/A 125810206Sandreas.hansson@arm.com // sample and reset the read-related stats as we are now 125910206Sandreas.hansson@arm.com // transitioning to writes, and all reads are done 126010206Sandreas.hansson@arm.com rdPerTurnAround.sample(readsThisTime); 126110206Sandreas.hansson@arm.com readsThisTime = 0; 126210206Sandreas.hansson@arm.com 126310206Sandreas.hansson@arm.com // now proceed to do the actual writes 126410206Sandreas.hansson@arm.com busState = WRITE; 126510393Swendy.elsasser@arm.com switched_cmd_type = true; 126610206Sandreas.hansson@arm.com } else if (busState == WRITE_TO_READ) { 126710206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 126810206Sandreas.hansson@arm.com "waiting\n", writesThisTime, writeQueue.size()); 126910206Sandreas.hansson@arm.com 127010206Sandreas.hansson@arm.com wrPerTurnAround.sample(writesThisTime); 127110206Sandreas.hansson@arm.com writesThisTime = 0; 127210206Sandreas.hansson@arm.com 127310206Sandreas.hansson@arm.com busState = READ; 127410393Swendy.elsasser@arm.com switched_cmd_type = true; 127510206Sandreas.hansson@arm.com } 127610206Sandreas.hansson@arm.com 127710206Sandreas.hansson@arm.com // when we get here it is either a read or a write 127810206Sandreas.hansson@arm.com if (busState == READ) { 127910206Sandreas.hansson@arm.com 128010206Sandreas.hansson@arm.com // track if we should switch or not 128110206Sandreas.hansson@arm.com bool switch_to_writes = false; 128210206Sandreas.hansson@arm.com 128310206Sandreas.hansson@arm.com if (readQueue.empty()) { 128410206Sandreas.hansson@arm.com // In the case there is no read request to go next, 128510206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 128610206Sandreas.hansson@arm.com // if we are draining) 128710206Sandreas.hansson@arm.com if (!writeQueue.empty() && 128810913Sandreas.sandberg@arm.com (drainState() == DrainState::Draining || 128910913Sandreas.sandberg@arm.com writeQueue.size() > writeLowThreshold)) { 129010206Sandreas.hansson@arm.com 129110206Sandreas.hansson@arm.com switch_to_writes = true; 129210206Sandreas.hansson@arm.com } else { 129310206Sandreas.hansson@arm.com // check if we are drained 129410913Sandreas.sandberg@arm.com if (drainState() == DrainState::Draining && 129510913Sandreas.sandberg@arm.com respQueue.empty()) { 129610913Sandreas.sandberg@arm.com 129710509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 129810913Sandreas.sandberg@arm.com signalDrainDone(); 129910206Sandreas.hansson@arm.com } 130010206Sandreas.hansson@arm.com 130110206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 130210206Sandreas.hansson@arm.com // event for the next request 130310206Sandreas.hansson@arm.com return; 130410206Sandreas.hansson@arm.com } 130510206Sandreas.hansson@arm.com } else { 130610618SOmar.Naji@arm.com // bool to check if there is a read to a free rank 130710618SOmar.Naji@arm.com bool found_read = false; 130810618SOmar.Naji@arm.com 130910206Sandreas.hansson@arm.com // Figure out which read request goes next, and move it to the 131010206Sandreas.hansson@arm.com // front of the read queue 131110890Swendy.elsasser@arm.com // If we are changing command type, incorporate the minimum 131210890Swendy.elsasser@arm.com // bus turnaround delay which will be tCS (different rank) case 131310890Swendy.elsasser@arm.com found_read = chooseNext(readQueue, 131410890Swendy.elsasser@arm.com switched_cmd_type ? tCS : 0); 131510618SOmar.Naji@arm.com 131610618SOmar.Naji@arm.com // if no read to an available rank is found then return 131710618SOmar.Naji@arm.com // at this point. There could be writes to the available ranks 131810618SOmar.Naji@arm.com // which are above the required threshold. However, to 131910618SOmar.Naji@arm.com // avoid adding more complexity to the code, return and wait 132010618SOmar.Naji@arm.com // for a refresh event to kick things into action again. 132110618SOmar.Naji@arm.com if (!found_read) 132210618SOmar.Naji@arm.com return; 132310206Sandreas.hansson@arm.com 132410215Sandreas.hansson@arm.com DRAMPacket* dram_pkt = readQueue.front(); 132510618SOmar.Naji@arm.com assert(dram_pkt->rankRef.isAvailable()); 132610393Swendy.elsasser@arm.com // here we get a bit creative and shift the bus busy time not 132710393Swendy.elsasser@arm.com // just the tWTR, but also a CAS latency to capture the fact 132810393Swendy.elsasser@arm.com // that we are allowed to prepare a new bank, but not issue a 132910393Swendy.elsasser@arm.com // read command until after tWTR, in essence we capture a 133010393Swendy.elsasser@arm.com // bubble on the data bus that is tWTR + tCL 133110394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 133210394Swendy.elsasser@arm.com busBusyUntil += tWTR + tCL; 133310393Swendy.elsasser@arm.com } 133410393Swendy.elsasser@arm.com 133510215Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 133610206Sandreas.hansson@arm.com 133710206Sandreas.hansson@arm.com // At this point we're done dealing with the request 133810215Sandreas.hansson@arm.com readQueue.pop_front(); 133910215Sandreas.hansson@arm.com 134010215Sandreas.hansson@arm.com // sanity check 134110215Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 134210215Sandreas.hansson@arm.com assert(dram_pkt->readyTime >= curTick()); 134310215Sandreas.hansson@arm.com 134410215Sandreas.hansson@arm.com // Insert into response queue. It will be sent back to the 134510215Sandreas.hansson@arm.com // requestor at its readyTime 134610215Sandreas.hansson@arm.com if (respQueue.empty()) { 134710215Sandreas.hansson@arm.com assert(!respondEvent.scheduled()); 134810215Sandreas.hansson@arm.com schedule(respondEvent, dram_pkt->readyTime); 134910215Sandreas.hansson@arm.com } else { 135010215Sandreas.hansson@arm.com assert(respQueue.back()->readyTime <= dram_pkt->readyTime); 135110215Sandreas.hansson@arm.com assert(respondEvent.scheduled()); 135210215Sandreas.hansson@arm.com } 135310215Sandreas.hansson@arm.com 135410215Sandreas.hansson@arm.com respQueue.push_back(dram_pkt); 135510206Sandreas.hansson@arm.com 135610206Sandreas.hansson@arm.com // we have so many writes that we have to transition 135710206Sandreas.hansson@arm.com if (writeQueue.size() > writeHighThreshold) { 135810206Sandreas.hansson@arm.com switch_to_writes = true; 135910206Sandreas.hansson@arm.com } 136010206Sandreas.hansson@arm.com } 136110206Sandreas.hansson@arm.com 136210206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 136310206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 136410206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 136510206Sandreas.hansson@arm.com if (switch_to_writes) { 136610206Sandreas.hansson@arm.com // transition to writing 136710206Sandreas.hansson@arm.com busState = READ_TO_WRITE; 136810206Sandreas.hansson@arm.com } 13699352SN/A } else { 137010618SOmar.Naji@arm.com // bool to check if write to free rank is found 137110618SOmar.Naji@arm.com bool found_write = false; 137210618SOmar.Naji@arm.com 137310890Swendy.elsasser@arm.com // If we are changing command type, incorporate the minimum 137410890Swendy.elsasser@arm.com // bus turnaround delay 137510890Swendy.elsasser@arm.com found_write = chooseNext(writeQueue, 137610890Swendy.elsasser@arm.com switched_cmd_type ? std::min(tRTW, tCS) : 0); 137710618SOmar.Naji@arm.com 137810618SOmar.Naji@arm.com // if no writes to an available rank are found then return. 137910618SOmar.Naji@arm.com // There could be reads to the available ranks. However, to avoid 138010618SOmar.Naji@arm.com // adding more complexity to the code, return at this point and wait 138110618SOmar.Naji@arm.com // for a refresh event to kick things into action again. 138210618SOmar.Naji@arm.com if (!found_write) 138310618SOmar.Naji@arm.com return; 138410618SOmar.Naji@arm.com 138510206Sandreas.hansson@arm.com DRAMPacket* dram_pkt = writeQueue.front(); 138610618SOmar.Naji@arm.com assert(dram_pkt->rankRef.isAvailable()); 138710206Sandreas.hansson@arm.com // sanity check 138810206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 138910393Swendy.elsasser@arm.com 139010394Swendy.elsasser@arm.com // add a bubble to the data bus, as defined by the 139110394Swendy.elsasser@arm.com // tRTW when access is to the same rank as previous burst 139210394Swendy.elsasser@arm.com // Different rank timing is handled with tCS, which is 139310394Swendy.elsasser@arm.com // applied to colAllowedAt 139410394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 139510394Swendy.elsasser@arm.com busBusyUntil += tRTW; 139610393Swendy.elsasser@arm.com } 139710393Swendy.elsasser@arm.com 139810206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 139910206Sandreas.hansson@arm.com 140010206Sandreas.hansson@arm.com writeQueue.pop_front(); 140110889Sandreas.hansson@arm.com isInWriteQueue.erase(burstAlign(dram_pkt->addr)); 140210206Sandreas.hansson@arm.com delete dram_pkt; 140310206Sandreas.hansson@arm.com 140410206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 140510206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 140610206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 140710206Sandreas.hansson@arm.com // writes, then switch to reads. 140810206Sandreas.hansson@arm.com if (writeQueue.empty() || 140910206Sandreas.hansson@arm.com (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 141010913Sandreas.sandberg@arm.com drainState() != DrainState::Draining) || 141110206Sandreas.hansson@arm.com (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 141210206Sandreas.hansson@arm.com // turn the bus back around for reads again 141310206Sandreas.hansson@arm.com busState = WRITE_TO_READ; 141410206Sandreas.hansson@arm.com 141510206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 141610206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 141710206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 141810206Sandreas.hansson@arm.com // nothing to do 141910206Sandreas.hansson@arm.com } 142010206Sandreas.hansson@arm.com } 142110618SOmar.Naji@arm.com // It is possible that a refresh to another rank kicks things back into 142210618SOmar.Naji@arm.com // action before reaching this point. 142310618SOmar.Naji@arm.com if (!nextReqEvent.scheduled()) 142410618SOmar.Naji@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 142510206Sandreas.hansson@arm.com 142610206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 142710206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 142810206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 142910206Sandreas.hansson@arm.com // the next request processing 143010206Sandreas.hansson@arm.com if (retryWrReq && writeQueue.size() < writeBufferSize) { 143110206Sandreas.hansson@arm.com retryWrReq = false; 143210713Sandreas.hansson@arm.com port.sendRetryReq(); 14339352SN/A } 14349243SN/A} 14359243SN/A 143610890Swendy.elsasser@arm.compair<uint64_t, bool> 143710393Swendy.elsasser@arm.comDRAMCtrl::minBankPrep(const deque<DRAMPacket*>& queue, 143810890Swendy.elsasser@arm.com Tick min_col_at) const 14399967SN/A{ 14409967SN/A uint64_t bank_mask = 0; 144110211Sandreas.hansson@arm.com Tick min_act_at = MaxTick; 14429967SN/A 144310890Swendy.elsasser@arm.com // latest Tick for which ACT can occur without incurring additoinal 144410890Swendy.elsasser@arm.com // delay on the data bus 144510890Swendy.elsasser@arm.com const Tick hidden_act_max = std::max(min_col_at - tRCD, curTick()); 144610393Swendy.elsasser@arm.com 144710890Swendy.elsasser@arm.com // Flag condition when burst can issue back-to-back with previous burst 144810890Swendy.elsasser@arm.com bool found_seamless_bank = false; 144910890Swendy.elsasser@arm.com 145010890Swendy.elsasser@arm.com // Flag condition when bank can be opened without incurring additional 145110890Swendy.elsasser@arm.com // delay on the data bus 145210890Swendy.elsasser@arm.com bool hidden_bank_prep = false; 145310393Swendy.elsasser@arm.com 145410393Swendy.elsasser@arm.com // determine if we have queued transactions targetting the 14559967SN/A // bank in question 14569967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 145710618SOmar.Naji@arm.com for (const auto& p : queue) { 145811321Ssteve.reinhardt@amd.com if (p->rankRef.isAvailable()) 145910618SOmar.Naji@arm.com got_waiting[p->bankId] = true; 14609967SN/A } 14619967SN/A 146210890Swendy.elsasser@arm.com // Find command with optimal bank timing 146310890Swendy.elsasser@arm.com // Will prioritize commands that can issue seamlessly. 14649967SN/A for (int i = 0; i < ranksPerChannel; i++) { 14659967SN/A for (int j = 0; j < banksPerRank; j++) { 146610618SOmar.Naji@arm.com uint16_t bank_id = i * banksPerRank + j; 146710211Sandreas.hansson@arm.com 14689967SN/A // if we have waiting requests for the bank, and it is 14699967SN/A // amongst the first available, update the mask 147010211Sandreas.hansson@arm.com if (got_waiting[bank_id]) { 147110618SOmar.Naji@arm.com // make sure this rank is not currently refreshing. 147210618SOmar.Naji@arm.com assert(ranks[i]->isAvailable()); 147310211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue 147410211Sandreas.hansson@arm.com // an activate, ignoring any rank-to-rank switching 147510393Swendy.elsasser@arm.com // cost in this calculation 147610618SOmar.Naji@arm.com Tick act_at = ranks[i]->banks[j].openRow == Bank::NO_ROW ? 147710890Swendy.elsasser@arm.com std::max(ranks[i]->banks[j].actAllowedAt, curTick()) : 147810618SOmar.Naji@arm.com std::max(ranks[i]->banks[j].preAllowedAt, curTick()) + tRP; 147910211Sandreas.hansson@arm.com 148010890Swendy.elsasser@arm.com // When is the earliest the R/W burst can issue? 148110890Swendy.elsasser@arm.com Tick col_at = std::max(ranks[i]->banks[j].colAllowedAt, 148210890Swendy.elsasser@arm.com act_at + tRCD); 148310393Swendy.elsasser@arm.com 148410890Swendy.elsasser@arm.com // bank can issue burst back-to-back (seamlessly) with 148510890Swendy.elsasser@arm.com // previous burst 148610890Swendy.elsasser@arm.com bool new_seamless_bank = col_at <= min_col_at; 148710393Swendy.elsasser@arm.com 148810890Swendy.elsasser@arm.com // if we found a new seamless bank or we have no 148910890Swendy.elsasser@arm.com // seamless banks, and got a bank with an earlier 149010890Swendy.elsasser@arm.com // activate time, it should be added to the bit mask 149110890Swendy.elsasser@arm.com if (new_seamless_bank || 149210890Swendy.elsasser@arm.com (!found_seamless_bank && act_at <= min_act_at)) { 149310890Swendy.elsasser@arm.com // if we did not have a seamless bank before, and 149410890Swendy.elsasser@arm.com // we do now, reset the bank mask, also reset it 149510890Swendy.elsasser@arm.com // if we have not yet found a seamless bank and 149610890Swendy.elsasser@arm.com // the activate time is smaller than what we have 149710890Swendy.elsasser@arm.com // seen so far 149810890Swendy.elsasser@arm.com if (!found_seamless_bank && 149910890Swendy.elsasser@arm.com (new_seamless_bank || act_at < min_act_at)) { 150010890Swendy.elsasser@arm.com bank_mask = 0; 150110393Swendy.elsasser@arm.com } 150210890Swendy.elsasser@arm.com 150310890Swendy.elsasser@arm.com found_seamless_bank |= new_seamless_bank; 150410890Swendy.elsasser@arm.com 150510890Swendy.elsasser@arm.com // ACT can occur 'behind the scenes' 150610890Swendy.elsasser@arm.com hidden_bank_prep = act_at <= hidden_act_max; 150710890Swendy.elsasser@arm.com 150810890Swendy.elsasser@arm.com // set the bit corresponding to the available bank 150910890Swendy.elsasser@arm.com replaceBits(bank_mask, bank_id, bank_id, 1); 151010890Swendy.elsasser@arm.com min_act_at = act_at; 151110211Sandreas.hansson@arm.com } 15129967SN/A } 15139967SN/A } 15149967SN/A } 151510211Sandreas.hansson@arm.com 151610890Swendy.elsasser@arm.com return make_pair(bank_mask, hidden_bank_prep); 15179967SN/A} 15189967SN/A 151910618SOmar.Naji@arm.comDRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p) 152010618SOmar.Naji@arm.com : EventManager(&_memory), memory(_memory), 152110618SOmar.Naji@arm.com pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), pwrStateTick(0), 152210618SOmar.Naji@arm.com refreshState(REF_IDLE), refreshDueAt(0), 152310618SOmar.Naji@arm.com power(_p, false), numBanksActive(0), 152410618SOmar.Naji@arm.com activateEvent(*this), prechargeEvent(*this), 152510618SOmar.Naji@arm.com refreshEvent(*this), powerEvent(*this) 152610618SOmar.Naji@arm.com{ } 152710618SOmar.Naji@arm.com 15289243SN/Avoid 152910618SOmar.Naji@arm.comDRAMCtrl::Rank::startup(Tick ref_tick) 153010618SOmar.Naji@arm.com{ 153110618SOmar.Naji@arm.com assert(ref_tick > curTick()); 153210618SOmar.Naji@arm.com 153310618SOmar.Naji@arm.com pwrStateTick = curTick(); 153410618SOmar.Naji@arm.com 153510618SOmar.Naji@arm.com // kick off the refresh, and give ourselves enough time to 153610618SOmar.Naji@arm.com // precharge 153710618SOmar.Naji@arm.com schedule(refreshEvent, ref_tick); 153810618SOmar.Naji@arm.com} 153910618SOmar.Naji@arm.com 154010618SOmar.Naji@arm.comvoid 154110619Sandreas.hansson@arm.comDRAMCtrl::Rank::suspend() 154210619Sandreas.hansson@arm.com{ 154310619Sandreas.hansson@arm.com deschedule(refreshEvent); 154410619Sandreas.hansson@arm.com} 154510619Sandreas.hansson@arm.com 154610619Sandreas.hansson@arm.comvoid 154710618SOmar.Naji@arm.comDRAMCtrl::Rank::checkDrainDone() 154810618SOmar.Naji@arm.com{ 154910618SOmar.Naji@arm.com // if this rank was waiting to drain it is now able to proceed to 155010618SOmar.Naji@arm.com // precharge 155110618SOmar.Naji@arm.com if (refreshState == REF_DRAIN) { 155210618SOmar.Naji@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 155310618SOmar.Naji@arm.com 155410618SOmar.Naji@arm.com refreshState = REF_PRE; 155510618SOmar.Naji@arm.com 155610618SOmar.Naji@arm.com // hand control back to the refresh event loop 155710618SOmar.Naji@arm.com schedule(refreshEvent, curTick()); 155810618SOmar.Naji@arm.com } 155910618SOmar.Naji@arm.com} 156010618SOmar.Naji@arm.com 156110618SOmar.Naji@arm.comvoid 156210618SOmar.Naji@arm.comDRAMCtrl::Rank::processActivateEvent() 156310618SOmar.Naji@arm.com{ 156410618SOmar.Naji@arm.com // we should transition to the active state as soon as any bank is active 156510618SOmar.Naji@arm.com if (pwrState != PWR_ACT) 156610618SOmar.Naji@arm.com // note that at this point numBanksActive could be back at 156710618SOmar.Naji@arm.com // zero again due to a precharge scheduled in the future 156810618SOmar.Naji@arm.com schedulePowerEvent(PWR_ACT, curTick()); 156910618SOmar.Naji@arm.com} 157010618SOmar.Naji@arm.com 157110618SOmar.Naji@arm.comvoid 157210618SOmar.Naji@arm.comDRAMCtrl::Rank::processPrechargeEvent() 157310618SOmar.Naji@arm.com{ 157410618SOmar.Naji@arm.com // if we reached zero, then special conditions apply as we track 157510618SOmar.Naji@arm.com // if all banks are precharged for the power models 157610618SOmar.Naji@arm.com if (numBanksActive == 0) { 157710618SOmar.Naji@arm.com // we should transition to the idle state when the last bank 157810618SOmar.Naji@arm.com // is precharged 157910618SOmar.Naji@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 158010618SOmar.Naji@arm.com } 158110618SOmar.Naji@arm.com} 158210618SOmar.Naji@arm.com 158310618SOmar.Naji@arm.comvoid 158410618SOmar.Naji@arm.comDRAMCtrl::Rank::processRefreshEvent() 15859243SN/A{ 158610207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 158710207Sandreas.hansson@arm.com if (refreshState == REF_IDLE) { 158810207Sandreas.hansson@arm.com // remember when the refresh is due 158910207Sandreas.hansson@arm.com refreshDueAt = curTick(); 15909243SN/A 159110207Sandreas.hansson@arm.com // proceed to drain 159210207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 15939243SN/A 159410207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 159510207Sandreas.hansson@arm.com } 159610207Sandreas.hansson@arm.com 159710618SOmar.Naji@arm.com // let any scheduled read or write to the same rank go ahead, 159810618SOmar.Naji@arm.com // after which it will 159910207Sandreas.hansson@arm.com // hand control back to this event loop 160010207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 160110618SOmar.Naji@arm.com // if a request is at the moment being handled and this request is 160210618SOmar.Naji@arm.com // accessing the current rank then wait for it to finish 160310618SOmar.Naji@arm.com if ((rank == memory.activeRank) 160410618SOmar.Naji@arm.com && (memory.nextReqEvent.scheduled())) { 160510207Sandreas.hansson@arm.com // hand control over to the request loop until it is 160610207Sandreas.hansson@arm.com // evaluated next 160710207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 160810207Sandreas.hansson@arm.com 160910207Sandreas.hansson@arm.com return; 161010207Sandreas.hansson@arm.com } else { 161110207Sandreas.hansson@arm.com refreshState = REF_PRE; 161210207Sandreas.hansson@arm.com } 161310207Sandreas.hansson@arm.com } 161410207Sandreas.hansson@arm.com 161510207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 161610207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 161710208Sandreas.hansson@arm.com // precharge any active bank if we are not already in the idle 161810208Sandreas.hansson@arm.com // state 161910208Sandreas.hansson@arm.com if (pwrState != PWR_IDLE) { 162010214Sandreas.hansson@arm.com // at the moment, we use a precharge all even if there is 162110214Sandreas.hansson@arm.com // only a single bank open 162210208Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 162310214Sandreas.hansson@arm.com 162410214Sandreas.hansson@arm.com // first determine when we can precharge 162510214Sandreas.hansson@arm.com Tick pre_at = curTick(); 162610618SOmar.Naji@arm.com 162710618SOmar.Naji@arm.com for (auto &b : banks) { 162810618SOmar.Naji@arm.com // respect both causality and any existing bank 162910618SOmar.Naji@arm.com // constraints, some banks could already have a 163010618SOmar.Naji@arm.com // (auto) precharge scheduled 163110618SOmar.Naji@arm.com pre_at = std::max(b.preAllowedAt, pre_at); 163210618SOmar.Naji@arm.com } 163310618SOmar.Naji@arm.com 163410618SOmar.Naji@arm.com // make sure all banks per rank are precharged, and for those that 163510618SOmar.Naji@arm.com // already are, update their availability 163610618SOmar.Naji@arm.com Tick act_allowed_at = pre_at + memory.tRP; 163710618SOmar.Naji@arm.com 163810618SOmar.Naji@arm.com for (auto &b : banks) { 163910618SOmar.Naji@arm.com if (b.openRow != Bank::NO_ROW) { 164010618SOmar.Naji@arm.com memory.prechargeBank(*this, b, pre_at, false); 164110618SOmar.Naji@arm.com } else { 164210618SOmar.Naji@arm.com b.actAllowedAt = std::max(b.actAllowedAt, act_allowed_at); 164310618SOmar.Naji@arm.com b.preAllowedAt = std::max(b.preAllowedAt, pre_at); 164410214Sandreas.hansson@arm.com } 164510214Sandreas.hansson@arm.com } 164610214Sandreas.hansson@arm.com 164710618SOmar.Naji@arm.com // precharge all banks in rank 164810618SOmar.Naji@arm.com power.powerlib.doCommand(MemCommand::PREA, 0, 164910618SOmar.Naji@arm.com divCeil(pre_at, memory.tCK) - 165010618SOmar.Naji@arm.com memory.timeStampOffset); 165110214Sandreas.hansson@arm.com 165210618SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PREA,0,%d\n", 165310618SOmar.Naji@arm.com divCeil(pre_at, memory.tCK) - 165410618SOmar.Naji@arm.com memory.timeStampOffset, rank); 165510208Sandreas.hansson@arm.com } else { 165610208Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 165710208Sandreas.hansson@arm.com 165810208Sandreas.hansson@arm.com // go ahead and kick the power state machine into gear if 165910208Sandreas.hansson@arm.com // we are already idle 166010208Sandreas.hansson@arm.com schedulePowerEvent(PWR_REF, curTick()); 16619975SN/A } 16629975SN/A 166310208Sandreas.hansson@arm.com refreshState = REF_RUN; 166410208Sandreas.hansson@arm.com assert(numBanksActive == 0); 16659243SN/A 166610208Sandreas.hansson@arm.com // wait for all banks to be precharged, at which point the 166710208Sandreas.hansson@arm.com // power state machine will transition to the idle state, and 166810208Sandreas.hansson@arm.com // automatically move to a refresh, at that point it will also 166910208Sandreas.hansson@arm.com // call this method to get the refresh event loop going again 167010207Sandreas.hansson@arm.com return; 167110207Sandreas.hansson@arm.com } 167210207Sandreas.hansson@arm.com 167310207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 167410207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 167510207Sandreas.hansson@arm.com // should never get here with any banks active 167610207Sandreas.hansson@arm.com assert(numBanksActive == 0); 167710208Sandreas.hansson@arm.com assert(pwrState == PWR_REF); 167810207Sandreas.hansson@arm.com 167910618SOmar.Naji@arm.com Tick ref_done_at = curTick() + memory.tRFC; 168010207Sandreas.hansson@arm.com 168110618SOmar.Naji@arm.com for (auto &b : banks) { 168210618SOmar.Naji@arm.com b.actAllowedAt = ref_done_at; 168310618SOmar.Naji@arm.com } 168410247Sandreas.hansson@arm.com 168510618SOmar.Naji@arm.com // at the moment this affects all ranks 168610618SOmar.Naji@arm.com power.powerlib.doCommand(MemCommand::REF, 0, 168710618SOmar.Naji@arm.com divCeil(curTick(), memory.tCK) - 168810618SOmar.Naji@arm.com memory.timeStampOffset); 168910432SOmar.Naji@arm.com 169010618SOmar.Naji@arm.com // at the moment sort the list of commands and update the counters 169110618SOmar.Naji@arm.com // for DRAMPower libray when doing a refresh 169210618SOmar.Naji@arm.com sort(power.powerlib.cmdList.begin(), 169310618SOmar.Naji@arm.com power.powerlib.cmdList.end(), DRAMCtrl::sortTime); 169410432SOmar.Naji@arm.com 169510618SOmar.Naji@arm.com // update the counters for DRAMPower, passing false to 169610618SOmar.Naji@arm.com // indicate that this is not the last command in the 169710618SOmar.Naji@arm.com // list. DRAMPower requires this information for the 169810618SOmar.Naji@arm.com // correct calculation of the background energy at the end 169910618SOmar.Naji@arm.com // of the simulation. Ideally we would want to call this 170010618SOmar.Naji@arm.com // function with true once at the end of the 170110618SOmar.Naji@arm.com // simulation. However, the discarded energy is extremly 170210618SOmar.Naji@arm.com // small and does not effect the final results. 170310618SOmar.Naji@arm.com power.powerlib.updateCounters(false); 170410432SOmar.Naji@arm.com 170510618SOmar.Naji@arm.com // call the energy function 170610618SOmar.Naji@arm.com power.powerlib.calcEnergy(); 170710432SOmar.Naji@arm.com 170810618SOmar.Naji@arm.com // Update the stats 170910618SOmar.Naji@arm.com updatePowerStats(); 171010432SOmar.Naji@arm.com 171110618SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), memory.tCK) - 171210618SOmar.Naji@arm.com memory.timeStampOffset, rank); 171310207Sandreas.hansson@arm.com 171410207Sandreas.hansson@arm.com // make sure we did not wait so long that we cannot make up 171510207Sandreas.hansson@arm.com // for it 171610618SOmar.Naji@arm.com if (refreshDueAt + memory.tREFI < ref_done_at) { 171710207Sandreas.hansson@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 171810207Sandreas.hansson@arm.com } 171910207Sandreas.hansson@arm.com 172010207Sandreas.hansson@arm.com // compensate for the delay in actually performing the refresh 172110207Sandreas.hansson@arm.com // when scheduling the next one 172210618SOmar.Naji@arm.com schedule(refreshEvent, refreshDueAt + memory.tREFI - memory.tRP); 172310207Sandreas.hansson@arm.com 172410208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 172510207Sandreas.hansson@arm.com 172610208Sandreas.hansson@arm.com // move to the idle power state once the refresh is done, this 172710208Sandreas.hansson@arm.com // will also move the refresh state machine to the refresh 172810208Sandreas.hansson@arm.com // idle state 172910211Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, ref_done_at); 173010207Sandreas.hansson@arm.com 173110208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n", 173210618SOmar.Naji@arm.com ref_done_at, refreshDueAt + memory.tREFI); 173310208Sandreas.hansson@arm.com } 173410208Sandreas.hansson@arm.com} 173510208Sandreas.hansson@arm.com 173610208Sandreas.hansson@arm.comvoid 173710618SOmar.Naji@arm.comDRAMCtrl::Rank::schedulePowerEvent(PowerState pwr_state, Tick tick) 173810208Sandreas.hansson@arm.com{ 173910208Sandreas.hansson@arm.com // respect causality 174010208Sandreas.hansson@arm.com assert(tick >= curTick()); 174110208Sandreas.hansson@arm.com 174210208Sandreas.hansson@arm.com if (!powerEvent.scheduled()) { 174310208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 174410208Sandreas.hansson@arm.com tick, pwr_state); 174510208Sandreas.hansson@arm.com 174610208Sandreas.hansson@arm.com // insert the new transition 174710208Sandreas.hansson@arm.com pwrStateTrans = pwr_state; 174810208Sandreas.hansson@arm.com 174910208Sandreas.hansson@arm.com schedule(powerEvent, tick); 175010208Sandreas.hansson@arm.com } else { 175110208Sandreas.hansson@arm.com panic("Scheduled power event at %llu to state %d, " 175210208Sandreas.hansson@arm.com "with scheduled event at %llu to %d\n", tick, pwr_state, 175310208Sandreas.hansson@arm.com powerEvent.when(), pwrStateTrans); 175410208Sandreas.hansson@arm.com } 175510208Sandreas.hansson@arm.com} 175610208Sandreas.hansson@arm.com 175710208Sandreas.hansson@arm.comvoid 175810618SOmar.Naji@arm.comDRAMCtrl::Rank::processPowerEvent() 175910208Sandreas.hansson@arm.com{ 176010208Sandreas.hansson@arm.com // remember where we were, and for how long 176110208Sandreas.hansson@arm.com Tick duration = curTick() - pwrStateTick; 176210208Sandreas.hansson@arm.com PowerState prev_state = pwrState; 176310208Sandreas.hansson@arm.com 176410208Sandreas.hansson@arm.com // update the accounting 176510208Sandreas.hansson@arm.com pwrStateTime[prev_state] += duration; 176610208Sandreas.hansson@arm.com 176710208Sandreas.hansson@arm.com pwrState = pwrStateTrans; 176810208Sandreas.hansson@arm.com pwrStateTick = curTick(); 176910208Sandreas.hansson@arm.com 177010208Sandreas.hansson@arm.com if (pwrState == PWR_IDLE) { 177110208Sandreas.hansson@arm.com DPRINTF(DRAMState, "All banks precharged\n"); 177210208Sandreas.hansson@arm.com 177310208Sandreas.hansson@arm.com // if we were refreshing, make sure we start scheduling requests again 177410208Sandreas.hansson@arm.com if (prev_state == PWR_REF) { 177510208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 177610208Sandreas.hansson@arm.com assert(pwrState == PWR_IDLE); 177710208Sandreas.hansson@arm.com 177810208Sandreas.hansson@arm.com // kick things into action again 177910208Sandreas.hansson@arm.com refreshState = REF_IDLE; 178010618SOmar.Naji@arm.com // a request event could be already scheduled by the state 178110618SOmar.Naji@arm.com // machine of the other rank 178210618SOmar.Naji@arm.com if (!memory.nextReqEvent.scheduled()) 178310618SOmar.Naji@arm.com schedule(memory.nextReqEvent, curTick()); 178410208Sandreas.hansson@arm.com } else { 178510208Sandreas.hansson@arm.com assert(prev_state == PWR_ACT); 178610208Sandreas.hansson@arm.com 178710208Sandreas.hansson@arm.com // if we have a pending refresh, and are now moving to 178810208Sandreas.hansson@arm.com // the idle state, direclty transition to a refresh 178910208Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 179010208Sandreas.hansson@arm.com // there should be nothing waiting at this point 179110208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 179210208Sandreas.hansson@arm.com 179310208Sandreas.hansson@arm.com // update the state in zero time and proceed below 179410208Sandreas.hansson@arm.com pwrState = PWR_REF; 179510208Sandreas.hansson@arm.com } 179610208Sandreas.hansson@arm.com } 179710208Sandreas.hansson@arm.com } 179810208Sandreas.hansson@arm.com 179910208Sandreas.hansson@arm.com // we transition to the refresh state, let the refresh state 180010208Sandreas.hansson@arm.com // machine know of this state update and let it deal with the 180110208Sandreas.hansson@arm.com // scheduling of the next power state transition as well as the 180210208Sandreas.hansson@arm.com // following refresh 180310208Sandreas.hansson@arm.com if (pwrState == PWR_REF) { 180410208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refreshing\n"); 180510208Sandreas.hansson@arm.com // kick the refresh event loop into action again, and that 180610208Sandreas.hansson@arm.com // in turn will schedule a transition to the idle power 180710208Sandreas.hansson@arm.com // state once the refresh is done 180810208Sandreas.hansson@arm.com assert(refreshState == REF_RUN); 180910208Sandreas.hansson@arm.com processRefreshEvent(); 181010207Sandreas.hansson@arm.com } 18119243SN/A} 18129243SN/A 18139243SN/Avoid 181410618SOmar.Naji@arm.comDRAMCtrl::Rank::updatePowerStats() 181510432SOmar.Naji@arm.com{ 181610432SOmar.Naji@arm.com // Get the energy and power from DRAMPower 181710432SOmar.Naji@arm.com Data::MemoryPowerModel::Energy energy = 181810618SOmar.Naji@arm.com power.powerlib.getEnergy(); 181910618SOmar.Naji@arm.com Data::MemoryPowerModel::Power rank_power = 182010618SOmar.Naji@arm.com power.powerlib.getPower(); 182110432SOmar.Naji@arm.com 182210618SOmar.Naji@arm.com actEnergy = energy.act_energy * memory.devicesPerRank; 182310618SOmar.Naji@arm.com preEnergy = energy.pre_energy * memory.devicesPerRank; 182410618SOmar.Naji@arm.com readEnergy = energy.read_energy * memory.devicesPerRank; 182510618SOmar.Naji@arm.com writeEnergy = energy.write_energy * memory.devicesPerRank; 182610618SOmar.Naji@arm.com refreshEnergy = energy.ref_energy * memory.devicesPerRank; 182710618SOmar.Naji@arm.com actBackEnergy = energy.act_stdby_energy * memory.devicesPerRank; 182810618SOmar.Naji@arm.com preBackEnergy = energy.pre_stdby_energy * memory.devicesPerRank; 182910618SOmar.Naji@arm.com totalEnergy = energy.total_energy * memory.devicesPerRank; 183010618SOmar.Naji@arm.com averagePower = rank_power.average_power * memory.devicesPerRank; 183110432SOmar.Naji@arm.com} 183210432SOmar.Naji@arm.com 183310432SOmar.Naji@arm.comvoid 183410618SOmar.Naji@arm.comDRAMCtrl::Rank::regStats() 183510618SOmar.Naji@arm.com{ 183610618SOmar.Naji@arm.com using namespace Stats; 183710618SOmar.Naji@arm.com 183810618SOmar.Naji@arm.com pwrStateTime 183910618SOmar.Naji@arm.com .init(5) 184010618SOmar.Naji@arm.com .name(name() + ".memoryStateTime") 184110618SOmar.Naji@arm.com .desc("Time in different power states"); 184210618SOmar.Naji@arm.com pwrStateTime.subname(0, "IDLE"); 184310618SOmar.Naji@arm.com pwrStateTime.subname(1, "REF"); 184410618SOmar.Naji@arm.com pwrStateTime.subname(2, "PRE_PDN"); 184510618SOmar.Naji@arm.com pwrStateTime.subname(3, "ACT"); 184610618SOmar.Naji@arm.com pwrStateTime.subname(4, "ACT_PDN"); 184710618SOmar.Naji@arm.com 184810618SOmar.Naji@arm.com actEnergy 184910618SOmar.Naji@arm.com .name(name() + ".actEnergy") 185010618SOmar.Naji@arm.com .desc("Energy for activate commands per rank (pJ)"); 185110618SOmar.Naji@arm.com 185210618SOmar.Naji@arm.com preEnergy 185310618SOmar.Naji@arm.com .name(name() + ".preEnergy") 185410618SOmar.Naji@arm.com .desc("Energy for precharge commands per rank (pJ)"); 185510618SOmar.Naji@arm.com 185610618SOmar.Naji@arm.com readEnergy 185710618SOmar.Naji@arm.com .name(name() + ".readEnergy") 185810618SOmar.Naji@arm.com .desc("Energy for read commands per rank (pJ)"); 185910618SOmar.Naji@arm.com 186010618SOmar.Naji@arm.com writeEnergy 186110618SOmar.Naji@arm.com .name(name() + ".writeEnergy") 186210618SOmar.Naji@arm.com .desc("Energy for write commands per rank (pJ)"); 186310618SOmar.Naji@arm.com 186410618SOmar.Naji@arm.com refreshEnergy 186510618SOmar.Naji@arm.com .name(name() + ".refreshEnergy") 186610618SOmar.Naji@arm.com .desc("Energy for refresh commands per rank (pJ)"); 186710618SOmar.Naji@arm.com 186810618SOmar.Naji@arm.com actBackEnergy 186910618SOmar.Naji@arm.com .name(name() + ".actBackEnergy") 187010618SOmar.Naji@arm.com .desc("Energy for active background per rank (pJ)"); 187110618SOmar.Naji@arm.com 187210618SOmar.Naji@arm.com preBackEnergy 187310618SOmar.Naji@arm.com .name(name() + ".preBackEnergy") 187410618SOmar.Naji@arm.com .desc("Energy for precharge background per rank (pJ)"); 187510618SOmar.Naji@arm.com 187610618SOmar.Naji@arm.com totalEnergy 187710618SOmar.Naji@arm.com .name(name() + ".totalEnergy") 187810618SOmar.Naji@arm.com .desc("Total energy per rank (pJ)"); 187910618SOmar.Naji@arm.com 188010618SOmar.Naji@arm.com averagePower 188110618SOmar.Naji@arm.com .name(name() + ".averagePower") 188210618SOmar.Naji@arm.com .desc("Core power per rank (mW)"); 188310618SOmar.Naji@arm.com} 188410618SOmar.Naji@arm.comvoid 188510146Sandreas.hansson@arm.comDRAMCtrl::regStats() 18869243SN/A{ 18879243SN/A using namespace Stats; 18889243SN/A 18899243SN/A AbstractMemory::regStats(); 18909243SN/A 189110618SOmar.Naji@arm.com for (auto r : ranks) { 189210618SOmar.Naji@arm.com r->regStats(); 189310618SOmar.Naji@arm.com } 189410618SOmar.Naji@arm.com 18959243SN/A readReqs 18969243SN/A .name(name() + ".readReqs") 18979977SN/A .desc("Number of read requests accepted"); 18989243SN/A 18999243SN/A writeReqs 19009243SN/A .name(name() + ".writeReqs") 19019977SN/A .desc("Number of write requests accepted"); 19029831SN/A 19039831SN/A readBursts 19049831SN/A .name(name() + ".readBursts") 19059977SN/A .desc("Number of DRAM read bursts, " 19069977SN/A "including those serviced by the write queue"); 19079831SN/A 19089831SN/A writeBursts 19099831SN/A .name(name() + ".writeBursts") 19109977SN/A .desc("Number of DRAM write bursts, " 19119977SN/A "including those merged in the write queue"); 19129243SN/A 19139243SN/A servicedByWrQ 19149243SN/A .name(name() + ".servicedByWrQ") 19159977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 19169977SN/A 19179977SN/A mergedWrBursts 19189977SN/A .name(name() + ".mergedWrBursts") 19199977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 19209243SN/A 19219243SN/A neitherReadNorWrite 19229977SN/A .name(name() + ".neitherReadNorWriteReqs") 19239977SN/A .desc("Number of requests that are neither read nor write"); 19249243SN/A 19259977SN/A perBankRdBursts 19269243SN/A .init(banksPerRank * ranksPerChannel) 19279977SN/A .name(name() + ".perBankRdBursts") 19289977SN/A .desc("Per bank write bursts"); 19299243SN/A 19309977SN/A perBankWrBursts 19319243SN/A .init(banksPerRank * ranksPerChannel) 19329977SN/A .name(name() + ".perBankWrBursts") 19339977SN/A .desc("Per bank write bursts"); 19349243SN/A 19359243SN/A avgRdQLen 19369243SN/A .name(name() + ".avgRdQLen") 19379977SN/A .desc("Average read queue length when enqueuing") 19389243SN/A .precision(2); 19399243SN/A 19409243SN/A avgWrQLen 19419243SN/A .name(name() + ".avgWrQLen") 19429977SN/A .desc("Average write queue length when enqueuing") 19439243SN/A .precision(2); 19449243SN/A 19459243SN/A totQLat 19469243SN/A .name(name() + ".totQLat") 19479977SN/A .desc("Total ticks spent queuing"); 19489243SN/A 19499243SN/A totBusLat 19509243SN/A .name(name() + ".totBusLat") 19519977SN/A .desc("Total ticks spent in databus transfers"); 19529243SN/A 19539243SN/A totMemAccLat 19549243SN/A .name(name() + ".totMemAccLat") 19559977SN/A .desc("Total ticks spent from burst creation until serviced " 19569977SN/A "by the DRAM"); 19579243SN/A 19589243SN/A avgQLat 19599243SN/A .name(name() + ".avgQLat") 19609977SN/A .desc("Average queueing delay per DRAM burst") 19619243SN/A .precision(2); 19629243SN/A 19639831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 19649243SN/A 19659243SN/A avgBusLat 19669243SN/A .name(name() + ".avgBusLat") 19679977SN/A .desc("Average bus latency per DRAM burst") 19689243SN/A .precision(2); 19699243SN/A 19709831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 19719243SN/A 19729243SN/A avgMemAccLat 19739243SN/A .name(name() + ".avgMemAccLat") 19749977SN/A .desc("Average memory access latency per DRAM burst") 19759243SN/A .precision(2); 19769243SN/A 19779831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 19789243SN/A 19799243SN/A numRdRetry 19809243SN/A .name(name() + ".numRdRetry") 19819977SN/A .desc("Number of times read queue was full causing retry"); 19829243SN/A 19839243SN/A numWrRetry 19849243SN/A .name(name() + ".numWrRetry") 19859977SN/A .desc("Number of times write queue was full causing retry"); 19869243SN/A 19879243SN/A readRowHits 19889243SN/A .name(name() + ".readRowHits") 19899243SN/A .desc("Number of row buffer hits during reads"); 19909243SN/A 19919243SN/A writeRowHits 19929243SN/A .name(name() + ".writeRowHits") 19939243SN/A .desc("Number of row buffer hits during writes"); 19949243SN/A 19959243SN/A readRowHitRate 19969243SN/A .name(name() + ".readRowHitRate") 19979243SN/A .desc("Row buffer hit rate for reads") 19989243SN/A .precision(2); 19999243SN/A 20009831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 20019243SN/A 20029243SN/A writeRowHitRate 20039243SN/A .name(name() + ".writeRowHitRate") 20049243SN/A .desc("Row buffer hit rate for writes") 20059243SN/A .precision(2); 20069243SN/A 20079977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 20089243SN/A 20099243SN/A readPktSize 20109831SN/A .init(ceilLog2(burstSize) + 1) 20119243SN/A .name(name() + ".readPktSize") 20129977SN/A .desc("Read request sizes (log2)"); 20139243SN/A 20149243SN/A writePktSize 20159831SN/A .init(ceilLog2(burstSize) + 1) 20169243SN/A .name(name() + ".writePktSize") 20179977SN/A .desc("Write request sizes (log2)"); 20189243SN/A 20199243SN/A rdQLenPdf 20209567SN/A .init(readBufferSize) 20219243SN/A .name(name() + ".rdQLenPdf") 20229243SN/A .desc("What read queue length does an incoming req see"); 20239243SN/A 20249243SN/A wrQLenPdf 20259567SN/A .init(writeBufferSize) 20269243SN/A .name(name() + ".wrQLenPdf") 20279243SN/A .desc("What write queue length does an incoming req see"); 20289243SN/A 20299727SN/A bytesPerActivate 203010141SN/A .init(maxAccessesPerRow) 20319727SN/A .name(name() + ".bytesPerActivate") 20329727SN/A .desc("Bytes accessed per row activation") 20339727SN/A .flags(nozero); 20349243SN/A 203510147Sandreas.hansson@arm.com rdPerTurnAround 203610147Sandreas.hansson@arm.com .init(readBufferSize) 203710147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 203810147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 203910147Sandreas.hansson@arm.com .flags(nozero); 204010147Sandreas.hansson@arm.com 204110147Sandreas.hansson@arm.com wrPerTurnAround 204210147Sandreas.hansson@arm.com .init(writeBufferSize) 204310147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 204410147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 204510147Sandreas.hansson@arm.com .flags(nozero); 204610147Sandreas.hansson@arm.com 20479975SN/A bytesReadDRAM 20489975SN/A .name(name() + ".bytesReadDRAM") 20499975SN/A .desc("Total number of bytes read from DRAM"); 20509975SN/A 20519975SN/A bytesReadWrQ 20529975SN/A .name(name() + ".bytesReadWrQ") 20539975SN/A .desc("Total number of bytes read from write queue"); 20549243SN/A 20559243SN/A bytesWritten 20569243SN/A .name(name() + ".bytesWritten") 20579977SN/A .desc("Total number of bytes written to DRAM"); 20589243SN/A 20599977SN/A bytesReadSys 20609977SN/A .name(name() + ".bytesReadSys") 20619977SN/A .desc("Total read bytes from the system interface side"); 20629243SN/A 20639977SN/A bytesWrittenSys 20649977SN/A .name(name() + ".bytesWrittenSys") 20659977SN/A .desc("Total written bytes from the system interface side"); 20669243SN/A 20679243SN/A avgRdBW 20689243SN/A .name(name() + ".avgRdBW") 20699977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 20709243SN/A .precision(2); 20719243SN/A 20729977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 20739243SN/A 20749243SN/A avgWrBW 20759243SN/A .name(name() + ".avgWrBW") 20769977SN/A .desc("Average achieved write bandwidth in MiByte/s") 20779243SN/A .precision(2); 20789243SN/A 20799243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 20809243SN/A 20819977SN/A avgRdBWSys 20829977SN/A .name(name() + ".avgRdBWSys") 20839977SN/A .desc("Average system read bandwidth in MiByte/s") 20849243SN/A .precision(2); 20859243SN/A 20869977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 20879243SN/A 20889977SN/A avgWrBWSys 20899977SN/A .name(name() + ".avgWrBWSys") 20909977SN/A .desc("Average system write bandwidth in MiByte/s") 20919243SN/A .precision(2); 20929243SN/A 20939977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 20949243SN/A 20959243SN/A peakBW 20969243SN/A .name(name() + ".peakBW") 20979977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 20989243SN/A .precision(2); 20999243SN/A 21009831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 21019243SN/A 21029243SN/A busUtil 21039243SN/A .name(name() + ".busUtil") 21049243SN/A .desc("Data bus utilization in percentage") 21059243SN/A .precision(2); 21069243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 21079243SN/A 21089243SN/A totGap 21099243SN/A .name(name() + ".totGap") 21109243SN/A .desc("Total gap between requests"); 21119243SN/A 21129243SN/A avgGap 21139243SN/A .name(name() + ".avgGap") 21149243SN/A .desc("Average gap between requests") 21159243SN/A .precision(2); 21169243SN/A 21179243SN/A avgGap = totGap / (readReqs + writeReqs); 21189975SN/A 21199975SN/A // Stats for DRAM Power calculation based on Micron datasheet 21209975SN/A busUtilRead 21219975SN/A .name(name() + ".busUtilRead") 21229975SN/A .desc("Data bus utilization in percentage for reads") 21239975SN/A .precision(2); 21249975SN/A 21259975SN/A busUtilRead = avgRdBW / peakBW * 100; 21269975SN/A 21279975SN/A busUtilWrite 21289975SN/A .name(name() + ".busUtilWrite") 21299975SN/A .desc("Data bus utilization in percentage for writes") 21309975SN/A .precision(2); 21319975SN/A 21329975SN/A busUtilWrite = avgWrBW / peakBW * 100; 21339975SN/A 21349975SN/A pageHitRate 21359975SN/A .name(name() + ".pageHitRate") 21369975SN/A .desc("Row buffer hit rate, read and write combined") 21379975SN/A .precision(2); 21389975SN/A 21399977SN/A pageHitRate = (writeRowHits + readRowHits) / 21409977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 21419243SN/A} 21429243SN/A 21439243SN/Avoid 214410146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 21459243SN/A{ 21469243SN/A // rely on the abstract memory 21479243SN/A functionalAccess(pkt); 21489243SN/A} 21499243SN/A 21509294SN/ABaseSlavePort& 215110146Sandreas.hansson@arm.comDRAMCtrl::getSlavePort(const string &if_name, PortID idx) 21529243SN/A{ 21539243SN/A if (if_name != "port") { 21549243SN/A return MemObject::getSlavePort(if_name, idx); 21559243SN/A } else { 21569243SN/A return port; 21579243SN/A } 21589243SN/A} 21599243SN/A 216010913Sandreas.sandberg@arm.comDrainState 216110913Sandreas.sandberg@arm.comDRAMCtrl::drain() 21629243SN/A{ 21639243SN/A // if there is anything in any of our internal queues, keep track 21649243SN/A // of that as well 216510913Sandreas.sandberg@arm.com if (!(writeQueue.empty() && readQueue.empty() && respQueue.empty())) { 21669352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 21679567SN/A " resp: %d\n", writeQueue.size(), readQueue.size(), 21689567SN/A respQueue.size()); 216910206Sandreas.hansson@arm.com 21709352SN/A // the only part that is not drained automatically over time 217110206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 217210206Sandreas.hansson@arm.com if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 217310206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 217410206Sandreas.hansson@arm.com } 217510913Sandreas.sandberg@arm.com return DrainState::Draining; 217610912Sandreas.sandberg@arm.com } else { 217710913Sandreas.sandberg@arm.com return DrainState::Drained; 21789243SN/A } 21799243SN/A} 21809243SN/A 218110619Sandreas.hansson@arm.comvoid 218210619Sandreas.hansson@arm.comDRAMCtrl::drainResume() 218310619Sandreas.hansson@arm.com{ 218410619Sandreas.hansson@arm.com if (!isTimingMode && system()->isTimingMode()) { 218510619Sandreas.hansson@arm.com // if we switched to timing mode, kick things into action, 218610619Sandreas.hansson@arm.com // and behave as if we restored from a checkpoint 218710619Sandreas.hansson@arm.com startup(); 218810619Sandreas.hansson@arm.com } else if (isTimingMode && !system()->isTimingMode()) { 218910619Sandreas.hansson@arm.com // if we switch from timing mode, stop the refresh events to 219010619Sandreas.hansson@arm.com // not cause issues with KVM 219110619Sandreas.hansson@arm.com for (auto r : ranks) { 219210619Sandreas.hansson@arm.com r->suspend(); 219310619Sandreas.hansson@arm.com } 219410619Sandreas.hansson@arm.com } 219510619Sandreas.hansson@arm.com 219610619Sandreas.hansson@arm.com // update the mode 219710619Sandreas.hansson@arm.com isTimingMode = system()->isTimingMode(); 219810619Sandreas.hansson@arm.com} 219910619Sandreas.hansson@arm.com 220010146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 22019243SN/A : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 22029243SN/A memory(_memory) 22039243SN/A{ } 22049243SN/A 22059243SN/AAddrRangeList 220610146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 22079243SN/A{ 22089243SN/A AddrRangeList ranges; 22099243SN/A ranges.push_back(memory.getAddrRange()); 22109243SN/A return ranges; 22119243SN/A} 22129243SN/A 22139243SN/Avoid 221410146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 22159243SN/A{ 22169243SN/A pkt->pushLabel(memory.name()); 22179243SN/A 22189243SN/A if (!queue.checkFunctional(pkt)) { 22199243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 22209243SN/A // calls recvAtomic() and throws away the latency; we can save a 22219243SN/A // little here by just not calculating the latency. 22229243SN/A memory.recvFunctional(pkt); 22239243SN/A } 22249243SN/A 22259243SN/A pkt->popLabel(); 22269243SN/A} 22279243SN/A 22289243SN/ATick 222910146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 22309243SN/A{ 22319243SN/A return memory.recvAtomic(pkt); 22329243SN/A} 22339243SN/A 22349243SN/Abool 223510146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 22369243SN/A{ 22379243SN/A // pass it to the memory controller 22389243SN/A return memory.recvTimingReq(pkt); 22399243SN/A} 22409243SN/A 224110146Sandreas.hansson@arm.comDRAMCtrl* 224210146Sandreas.hansson@arm.comDRAMCtrlParams::create() 22439243SN/A{ 224410146Sandreas.hansson@arm.com return new DRAMCtrl(this); 22459243SN/A} 2246