dram_ctrl.cc revision 11190
1/*
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2013 Amin Farmahini-Farahani
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Andreas Hansson
41 *          Ani Udipi
42 *          Neha Agarwal
43 *          Omar Naji
44 */
45
46#include "base/bitfield.hh"
47#include "base/trace.hh"
48#include "debug/DRAM.hh"
49#include "debug/DRAMPower.hh"
50#include "debug/DRAMState.hh"
51#include "debug/Drain.hh"
52#include "mem/dram_ctrl.hh"
53#include "sim/system.hh"
54
55using namespace std;
56using namespace Data;
57
58DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
59    AbstractMemory(p),
60    port(name() + ".port", *this), isTimingMode(false),
61    retryRdReq(false), retryWrReq(false),
62    busState(READ),
63    nextReqEvent(this), respondEvent(this),
64    deviceSize(p->device_size),
65    deviceBusWidth(p->device_bus_width), burstLength(p->burst_length),
66    deviceRowBufferSize(p->device_rowbuffer_size),
67    devicesPerRank(p->devices_per_rank),
68    burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8),
69    rowBufferSize(devicesPerRank * deviceRowBufferSize),
70    columnsPerRowBuffer(rowBufferSize / burstSize),
71    columnsPerStripe(range.interleaved() ? range.granularity() / burstSize : 1),
72    ranksPerChannel(p->ranks_per_channel),
73    bankGroupsPerRank(p->bank_groups_per_rank),
74    bankGroupArch(p->bank_groups_per_rank > 0),
75    banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0),
76    readBufferSize(p->read_buffer_size),
77    writeBufferSize(p->write_buffer_size),
78    writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0),
79    writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0),
80    minWritesPerSwitch(p->min_writes_per_switch),
81    writesThisTime(0), readsThisTime(0),
82    tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST),
83    tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS),
84    tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD),
85    tRRD_L(p->tRRD_L), tXAW(p->tXAW), activationLimit(p->activation_limit),
86    memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping),
87    pageMgmt(p->page_policy),
88    maxAccessesPerRow(p->max_accesses_per_row),
89    frontendLatency(p->static_frontend_latency),
90    backendLatency(p->static_backend_latency),
91    busBusyUntil(0), prevArrival(0),
92    nextReqTime(0), activeRank(0), timeStampOffset(0)
93{
94    // sanity check the ranks since we rely on bit slicing for the
95    // address decoding
96    fatal_if(!isPowerOf2(ranksPerChannel), "DRAM rank count of %d is not "
97             "allowed, must be a power of two\n", ranksPerChannel);
98
99    fatal_if(!isPowerOf2(burstSize), "DRAM burst size %d is not allowed, "
100             "must be a power of two\n", burstSize);
101
102    for (int i = 0; i < ranksPerChannel; i++) {
103        Rank* rank = new Rank(*this, p);
104        ranks.push_back(rank);
105
106        rank->actTicks.resize(activationLimit, 0);
107        rank->banks.resize(banksPerRank);
108        rank->rank = i;
109
110        for (int b = 0; b < banksPerRank; b++) {
111            rank->banks[b].bank = b;
112            // GDDR addressing of banks to BG is linear.
113            // Here we assume that all DRAM generations address bank groups as
114            // follows:
115            if (bankGroupArch) {
116                // Simply assign lower bits to bank group in order to
117                // rotate across bank groups as banks are incremented
118                // e.g. with 4 banks per bank group and 16 banks total:
119                //    banks 0,4,8,12  are in bank group 0
120                //    banks 1,5,9,13  are in bank group 1
121                //    banks 2,6,10,14 are in bank group 2
122                //    banks 3,7,11,15 are in bank group 3
123                rank->banks[b].bankgr = b % bankGroupsPerRank;
124            } else {
125                // No bank groups; simply assign to bank number
126                rank->banks[b].bankgr = b;
127            }
128        }
129    }
130
131    // perform a basic check of the write thresholds
132    if (p->write_low_thresh_perc >= p->write_high_thresh_perc)
133        fatal("Write buffer low threshold %d must be smaller than the "
134              "high threshold %d\n", p->write_low_thresh_perc,
135              p->write_high_thresh_perc);
136
137    // determine the rows per bank by looking at the total capacity
138    uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size());
139
140    // determine the dram actual capacity from the DRAM config in Mbytes
141    uint64_t deviceCapacity = deviceSize / (1024 * 1024) * devicesPerRank *
142        ranksPerChannel;
143
144    // if actual DRAM size does not match memory capacity in system warn!
145    if (deviceCapacity != capacity / (1024 * 1024))
146        warn("DRAM device capacity (%d Mbytes) does not match the "
147             "address range assigned (%d Mbytes)\n", deviceCapacity,
148             capacity / (1024 * 1024));
149
150    DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity,
151            AbstractMemory::size());
152
153    DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n",
154            rowBufferSize, columnsPerRowBuffer);
155
156    rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel);
157
158    // some basic sanity checks
159    if (tREFI <= tRP || tREFI <= tRFC) {
160        fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n",
161              tREFI, tRP, tRFC);
162    }
163
164    // basic bank group architecture checks ->
165    if (bankGroupArch) {
166        // must have at least one bank per bank group
167        if (bankGroupsPerRank > banksPerRank) {
168            fatal("banks per rank (%d) must be equal to or larger than "
169                  "banks groups per rank (%d)\n",
170                  banksPerRank, bankGroupsPerRank);
171        }
172        // must have same number of banks in each bank group
173        if ((banksPerRank % bankGroupsPerRank) != 0) {
174            fatal("Banks per rank (%d) must be evenly divisible by bank groups "
175                  "per rank (%d) for equal banks per bank group\n",
176                  banksPerRank, bankGroupsPerRank);
177        }
178        // tCCD_L should be greater than minimal, back-to-back burst delay
179        if (tCCD_L <= tBURST) {
180            fatal("tCCD_L (%d) should be larger than tBURST (%d) when "
181                  "bank groups per rank (%d) is greater than 1\n",
182                  tCCD_L, tBURST, bankGroupsPerRank);
183        }
184        // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay
185        // some datasheets might specify it equal to tRRD
186        if (tRRD_L < tRRD) {
187            fatal("tRRD_L (%d) should be larger than tRRD (%d) when "
188                  "bank groups per rank (%d) is greater than 1\n",
189                  tRRD_L, tRRD, bankGroupsPerRank);
190        }
191    }
192
193}
194
195void
196DRAMCtrl::init()
197{
198    AbstractMemory::init();
199
200   if (!port.isConnected()) {
201        fatal("DRAMCtrl %s is unconnected!\n", name());
202    } else {
203        port.sendRangeChange();
204    }
205
206    // a bit of sanity checks on the interleaving, save it for here to
207    // ensure that the system pointer is initialised
208    if (range.interleaved()) {
209        if (channels != range.stripes())
210            fatal("%s has %d interleaved address stripes but %d channel(s)\n",
211                  name(), range.stripes(), channels);
212
213        if (addrMapping == Enums::RoRaBaChCo) {
214            if (rowBufferSize != range.granularity()) {
215                fatal("Channel interleaving of %s doesn't match RoRaBaChCo "
216                      "address map\n", name());
217            }
218        } else if (addrMapping == Enums::RoRaBaCoCh ||
219                   addrMapping == Enums::RoCoRaBaCh) {
220            // for the interleavings with channel bits in the bottom,
221            // if the system uses a channel striping granularity that
222            // is larger than the DRAM burst size, then map the
223            // sequential accesses within a stripe to a number of
224            // columns in the DRAM, effectively placing some of the
225            // lower-order column bits as the least-significant bits
226            // of the address (above the ones denoting the burst size)
227            assert(columnsPerStripe >= 1);
228
229            // channel striping has to be done at a granularity that
230            // is equal or larger to a cache line
231            if (system()->cacheLineSize() > range.granularity()) {
232                fatal("Channel interleaving of %s must be at least as large "
233                      "as the cache line size\n", name());
234            }
235
236            // ...and equal or smaller than the row-buffer size
237            if (rowBufferSize < range.granularity()) {
238                fatal("Channel interleaving of %s must be at most as large "
239                      "as the row-buffer size\n", name());
240            }
241            // this is essentially the check above, so just to be sure
242            assert(columnsPerStripe <= columnsPerRowBuffer);
243        }
244    }
245}
246
247void
248DRAMCtrl::startup()
249{
250    // remember the memory system mode of operation
251    isTimingMode = system()->isTimingMode();
252
253    if (isTimingMode) {
254        // timestamp offset should be in clock cycles for DRAMPower
255        timeStampOffset = divCeil(curTick(), tCK);
256
257        // update the start tick for the precharge accounting to the
258        // current tick
259        for (auto r : ranks) {
260            r->startup(curTick() + tREFI - tRP);
261        }
262
263        // shift the bus busy time sufficiently far ahead that we never
264        // have to worry about negative values when computing the time for
265        // the next request, this will add an insignificant bubble at the
266        // start of simulation
267        busBusyUntil = curTick() + tRP + tRCD + tCL;
268    }
269}
270
271Tick
272DRAMCtrl::recvAtomic(PacketPtr pkt)
273{
274    DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr());
275
276    // do the actual memory access and turn the packet into a response
277    access(pkt);
278
279    Tick latency = 0;
280    if (!pkt->memInhibitAsserted() && pkt->hasData()) {
281        // this value is not supposed to be accurate, just enough to
282        // keep things going, mimic a closed page
283        latency = tRP + tRCD + tCL;
284    }
285    return latency;
286}
287
288bool
289DRAMCtrl::readQueueFull(unsigned int neededEntries) const
290{
291    DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n",
292            readBufferSize, readQueue.size() + respQueue.size(),
293            neededEntries);
294
295    return
296        (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize;
297}
298
299bool
300DRAMCtrl::writeQueueFull(unsigned int neededEntries) const
301{
302    DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n",
303            writeBufferSize, writeQueue.size(), neededEntries);
304    return (writeQueue.size() + neededEntries) > writeBufferSize;
305}
306
307DRAMCtrl::DRAMPacket*
308DRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size,
309                       bool isRead)
310{
311    // decode the address based on the address mapping scheme, with
312    // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and
313    // channel, respectively
314    uint8_t rank;
315    uint8_t bank;
316    // use a 64-bit unsigned during the computations as the row is
317    // always the top bits, and check before creating the DRAMPacket
318    uint64_t row;
319
320    // truncate the address to a DRAM burst, which makes it unique to
321    // a specific column, row, bank, rank and channel
322    Addr addr = dramPktAddr / burstSize;
323
324    // we have removed the lowest order address bits that denote the
325    // position within the column
326    if (addrMapping == Enums::RoRaBaChCo) {
327        // the lowest order bits denote the column to ensure that
328        // sequential cache lines occupy the same row
329        addr = addr / columnsPerRowBuffer;
330
331        // take out the channel part of the address
332        addr = addr / channels;
333
334        // after the channel bits, get the bank bits to interleave
335        // over the banks
336        bank = addr % banksPerRank;
337        addr = addr / banksPerRank;
338
339        // after the bank, we get the rank bits which thus interleaves
340        // over the ranks
341        rank = addr % ranksPerChannel;
342        addr = addr / ranksPerChannel;
343
344        // lastly, get the row bits, no need to remove them from addr
345        row = addr % rowsPerBank;
346    } else if (addrMapping == Enums::RoRaBaCoCh) {
347        // take out the lower-order column bits
348        addr = addr / columnsPerStripe;
349
350        // take out the channel part of the address
351        addr = addr / channels;
352
353        // next, the higher-order column bites
354        addr = addr / (columnsPerRowBuffer / columnsPerStripe);
355
356        // after the column bits, we get the bank bits to interleave
357        // over the banks
358        bank = addr % banksPerRank;
359        addr = addr / banksPerRank;
360
361        // after the bank, we get the rank bits which thus interleaves
362        // over the ranks
363        rank = addr % ranksPerChannel;
364        addr = addr / ranksPerChannel;
365
366        // lastly, get the row bits, no need to remove them from addr
367        row = addr % rowsPerBank;
368    } else if (addrMapping == Enums::RoCoRaBaCh) {
369        // optimise for closed page mode and utilise maximum
370        // parallelism of the DRAM (at the cost of power)
371
372        // take out the lower-order column bits
373        addr = addr / columnsPerStripe;
374
375        // take out the channel part of the address, not that this has
376        // to match with how accesses are interleaved between the
377        // controllers in the address mapping
378        addr = addr / channels;
379
380        // start with the bank bits, as this provides the maximum
381        // opportunity for parallelism between requests
382        bank = addr % banksPerRank;
383        addr = addr / banksPerRank;
384
385        // next get the rank bits
386        rank = addr % ranksPerChannel;
387        addr = addr / ranksPerChannel;
388
389        // next, the higher-order column bites
390        addr = addr / (columnsPerRowBuffer / columnsPerStripe);
391
392        // lastly, get the row bits, no need to remove them from addr
393        row = addr % rowsPerBank;
394    } else
395        panic("Unknown address mapping policy chosen!");
396
397    assert(rank < ranksPerChannel);
398    assert(bank < banksPerRank);
399    assert(row < rowsPerBank);
400    assert(row < Bank::NO_ROW);
401
402    DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n",
403            dramPktAddr, rank, bank, row);
404
405    // create the corresponding DRAM packet with the entry time and
406    // ready time set to the current tick, the latter will be updated
407    // later
408    uint16_t bank_id = banksPerRank * rank + bank;
409    return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr,
410                          size, ranks[rank]->banks[bank], *ranks[rank]);
411}
412
413void
414DRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount)
415{
416    // only add to the read queue here. whenever the request is
417    // eventually done, set the readyTime, and call schedule()
418    assert(!pkt->isWrite());
419
420    assert(pktCount != 0);
421
422    // if the request size is larger than burst size, the pkt is split into
423    // multiple DRAM packets
424    // Note if the pkt starting address is not aligened to burst size, the
425    // address of first DRAM packet is kept unaliged. Subsequent DRAM packets
426    // are aligned to burst size boundaries. This is to ensure we accurately
427    // check read packets against packets in write queue.
428    Addr addr = pkt->getAddr();
429    unsigned pktsServicedByWrQ = 0;
430    BurstHelper* burst_helper = NULL;
431    for (int cnt = 0; cnt < pktCount; ++cnt) {
432        unsigned size = std::min((addr | (burstSize - 1)) + 1,
433                        pkt->getAddr() + pkt->getSize()) - addr;
434        readPktSize[ceilLog2(size)]++;
435        readBursts++;
436
437        // First check write buffer to see if the data is already at
438        // the controller
439        bool foundInWrQ = false;
440        Addr burst_addr = burstAlign(addr);
441        // if the burst address is not present then there is no need
442        // looking any further
443        if (isInWriteQueue.find(burst_addr) != isInWriteQueue.end()) {
444            for (const auto& p : writeQueue) {
445                // check if the read is subsumed in the write queue
446                // packet we are looking at
447                if (p->addr <= addr && (addr + size) <= (p->addr + p->size)) {
448                    foundInWrQ = true;
449                    servicedByWrQ++;
450                    pktsServicedByWrQ++;
451                    DPRINTF(DRAM, "Read to addr %lld with size %d serviced by "
452                            "write queue\n", addr, size);
453                    bytesReadWrQ += burstSize;
454                    break;
455                }
456            }
457        }
458
459        // If not found in the write q, make a DRAM packet and
460        // push it onto the read queue
461        if (!foundInWrQ) {
462
463            // Make the burst helper for split packets
464            if (pktCount > 1 && burst_helper == NULL) {
465                DPRINTF(DRAM, "Read to addr %lld translates to %d "
466                        "dram requests\n", pkt->getAddr(), pktCount);
467                burst_helper = new BurstHelper(pktCount);
468            }
469
470            DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true);
471            dram_pkt->burstHelper = burst_helper;
472
473            assert(!readQueueFull(1));
474            rdQLenPdf[readQueue.size() + respQueue.size()]++;
475
476            DPRINTF(DRAM, "Adding to read queue\n");
477
478            readQueue.push_back(dram_pkt);
479
480            // Update stats
481            avgRdQLen = readQueue.size() + respQueue.size();
482        }
483
484        // Starting address of next dram pkt (aligend to burstSize boundary)
485        addr = (addr | (burstSize - 1)) + 1;
486    }
487
488    // If all packets are serviced by write queue, we send the repsonse back
489    if (pktsServicedByWrQ == pktCount) {
490        accessAndRespond(pkt, frontendLatency);
491        return;
492    }
493
494    // Update how many split packets are serviced by write queue
495    if (burst_helper != NULL)
496        burst_helper->burstsServiced = pktsServicedByWrQ;
497
498    // If we are not already scheduled to get a request out of the
499    // queue, do so now
500    if (!nextReqEvent.scheduled()) {
501        DPRINTF(DRAM, "Request scheduled immediately\n");
502        schedule(nextReqEvent, curTick());
503    }
504}
505
506void
507DRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
508{
509    // only add to the write queue here. whenever the request is
510    // eventually done, set the readyTime, and call schedule()
511    assert(pkt->isWrite());
512
513    // if the request size is larger than burst size, the pkt is split into
514    // multiple DRAM packets
515    Addr addr = pkt->getAddr();
516    for (int cnt = 0; cnt < pktCount; ++cnt) {
517        unsigned size = std::min((addr | (burstSize - 1)) + 1,
518                        pkt->getAddr() + pkt->getSize()) - addr;
519        writePktSize[ceilLog2(size)]++;
520        writeBursts++;
521
522        // see if we can merge with an existing item in the write
523        // queue and keep track of whether we have merged or not
524        bool merged = isInWriteQueue.find(burstAlign(addr)) !=
525            isInWriteQueue.end();
526
527        // if the item was not merged we need to create a new write
528        // and enqueue it
529        if (!merged) {
530            DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false);
531
532            assert(writeQueue.size() < writeBufferSize);
533            wrQLenPdf[writeQueue.size()]++;
534
535            DPRINTF(DRAM, "Adding to write queue\n");
536
537            writeQueue.push_back(dram_pkt);
538            isInWriteQueue.insert(burstAlign(addr));
539            assert(writeQueue.size() == isInWriteQueue.size());
540
541            // Update stats
542            avgWrQLen = writeQueue.size();
543        } else {
544            DPRINTF(DRAM, "Merging write burst with existing queue entry\n");
545
546            // keep track of the fact that this burst effectively
547            // disappeared as it was merged with an existing one
548            mergedWrBursts++;
549        }
550
551        // Starting address of next dram pkt (aligend to burstSize boundary)
552        addr = (addr | (burstSize - 1)) + 1;
553    }
554
555    // we do not wait for the writes to be send to the actual memory,
556    // but instead take responsibility for the consistency here and
557    // snoop the write queue for any upcoming reads
558    // @todo, if a pkt size is larger than burst size, we might need a
559    // different front end latency
560    accessAndRespond(pkt, frontendLatency);
561
562    // If we are not already scheduled to get a request out of the
563    // queue, do so now
564    if (!nextReqEvent.scheduled()) {
565        DPRINTF(DRAM, "Request scheduled immediately\n");
566        schedule(nextReqEvent, curTick());
567    }
568}
569
570void
571DRAMCtrl::printQs() const {
572    DPRINTF(DRAM, "===READ QUEUE===\n\n");
573    for (auto i = readQueue.begin() ;  i != readQueue.end() ; ++i) {
574        DPRINTF(DRAM, "Read %lu\n", (*i)->addr);
575    }
576    DPRINTF(DRAM, "\n===RESP QUEUE===\n\n");
577    for (auto i = respQueue.begin() ;  i != respQueue.end() ; ++i) {
578        DPRINTF(DRAM, "Response %lu\n", (*i)->addr);
579    }
580    DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n");
581    for (auto i = writeQueue.begin() ;  i != writeQueue.end() ; ++i) {
582        DPRINTF(DRAM, "Write %lu\n", (*i)->addr);
583    }
584}
585
586bool
587DRAMCtrl::recvTimingReq(PacketPtr pkt)
588{
589    // This is where we enter from the outside world
590    DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n",
591            pkt->cmdString(), pkt->getAddr(), pkt->getSize());
592
593    // simply drop inhibited packets and clean evictions
594    if (pkt->memInhibitAsserted() ||
595        pkt->cmd == MemCmd::CleanEvict) {
596        DPRINTF(DRAM, "Inhibited packet or clean evict -- Dropping it now\n");
597        pendingDelete.reset(pkt);
598        return true;
599    }
600
601    // Calc avg gap between requests
602    if (prevArrival != 0) {
603        totGap += curTick() - prevArrival;
604    }
605    prevArrival = curTick();
606
607
608    // Find out how many dram packets a pkt translates to
609    // If the burst size is equal or larger than the pkt size, then a pkt
610    // translates to only one dram packet. Otherwise, a pkt translates to
611    // multiple dram packets
612    unsigned size = pkt->getSize();
613    unsigned offset = pkt->getAddr() & (burstSize - 1);
614    unsigned int dram_pkt_count = divCeil(offset + size, burstSize);
615
616    // check local buffers and do not accept if full
617    if (pkt->isRead()) {
618        assert(size != 0);
619        if (readQueueFull(dram_pkt_count)) {
620            DPRINTF(DRAM, "Read queue full, not accepting\n");
621            // remember that we have to retry this port
622            retryRdReq = true;
623            numRdRetry++;
624            return false;
625        } else {
626            addToReadQueue(pkt, dram_pkt_count);
627            readReqs++;
628            bytesReadSys += size;
629        }
630    } else if (pkt->isWrite()) {
631        assert(size != 0);
632        if (writeQueueFull(dram_pkt_count)) {
633            DPRINTF(DRAM, "Write queue full, not accepting\n");
634            // remember that we have to retry this port
635            retryWrReq = true;
636            numWrRetry++;
637            return false;
638        } else {
639            addToWriteQueue(pkt, dram_pkt_count);
640            writeReqs++;
641            bytesWrittenSys += size;
642        }
643    } else {
644        DPRINTF(DRAM,"Neither read nor write, ignore timing\n");
645        neitherReadNorWrite++;
646        accessAndRespond(pkt, 1);
647    }
648
649    return true;
650}
651
652void
653DRAMCtrl::processRespondEvent()
654{
655    DPRINTF(DRAM,
656            "processRespondEvent(): Some req has reached its readyTime\n");
657
658    DRAMPacket* dram_pkt = respQueue.front();
659
660    if (dram_pkt->burstHelper) {
661        // it is a split packet
662        dram_pkt->burstHelper->burstsServiced++;
663        if (dram_pkt->burstHelper->burstsServiced ==
664            dram_pkt->burstHelper->burstCount) {
665            // we have now serviced all children packets of a system packet
666            // so we can now respond to the requester
667            // @todo we probably want to have a different front end and back
668            // end latency for split packets
669            accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency);
670            delete dram_pkt->burstHelper;
671            dram_pkt->burstHelper = NULL;
672        }
673    } else {
674        // it is not a split packet
675        accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency);
676    }
677
678    delete respQueue.front();
679    respQueue.pop_front();
680
681    if (!respQueue.empty()) {
682        assert(respQueue.front()->readyTime >= curTick());
683        assert(!respondEvent.scheduled());
684        schedule(respondEvent, respQueue.front()->readyTime);
685    } else {
686        // if there is nothing left in any queue, signal a drain
687        if (drainState() == DrainState::Draining &&
688            writeQueue.empty() && readQueue.empty()) {
689
690            DPRINTF(Drain, "DRAM controller done draining\n");
691            signalDrainDone();
692        }
693    }
694
695    // We have made a location in the queue available at this point,
696    // so if there is a read that was forced to wait, retry now
697    if (retryRdReq) {
698        retryRdReq = false;
699        port.sendRetryReq();
700    }
701}
702
703bool
704DRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay)
705{
706    // This method does the arbitration between requests. The chosen
707    // packet is simply moved to the head of the queue. The other
708    // methods know that this is the place to look. For example, with
709    // FCFS, this method does nothing
710    assert(!queue.empty());
711
712    // bool to indicate if a packet to an available rank is found
713    bool found_packet = false;
714    if (queue.size() == 1) {
715        DRAMPacket* dram_pkt = queue.front();
716        // available rank corresponds to state refresh idle
717        if (ranks[dram_pkt->rank]->isAvailable()) {
718            found_packet = true;
719            DPRINTF(DRAM, "Single request, going to a free rank\n");
720        } else {
721            DPRINTF(DRAM, "Single request, going to a busy rank\n");
722        }
723        return found_packet;
724    }
725
726    if (memSchedPolicy == Enums::fcfs) {
727        // check if there is a packet going to a free rank
728        for(auto i = queue.begin(); i != queue.end() ; ++i) {
729            DRAMPacket* dram_pkt = *i;
730            if (ranks[dram_pkt->rank]->isAvailable()) {
731                queue.erase(i);
732                queue.push_front(dram_pkt);
733                found_packet = true;
734                break;
735            }
736        }
737    } else if (memSchedPolicy == Enums::frfcfs) {
738        found_packet = reorderQueue(queue, extra_col_delay);
739    } else
740        panic("No scheduling policy chosen\n");
741    return found_packet;
742}
743
744bool
745DRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay)
746{
747    // Only determine this if needed
748    uint64_t earliest_banks = 0;
749    bool hidden_bank_prep = false;
750
751    // search for seamless row hits first, if no seamless row hit is
752    // found then determine if there are other packets that can be issued
753    // without incurring additional bus delay due to bank timing
754    // Will select closed rows first to enable more open row possibilies
755    // in future selections
756    bool found_hidden_bank = false;
757
758    // remember if we found a row hit, not seamless, but bank prepped
759    // and ready
760    bool found_prepped_pkt = false;
761
762    // if we have no row hit, prepped or not, and no seamless packet,
763    // just go for the earliest possible
764    bool found_earliest_pkt = false;
765
766    auto selected_pkt_it = queue.end();
767
768    // time we need to issue a column command to be seamless
769    const Tick min_col_at = std::max(busBusyUntil - tCL + extra_col_delay,
770                                     curTick());
771
772    for (auto i = queue.begin(); i != queue.end() ; ++i) {
773        DRAMPacket* dram_pkt = *i;
774        const Bank& bank = dram_pkt->bankRef;
775
776        // check if rank is available, if not, jump to the next packet
777        if (dram_pkt->rankRef.isAvailable()) {
778            // check if it is a row hit
779            if (bank.openRow == dram_pkt->row) {
780                // no additional rank-to-rank or same bank-group
781                // delays, or we switched read/write and might as well
782                // go for the row hit
783                if (bank.colAllowedAt <= min_col_at) {
784                    // FCFS within the hits, giving priority to
785                    // commands that can issue seamlessly, without
786                    // additional delay, such as same rank accesses
787                    // and/or different bank-group accesses
788                    DPRINTF(DRAM, "Seamless row buffer hit\n");
789                    selected_pkt_it = i;
790                    // no need to look through the remaining queue entries
791                    break;
792                } else if (!found_hidden_bank && !found_prepped_pkt) {
793                    // if we did not find a packet to a closed row that can
794                    // issue the bank commands without incurring delay, and
795                    // did not yet find a packet to a prepped row, remember
796                    // the current one
797                    selected_pkt_it = i;
798                    found_prepped_pkt = true;
799                    DPRINTF(DRAM, "Prepped row buffer hit\n");
800                }
801            } else if (!found_earliest_pkt) {
802                // if we have not initialised the bank status, do it
803                // now, and only once per scheduling decisions
804                if (earliest_banks == 0) {
805                    // determine entries with earliest bank delay
806                    pair<uint64_t, bool> bankStatus =
807                        minBankPrep(queue, min_col_at);
808                    earliest_banks = bankStatus.first;
809                    hidden_bank_prep = bankStatus.second;
810                }
811
812                // bank is amongst first available banks
813                // minBankPrep will give priority to packets that can
814                // issue seamlessly
815                if (bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) {
816                    found_earliest_pkt = true;
817                    found_hidden_bank = hidden_bank_prep;
818
819                    // give priority to packets that can issue
820                    // bank commands 'behind the scenes'
821                    // any additional delay if any will be due to
822                    // col-to-col command requirements
823                    if (hidden_bank_prep || !found_prepped_pkt)
824                        selected_pkt_it = i;
825                }
826            }
827        }
828    }
829
830    if (selected_pkt_it != queue.end()) {
831        DRAMPacket* selected_pkt = *selected_pkt_it;
832        queue.erase(selected_pkt_it);
833        queue.push_front(selected_pkt);
834        return true;
835    }
836
837    return false;
838}
839
840void
841DRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency)
842{
843    DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr());
844
845    bool needsResponse = pkt->needsResponse();
846    // do the actual memory access which also turns the packet into a
847    // response
848    access(pkt);
849
850    // turn packet around to go back to requester if response expected
851    if (needsResponse) {
852        // access already turned the packet into a response
853        assert(pkt->isResponse());
854        // response_time consumes the static latency and is charged also
855        // with headerDelay that takes into account the delay provided by
856        // the xbar and also the payloadDelay that takes into account the
857        // number of data beats.
858        Tick response_time = curTick() + static_latency + pkt->headerDelay +
859                             pkt->payloadDelay;
860        // Here we reset the timing of the packet before sending it out.
861        pkt->headerDelay = pkt->payloadDelay = 0;
862
863        // queue the packet in the response queue to be sent out after
864        // the static latency has passed
865        port.schedTimingResp(pkt, response_time);
866    } else {
867        // @todo the packet is going to be deleted, and the DRAMPacket
868        // is still having a pointer to it
869        pendingDelete.reset(pkt);
870    }
871
872    DPRINTF(DRAM, "Done\n");
873
874    return;
875}
876
877void
878DRAMCtrl::activateBank(Rank& rank_ref, Bank& bank_ref,
879                       Tick act_tick, uint32_t row)
880{
881    assert(rank_ref.actTicks.size() == activationLimit);
882
883    DPRINTF(DRAM, "Activate at tick %d\n", act_tick);
884
885    // update the open row
886    assert(bank_ref.openRow == Bank::NO_ROW);
887    bank_ref.openRow = row;
888
889    // start counting anew, this covers both the case when we
890    // auto-precharged, and when this access is forced to
891    // precharge
892    bank_ref.bytesAccessed = 0;
893    bank_ref.rowAccesses = 0;
894
895    ++rank_ref.numBanksActive;
896    assert(rank_ref.numBanksActive <= banksPerRank);
897
898    DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n",
899            bank_ref.bank, rank_ref.rank, act_tick,
900            ranks[rank_ref.rank]->numBanksActive);
901
902    rank_ref.power.powerlib.doCommand(MemCommand::ACT, bank_ref.bank,
903                                      divCeil(act_tick, tCK) -
904                                      timeStampOffset);
905
906    DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK) -
907            timeStampOffset, bank_ref.bank, rank_ref.rank);
908
909    // The next access has to respect tRAS for this bank
910    bank_ref.preAllowedAt = act_tick + tRAS;
911
912    // Respect the row-to-column command delay
913    bank_ref.colAllowedAt = std::max(act_tick + tRCD, bank_ref.colAllowedAt);
914
915    // start by enforcing tRRD
916    for(int i = 0; i < banksPerRank; i++) {
917        // next activate to any bank in this rank must not happen
918        // before tRRD
919        if (bankGroupArch && (bank_ref.bankgr == rank_ref.banks[i].bankgr)) {
920            // bank group architecture requires longer delays between
921            // ACT commands within the same bank group.  Use tRRD_L
922            // in this case
923            rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD_L,
924                                             rank_ref.banks[i].actAllowedAt);
925        } else {
926            // use shorter tRRD value when either
927            // 1) bank group architecture is not supportted
928            // 2) bank is in a different bank group
929            rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD,
930                                             rank_ref.banks[i].actAllowedAt);
931        }
932    }
933
934    // next, we deal with tXAW, if the activation limit is disabled
935    // then we directly schedule an activate power event
936    if (!rank_ref.actTicks.empty()) {
937        // sanity check
938        if (rank_ref.actTicks.back() &&
939           (act_tick - rank_ref.actTicks.back()) < tXAW) {
940            panic("Got %d activates in window %d (%llu - %llu) which "
941                  "is smaller than %llu\n", activationLimit, act_tick -
942                  rank_ref.actTicks.back(), act_tick,
943                  rank_ref.actTicks.back(), tXAW);
944        }
945
946        // shift the times used for the book keeping, the last element
947        // (highest index) is the oldest one and hence the lowest value
948        rank_ref.actTicks.pop_back();
949
950        // record an new activation (in the future)
951        rank_ref.actTicks.push_front(act_tick);
952
953        // cannot activate more than X times in time window tXAW, push the
954        // next one (the X + 1'st activate) to be tXAW away from the
955        // oldest in our window of X
956        if (rank_ref.actTicks.back() &&
957           (act_tick - rank_ref.actTicks.back()) < tXAW) {
958            DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate "
959                    "no earlier than %llu\n", activationLimit,
960                    rank_ref.actTicks.back() + tXAW);
961            for(int j = 0; j < banksPerRank; j++)
962                // next activate must not happen before end of window
963                rank_ref.banks[j].actAllowedAt =
964                    std::max(rank_ref.actTicks.back() + tXAW,
965                             rank_ref.banks[j].actAllowedAt);
966        }
967    }
968
969    // at the point when this activate takes place, make sure we
970    // transition to the active power state
971    if (!rank_ref.activateEvent.scheduled())
972        schedule(rank_ref.activateEvent, act_tick);
973    else if (rank_ref.activateEvent.when() > act_tick)
974        // move it sooner in time
975        reschedule(rank_ref.activateEvent, act_tick);
976}
977
978void
979DRAMCtrl::prechargeBank(Rank& rank_ref, Bank& bank, Tick pre_at, bool trace)
980{
981    // make sure the bank has an open row
982    assert(bank.openRow != Bank::NO_ROW);
983
984    // sample the bytes per activate here since we are closing
985    // the page
986    bytesPerActivate.sample(bank.bytesAccessed);
987
988    bank.openRow = Bank::NO_ROW;
989
990    // no precharge allowed before this one
991    bank.preAllowedAt = pre_at;
992
993    Tick pre_done_at = pre_at + tRP;
994
995    bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at);
996
997    assert(rank_ref.numBanksActive != 0);
998    --rank_ref.numBanksActive;
999
1000    DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got "
1001            "%d active\n", bank.bank, rank_ref.rank, pre_at,
1002            rank_ref.numBanksActive);
1003
1004    if (trace) {
1005
1006        rank_ref.power.powerlib.doCommand(MemCommand::PRE, bank.bank,
1007                                                divCeil(pre_at, tCK) -
1008                                                timeStampOffset);
1009        DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK) -
1010                timeStampOffset, bank.bank, rank_ref.rank);
1011    }
1012    // if we look at the current number of active banks we might be
1013    // tempted to think the DRAM is now idle, however this can be
1014    // undone by an activate that is scheduled to happen before we
1015    // would have reached the idle state, so schedule an event and
1016    // rather check once we actually make it to the point in time when
1017    // the (last) precharge takes place
1018    if (!rank_ref.prechargeEvent.scheduled())
1019        schedule(rank_ref.prechargeEvent, pre_done_at);
1020    else if (rank_ref.prechargeEvent.when() < pre_done_at)
1021        reschedule(rank_ref.prechargeEvent, pre_done_at);
1022}
1023
1024void
1025DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt)
1026{
1027    DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
1028            dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row);
1029
1030    // get the rank
1031    Rank& rank = dram_pkt->rankRef;
1032
1033    // get the bank
1034    Bank& bank = dram_pkt->bankRef;
1035
1036    // for the state we need to track if it is a row hit or not
1037    bool row_hit = true;
1038
1039    // respect any constraints on the command (e.g. tRCD or tCCD)
1040    Tick cmd_at = std::max(bank.colAllowedAt, curTick());
1041
1042    // Determine the access latency and update the bank state
1043    if (bank.openRow == dram_pkt->row) {
1044        // nothing to do
1045    } else {
1046        row_hit = false;
1047
1048        // If there is a page open, precharge it.
1049        if (bank.openRow != Bank::NO_ROW) {
1050            prechargeBank(rank, bank, std::max(bank.preAllowedAt, curTick()));
1051        }
1052
1053        // next we need to account for the delay in activating the
1054        // page
1055        Tick act_tick = std::max(bank.actAllowedAt, curTick());
1056
1057        // Record the activation and deal with all the global timing
1058        // constraints caused be a new activation (tRRD and tXAW)
1059        activateBank(rank, bank, act_tick, dram_pkt->row);
1060
1061        // issue the command as early as possible
1062        cmd_at = bank.colAllowedAt;
1063    }
1064
1065    // we need to wait until the bus is available before we can issue
1066    // the command
1067    cmd_at = std::max(cmd_at, busBusyUntil - tCL);
1068
1069    // update the packet ready time
1070    dram_pkt->readyTime = cmd_at + tCL + tBURST;
1071
1072    // only one burst can use the bus at any one point in time
1073    assert(dram_pkt->readyTime - busBusyUntil >= tBURST);
1074
1075    // update the time for the next read/write burst for each
1076    // bank (add a max with tCCD/tCCD_L here)
1077    Tick cmd_dly;
1078    for(int j = 0; j < ranksPerChannel; j++) {
1079        for(int i = 0; i < banksPerRank; i++) {
1080            // next burst to same bank group in this rank must not happen
1081            // before tCCD_L.  Different bank group timing requirement is
1082            // tBURST; Add tCS for different ranks
1083            if (dram_pkt->rank == j) {
1084                if (bankGroupArch &&
1085                   (bank.bankgr == ranks[j]->banks[i].bankgr)) {
1086                    // bank group architecture requires longer delays between
1087                    // RD/WR burst commands to the same bank group.
1088                    // Use tCCD_L in this case
1089                    cmd_dly = tCCD_L;
1090                } else {
1091                    // use tBURST (equivalent to tCCD_S), the shorter
1092                    // cas-to-cas delay value, when either:
1093                    // 1) bank group architecture is not supportted
1094                    // 2) bank is in a different bank group
1095                    cmd_dly = tBURST;
1096                }
1097            } else {
1098                // different rank is by default in a different bank group
1099                // use tBURST (equivalent to tCCD_S), which is the shorter
1100                // cas-to-cas delay in this case
1101                // Add tCS to account for rank-to-rank bus delay requirements
1102                cmd_dly = tBURST + tCS;
1103            }
1104            ranks[j]->banks[i].colAllowedAt = std::max(cmd_at + cmd_dly,
1105                                             ranks[j]->banks[i].colAllowedAt);
1106        }
1107    }
1108
1109    // Save rank of current access
1110    activeRank = dram_pkt->rank;
1111
1112    // If this is a write, we also need to respect the write recovery
1113    // time before a precharge, in the case of a read, respect the
1114    // read to precharge constraint
1115    bank.preAllowedAt = std::max(bank.preAllowedAt,
1116                                 dram_pkt->isRead ? cmd_at + tRTP :
1117                                 dram_pkt->readyTime + tWR);
1118
1119    // increment the bytes accessed and the accesses per row
1120    bank.bytesAccessed += burstSize;
1121    ++bank.rowAccesses;
1122
1123    // if we reached the max, then issue with an auto-precharge
1124    bool auto_precharge = pageMgmt == Enums::close ||
1125        bank.rowAccesses == maxAccessesPerRow;
1126
1127    // if we did not hit the limit, we might still want to
1128    // auto-precharge
1129    if (!auto_precharge &&
1130        (pageMgmt == Enums::open_adaptive ||
1131         pageMgmt == Enums::close_adaptive)) {
1132        // a twist on the open and close page policies:
1133        // 1) open_adaptive page policy does not blindly keep the
1134        // page open, but close it if there are no row hits, and there
1135        // are bank conflicts in the queue
1136        // 2) close_adaptive page policy does not blindly close the
1137        // page, but closes it only if there are no row hits in the queue.
1138        // In this case, only force an auto precharge when there
1139        // are no same page hits in the queue
1140        bool got_more_hits = false;
1141        bool got_bank_conflict = false;
1142
1143        // either look at the read queue or write queue
1144        const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue :
1145            writeQueue;
1146        auto p = queue.begin();
1147        // make sure we are not considering the packet that we are
1148        // currently dealing with (which is the head of the queue)
1149        ++p;
1150
1151        // keep on looking until we find a hit or reach the end of the queue
1152        // 1) if a hit is found, then both open and close adaptive policies keep
1153        // the page open
1154        // 2) if no hit is found, got_bank_conflict is set to true if a bank
1155        // conflict request is waiting in the queue
1156        while (!got_more_hits && p != queue.end()) {
1157            bool same_rank_bank = (dram_pkt->rank == (*p)->rank) &&
1158                (dram_pkt->bank == (*p)->bank);
1159            bool same_row = dram_pkt->row == (*p)->row;
1160            got_more_hits |= same_rank_bank && same_row;
1161            got_bank_conflict |= same_rank_bank && !same_row;
1162            ++p;
1163        }
1164
1165        // auto pre-charge when either
1166        // 1) open_adaptive policy, we have not got any more hits, and
1167        //    have a bank conflict
1168        // 2) close_adaptive policy and we have not got any more hits
1169        auto_precharge = !got_more_hits &&
1170            (got_bank_conflict || pageMgmt == Enums::close_adaptive);
1171    }
1172
1173    // DRAMPower trace command to be written
1174    std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR";
1175
1176    // MemCommand required for DRAMPower library
1177    MemCommand::cmds command = (mem_cmd == "RD") ? MemCommand::RD :
1178                                                   MemCommand::WR;
1179
1180    // if this access should use auto-precharge, then we are
1181    // closing the row
1182    if (auto_precharge) {
1183        // if auto-precharge push a PRE command at the correct tick to the
1184        // list used by DRAMPower library to calculate power
1185        prechargeBank(rank, bank, std::max(curTick(), bank.preAllowedAt));
1186
1187        DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId);
1188    }
1189
1190    // Update bus state
1191    busBusyUntil = dram_pkt->readyTime;
1192
1193    DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n",
1194            dram_pkt->addr, dram_pkt->readyTime, busBusyUntil);
1195
1196    dram_pkt->rankRef.power.powerlib.doCommand(command, dram_pkt->bank,
1197                                                 divCeil(cmd_at, tCK) -
1198                                                 timeStampOffset);
1199
1200    DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK) -
1201            timeStampOffset, mem_cmd, dram_pkt->bank, dram_pkt->rank);
1202
1203    // Update the minimum timing between the requests, this is a
1204    // conservative estimate of when we have to schedule the next
1205    // request to not introduce any unecessary bubbles. In most cases
1206    // we will wake up sooner than we have to.
1207    nextReqTime = busBusyUntil - (tRP + tRCD + tCL);
1208
1209    // Update the stats and schedule the next request
1210    if (dram_pkt->isRead) {
1211        ++readsThisTime;
1212        if (row_hit)
1213            readRowHits++;
1214        bytesReadDRAM += burstSize;
1215        perBankRdBursts[dram_pkt->bankId]++;
1216
1217        // Update latency stats
1218        totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime;
1219        totBusLat += tBURST;
1220        totQLat += cmd_at - dram_pkt->entryTime;
1221    } else {
1222        ++writesThisTime;
1223        if (row_hit)
1224            writeRowHits++;
1225        bytesWritten += burstSize;
1226        perBankWrBursts[dram_pkt->bankId]++;
1227    }
1228}
1229
1230void
1231DRAMCtrl::processNextReqEvent()
1232{
1233    int busyRanks = 0;
1234    for (auto r : ranks) {
1235        if (!r->isAvailable()) {
1236            // rank is busy refreshing
1237            busyRanks++;
1238
1239            // let the rank know that if it was waiting to drain, it
1240            // is now done and ready to proceed
1241            r->checkDrainDone();
1242        }
1243    }
1244
1245    if (busyRanks == ranksPerChannel) {
1246        // if all ranks are refreshing wait for them to finish
1247        // and stall this state machine without taking any further
1248        // action, and do not schedule a new nextReqEvent
1249        return;
1250    }
1251
1252    // pre-emptively set to false.  Overwrite if in READ_TO_WRITE
1253    // or WRITE_TO_READ state
1254    bool switched_cmd_type = false;
1255    if (busState == READ_TO_WRITE) {
1256        DPRINTF(DRAM, "Switching to writes after %d reads with %d reads "
1257                "waiting\n", readsThisTime, readQueue.size());
1258
1259        // sample and reset the read-related stats as we are now
1260        // transitioning to writes, and all reads are done
1261        rdPerTurnAround.sample(readsThisTime);
1262        readsThisTime = 0;
1263
1264        // now proceed to do the actual writes
1265        busState = WRITE;
1266        switched_cmd_type = true;
1267    } else if (busState == WRITE_TO_READ) {
1268        DPRINTF(DRAM, "Switching to reads after %d writes with %d writes "
1269                "waiting\n", writesThisTime, writeQueue.size());
1270
1271        wrPerTurnAround.sample(writesThisTime);
1272        writesThisTime = 0;
1273
1274        busState = READ;
1275        switched_cmd_type = true;
1276    }
1277
1278    // when we get here it is either a read or a write
1279    if (busState == READ) {
1280
1281        // track if we should switch or not
1282        bool switch_to_writes = false;
1283
1284        if (readQueue.empty()) {
1285            // In the case there is no read request to go next,
1286            // trigger writes if we have passed the low threshold (or
1287            // if we are draining)
1288            if (!writeQueue.empty() &&
1289                (drainState() == DrainState::Draining ||
1290                 writeQueue.size() > writeLowThreshold)) {
1291
1292                switch_to_writes = true;
1293            } else {
1294                // check if we are drained
1295                if (drainState() == DrainState::Draining &&
1296                    respQueue.empty()) {
1297
1298                    DPRINTF(Drain, "DRAM controller done draining\n");
1299                    signalDrainDone();
1300                }
1301
1302                // nothing to do, not even any point in scheduling an
1303                // event for the next request
1304                return;
1305            }
1306        } else {
1307            // bool to check if there is a read to a free rank
1308            bool found_read = false;
1309
1310            // Figure out which read request goes next, and move it to the
1311            // front of the read queue
1312            // If we are changing command type, incorporate the minimum
1313            // bus turnaround delay which will be tCS (different rank) case
1314            found_read = chooseNext(readQueue,
1315                             switched_cmd_type ? tCS : 0);
1316
1317            // if no read to an available rank is found then return
1318            // at this point. There could be writes to the available ranks
1319            // which are above the required threshold. However, to
1320            // avoid adding more complexity to the code, return and wait
1321            // for a refresh event to kick things into action again.
1322            if (!found_read)
1323                return;
1324
1325            DRAMPacket* dram_pkt = readQueue.front();
1326            assert(dram_pkt->rankRef.isAvailable());
1327            // here we get a bit creative and shift the bus busy time not
1328            // just the tWTR, but also a CAS latency to capture the fact
1329            // that we are allowed to prepare a new bank, but not issue a
1330            // read command until after tWTR, in essence we capture a
1331            // bubble on the data bus that is tWTR + tCL
1332            if (switched_cmd_type && dram_pkt->rank == activeRank) {
1333                busBusyUntil += tWTR + tCL;
1334            }
1335
1336            doDRAMAccess(dram_pkt);
1337
1338            // At this point we're done dealing with the request
1339            readQueue.pop_front();
1340
1341            // sanity check
1342            assert(dram_pkt->size <= burstSize);
1343            assert(dram_pkt->readyTime >= curTick());
1344
1345            // Insert into response queue. It will be sent back to the
1346            // requestor at its readyTime
1347            if (respQueue.empty()) {
1348                assert(!respondEvent.scheduled());
1349                schedule(respondEvent, dram_pkt->readyTime);
1350            } else {
1351                assert(respQueue.back()->readyTime <= dram_pkt->readyTime);
1352                assert(respondEvent.scheduled());
1353            }
1354
1355            respQueue.push_back(dram_pkt);
1356
1357            // we have so many writes that we have to transition
1358            if (writeQueue.size() > writeHighThreshold) {
1359                switch_to_writes = true;
1360            }
1361        }
1362
1363        // switching to writes, either because the read queue is empty
1364        // and the writes have passed the low threshold (or we are
1365        // draining), or because the writes hit the hight threshold
1366        if (switch_to_writes) {
1367            // transition to writing
1368            busState = READ_TO_WRITE;
1369        }
1370    } else {
1371        // bool to check if write to free rank is found
1372        bool found_write = false;
1373
1374        // If we are changing command type, incorporate the minimum
1375        // bus turnaround delay
1376        found_write = chooseNext(writeQueue,
1377                                 switched_cmd_type ? std::min(tRTW, tCS) : 0);
1378
1379        // if no writes to an available rank are found then return.
1380        // There could be reads to the available ranks. However, to avoid
1381        // adding more complexity to the code, return at this point and wait
1382        // for a refresh event to kick things into action again.
1383        if (!found_write)
1384            return;
1385
1386        DRAMPacket* dram_pkt = writeQueue.front();
1387        assert(dram_pkt->rankRef.isAvailable());
1388        // sanity check
1389        assert(dram_pkt->size <= burstSize);
1390
1391        // add a bubble to the data bus, as defined by the
1392        // tRTW when access is to the same rank as previous burst
1393        // Different rank timing is handled with tCS, which is
1394        // applied to colAllowedAt
1395        if (switched_cmd_type && dram_pkt->rank == activeRank) {
1396            busBusyUntil += tRTW;
1397        }
1398
1399        doDRAMAccess(dram_pkt);
1400
1401        writeQueue.pop_front();
1402        isInWriteQueue.erase(burstAlign(dram_pkt->addr));
1403        delete dram_pkt;
1404
1405        // If we emptied the write queue, or got sufficiently below the
1406        // threshold (using the minWritesPerSwitch as the hysteresis) and
1407        // are not draining, or we have reads waiting and have done enough
1408        // writes, then switch to reads.
1409        if (writeQueue.empty() ||
1410            (writeQueue.size() + minWritesPerSwitch < writeLowThreshold &&
1411             drainState() != DrainState::Draining) ||
1412            (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) {
1413            // turn the bus back around for reads again
1414            busState = WRITE_TO_READ;
1415
1416            // note that the we switch back to reads also in the idle
1417            // case, which eventually will check for any draining and
1418            // also pause any further scheduling if there is really
1419            // nothing to do
1420        }
1421    }
1422    // It is possible that a refresh to another rank kicks things back into
1423    // action before reaching this point.
1424    if (!nextReqEvent.scheduled())
1425        schedule(nextReqEvent, std::max(nextReqTime, curTick()));
1426
1427    // If there is space available and we have writes waiting then let
1428    // them retry. This is done here to ensure that the retry does not
1429    // cause a nextReqEvent to be scheduled before we do so as part of
1430    // the next request processing
1431    if (retryWrReq && writeQueue.size() < writeBufferSize) {
1432        retryWrReq = false;
1433        port.sendRetryReq();
1434    }
1435}
1436
1437pair<uint64_t, bool>
1438DRAMCtrl::minBankPrep(const deque<DRAMPacket*>& queue,
1439                      Tick min_col_at) const
1440{
1441    uint64_t bank_mask = 0;
1442    Tick min_act_at = MaxTick;
1443
1444    // latest Tick for which ACT can occur without incurring additoinal
1445    // delay on the data bus
1446    const Tick hidden_act_max = std::max(min_col_at - tRCD, curTick());
1447
1448    // Flag condition when burst can issue back-to-back with previous burst
1449    bool found_seamless_bank = false;
1450
1451    // Flag condition when bank can be opened without incurring additional
1452    // delay on the data bus
1453    bool hidden_bank_prep = false;
1454
1455    // determine if we have queued transactions targetting the
1456    // bank in question
1457    vector<bool> got_waiting(ranksPerChannel * banksPerRank, false);
1458    for (const auto& p : queue) {
1459        if(p->rankRef.isAvailable())
1460            got_waiting[p->bankId] = true;
1461    }
1462
1463    // Find command with optimal bank timing
1464    // Will prioritize commands that can issue seamlessly.
1465    for (int i = 0; i < ranksPerChannel; i++) {
1466        for (int j = 0; j < banksPerRank; j++) {
1467            uint16_t bank_id = i * banksPerRank + j;
1468
1469            // if we have waiting requests for the bank, and it is
1470            // amongst the first available, update the mask
1471            if (got_waiting[bank_id]) {
1472                // make sure this rank is not currently refreshing.
1473                assert(ranks[i]->isAvailable());
1474                // simplistic approximation of when the bank can issue
1475                // an activate, ignoring any rank-to-rank switching
1476                // cost in this calculation
1477                Tick act_at = ranks[i]->banks[j].openRow == Bank::NO_ROW ?
1478                    std::max(ranks[i]->banks[j].actAllowedAt, curTick()) :
1479                    std::max(ranks[i]->banks[j].preAllowedAt, curTick()) + tRP;
1480
1481                // When is the earliest the R/W burst can issue?
1482                Tick col_at = std::max(ranks[i]->banks[j].colAllowedAt,
1483                                       act_at + tRCD);
1484
1485                // bank can issue burst back-to-back (seamlessly) with
1486                // previous burst
1487                bool new_seamless_bank = col_at <= min_col_at;
1488
1489                // if we found a new seamless bank or we have no
1490                // seamless banks, and got a bank with an earlier
1491                // activate time, it should be added to the bit mask
1492                if (new_seamless_bank ||
1493                    (!found_seamless_bank && act_at <= min_act_at)) {
1494                    // if we did not have a seamless bank before, and
1495                    // we do now, reset the bank mask, also reset it
1496                    // if we have not yet found a seamless bank and
1497                    // the activate time is smaller than what we have
1498                    // seen so far
1499                    if (!found_seamless_bank &&
1500                        (new_seamless_bank || act_at < min_act_at)) {
1501                        bank_mask = 0;
1502                    }
1503
1504                    found_seamless_bank |= new_seamless_bank;
1505
1506                    // ACT can occur 'behind the scenes'
1507                    hidden_bank_prep = act_at <= hidden_act_max;
1508
1509                    // set the bit corresponding to the available bank
1510                    replaceBits(bank_mask, bank_id, bank_id, 1);
1511                    min_act_at = act_at;
1512                }
1513            }
1514        }
1515    }
1516
1517    return make_pair(bank_mask, hidden_bank_prep);
1518}
1519
1520DRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p)
1521    : EventManager(&_memory), memory(_memory),
1522      pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), pwrStateTick(0),
1523      refreshState(REF_IDLE), refreshDueAt(0),
1524      power(_p, false), numBanksActive(0),
1525      activateEvent(*this), prechargeEvent(*this),
1526      refreshEvent(*this), powerEvent(*this)
1527{ }
1528
1529void
1530DRAMCtrl::Rank::startup(Tick ref_tick)
1531{
1532    assert(ref_tick > curTick());
1533
1534    pwrStateTick = curTick();
1535
1536    // kick off the refresh, and give ourselves enough time to
1537    // precharge
1538    schedule(refreshEvent, ref_tick);
1539}
1540
1541void
1542DRAMCtrl::Rank::suspend()
1543{
1544    deschedule(refreshEvent);
1545}
1546
1547void
1548DRAMCtrl::Rank::checkDrainDone()
1549{
1550    // if this rank was waiting to drain it is now able to proceed to
1551    // precharge
1552    if (refreshState == REF_DRAIN) {
1553        DPRINTF(DRAM, "Refresh drain done, now precharging\n");
1554
1555        refreshState = REF_PRE;
1556
1557        // hand control back to the refresh event loop
1558        schedule(refreshEvent, curTick());
1559    }
1560}
1561
1562void
1563DRAMCtrl::Rank::processActivateEvent()
1564{
1565    // we should transition to the active state as soon as any bank is active
1566    if (pwrState != PWR_ACT)
1567        // note that at this point numBanksActive could be back at
1568        // zero again due to a precharge scheduled in the future
1569        schedulePowerEvent(PWR_ACT, curTick());
1570}
1571
1572void
1573DRAMCtrl::Rank::processPrechargeEvent()
1574{
1575    // if we reached zero, then special conditions apply as we track
1576    // if all banks are precharged for the power models
1577    if (numBanksActive == 0) {
1578        // we should transition to the idle state when the last bank
1579        // is precharged
1580        schedulePowerEvent(PWR_IDLE, curTick());
1581    }
1582}
1583
1584void
1585DRAMCtrl::Rank::processRefreshEvent()
1586{
1587    // when first preparing the refresh, remember when it was due
1588    if (refreshState == REF_IDLE) {
1589        // remember when the refresh is due
1590        refreshDueAt = curTick();
1591
1592        // proceed to drain
1593        refreshState = REF_DRAIN;
1594
1595        DPRINTF(DRAM, "Refresh due\n");
1596    }
1597
1598    // let any scheduled read or write to the same rank go ahead,
1599    // after which it will
1600    // hand control back to this event loop
1601    if (refreshState == REF_DRAIN) {
1602        // if a request is at the moment being handled and this request is
1603        // accessing the current rank then wait for it to finish
1604        if ((rank == memory.activeRank)
1605            && (memory.nextReqEvent.scheduled())) {
1606            // hand control over to the request loop until it is
1607            // evaluated next
1608            DPRINTF(DRAM, "Refresh awaiting draining\n");
1609
1610            return;
1611        } else {
1612            refreshState = REF_PRE;
1613        }
1614    }
1615
1616    // at this point, ensure that all banks are precharged
1617    if (refreshState == REF_PRE) {
1618        // precharge any active bank if we are not already in the idle
1619        // state
1620        if (pwrState != PWR_IDLE) {
1621            // at the moment, we use a precharge all even if there is
1622            // only a single bank open
1623            DPRINTF(DRAM, "Precharging all\n");
1624
1625            // first determine when we can precharge
1626            Tick pre_at = curTick();
1627
1628            for (auto &b : banks) {
1629                // respect both causality and any existing bank
1630                // constraints, some banks could already have a
1631                // (auto) precharge scheduled
1632                pre_at = std::max(b.preAllowedAt, pre_at);
1633            }
1634
1635            // make sure all banks per rank are precharged, and for those that
1636            // already are, update their availability
1637            Tick act_allowed_at = pre_at + memory.tRP;
1638
1639            for (auto &b : banks) {
1640                if (b.openRow != Bank::NO_ROW) {
1641                    memory.prechargeBank(*this, b, pre_at, false);
1642                } else {
1643                    b.actAllowedAt = std::max(b.actAllowedAt, act_allowed_at);
1644                    b.preAllowedAt = std::max(b.preAllowedAt, pre_at);
1645                }
1646            }
1647
1648            // precharge all banks in rank
1649            power.powerlib.doCommand(MemCommand::PREA, 0,
1650                                     divCeil(pre_at, memory.tCK) -
1651                                     memory.timeStampOffset);
1652
1653            DPRINTF(DRAMPower, "%llu,PREA,0,%d\n",
1654                    divCeil(pre_at, memory.tCK) -
1655                            memory.timeStampOffset, rank);
1656        } else {
1657            DPRINTF(DRAM, "All banks already precharged, starting refresh\n");
1658
1659            // go ahead and kick the power state machine into gear if
1660            // we are already idle
1661            schedulePowerEvent(PWR_REF, curTick());
1662        }
1663
1664        refreshState = REF_RUN;
1665        assert(numBanksActive == 0);
1666
1667        // wait for all banks to be precharged, at which point the
1668        // power state machine will transition to the idle state, and
1669        // automatically move to a refresh, at that point it will also
1670        // call this method to get the refresh event loop going again
1671        return;
1672    }
1673
1674    // last but not least we perform the actual refresh
1675    if (refreshState == REF_RUN) {
1676        // should never get here with any banks active
1677        assert(numBanksActive == 0);
1678        assert(pwrState == PWR_REF);
1679
1680        Tick ref_done_at = curTick() + memory.tRFC;
1681
1682        for (auto &b : banks) {
1683            b.actAllowedAt = ref_done_at;
1684        }
1685
1686        // at the moment this affects all ranks
1687        power.powerlib.doCommand(MemCommand::REF, 0,
1688                                 divCeil(curTick(), memory.tCK) -
1689                                 memory.timeStampOffset);
1690
1691        // at the moment sort the list of commands and update the counters
1692        // for DRAMPower libray when doing a refresh
1693        sort(power.powerlib.cmdList.begin(),
1694             power.powerlib.cmdList.end(), DRAMCtrl::sortTime);
1695
1696        // update the counters for DRAMPower, passing false to
1697        // indicate that this is not the last command in the
1698        // list. DRAMPower requires this information for the
1699        // correct calculation of the background energy at the end
1700        // of the simulation. Ideally we would want to call this
1701        // function with true once at the end of the
1702        // simulation. However, the discarded energy is extremly
1703        // small and does not effect the final results.
1704        power.powerlib.updateCounters(false);
1705
1706        // call the energy function
1707        power.powerlib.calcEnergy();
1708
1709        // Update the stats
1710        updatePowerStats();
1711
1712        DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), memory.tCK) -
1713                memory.timeStampOffset, rank);
1714
1715        // make sure we did not wait so long that we cannot make up
1716        // for it
1717        if (refreshDueAt + memory.tREFI < ref_done_at) {
1718            fatal("Refresh was delayed so long we cannot catch up\n");
1719        }
1720
1721        // compensate for the delay in actually performing the refresh
1722        // when scheduling the next one
1723        schedule(refreshEvent, refreshDueAt + memory.tREFI - memory.tRP);
1724
1725        assert(!powerEvent.scheduled());
1726
1727        // move to the idle power state once the refresh is done, this
1728        // will also move the refresh state machine to the refresh
1729        // idle state
1730        schedulePowerEvent(PWR_IDLE, ref_done_at);
1731
1732        DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n",
1733                ref_done_at, refreshDueAt + memory.tREFI);
1734    }
1735}
1736
1737void
1738DRAMCtrl::Rank::schedulePowerEvent(PowerState pwr_state, Tick tick)
1739{
1740    // respect causality
1741    assert(tick >= curTick());
1742
1743    if (!powerEvent.scheduled()) {
1744        DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n",
1745                tick, pwr_state);
1746
1747        // insert the new transition
1748        pwrStateTrans = pwr_state;
1749
1750        schedule(powerEvent, tick);
1751    } else {
1752        panic("Scheduled power event at %llu to state %d, "
1753              "with scheduled event at %llu to %d\n", tick, pwr_state,
1754              powerEvent.when(), pwrStateTrans);
1755    }
1756}
1757
1758void
1759DRAMCtrl::Rank::processPowerEvent()
1760{
1761    // remember where we were, and for how long
1762    Tick duration = curTick() - pwrStateTick;
1763    PowerState prev_state = pwrState;
1764
1765    // update the accounting
1766    pwrStateTime[prev_state] += duration;
1767
1768    pwrState = pwrStateTrans;
1769    pwrStateTick = curTick();
1770
1771    if (pwrState == PWR_IDLE) {
1772        DPRINTF(DRAMState, "All banks precharged\n");
1773
1774        // if we were refreshing, make sure we start scheduling requests again
1775        if (prev_state == PWR_REF) {
1776            DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration);
1777            assert(pwrState == PWR_IDLE);
1778
1779            // kick things into action again
1780            refreshState = REF_IDLE;
1781            // a request event could be already scheduled by the state
1782            // machine of the other rank
1783            if (!memory.nextReqEvent.scheduled())
1784                schedule(memory.nextReqEvent, curTick());
1785        } else {
1786            assert(prev_state == PWR_ACT);
1787
1788            // if we have a pending refresh, and are now moving to
1789            // the idle state, direclty transition to a refresh
1790            if (refreshState == REF_RUN) {
1791                // there should be nothing waiting at this point
1792                assert(!powerEvent.scheduled());
1793
1794                // update the state in zero time and proceed below
1795                pwrState = PWR_REF;
1796            }
1797        }
1798    }
1799
1800    // we transition to the refresh state, let the refresh state
1801    // machine know of this state update and let it deal with the
1802    // scheduling of the next power state transition as well as the
1803    // following refresh
1804    if (pwrState == PWR_REF) {
1805        DPRINTF(DRAMState, "Refreshing\n");
1806        // kick the refresh event loop into action again, and that
1807        // in turn will schedule a transition to the idle power
1808        // state once the refresh is done
1809        assert(refreshState == REF_RUN);
1810        processRefreshEvent();
1811    }
1812}
1813
1814void
1815DRAMCtrl::Rank::updatePowerStats()
1816{
1817    // Get the energy and power from DRAMPower
1818    Data::MemoryPowerModel::Energy energy =
1819        power.powerlib.getEnergy();
1820    Data::MemoryPowerModel::Power rank_power =
1821        power.powerlib.getPower();
1822
1823    actEnergy = energy.act_energy * memory.devicesPerRank;
1824    preEnergy = energy.pre_energy * memory.devicesPerRank;
1825    readEnergy = energy.read_energy * memory.devicesPerRank;
1826    writeEnergy = energy.write_energy * memory.devicesPerRank;
1827    refreshEnergy = energy.ref_energy * memory.devicesPerRank;
1828    actBackEnergy = energy.act_stdby_energy * memory.devicesPerRank;
1829    preBackEnergy = energy.pre_stdby_energy * memory.devicesPerRank;
1830    totalEnergy = energy.total_energy * memory.devicesPerRank;
1831    averagePower = rank_power.average_power * memory.devicesPerRank;
1832}
1833
1834void
1835DRAMCtrl::Rank::regStats()
1836{
1837    using namespace Stats;
1838
1839    pwrStateTime
1840        .init(5)
1841        .name(name() + ".memoryStateTime")
1842        .desc("Time in different power states");
1843    pwrStateTime.subname(0, "IDLE");
1844    pwrStateTime.subname(1, "REF");
1845    pwrStateTime.subname(2, "PRE_PDN");
1846    pwrStateTime.subname(3, "ACT");
1847    pwrStateTime.subname(4, "ACT_PDN");
1848
1849    actEnergy
1850        .name(name() + ".actEnergy")
1851        .desc("Energy for activate commands per rank (pJ)");
1852
1853    preEnergy
1854        .name(name() + ".preEnergy")
1855        .desc("Energy for precharge commands per rank (pJ)");
1856
1857    readEnergy
1858        .name(name() + ".readEnergy")
1859        .desc("Energy for read commands per rank (pJ)");
1860
1861    writeEnergy
1862        .name(name() + ".writeEnergy")
1863        .desc("Energy for write commands per rank (pJ)");
1864
1865    refreshEnergy
1866        .name(name() + ".refreshEnergy")
1867        .desc("Energy for refresh commands per rank (pJ)");
1868
1869    actBackEnergy
1870        .name(name() + ".actBackEnergy")
1871        .desc("Energy for active background per rank (pJ)");
1872
1873    preBackEnergy
1874        .name(name() + ".preBackEnergy")
1875        .desc("Energy for precharge background per rank (pJ)");
1876
1877    totalEnergy
1878        .name(name() + ".totalEnergy")
1879        .desc("Total energy per rank (pJ)");
1880
1881    averagePower
1882        .name(name() + ".averagePower")
1883        .desc("Core power per rank (mW)");
1884}
1885void
1886DRAMCtrl::regStats()
1887{
1888    using namespace Stats;
1889
1890    AbstractMemory::regStats();
1891
1892    for (auto r : ranks) {
1893        r->regStats();
1894    }
1895
1896    readReqs
1897        .name(name() + ".readReqs")
1898        .desc("Number of read requests accepted");
1899
1900    writeReqs
1901        .name(name() + ".writeReqs")
1902        .desc("Number of write requests accepted");
1903
1904    readBursts
1905        .name(name() + ".readBursts")
1906        .desc("Number of DRAM read bursts, "
1907              "including those serviced by the write queue");
1908
1909    writeBursts
1910        .name(name() + ".writeBursts")
1911        .desc("Number of DRAM write bursts, "
1912              "including those merged in the write queue");
1913
1914    servicedByWrQ
1915        .name(name() + ".servicedByWrQ")
1916        .desc("Number of DRAM read bursts serviced by the write queue");
1917
1918    mergedWrBursts
1919        .name(name() + ".mergedWrBursts")
1920        .desc("Number of DRAM write bursts merged with an existing one");
1921
1922    neitherReadNorWrite
1923        .name(name() + ".neitherReadNorWriteReqs")
1924        .desc("Number of requests that are neither read nor write");
1925
1926    perBankRdBursts
1927        .init(banksPerRank * ranksPerChannel)
1928        .name(name() + ".perBankRdBursts")
1929        .desc("Per bank write bursts");
1930
1931    perBankWrBursts
1932        .init(banksPerRank * ranksPerChannel)
1933        .name(name() + ".perBankWrBursts")
1934        .desc("Per bank write bursts");
1935
1936    avgRdQLen
1937        .name(name() + ".avgRdQLen")
1938        .desc("Average read queue length when enqueuing")
1939        .precision(2);
1940
1941    avgWrQLen
1942        .name(name() + ".avgWrQLen")
1943        .desc("Average write queue length when enqueuing")
1944        .precision(2);
1945
1946    totQLat
1947        .name(name() + ".totQLat")
1948        .desc("Total ticks spent queuing");
1949
1950    totBusLat
1951        .name(name() + ".totBusLat")
1952        .desc("Total ticks spent in databus transfers");
1953
1954    totMemAccLat
1955        .name(name() + ".totMemAccLat")
1956        .desc("Total ticks spent from burst creation until serviced "
1957              "by the DRAM");
1958
1959    avgQLat
1960        .name(name() + ".avgQLat")
1961        .desc("Average queueing delay per DRAM burst")
1962        .precision(2);
1963
1964    avgQLat = totQLat / (readBursts - servicedByWrQ);
1965
1966    avgBusLat
1967        .name(name() + ".avgBusLat")
1968        .desc("Average bus latency per DRAM burst")
1969        .precision(2);
1970
1971    avgBusLat = totBusLat / (readBursts - servicedByWrQ);
1972
1973    avgMemAccLat
1974        .name(name() + ".avgMemAccLat")
1975        .desc("Average memory access latency per DRAM burst")
1976        .precision(2);
1977
1978    avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ);
1979
1980    numRdRetry
1981        .name(name() + ".numRdRetry")
1982        .desc("Number of times read queue was full causing retry");
1983
1984    numWrRetry
1985        .name(name() + ".numWrRetry")
1986        .desc("Number of times write queue was full causing retry");
1987
1988    readRowHits
1989        .name(name() + ".readRowHits")
1990        .desc("Number of row buffer hits during reads");
1991
1992    writeRowHits
1993        .name(name() + ".writeRowHits")
1994        .desc("Number of row buffer hits during writes");
1995
1996    readRowHitRate
1997        .name(name() + ".readRowHitRate")
1998        .desc("Row buffer hit rate for reads")
1999        .precision(2);
2000
2001    readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100;
2002
2003    writeRowHitRate
2004        .name(name() + ".writeRowHitRate")
2005        .desc("Row buffer hit rate for writes")
2006        .precision(2);
2007
2008    writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100;
2009
2010    readPktSize
2011        .init(ceilLog2(burstSize) + 1)
2012        .name(name() + ".readPktSize")
2013        .desc("Read request sizes (log2)");
2014
2015     writePktSize
2016        .init(ceilLog2(burstSize) + 1)
2017        .name(name() + ".writePktSize")
2018        .desc("Write request sizes (log2)");
2019
2020     rdQLenPdf
2021        .init(readBufferSize)
2022        .name(name() + ".rdQLenPdf")
2023        .desc("What read queue length does an incoming req see");
2024
2025     wrQLenPdf
2026        .init(writeBufferSize)
2027        .name(name() + ".wrQLenPdf")
2028        .desc("What write queue length does an incoming req see");
2029
2030     bytesPerActivate
2031         .init(maxAccessesPerRow)
2032         .name(name() + ".bytesPerActivate")
2033         .desc("Bytes accessed per row activation")
2034         .flags(nozero);
2035
2036     rdPerTurnAround
2037         .init(readBufferSize)
2038         .name(name() + ".rdPerTurnAround")
2039         .desc("Reads before turning the bus around for writes")
2040         .flags(nozero);
2041
2042     wrPerTurnAround
2043         .init(writeBufferSize)
2044         .name(name() + ".wrPerTurnAround")
2045         .desc("Writes before turning the bus around for reads")
2046         .flags(nozero);
2047
2048    bytesReadDRAM
2049        .name(name() + ".bytesReadDRAM")
2050        .desc("Total number of bytes read from DRAM");
2051
2052    bytesReadWrQ
2053        .name(name() + ".bytesReadWrQ")
2054        .desc("Total number of bytes read from write queue");
2055
2056    bytesWritten
2057        .name(name() + ".bytesWritten")
2058        .desc("Total number of bytes written to DRAM");
2059
2060    bytesReadSys
2061        .name(name() + ".bytesReadSys")
2062        .desc("Total read bytes from the system interface side");
2063
2064    bytesWrittenSys
2065        .name(name() + ".bytesWrittenSys")
2066        .desc("Total written bytes from the system interface side");
2067
2068    avgRdBW
2069        .name(name() + ".avgRdBW")
2070        .desc("Average DRAM read bandwidth in MiByte/s")
2071        .precision(2);
2072
2073    avgRdBW = (bytesReadDRAM / 1000000) / simSeconds;
2074
2075    avgWrBW
2076        .name(name() + ".avgWrBW")
2077        .desc("Average achieved write bandwidth in MiByte/s")
2078        .precision(2);
2079
2080    avgWrBW = (bytesWritten / 1000000) / simSeconds;
2081
2082    avgRdBWSys
2083        .name(name() + ".avgRdBWSys")
2084        .desc("Average system read bandwidth in MiByte/s")
2085        .precision(2);
2086
2087    avgRdBWSys = (bytesReadSys / 1000000) / simSeconds;
2088
2089    avgWrBWSys
2090        .name(name() + ".avgWrBWSys")
2091        .desc("Average system write bandwidth in MiByte/s")
2092        .precision(2);
2093
2094    avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds;
2095
2096    peakBW
2097        .name(name() + ".peakBW")
2098        .desc("Theoretical peak bandwidth in MiByte/s")
2099        .precision(2);
2100
2101    peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000;
2102
2103    busUtil
2104        .name(name() + ".busUtil")
2105        .desc("Data bus utilization in percentage")
2106        .precision(2);
2107    busUtil = (avgRdBW + avgWrBW) / peakBW * 100;
2108
2109    totGap
2110        .name(name() + ".totGap")
2111        .desc("Total gap between requests");
2112
2113    avgGap
2114        .name(name() + ".avgGap")
2115        .desc("Average gap between requests")
2116        .precision(2);
2117
2118    avgGap = totGap / (readReqs + writeReqs);
2119
2120    // Stats for DRAM Power calculation based on Micron datasheet
2121    busUtilRead
2122        .name(name() + ".busUtilRead")
2123        .desc("Data bus utilization in percentage for reads")
2124        .precision(2);
2125
2126    busUtilRead = avgRdBW / peakBW * 100;
2127
2128    busUtilWrite
2129        .name(name() + ".busUtilWrite")
2130        .desc("Data bus utilization in percentage for writes")
2131        .precision(2);
2132
2133    busUtilWrite = avgWrBW / peakBW * 100;
2134
2135    pageHitRate
2136        .name(name() + ".pageHitRate")
2137        .desc("Row buffer hit rate, read and write combined")
2138        .precision(2);
2139
2140    pageHitRate = (writeRowHits + readRowHits) /
2141        (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100;
2142}
2143
2144void
2145DRAMCtrl::recvFunctional(PacketPtr pkt)
2146{
2147    // rely on the abstract memory
2148    functionalAccess(pkt);
2149}
2150
2151BaseSlavePort&
2152DRAMCtrl::getSlavePort(const string &if_name, PortID idx)
2153{
2154    if (if_name != "port") {
2155        return MemObject::getSlavePort(if_name, idx);
2156    } else {
2157        return port;
2158    }
2159}
2160
2161DrainState
2162DRAMCtrl::drain()
2163{
2164    // if there is anything in any of our internal queues, keep track
2165    // of that as well
2166    if (!(writeQueue.empty() && readQueue.empty() && respQueue.empty())) {
2167        DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d,"
2168                " resp: %d\n", writeQueue.size(), readQueue.size(),
2169                respQueue.size());
2170
2171        // the only part that is not drained automatically over time
2172        // is the write queue, thus kick things into action if needed
2173        if (!writeQueue.empty() && !nextReqEvent.scheduled()) {
2174            schedule(nextReqEvent, curTick());
2175        }
2176        return DrainState::Draining;
2177    } else {
2178        return DrainState::Drained;
2179    }
2180}
2181
2182void
2183DRAMCtrl::drainResume()
2184{
2185    if (!isTimingMode && system()->isTimingMode()) {
2186        // if we switched to timing mode, kick things into action,
2187        // and behave as if we restored from a checkpoint
2188        startup();
2189    } else if (isTimingMode && !system()->isTimingMode()) {
2190        // if we switch from timing mode, stop the refresh events to
2191        // not cause issues with KVM
2192        for (auto r : ranks) {
2193            r->suspend();
2194        }
2195    }
2196
2197    // update the mode
2198    isTimingMode = system()->isTimingMode();
2199}
2200
2201DRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory)
2202    : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this),
2203      memory(_memory)
2204{ }
2205
2206AddrRangeList
2207DRAMCtrl::MemoryPort::getAddrRanges() const
2208{
2209    AddrRangeList ranges;
2210    ranges.push_back(memory.getAddrRange());
2211    return ranges;
2212}
2213
2214void
2215DRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt)
2216{
2217    pkt->pushLabel(memory.name());
2218
2219    if (!queue.checkFunctional(pkt)) {
2220        // Default implementation of SimpleTimingPort::recvFunctional()
2221        // calls recvAtomic() and throws away the latency; we can save a
2222        // little here by just not calculating the latency.
2223        memory.recvFunctional(pkt);
2224    }
2225
2226    pkt->popLabel();
2227}
2228
2229Tick
2230DRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt)
2231{
2232    return memory.recvAtomic(pkt);
2233}
2234
2235bool
2236DRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt)
2237{
2238    // pass it to the memory controller
2239    return memory.recvTimingReq(pkt);
2240}
2241
2242DRAMCtrl*
2243DRAMCtrlParams::create()
2244{
2245    return new DRAMCtrl(this);
2246}
2247