dram_ctrl.cc revision 10620
19243SN/A/* 210206Sandreas.hansson@arm.com * Copyright (c) 2010-2014 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 4310618SOmar.Naji@arm.com * Omar Naji 449243SN/A */ 459243SN/A 4610146Sandreas.hansson@arm.com#include "base/bitfield.hh" 479356SN/A#include "base/trace.hh" 4810146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 4910247Sandreas.hansson@arm.com#include "debug/DRAMPower.hh" 5010208Sandreas.hansson@arm.com#include "debug/DRAMState.hh" 519352SN/A#include "debug/Drain.hh" 5210146Sandreas.hansson@arm.com#include "mem/dram_ctrl.hh" 539814SN/A#include "sim/system.hh" 549243SN/A 559243SN/Ausing namespace std; 5610432SOmar.Naji@arm.comusing namespace Data; 579243SN/A 5810146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 599243SN/A AbstractMemory(p), 6010619Sandreas.hansson@arm.com port(name() + ".port", *this), isTimingMode(false), 619243SN/A retryRdReq(false), retryWrReq(false), 6210211Sandreas.hansson@arm.com busState(READ), 6310618SOmar.Naji@arm.com nextReqEvent(this), respondEvent(this), 6410208Sandreas.hansson@arm.com drainManager(NULL), 6510489SOmar.Naji@arm.com deviceSize(p->device_size), 669831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 679831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 689831SN/A devicesPerRank(p->devices_per_rank), 699831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 709831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 7110140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 7210286Sandreas.hansson@arm.com columnsPerStripe(range.granularity() / burstSize), 739243SN/A ranksPerChannel(p->ranks_per_channel), 7410394Swendy.elsasser@arm.com bankGroupsPerRank(p->bank_groups_per_rank), 7510394Swendy.elsasser@arm.com bankGroupArch(p->bank_groups_per_rank > 0), 769566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 779243SN/A readBufferSize(p->read_buffer_size), 789243SN/A writeBufferSize(p->write_buffer_size), 7910140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 8010140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 8110147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 8210147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 8310393Swendy.elsasser@arm.com tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST), 8410394Swendy.elsasser@arm.com tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), 8510394Swendy.elsasser@arm.com tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 8610394Swendy.elsasser@arm.com tRRD_L(p->tRRD_L), tXAW(p->tXAW), activationLimit(p->activation_limit), 879243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 889243SN/A pageMgmt(p->page_policy), 8910141SN/A maxAccessesPerRow(p->max_accesses_per_row), 909726SN/A frontendLatency(p->static_frontend_latency), 919726SN/A backendLatency(p->static_backend_latency), 9210618SOmar.Naji@arm.com busBusyUntil(0), prevArrival(0), 9310618SOmar.Naji@arm.com nextReqTime(0), activeRank(0), timeStampOffset(0) 949243SN/A{ 9510620Sandreas.hansson@arm.com // sanity check the ranks since we rely on bit slicing for the 9610620Sandreas.hansson@arm.com // address decoding 9710620Sandreas.hansson@arm.com fatal_if(!isPowerOf2(ranksPerChannel), "DRAM rank count of %d is not " 9810620Sandreas.hansson@arm.com "allowed, must be a power of two\n", ranksPerChannel); 9910620Sandreas.hansson@arm.com 10010618SOmar.Naji@arm.com for (int i = 0; i < ranksPerChannel; i++) { 10110618SOmar.Naji@arm.com Rank* rank = new Rank(*this, p); 10210618SOmar.Naji@arm.com ranks.push_back(rank); 10310432SOmar.Naji@arm.com 10410618SOmar.Naji@arm.com rank->actTicks.resize(activationLimit, 0); 10510618SOmar.Naji@arm.com rank->banks.resize(banksPerRank); 10610618SOmar.Naji@arm.com rank->rank = i; 10710432SOmar.Naji@arm.com 10810246Sandreas.hansson@arm.com for (int b = 0; b < banksPerRank; b++) { 10910618SOmar.Naji@arm.com rank->banks[b].bank = b; 11010561SOmar.Naji@arm.com // GDDR addressing of banks to BG is linear. 11110561SOmar.Naji@arm.com // Here we assume that all DRAM generations address bank groups as 11210561SOmar.Naji@arm.com // follows: 11310394Swendy.elsasser@arm.com if (bankGroupArch) { 11410394Swendy.elsasser@arm.com // Simply assign lower bits to bank group in order to 11510394Swendy.elsasser@arm.com // rotate across bank groups as banks are incremented 11610394Swendy.elsasser@arm.com // e.g. with 4 banks per bank group and 16 banks total: 11710394Swendy.elsasser@arm.com // banks 0,4,8,12 are in bank group 0 11810394Swendy.elsasser@arm.com // banks 1,5,9,13 are in bank group 1 11910394Swendy.elsasser@arm.com // banks 2,6,10,14 are in bank group 2 12010394Swendy.elsasser@arm.com // banks 3,7,11,15 are in bank group 3 12110618SOmar.Naji@arm.com rank->banks[b].bankgr = b % bankGroupsPerRank; 12210394Swendy.elsasser@arm.com } else { 12310394Swendy.elsasser@arm.com // No bank groups; simply assign to bank number 12410618SOmar.Naji@arm.com rank->banks[b].bankgr = b; 12510394Swendy.elsasser@arm.com } 12610246Sandreas.hansson@arm.com } 12710246Sandreas.hansson@arm.com } 12810246Sandreas.hansson@arm.com 12910140SN/A // perform a basic check of the write thresholds 13010140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 13110140SN/A fatal("Write buffer low threshold %d must be smaller than the " 13210140SN/A "high threshold %d\n", p->write_low_thresh_perc, 13310140SN/A p->write_high_thresh_perc); 1349243SN/A 1359243SN/A // determine the rows per bank by looking at the total capacity 1369567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1379243SN/A 13810489SOmar.Naji@arm.com // determine the dram actual capacity from the DRAM config in Mbytes 13910489SOmar.Naji@arm.com uint64_t deviceCapacity = deviceSize / (1024 * 1024) * devicesPerRank * 14010489SOmar.Naji@arm.com ranksPerChannel; 14110489SOmar.Naji@arm.com 14210489SOmar.Naji@arm.com // if actual DRAM size does not match memory capacity in system warn! 14310489SOmar.Naji@arm.com if (deviceCapacity != capacity / (1024 * 1024)) 14410489SOmar.Naji@arm.com warn("DRAM device capacity (%d Mbytes) does not match the " 14510489SOmar.Naji@arm.com "address range assigned (%d Mbytes)\n", deviceCapacity, 14610489SOmar.Naji@arm.com capacity / (1024 * 1024)); 14710489SOmar.Naji@arm.com 1489243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1499243SN/A AbstractMemory::size()); 1509831SN/A 1519831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1529831SN/A rowBufferSize, columnsPerRowBuffer); 1539831SN/A 1549831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1559243SN/A 15610286Sandreas.hansson@arm.com // a bit of sanity checks on the interleaving 1579566SN/A if (range.interleaved()) { 1589566SN/A if (channels != range.stripes()) 15910143SN/A fatal("%s has %d interleaved address stripes but %d channel(s)\n", 1609566SN/A name(), range.stripes(), channels); 1619566SN/A 16210136SN/A if (addrMapping == Enums::RoRaBaChCo) { 1639831SN/A if (rowBufferSize != range.granularity()) { 16410286Sandreas.hansson@arm.com fatal("Channel interleaving of %s doesn't match RoRaBaChCo " 16510136SN/A "address map\n", name()); 1669566SN/A } 16710286Sandreas.hansson@arm.com } else if (addrMapping == Enums::RoRaBaCoCh || 16810286Sandreas.hansson@arm.com addrMapping == Enums::RoCoRaBaCh) { 16910286Sandreas.hansson@arm.com // for the interleavings with channel bits in the bottom, 17010286Sandreas.hansson@arm.com // if the system uses a channel striping granularity that 17110286Sandreas.hansson@arm.com // is larger than the DRAM burst size, then map the 17210286Sandreas.hansson@arm.com // sequential accesses within a stripe to a number of 17310286Sandreas.hansson@arm.com // columns in the DRAM, effectively placing some of the 17410286Sandreas.hansson@arm.com // lower-order column bits as the least-significant bits 17510286Sandreas.hansson@arm.com // of the address (above the ones denoting the burst size) 17610286Sandreas.hansson@arm.com assert(columnsPerStripe >= 1); 17710286Sandreas.hansson@arm.com 17810286Sandreas.hansson@arm.com // channel striping has to be done at a granularity that 17910286Sandreas.hansson@arm.com // is equal or larger to a cache line 18010286Sandreas.hansson@arm.com if (system()->cacheLineSize() > range.granularity()) { 18110286Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at least as large " 18210286Sandreas.hansson@arm.com "as the cache line size\n", name()); 1839669SN/A } 18410286Sandreas.hansson@arm.com 18510286Sandreas.hansson@arm.com // ...and equal or smaller than the row-buffer size 18610286Sandreas.hansson@arm.com if (rowBufferSize < range.granularity()) { 18710286Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at most as large " 18810286Sandreas.hansson@arm.com "as the row-buffer size\n", name()); 18910286Sandreas.hansson@arm.com } 19010286Sandreas.hansson@arm.com // this is essentially the check above, so just to be sure 19110286Sandreas.hansson@arm.com assert(columnsPerStripe <= columnsPerRowBuffer); 1929566SN/A } 1939566SN/A } 19410207Sandreas.hansson@arm.com 19510207Sandreas.hansson@arm.com // some basic sanity checks 19610207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 19710207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 19810207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 19910207Sandreas.hansson@arm.com } 20010394Swendy.elsasser@arm.com 20110394Swendy.elsasser@arm.com // basic bank group architecture checks -> 20210394Swendy.elsasser@arm.com if (bankGroupArch) { 20310394Swendy.elsasser@arm.com // must have at least one bank per bank group 20410394Swendy.elsasser@arm.com if (bankGroupsPerRank > banksPerRank) { 20510394Swendy.elsasser@arm.com fatal("banks per rank (%d) must be equal to or larger than " 20610394Swendy.elsasser@arm.com "banks groups per rank (%d)\n", 20710394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 20810394Swendy.elsasser@arm.com } 20910394Swendy.elsasser@arm.com // must have same number of banks in each bank group 21010394Swendy.elsasser@arm.com if ((banksPerRank % bankGroupsPerRank) != 0) { 21110394Swendy.elsasser@arm.com fatal("Banks per rank (%d) must be evenly divisible by bank groups " 21210394Swendy.elsasser@arm.com "per rank (%d) for equal banks per bank group\n", 21310394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 21410394Swendy.elsasser@arm.com } 21510394Swendy.elsasser@arm.com // tCCD_L should be greater than minimal, back-to-back burst delay 21610394Swendy.elsasser@arm.com if (tCCD_L <= tBURST) { 21710394Swendy.elsasser@arm.com fatal("tCCD_L (%d) should be larger than tBURST (%d) when " 21810394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 21910394Swendy.elsasser@arm.com tCCD_L, tBURST, bankGroupsPerRank); 22010394Swendy.elsasser@arm.com } 22110394Swendy.elsasser@arm.com // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay 22210561SOmar.Naji@arm.com // some datasheets might specify it equal to tRRD 22310561SOmar.Naji@arm.com if (tRRD_L < tRRD) { 22410394Swendy.elsasser@arm.com fatal("tRRD_L (%d) should be larger than tRRD (%d) when " 22510394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 22610394Swendy.elsasser@arm.com tRRD_L, tRRD, bankGroupsPerRank); 22710394Swendy.elsasser@arm.com } 22810394Swendy.elsasser@arm.com } 22910394Swendy.elsasser@arm.com 2309243SN/A} 2319243SN/A 2329243SN/Avoid 23310146Sandreas.hansson@arm.comDRAMCtrl::init() 23410140SN/A{ 23510466Sandreas.hansson@arm.com AbstractMemory::init(); 23610466Sandreas.hansson@arm.com 23710466Sandreas.hansson@arm.com if (!port.isConnected()) { 23810146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 23910140SN/A } else { 24010140SN/A port.sendRangeChange(); 24110140SN/A } 24210140SN/A} 24310140SN/A 24410140SN/Avoid 24510146Sandreas.hansson@arm.comDRAMCtrl::startup() 2469243SN/A{ 24710619Sandreas.hansson@arm.com // remember the memory system mode of operation 24810619Sandreas.hansson@arm.com isTimingMode = system()->isTimingMode(); 24910618SOmar.Naji@arm.com 25010619Sandreas.hansson@arm.com if (isTimingMode) { 25110619Sandreas.hansson@arm.com // timestamp offset should be in clock cycles for DRAMPower 25210619Sandreas.hansson@arm.com timeStampOffset = divCeil(curTick(), tCK); 25310619Sandreas.hansson@arm.com 25410619Sandreas.hansson@arm.com // update the start tick for the precharge accounting to the 25510619Sandreas.hansson@arm.com // current tick 25610619Sandreas.hansson@arm.com for (auto r : ranks) { 25710619Sandreas.hansson@arm.com r->startup(curTick() + tREFI - tRP); 25810619Sandreas.hansson@arm.com } 25910619Sandreas.hansson@arm.com 26010619Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 26110619Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 26210619Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 26310619Sandreas.hansson@arm.com // start of simulation 26410619Sandreas.hansson@arm.com busBusyUntil = curTick() + tRP + tRCD + tCL; 26510618SOmar.Naji@arm.com } 2669243SN/A} 2679243SN/A 2689243SN/ATick 26910146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 2709243SN/A{ 2719243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 2729243SN/A 2739243SN/A // do the actual memory access and turn the packet into a response 2749243SN/A access(pkt); 2759243SN/A 2769243SN/A Tick latency = 0; 2779243SN/A if (!pkt->memInhibitAsserted() && pkt->hasData()) { 2789243SN/A // this value is not supposed to be accurate, just enough to 2799243SN/A // keep things going, mimic a closed page 2809243SN/A latency = tRP + tRCD + tCL; 2819243SN/A } 2829243SN/A return latency; 2839243SN/A} 2849243SN/A 2859243SN/Abool 28610146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 2879243SN/A{ 2889831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 2899831SN/A readBufferSize, readQueue.size() + respQueue.size(), 2909831SN/A neededEntries); 2919243SN/A 2929831SN/A return 2939831SN/A (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 2949243SN/A} 2959243SN/A 2969243SN/Abool 29710146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 2989243SN/A{ 2999831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 3009831SN/A writeBufferSize, writeQueue.size(), neededEntries); 3019831SN/A return (writeQueue.size() + neededEntries) > writeBufferSize; 3029243SN/A} 3039243SN/A 30410146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 30510146Sandreas.hansson@arm.comDRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 30610143SN/A bool isRead) 3079243SN/A{ 3089669SN/A // decode the address based on the address mapping scheme, with 30910136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 31010136SN/A // channel, respectively 3119243SN/A uint8_t rank; 3129967SN/A uint8_t bank; 31310245Sandreas.hansson@arm.com // use a 64-bit unsigned during the computations as the row is 31410245Sandreas.hansson@arm.com // always the top bits, and check before creating the DRAMPacket 31510245Sandreas.hansson@arm.com uint64_t row; 3169243SN/A 31710286Sandreas.hansson@arm.com // truncate the address to a DRAM burst, which makes it unique to 31810286Sandreas.hansson@arm.com // a specific column, row, bank, rank and channel 3199831SN/A Addr addr = dramPktAddr / burstSize; 3209243SN/A 3219491SN/A // we have removed the lowest order address bits that denote the 3229831SN/A // position within the column 32310136SN/A if (addrMapping == Enums::RoRaBaChCo) { 3249491SN/A // the lowest order bits denote the column to ensure that 3259491SN/A // sequential cache lines occupy the same row 3269831SN/A addr = addr / columnsPerRowBuffer; 3279243SN/A 3289669SN/A // take out the channel part of the address 3299566SN/A addr = addr / channels; 3309566SN/A 3319669SN/A // after the channel bits, get the bank bits to interleave 3329669SN/A // over the banks 3339669SN/A bank = addr % banksPerRank; 3349669SN/A addr = addr / banksPerRank; 3359669SN/A 3369669SN/A // after the bank, we get the rank bits which thus interleaves 3379669SN/A // over the ranks 3389669SN/A rank = addr % ranksPerChannel; 3399669SN/A addr = addr / ranksPerChannel; 3409669SN/A 3419669SN/A // lastly, get the row bits 3429669SN/A row = addr % rowsPerBank; 3439669SN/A addr = addr / rowsPerBank; 34410136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 34510286Sandreas.hansson@arm.com // take out the lower-order column bits 34610286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 34710286Sandreas.hansson@arm.com 3489669SN/A // take out the channel part of the address 3499669SN/A addr = addr / channels; 3509669SN/A 35110286Sandreas.hansson@arm.com // next, the higher-order column bites 35210286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3539669SN/A 3549669SN/A // after the column bits, we get the bank bits to interleave 3559491SN/A // over the banks 3569243SN/A bank = addr % banksPerRank; 3579243SN/A addr = addr / banksPerRank; 3589243SN/A 3599491SN/A // after the bank, we get the rank bits which thus interleaves 3609491SN/A // over the ranks 3619243SN/A rank = addr % ranksPerChannel; 3629243SN/A addr = addr / ranksPerChannel; 3639243SN/A 3649491SN/A // lastly, get the row bits 3659243SN/A row = addr % rowsPerBank; 3669243SN/A addr = addr / rowsPerBank; 36710136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 3689491SN/A // optimise for closed page mode and utilise maximum 3699491SN/A // parallelism of the DRAM (at the cost of power) 3709491SN/A 37110286Sandreas.hansson@arm.com // take out the lower-order column bits 37210286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 37310286Sandreas.hansson@arm.com 3749566SN/A // take out the channel part of the address, not that this has 3759566SN/A // to match with how accesses are interleaved between the 3769566SN/A // controllers in the address mapping 3779566SN/A addr = addr / channels; 3789566SN/A 3799491SN/A // start with the bank bits, as this provides the maximum 3809491SN/A // opportunity for parallelism between requests 3819243SN/A bank = addr % banksPerRank; 3829243SN/A addr = addr / banksPerRank; 3839243SN/A 3849491SN/A // next get the rank bits 3859243SN/A rank = addr % ranksPerChannel; 3869243SN/A addr = addr / ranksPerChannel; 3879243SN/A 38810286Sandreas.hansson@arm.com // next, the higher-order column bites 38910286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3909243SN/A 3919491SN/A // lastly, get the row bits 3929243SN/A row = addr % rowsPerBank; 3939243SN/A addr = addr / rowsPerBank; 3949243SN/A } else 3959243SN/A panic("Unknown address mapping policy chosen!"); 3969243SN/A 3979243SN/A assert(rank < ranksPerChannel); 3989243SN/A assert(bank < banksPerRank); 3999243SN/A assert(row < rowsPerBank); 40010245Sandreas.hansson@arm.com assert(row < Bank::NO_ROW); 4019243SN/A 4029243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 4039831SN/A dramPktAddr, rank, bank, row); 4049243SN/A 4059243SN/A // create the corresponding DRAM packet with the entry time and 4069567SN/A // ready time set to the current tick, the latter will be updated 4079567SN/A // later 4089967SN/A uint16_t bank_id = banksPerRank * rank + bank; 4099967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 41010618SOmar.Naji@arm.com size, ranks[rank]->banks[bank], *ranks[rank]); 4119243SN/A} 4129243SN/A 4139243SN/Avoid 41410146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 4159243SN/A{ 4169243SN/A // only add to the read queue here. whenever the request is 4179243SN/A // eventually done, set the readyTime, and call schedule() 4189243SN/A assert(!pkt->isWrite()); 4199243SN/A 4209831SN/A assert(pktCount != 0); 4219831SN/A 4229831SN/A // if the request size is larger than burst size, the pkt is split into 4239831SN/A // multiple DRAM packets 4249831SN/A // Note if the pkt starting address is not aligened to burst size, the 4259831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 4269831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 4279831SN/A // check read packets against packets in write queue. 4289243SN/A Addr addr = pkt->getAddr(); 4299831SN/A unsigned pktsServicedByWrQ = 0; 4309831SN/A BurstHelper* burst_helper = NULL; 4319831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4329831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4339831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4349831SN/A readPktSize[ceilLog2(size)]++; 4359831SN/A readBursts++; 4369243SN/A 4379831SN/A // First check write buffer to see if the data is already at 4389831SN/A // the controller 4399831SN/A bool foundInWrQ = false; 4409833SN/A for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) { 4419832SN/A // check if the read is subsumed in the write entry we are 4429832SN/A // looking at 4439832SN/A if ((*i)->addr <= addr && 4449832SN/A (addr + size) <= ((*i)->addr + (*i)->size)) { 4459831SN/A foundInWrQ = true; 4469831SN/A servicedByWrQ++; 4479831SN/A pktsServicedByWrQ++; 4489831SN/A DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 4499831SN/A "write queue\n", addr, size); 4509975SN/A bytesReadWrQ += burstSize; 4519831SN/A break; 4529831SN/A } 4539243SN/A } 4549831SN/A 4559831SN/A // If not found in the write q, make a DRAM packet and 4569831SN/A // push it onto the read queue 4579831SN/A if (!foundInWrQ) { 4589831SN/A 4599831SN/A // Make the burst helper for split packets 4609831SN/A if (pktCount > 1 && burst_helper == NULL) { 4619831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 4629831SN/A "dram requests\n", pkt->getAddr(), pktCount); 4639831SN/A burst_helper = new BurstHelper(pktCount); 4649831SN/A } 4659831SN/A 4669966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 4679831SN/A dram_pkt->burstHelper = burst_helper; 4689831SN/A 4699831SN/A assert(!readQueueFull(1)); 4709831SN/A rdQLenPdf[readQueue.size() + respQueue.size()]++; 4719831SN/A 4729831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 4739831SN/A 4749831SN/A readQueue.push_back(dram_pkt); 4759831SN/A 4769831SN/A // Update stats 4779831SN/A avgRdQLen = readQueue.size() + respQueue.size(); 4789831SN/A } 4799831SN/A 4809831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 4819831SN/A addr = (addr | (burstSize - 1)) + 1; 4829243SN/A } 4839243SN/A 4849831SN/A // If all packets are serviced by write queue, we send the repsonse back 4859831SN/A if (pktsServicedByWrQ == pktCount) { 4869831SN/A accessAndRespond(pkt, frontendLatency); 4879831SN/A return; 4889831SN/A } 4899243SN/A 4909831SN/A // Update how many split packets are serviced by write queue 4919831SN/A if (burst_helper != NULL) 4929831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 4939243SN/A 49410206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 49510206Sandreas.hansson@arm.com // queue, do so now 49610206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 4979567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 4989567SN/A schedule(nextReqEvent, curTick()); 4999243SN/A } 5009243SN/A} 5019243SN/A 5029243SN/Avoid 50310146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 5049243SN/A{ 5059243SN/A // only add to the write queue here. whenever the request is 5069243SN/A // eventually done, set the readyTime, and call schedule() 5079243SN/A assert(pkt->isWrite()); 5089243SN/A 5099831SN/A // if the request size is larger than burst size, the pkt is split into 5109831SN/A // multiple DRAM packets 5119831SN/A Addr addr = pkt->getAddr(); 5129831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 5139831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 5149831SN/A pkt->getAddr() + pkt->getSize()) - addr; 5159831SN/A writePktSize[ceilLog2(size)]++; 5169831SN/A writeBursts++; 5179243SN/A 5189832SN/A // see if we can merge with an existing item in the write 5199838SN/A // queue and keep track of whether we have merged or not so we 5209838SN/A // can stop at that point and also avoid enqueueing a new 5219838SN/A // request 5229832SN/A bool merged = false; 5239832SN/A auto w = writeQueue.begin(); 5249243SN/A 5259832SN/A while(!merged && w != writeQueue.end()) { 5269832SN/A // either of the two could be first, if they are the same 5279832SN/A // it does not matter which way we go 5289832SN/A if ((*w)->addr >= addr) { 5299838SN/A // the existing one starts after the new one, figure 5309838SN/A // out where the new one ends with respect to the 5319838SN/A // existing one 5329832SN/A if ((addr + size) >= ((*w)->addr + (*w)->size)) { 5339832SN/A // check if the existing one is completely 5349832SN/A // subsumed in the new one 5359832SN/A DPRINTF(DRAM, "Merging write covering existing burst\n"); 5369832SN/A merged = true; 5379832SN/A // update both the address and the size 5389832SN/A (*w)->addr = addr; 5399832SN/A (*w)->size = size; 5409832SN/A } else if ((addr + size) >= (*w)->addr && 5419832SN/A ((*w)->addr + (*w)->size - addr) <= burstSize) { 5429832SN/A // the new one is just before or partially 5439832SN/A // overlapping with the existing one, and together 5449832SN/A // they fit within a burst 5459832SN/A DPRINTF(DRAM, "Merging write before existing burst\n"); 5469832SN/A merged = true; 5479832SN/A // the existing queue item needs to be adjusted with 5489832SN/A // respect to both address and size 54910047SN/A (*w)->size = (*w)->addr + (*w)->size - addr; 5509832SN/A (*w)->addr = addr; 5519832SN/A } 5529832SN/A } else { 5539838SN/A // the new one starts after the current one, figure 5549838SN/A // out where the existing one ends with respect to the 5559838SN/A // new one 5569832SN/A if (((*w)->addr + (*w)->size) >= (addr + size)) { 5579832SN/A // check if the new one is completely subsumed in the 5589832SN/A // existing one 5599832SN/A DPRINTF(DRAM, "Merging write into existing burst\n"); 5609832SN/A merged = true; 5619832SN/A // no adjustments necessary 5629832SN/A } else if (((*w)->addr + (*w)->size) >= addr && 5639832SN/A (addr + size - (*w)->addr) <= burstSize) { 5649832SN/A // the existing one is just before or partially 5659832SN/A // overlapping with the new one, and together 5669832SN/A // they fit within a burst 5679832SN/A DPRINTF(DRAM, "Merging write after existing burst\n"); 5689832SN/A merged = true; 5699832SN/A // the address is right, and only the size has 5709832SN/A // to be adjusted 5719832SN/A (*w)->size = addr + size - (*w)->addr; 5729832SN/A } 5739832SN/A } 5749832SN/A ++w; 5759832SN/A } 5769243SN/A 5779832SN/A // if the item was not merged we need to create a new write 5789832SN/A // and enqueue it 5799832SN/A if (!merged) { 5809966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 5819243SN/A 5829832SN/A assert(writeQueue.size() < writeBufferSize); 5839832SN/A wrQLenPdf[writeQueue.size()]++; 5849243SN/A 5859832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 5869831SN/A 5879832SN/A writeQueue.push_back(dram_pkt); 5889831SN/A 5899832SN/A // Update stats 5909832SN/A avgWrQLen = writeQueue.size(); 5919977SN/A } else { 5929977SN/A // keep track of the fact that this burst effectively 5939977SN/A // disappeared as it was merged with an existing one 5949977SN/A mergedWrBursts++; 5959832SN/A } 5969832SN/A 5979831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 5989831SN/A addr = (addr | (burstSize - 1)) + 1; 5999831SN/A } 6009243SN/A 6019243SN/A // we do not wait for the writes to be send to the actual memory, 6029243SN/A // but instead take responsibility for the consistency here and 6039243SN/A // snoop the write queue for any upcoming reads 6049831SN/A // @todo, if a pkt size is larger than burst size, we might need a 6059831SN/A // different front end latency 6069726SN/A accessAndRespond(pkt, frontendLatency); 6079243SN/A 60810206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 60910206Sandreas.hansson@arm.com // queue, do so now 61010206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 61110206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 61210206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 6139243SN/A } 6149243SN/A} 6159243SN/A 6169243SN/Avoid 61710146Sandreas.hansson@arm.comDRAMCtrl::printQs() const { 6189243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 6199833SN/A for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 6209243SN/A DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 6219243SN/A } 6229243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 6239833SN/A for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 6249243SN/A DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 6259243SN/A } 6269243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 6279833SN/A for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 6289243SN/A DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 6299243SN/A } 6309243SN/A} 6319243SN/A 6329243SN/Abool 63310146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 6349243SN/A{ 6359349SN/A /// @todo temporary hack to deal with memory corruption issues until 6369349SN/A /// 4-phase transactions are complete 6379349SN/A for (int x = 0; x < pendingDelete.size(); x++) 6389349SN/A delete pendingDelete[x]; 6399349SN/A pendingDelete.clear(); 6409349SN/A 6419243SN/A // This is where we enter from the outside world 6429567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 6439831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 6449243SN/A 6459567SN/A // simply drop inhibited packets for now 6469567SN/A if (pkt->memInhibitAsserted()) { 64710143SN/A DPRINTF(DRAM, "Inhibited packet -- Dropping it now\n"); 6489567SN/A pendingDelete.push_back(pkt); 6499567SN/A return true; 6509567SN/A } 6519243SN/A 6529243SN/A // Calc avg gap between requests 6539243SN/A if (prevArrival != 0) { 6549243SN/A totGap += curTick() - prevArrival; 6559243SN/A } 6569243SN/A prevArrival = curTick(); 6579243SN/A 6589831SN/A 6599831SN/A // Find out how many dram packets a pkt translates to 6609831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 6619831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 6629831SN/A // multiple dram packets 6639243SN/A unsigned size = pkt->getSize(); 6649831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 6659831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 6669243SN/A 6679243SN/A // check local buffers and do not accept if full 6689243SN/A if (pkt->isRead()) { 6699567SN/A assert(size != 0); 6709831SN/A if (readQueueFull(dram_pkt_count)) { 6719567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 6729243SN/A // remember that we have to retry this port 6739243SN/A retryRdReq = true; 6749243SN/A numRdRetry++; 6759243SN/A return false; 6769243SN/A } else { 6779831SN/A addToReadQueue(pkt, dram_pkt_count); 6789243SN/A readReqs++; 6799977SN/A bytesReadSys += size; 6809243SN/A } 6819243SN/A } else if (pkt->isWrite()) { 6829567SN/A assert(size != 0); 6839831SN/A if (writeQueueFull(dram_pkt_count)) { 6849567SN/A DPRINTF(DRAM, "Write queue full, not accepting\n"); 6859243SN/A // remember that we have to retry this port 6869243SN/A retryWrReq = true; 6879243SN/A numWrRetry++; 6889243SN/A return false; 6899243SN/A } else { 6909831SN/A addToWriteQueue(pkt, dram_pkt_count); 6919243SN/A writeReqs++; 6929977SN/A bytesWrittenSys += size; 6939243SN/A } 6949243SN/A } else { 6959243SN/A DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 6969243SN/A neitherReadNorWrite++; 6979726SN/A accessAndRespond(pkt, 1); 6989243SN/A } 6999243SN/A 7009243SN/A return true; 7019243SN/A} 7029243SN/A 7039243SN/Avoid 70410146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 7059243SN/A{ 7069243SN/A DPRINTF(DRAM, 7079243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 7089243SN/A 7099831SN/A DRAMPacket* dram_pkt = respQueue.front(); 7109243SN/A 7119831SN/A if (dram_pkt->burstHelper) { 7129831SN/A // it is a split packet 7139831SN/A dram_pkt->burstHelper->burstsServiced++; 7149831SN/A if (dram_pkt->burstHelper->burstsServiced == 71510143SN/A dram_pkt->burstHelper->burstCount) { 7169831SN/A // we have now serviced all children packets of a system packet 7179831SN/A // so we can now respond to the requester 7189831SN/A // @todo we probably want to have a different front end and back 7199831SN/A // end latency for split packets 7209831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7219831SN/A delete dram_pkt->burstHelper; 7229831SN/A dram_pkt->burstHelper = NULL; 7239831SN/A } 7249831SN/A } else { 7259831SN/A // it is not a split packet 7269831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7279831SN/A } 7289243SN/A 7299831SN/A delete respQueue.front(); 7309831SN/A respQueue.pop_front(); 7319243SN/A 7329831SN/A if (!respQueue.empty()) { 7339831SN/A assert(respQueue.front()->readyTime >= curTick()); 7349831SN/A assert(!respondEvent.scheduled()); 7359831SN/A schedule(respondEvent, respQueue.front()->readyTime); 7369831SN/A } else { 7379831SN/A // if there is nothing left in any queue, signal a drain 7389831SN/A if (writeQueue.empty() && readQueue.empty() && 7399831SN/A drainManager) { 74010509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 7419831SN/A drainManager->signalDrainDone(); 7429831SN/A drainManager = NULL; 7439831SN/A } 7449831SN/A } 7459567SN/A 7469831SN/A // We have made a location in the queue available at this point, 7479831SN/A // so if there is a read that was forced to wait, retry now 7489831SN/A if (retryRdReq) { 7499831SN/A retryRdReq = false; 7509831SN/A port.sendRetry(); 7519831SN/A } 7529243SN/A} 7539243SN/A 75410618SOmar.Naji@arm.combool 75510393Swendy.elsasser@arm.comDRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue, bool switched_cmd_type) 7569243SN/A{ 75710206Sandreas.hansson@arm.com // This method does the arbitration between requests. The chosen 75810206Sandreas.hansson@arm.com // packet is simply moved to the head of the queue. The other 75910206Sandreas.hansson@arm.com // methods know that this is the place to look. For example, with 76010206Sandreas.hansson@arm.com // FCFS, this method does nothing 76110206Sandreas.hansson@arm.com assert(!queue.empty()); 7629243SN/A 76310618SOmar.Naji@arm.com // bool to indicate if a packet to an available rank is found 76410618SOmar.Naji@arm.com bool found_packet = false; 76510206Sandreas.hansson@arm.com if (queue.size() == 1) { 76610618SOmar.Naji@arm.com DRAMPacket* dram_pkt = queue.front(); 76710618SOmar.Naji@arm.com // available rank corresponds to state refresh idle 76810618SOmar.Naji@arm.com if (ranks[dram_pkt->rank]->isAvailable()) { 76910618SOmar.Naji@arm.com found_packet = true; 77010618SOmar.Naji@arm.com DPRINTF(DRAM, "Single request, going to a free rank\n"); 77110618SOmar.Naji@arm.com } else { 77210618SOmar.Naji@arm.com DPRINTF(DRAM, "Single request, going to a busy rank\n"); 77310618SOmar.Naji@arm.com } 77410618SOmar.Naji@arm.com return found_packet; 7759243SN/A } 7769243SN/A 7779243SN/A if (memSchedPolicy == Enums::fcfs) { 77810618SOmar.Naji@arm.com // check if there is a packet going to a free rank 77910618SOmar.Naji@arm.com for(auto i = queue.begin(); i != queue.end() ; ++i) { 78010618SOmar.Naji@arm.com DRAMPacket* dram_pkt = *i; 78110618SOmar.Naji@arm.com if (ranks[dram_pkt->rank]->isAvailable()) { 78210618SOmar.Naji@arm.com queue.erase(i); 78310618SOmar.Naji@arm.com queue.push_front(dram_pkt); 78410618SOmar.Naji@arm.com found_packet = true; 78510618SOmar.Naji@arm.com break; 78610618SOmar.Naji@arm.com } 78710618SOmar.Naji@arm.com } 7889243SN/A } else if (memSchedPolicy == Enums::frfcfs) { 78910618SOmar.Naji@arm.com found_packet = reorderQueue(queue, switched_cmd_type); 7909243SN/A } else 7919243SN/A panic("No scheduling policy chosen\n"); 79210618SOmar.Naji@arm.com return found_packet; 7939243SN/A} 7949243SN/A 79510618SOmar.Naji@arm.combool 79610393Swendy.elsasser@arm.comDRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue, bool switched_cmd_type) 7979974SN/A{ 7989974SN/A // Only determine this when needed 7999974SN/A uint64_t earliest_banks = 0; 8009974SN/A 8019974SN/A // Search for row hits first, if no row hit is found then schedule the 8029974SN/A // packet to one of the earliest banks available 80310618SOmar.Naji@arm.com bool found_packet = false; 8049974SN/A bool found_earliest_pkt = false; 80510393Swendy.elsasser@arm.com bool found_prepped_diff_rank_pkt = false; 80610618SOmar.Naji@arm.com auto selected_pkt_it = queue.end(); 8079974SN/A 8089974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 8099974SN/A DRAMPacket* dram_pkt = *i; 8109974SN/A const Bank& bank = dram_pkt->bankRef; 81110618SOmar.Naji@arm.com // check if rank is busy. If this is the case jump to the next packet 8129974SN/A // Check if it is a row hit 81310618SOmar.Naji@arm.com if (dram_pkt->rankRef.isAvailable()) { 81410618SOmar.Naji@arm.com if (bank.openRow == dram_pkt->row) { 81510618SOmar.Naji@arm.com if (dram_pkt->rank == activeRank || switched_cmd_type) { 81610618SOmar.Naji@arm.com // FCFS within the hits, giving priority to commands 81710618SOmar.Naji@arm.com // that access the same rank as the previous burst 81810618SOmar.Naji@arm.com // to minimize bus turnaround delays 81910618SOmar.Naji@arm.com // Only give rank prioity when command type is 82010618SOmar.Naji@arm.com // not changing 82110618SOmar.Naji@arm.com DPRINTF(DRAM, "Row buffer hit\n"); 82210618SOmar.Naji@arm.com selected_pkt_it = i; 82310618SOmar.Naji@arm.com break; 82410618SOmar.Naji@arm.com } else if (!found_prepped_diff_rank_pkt) { 82510618SOmar.Naji@arm.com // found row hit for command on different rank 82610618SOmar.Naji@arm.com // than prev burst 82710618SOmar.Naji@arm.com selected_pkt_it = i; 82810618SOmar.Naji@arm.com found_prepped_diff_rank_pkt = true; 82910618SOmar.Naji@arm.com } 83010618SOmar.Naji@arm.com } else if (!found_earliest_pkt & !found_prepped_diff_rank_pkt) { 83110618SOmar.Naji@arm.com // packet going to a rank which is currently not waiting for a 83210618SOmar.Naji@arm.com // refresh, No row hit and 83310618SOmar.Naji@arm.com // haven't found an entry with a row hit to a new rank 83410618SOmar.Naji@arm.com if (earliest_banks == 0) 83510618SOmar.Naji@arm.com // Determine entries with earliest bank prep delay 83610618SOmar.Naji@arm.com // Function will give priority to commands that access the 83710618SOmar.Naji@arm.com // same rank as previous burst and can prep 83810618SOmar.Naji@arm.com // the bank seamlessly 83910618SOmar.Naji@arm.com earliest_banks = minBankPrep(queue, switched_cmd_type); 84010211Sandreas.hansson@arm.com 84110618SOmar.Naji@arm.com // FCFS - Bank is first available bank 84210618SOmar.Naji@arm.com if (bits(earliest_banks, dram_pkt->bankId, 84310618SOmar.Naji@arm.com dram_pkt->bankId)) { 84410618SOmar.Naji@arm.com // Remember the packet to be scheduled to one of 84510618SOmar.Naji@arm.com // the earliest banks available, FCFS amongst the 84610618SOmar.Naji@arm.com // earliest banks 84710618SOmar.Naji@arm.com selected_pkt_it = i; 84810618SOmar.Naji@arm.com //if the packet found is going to a rank that is currently 84910618SOmar.Naji@arm.com //not busy then update the found_packet to true 85010618SOmar.Naji@arm.com found_earliest_pkt = true; 85110618SOmar.Naji@arm.com } 8529974SN/A } 8539974SN/A } 8549974SN/A } 8559974SN/A 85610618SOmar.Naji@arm.com if (selected_pkt_it != queue.end()) { 85710618SOmar.Naji@arm.com DRAMPacket* selected_pkt = *selected_pkt_it; 85810618SOmar.Naji@arm.com queue.erase(selected_pkt_it); 85910618SOmar.Naji@arm.com queue.push_front(selected_pkt); 86010618SOmar.Naji@arm.com found_packet = true; 86110618SOmar.Naji@arm.com } 86210618SOmar.Naji@arm.com return found_packet; 8639974SN/A} 8649974SN/A 8659974SN/Avoid 86610146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 8679243SN/A{ 8689243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 8699243SN/A 8709243SN/A bool needsResponse = pkt->needsResponse(); 8719243SN/A // do the actual memory access which also turns the packet into a 8729243SN/A // response 8739243SN/A access(pkt); 8749243SN/A 8759243SN/A // turn packet around to go back to requester if response expected 8769243SN/A if (needsResponse) { 8779243SN/A // access already turned the packet into a response 8789243SN/A assert(pkt->isResponse()); 8799243SN/A 8809549SN/A // @todo someone should pay for this 88110405Sandreas.hansson@arm.com pkt->firstWordDelay = pkt->lastWordDelay = 0; 8829549SN/A 8839726SN/A // queue the packet in the response queue to be sent out after 8849726SN/A // the static latency has passed 8859726SN/A port.schedTimingResp(pkt, curTick() + static_latency); 8869243SN/A } else { 8879587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 8889587SN/A // is still having a pointer to it 8899587SN/A pendingDelete.push_back(pkt); 8909243SN/A } 8919243SN/A 8929243SN/A DPRINTF(DRAM, "Done\n"); 8939243SN/A 8949243SN/A return; 8959243SN/A} 8969243SN/A 8979243SN/Avoid 89810618SOmar.Naji@arm.comDRAMCtrl::activateBank(Rank& rank_ref, Bank& bank_ref, 89910618SOmar.Naji@arm.com Tick act_tick, uint32_t row) 9009488SN/A{ 90110618SOmar.Naji@arm.com assert(rank_ref.actTicks.size() == activationLimit); 9029488SN/A 9039488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 9049488SN/A 90510207Sandreas.hansson@arm.com // update the open row 90610618SOmar.Naji@arm.com assert(bank_ref.openRow == Bank::NO_ROW); 90710618SOmar.Naji@arm.com bank_ref.openRow = row; 90810207Sandreas.hansson@arm.com 90910207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 91010207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 91110207Sandreas.hansson@arm.com // precharge 91210618SOmar.Naji@arm.com bank_ref.bytesAccessed = 0; 91310618SOmar.Naji@arm.com bank_ref.rowAccesses = 0; 91410207Sandreas.hansson@arm.com 91510618SOmar.Naji@arm.com ++rank_ref.numBanksActive; 91610618SOmar.Naji@arm.com assert(rank_ref.numBanksActive <= banksPerRank); 91710207Sandreas.hansson@arm.com 91810247Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n", 91910618SOmar.Naji@arm.com bank_ref.bank, rank_ref.rank, act_tick, 92010618SOmar.Naji@arm.com ranks[rank_ref.rank]->numBanksActive); 92110247Sandreas.hansson@arm.com 92210618SOmar.Naji@arm.com rank_ref.power.powerlib.doCommand(MemCommand::ACT, bank_ref.bank, 92310618SOmar.Naji@arm.com divCeil(act_tick, tCK) - 92410618SOmar.Naji@arm.com timeStampOffset); 92510432SOmar.Naji@arm.com 92610432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK) - 92710618SOmar.Naji@arm.com timeStampOffset, bank_ref.bank, rank_ref.rank); 9289975SN/A 92910211Sandreas.hansson@arm.com // The next access has to respect tRAS for this bank 93010618SOmar.Naji@arm.com bank_ref.preAllowedAt = act_tick + tRAS; 93110211Sandreas.hansson@arm.com 93210211Sandreas.hansson@arm.com // Respect the row-to-column command delay 93310618SOmar.Naji@arm.com bank_ref.colAllowedAt = std::max(act_tick + tRCD, bank_ref.colAllowedAt); 93410211Sandreas.hansson@arm.com 9359971SN/A // start by enforcing tRRD 9369971SN/A for(int i = 0; i < banksPerRank; i++) { 93710210Sandreas.hansson@arm.com // next activate to any bank in this rank must not happen 93810210Sandreas.hansson@arm.com // before tRRD 93910618SOmar.Naji@arm.com if (bankGroupArch && (bank_ref.bankgr == rank_ref.banks[i].bankgr)) { 94010394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 94110394Swendy.elsasser@arm.com // ACT commands within the same bank group. Use tRRD_L 94210394Swendy.elsasser@arm.com // in this case 94310618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD_L, 94410618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt); 94510394Swendy.elsasser@arm.com } else { 94610394Swendy.elsasser@arm.com // use shorter tRRD value when either 94710394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 94810394Swendy.elsasser@arm.com // 2) bank is in a different bank group 94910618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD, 95010618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt); 95110394Swendy.elsasser@arm.com } 9529971SN/A } 95310208Sandreas.hansson@arm.com 9549971SN/A // next, we deal with tXAW, if the activation limit is disabled 95510492SOmar.Naji@arm.com // then we directly schedule an activate power event 95610618SOmar.Naji@arm.com if (!rank_ref.actTicks.empty()) { 95710492SOmar.Naji@arm.com // sanity check 95810618SOmar.Naji@arm.com if (rank_ref.actTicks.back() && 95910618SOmar.Naji@arm.com (act_tick - rank_ref.actTicks.back()) < tXAW) { 96010492SOmar.Naji@arm.com panic("Got %d activates in window %d (%llu - %llu) which " 96110492SOmar.Naji@arm.com "is smaller than %llu\n", activationLimit, act_tick - 96210618SOmar.Naji@arm.com rank_ref.actTicks.back(), act_tick, 96310618SOmar.Naji@arm.com rank_ref.actTicks.back(), tXAW); 96410492SOmar.Naji@arm.com } 9659824SN/A 96610492SOmar.Naji@arm.com // shift the times used for the book keeping, the last element 96710492SOmar.Naji@arm.com // (highest index) is the oldest one and hence the lowest value 96810618SOmar.Naji@arm.com rank_ref.actTicks.pop_back(); 9699488SN/A 97010492SOmar.Naji@arm.com // record an new activation (in the future) 97110618SOmar.Naji@arm.com rank_ref.actTicks.push_front(act_tick); 9729488SN/A 97310492SOmar.Naji@arm.com // cannot activate more than X times in time window tXAW, push the 97410492SOmar.Naji@arm.com // next one (the X + 1'st activate) to be tXAW away from the 97510492SOmar.Naji@arm.com // oldest in our window of X 97610618SOmar.Naji@arm.com if (rank_ref.actTicks.back() && 97710618SOmar.Naji@arm.com (act_tick - rank_ref.actTicks.back()) < tXAW) { 97810492SOmar.Naji@arm.com DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate " 97910492SOmar.Naji@arm.com "no earlier than %llu\n", activationLimit, 98010618SOmar.Naji@arm.com rank_ref.actTicks.back() + tXAW); 9819488SN/A for(int j = 0; j < banksPerRank; j++) 9829488SN/A // next activate must not happen before end of window 98310618SOmar.Naji@arm.com rank_ref.banks[j].actAllowedAt = 98410618SOmar.Naji@arm.com std::max(rank_ref.actTicks.back() + tXAW, 98510618SOmar.Naji@arm.com rank_ref.banks[j].actAllowedAt); 98610492SOmar.Naji@arm.com } 9879488SN/A } 98810208Sandreas.hansson@arm.com 98910208Sandreas.hansson@arm.com // at the point when this activate takes place, make sure we 99010208Sandreas.hansson@arm.com // transition to the active power state 99110618SOmar.Naji@arm.com if (!rank_ref.activateEvent.scheduled()) 99210618SOmar.Naji@arm.com schedule(rank_ref.activateEvent, act_tick); 99310618SOmar.Naji@arm.com else if (rank_ref.activateEvent.when() > act_tick) 99410208Sandreas.hansson@arm.com // move it sooner in time 99510618SOmar.Naji@arm.com reschedule(rank_ref.activateEvent, act_tick); 99610208Sandreas.hansson@arm.com} 99710208Sandreas.hansson@arm.com 99810208Sandreas.hansson@arm.comvoid 99910618SOmar.Naji@arm.comDRAMCtrl::prechargeBank(Rank& rank_ref, Bank& bank, Tick pre_at, bool trace) 100010207Sandreas.hansson@arm.com{ 100110207Sandreas.hansson@arm.com // make sure the bank has an open row 100210207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 100310207Sandreas.hansson@arm.com 100410207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 100510207Sandreas.hansson@arm.com // the page 100610207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 100710207Sandreas.hansson@arm.com 100810207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 100910207Sandreas.hansson@arm.com 101010214Sandreas.hansson@arm.com // no precharge allowed before this one 101110214Sandreas.hansson@arm.com bank.preAllowedAt = pre_at; 101210214Sandreas.hansson@arm.com 101310211Sandreas.hansson@arm.com Tick pre_done_at = pre_at + tRP; 101410211Sandreas.hansson@arm.com 101510211Sandreas.hansson@arm.com bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at); 101610207Sandreas.hansson@arm.com 101710618SOmar.Naji@arm.com assert(rank_ref.numBanksActive != 0); 101810618SOmar.Naji@arm.com --rank_ref.numBanksActive; 101910207Sandreas.hansson@arm.com 102010247Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got " 102110618SOmar.Naji@arm.com "%d active\n", bank.bank, rank_ref.rank, pre_at, 102210618SOmar.Naji@arm.com rank_ref.numBanksActive); 102310247Sandreas.hansson@arm.com 102410432SOmar.Naji@arm.com if (trace) { 102510207Sandreas.hansson@arm.com 102610618SOmar.Naji@arm.com rank_ref.power.powerlib.doCommand(MemCommand::PRE, bank.bank, 102710432SOmar.Naji@arm.com divCeil(pre_at, tCK) - 102810432SOmar.Naji@arm.com timeStampOffset); 102910432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK) - 103010618SOmar.Naji@arm.com timeStampOffset, bank.bank, rank_ref.rank); 103110432SOmar.Naji@arm.com } 103210208Sandreas.hansson@arm.com // if we look at the current number of active banks we might be 103310208Sandreas.hansson@arm.com // tempted to think the DRAM is now idle, however this can be 103410208Sandreas.hansson@arm.com // undone by an activate that is scheduled to happen before we 103510208Sandreas.hansson@arm.com // would have reached the idle state, so schedule an event and 103610208Sandreas.hansson@arm.com // rather check once we actually make it to the point in time when 103710208Sandreas.hansson@arm.com // the (last) precharge takes place 103810618SOmar.Naji@arm.com if (!rank_ref.prechargeEvent.scheduled()) 103910618SOmar.Naji@arm.com schedule(rank_ref.prechargeEvent, pre_done_at); 104010618SOmar.Naji@arm.com else if (rank_ref.prechargeEvent.when() < pre_done_at) 104110618SOmar.Naji@arm.com reschedule(rank_ref.prechargeEvent, pre_done_at); 104210207Sandreas.hansson@arm.com} 104310207Sandreas.hansson@arm.com 104410207Sandreas.hansson@arm.comvoid 104510146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 10469243SN/A{ 10479243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 10489243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 10499243SN/A 105010618SOmar.Naji@arm.com // get the rank 105110618SOmar.Naji@arm.com Rank& rank = dram_pkt->rankRef; 105210618SOmar.Naji@arm.com 105310211Sandreas.hansson@arm.com // get the bank 10549967SN/A Bank& bank = dram_pkt->bankRef; 10559243SN/A 105610211Sandreas.hansson@arm.com // for the state we need to track if it is a row hit or not 105710211Sandreas.hansson@arm.com bool row_hit = true; 105810211Sandreas.hansson@arm.com 105910211Sandreas.hansson@arm.com // respect any constraints on the command (e.g. tRCD or tCCD) 106010211Sandreas.hansson@arm.com Tick cmd_at = std::max(bank.colAllowedAt, curTick()); 106110211Sandreas.hansson@arm.com 106210211Sandreas.hansson@arm.com // Determine the access latency and update the bank state 106310211Sandreas.hansson@arm.com if (bank.openRow == dram_pkt->row) { 106410211Sandreas.hansson@arm.com // nothing to do 106510209Sandreas.hansson@arm.com } else { 106610211Sandreas.hansson@arm.com row_hit = false; 106710211Sandreas.hansson@arm.com 106810209Sandreas.hansson@arm.com // If there is a page open, precharge it. 106910209Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 107010618SOmar.Naji@arm.com prechargeBank(rank, bank, std::max(bank.preAllowedAt, curTick())); 10719488SN/A } 10729973SN/A 107310211Sandreas.hansson@arm.com // next we need to account for the delay in activating the 107410211Sandreas.hansson@arm.com // page 107510211Sandreas.hansson@arm.com Tick act_tick = std::max(bank.actAllowedAt, curTick()); 10769973SN/A 107710210Sandreas.hansson@arm.com // Record the activation and deal with all the global timing 107810210Sandreas.hansson@arm.com // constraints caused be a new activation (tRRD and tXAW) 107910618SOmar.Naji@arm.com activateBank(rank, bank, act_tick, dram_pkt->row); 108010210Sandreas.hansson@arm.com 108110211Sandreas.hansson@arm.com // issue the command as early as possible 108210211Sandreas.hansson@arm.com cmd_at = bank.colAllowedAt; 108310209Sandreas.hansson@arm.com } 108410209Sandreas.hansson@arm.com 108510211Sandreas.hansson@arm.com // we need to wait until the bus is available before we can issue 108610211Sandreas.hansson@arm.com // the command 108710211Sandreas.hansson@arm.com cmd_at = std::max(cmd_at, busBusyUntil - tCL); 108810211Sandreas.hansson@arm.com 108910211Sandreas.hansson@arm.com // update the packet ready time 109010211Sandreas.hansson@arm.com dram_pkt->readyTime = cmd_at + tCL + tBURST; 109110211Sandreas.hansson@arm.com 109210211Sandreas.hansson@arm.com // only one burst can use the bus at any one point in time 109310211Sandreas.hansson@arm.com assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 109410211Sandreas.hansson@arm.com 109510394Swendy.elsasser@arm.com // update the time for the next read/write burst for each 109610394Swendy.elsasser@arm.com // bank (add a max with tCCD/tCCD_L here) 109710394Swendy.elsasser@arm.com Tick cmd_dly; 109810394Swendy.elsasser@arm.com for(int j = 0; j < ranksPerChannel; j++) { 109910394Swendy.elsasser@arm.com for(int i = 0; i < banksPerRank; i++) { 110010394Swendy.elsasser@arm.com // next burst to same bank group in this rank must not happen 110110394Swendy.elsasser@arm.com // before tCCD_L. Different bank group timing requirement is 110210394Swendy.elsasser@arm.com // tBURST; Add tCS for different ranks 110310394Swendy.elsasser@arm.com if (dram_pkt->rank == j) { 110410618SOmar.Naji@arm.com if (bankGroupArch && 110510618SOmar.Naji@arm.com (bank.bankgr == ranks[j]->banks[i].bankgr)) { 110610394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 110710394Swendy.elsasser@arm.com // RD/WR burst commands to the same bank group. 110810394Swendy.elsasser@arm.com // Use tCCD_L in this case 110910394Swendy.elsasser@arm.com cmd_dly = tCCD_L; 111010394Swendy.elsasser@arm.com } else { 111110394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), the shorter 111210394Swendy.elsasser@arm.com // cas-to-cas delay value, when either: 111310394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 111410394Swendy.elsasser@arm.com // 2) bank is in a different bank group 111510394Swendy.elsasser@arm.com cmd_dly = tBURST; 111610394Swendy.elsasser@arm.com } 111710394Swendy.elsasser@arm.com } else { 111810394Swendy.elsasser@arm.com // different rank is by default in a different bank group 111910394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), which is the shorter 112010394Swendy.elsasser@arm.com // cas-to-cas delay in this case 112110394Swendy.elsasser@arm.com // Add tCS to account for rank-to-rank bus delay requirements 112210394Swendy.elsasser@arm.com cmd_dly = tBURST + tCS; 112310394Swendy.elsasser@arm.com } 112410618SOmar.Naji@arm.com ranks[j]->banks[i].colAllowedAt = std::max(cmd_at + cmd_dly, 112510618SOmar.Naji@arm.com ranks[j]->banks[i].colAllowedAt); 112610394Swendy.elsasser@arm.com } 112710394Swendy.elsasser@arm.com } 112810211Sandreas.hansson@arm.com 112910393Swendy.elsasser@arm.com // Save rank of current access 113010393Swendy.elsasser@arm.com activeRank = dram_pkt->rank; 113110393Swendy.elsasser@arm.com 113210212Sandreas.hansson@arm.com // If this is a write, we also need to respect the write recovery 113310212Sandreas.hansson@arm.com // time before a precharge, in the case of a read, respect the 113410212Sandreas.hansson@arm.com // read to precharge constraint 113510212Sandreas.hansson@arm.com bank.preAllowedAt = std::max(bank.preAllowedAt, 113610212Sandreas.hansson@arm.com dram_pkt->isRead ? cmd_at + tRTP : 113710212Sandreas.hansson@arm.com dram_pkt->readyTime + tWR); 113810210Sandreas.hansson@arm.com 113910209Sandreas.hansson@arm.com // increment the bytes accessed and the accesses per row 114010209Sandreas.hansson@arm.com bank.bytesAccessed += burstSize; 114110209Sandreas.hansson@arm.com ++bank.rowAccesses; 114210209Sandreas.hansson@arm.com 114310209Sandreas.hansson@arm.com // if we reached the max, then issue with an auto-precharge 114410209Sandreas.hansson@arm.com bool auto_precharge = pageMgmt == Enums::close || 114510209Sandreas.hansson@arm.com bank.rowAccesses == maxAccessesPerRow; 114610209Sandreas.hansson@arm.com 114710209Sandreas.hansson@arm.com // if we did not hit the limit, we might still want to 114810209Sandreas.hansson@arm.com // auto-precharge 114910209Sandreas.hansson@arm.com if (!auto_precharge && 115010209Sandreas.hansson@arm.com (pageMgmt == Enums::open_adaptive || 115110209Sandreas.hansson@arm.com pageMgmt == Enums::close_adaptive)) { 115210209Sandreas.hansson@arm.com // a twist on the open and close page policies: 115310209Sandreas.hansson@arm.com // 1) open_adaptive page policy does not blindly keep the 115410209Sandreas.hansson@arm.com // page open, but close it if there are no row hits, and there 115510209Sandreas.hansson@arm.com // are bank conflicts in the queue 115610209Sandreas.hansson@arm.com // 2) close_adaptive page policy does not blindly close the 115710209Sandreas.hansson@arm.com // page, but closes it only if there are no row hits in the queue. 115810209Sandreas.hansson@arm.com // In this case, only force an auto precharge when there 115910209Sandreas.hansson@arm.com // are no same page hits in the queue 116010209Sandreas.hansson@arm.com bool got_more_hits = false; 116110209Sandreas.hansson@arm.com bool got_bank_conflict = false; 116210209Sandreas.hansson@arm.com 116310209Sandreas.hansson@arm.com // either look at the read queue or write queue 116410209Sandreas.hansson@arm.com const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 116510209Sandreas.hansson@arm.com writeQueue; 116610209Sandreas.hansson@arm.com auto p = queue.begin(); 116710209Sandreas.hansson@arm.com // make sure we are not considering the packet that we are 116810209Sandreas.hansson@arm.com // currently dealing with (which is the head of the queue) 116910209Sandreas.hansson@arm.com ++p; 117010209Sandreas.hansson@arm.com 117110209Sandreas.hansson@arm.com // keep on looking until we have found required condition or 117210209Sandreas.hansson@arm.com // reached the end 117310209Sandreas.hansson@arm.com while (!(got_more_hits && 117410209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive)) && 117510209Sandreas.hansson@arm.com p != queue.end()) { 117610209Sandreas.hansson@arm.com bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 117710209Sandreas.hansson@arm.com (dram_pkt->bank == (*p)->bank); 117810209Sandreas.hansson@arm.com bool same_row = dram_pkt->row == (*p)->row; 117910209Sandreas.hansson@arm.com got_more_hits |= same_rank_bank && same_row; 118010209Sandreas.hansson@arm.com got_bank_conflict |= same_rank_bank && !same_row; 11819973SN/A ++p; 118210141SN/A } 118310141SN/A 118410209Sandreas.hansson@arm.com // auto pre-charge when either 118510209Sandreas.hansson@arm.com // 1) open_adaptive policy, we have not got any more hits, and 118610209Sandreas.hansson@arm.com // have a bank conflict 118710209Sandreas.hansson@arm.com // 2) close_adaptive policy and we have not got any more hits 118810209Sandreas.hansson@arm.com auto_precharge = !got_more_hits && 118910209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive); 119010209Sandreas.hansson@arm.com } 119110142SN/A 119210247Sandreas.hansson@arm.com // DRAMPower trace command to be written 119310247Sandreas.hansson@arm.com std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR"; 119410247Sandreas.hansson@arm.com 119510432SOmar.Naji@arm.com // MemCommand required for DRAMPower library 119610432SOmar.Naji@arm.com MemCommand::cmds command = (mem_cmd == "RD") ? MemCommand::RD : 119710432SOmar.Naji@arm.com MemCommand::WR; 119810432SOmar.Naji@arm.com 119910209Sandreas.hansson@arm.com // if this access should use auto-precharge, then we are 120010209Sandreas.hansson@arm.com // closing the row 120110209Sandreas.hansson@arm.com if (auto_precharge) { 120210432SOmar.Naji@arm.com // if auto-precharge push a PRE command at the correct tick to the 120310432SOmar.Naji@arm.com // list used by DRAMPower library to calculate power 120410618SOmar.Naji@arm.com prechargeBank(rank, bank, std::max(curTick(), bank.preAllowedAt)); 12059973SN/A 120610209Sandreas.hansson@arm.com DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 120710209Sandreas.hansson@arm.com } 12089963SN/A 12099243SN/A // Update bus state 12109243SN/A busBusyUntil = dram_pkt->readyTime; 12119243SN/A 121210211Sandreas.hansson@arm.com DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n", 121310211Sandreas.hansson@arm.com dram_pkt->addr, dram_pkt->readyTime, busBusyUntil); 12149243SN/A 121510618SOmar.Naji@arm.com dram_pkt->rankRef.power.powerlib.doCommand(command, dram_pkt->bank, 121610432SOmar.Naji@arm.com divCeil(cmd_at, tCK) - 121710432SOmar.Naji@arm.com timeStampOffset); 121810432SOmar.Naji@arm.com 121910432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK) - 122010432SOmar.Naji@arm.com timeStampOffset, mem_cmd, dram_pkt->bank, dram_pkt->rank); 122110247Sandreas.hansson@arm.com 122210206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 122310206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 122410206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 122510206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 122610206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 12279972SN/A 122810206Sandreas.hansson@arm.com // Update the stats and schedule the next request 12299977SN/A if (dram_pkt->isRead) { 123010147Sandreas.hansson@arm.com ++readsThisTime; 123110211Sandreas.hansson@arm.com if (row_hit) 12329977SN/A readRowHits++; 12339977SN/A bytesReadDRAM += burstSize; 12349977SN/A perBankRdBursts[dram_pkt->bankId]++; 123510206Sandreas.hansson@arm.com 123610206Sandreas.hansson@arm.com // Update latency stats 123710206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 123810206Sandreas.hansson@arm.com totBusLat += tBURST; 123910211Sandreas.hansson@arm.com totQLat += cmd_at - dram_pkt->entryTime; 12409977SN/A } else { 124110147Sandreas.hansson@arm.com ++writesThisTime; 124210211Sandreas.hansson@arm.com if (row_hit) 12439977SN/A writeRowHits++; 12449977SN/A bytesWritten += burstSize; 12459977SN/A perBankWrBursts[dram_pkt->bankId]++; 12469243SN/A } 12479243SN/A} 12489243SN/A 12499243SN/Avoid 125010206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 12519243SN/A{ 125210618SOmar.Naji@arm.com int busyRanks = 0; 125310618SOmar.Naji@arm.com for (auto r : ranks) { 125410618SOmar.Naji@arm.com if (!r->isAvailable()) { 125510618SOmar.Naji@arm.com // rank is busy refreshing 125610618SOmar.Naji@arm.com busyRanks++; 125710618SOmar.Naji@arm.com 125810618SOmar.Naji@arm.com // let the rank know that if it was waiting to drain, it 125910618SOmar.Naji@arm.com // is now done and ready to proceed 126010618SOmar.Naji@arm.com r->checkDrainDone(); 126110618SOmar.Naji@arm.com } 126210618SOmar.Naji@arm.com } 126310618SOmar.Naji@arm.com 126410618SOmar.Naji@arm.com if (busyRanks == ranksPerChannel) { 126510618SOmar.Naji@arm.com // if all ranks are refreshing wait for them to finish 126610618SOmar.Naji@arm.com // and stall this state machine without taking any further 126710618SOmar.Naji@arm.com // action, and do not schedule a new nextReqEvent 126810618SOmar.Naji@arm.com return; 126910618SOmar.Naji@arm.com } 127010618SOmar.Naji@arm.com 127110393Swendy.elsasser@arm.com // pre-emptively set to false. Overwrite if in READ_TO_WRITE 127210393Swendy.elsasser@arm.com // or WRITE_TO_READ state 127310393Swendy.elsasser@arm.com bool switched_cmd_type = false; 127410206Sandreas.hansson@arm.com if (busState == READ_TO_WRITE) { 127510206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 127610206Sandreas.hansson@arm.com "waiting\n", readsThisTime, readQueue.size()); 12779243SN/A 127810206Sandreas.hansson@arm.com // sample and reset the read-related stats as we are now 127910206Sandreas.hansson@arm.com // transitioning to writes, and all reads are done 128010206Sandreas.hansson@arm.com rdPerTurnAround.sample(readsThisTime); 128110206Sandreas.hansson@arm.com readsThisTime = 0; 128210206Sandreas.hansson@arm.com 128310206Sandreas.hansson@arm.com // now proceed to do the actual writes 128410206Sandreas.hansson@arm.com busState = WRITE; 128510393Swendy.elsasser@arm.com switched_cmd_type = true; 128610206Sandreas.hansson@arm.com } else if (busState == WRITE_TO_READ) { 128710206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 128810206Sandreas.hansson@arm.com "waiting\n", writesThisTime, writeQueue.size()); 128910206Sandreas.hansson@arm.com 129010206Sandreas.hansson@arm.com wrPerTurnAround.sample(writesThisTime); 129110206Sandreas.hansson@arm.com writesThisTime = 0; 129210206Sandreas.hansson@arm.com 129310206Sandreas.hansson@arm.com busState = READ; 129410393Swendy.elsasser@arm.com switched_cmd_type = true; 129510206Sandreas.hansson@arm.com } 129610206Sandreas.hansson@arm.com 129710206Sandreas.hansson@arm.com // when we get here it is either a read or a write 129810206Sandreas.hansson@arm.com if (busState == READ) { 129910206Sandreas.hansson@arm.com 130010206Sandreas.hansson@arm.com // track if we should switch or not 130110206Sandreas.hansson@arm.com bool switch_to_writes = false; 130210206Sandreas.hansson@arm.com 130310206Sandreas.hansson@arm.com if (readQueue.empty()) { 130410206Sandreas.hansson@arm.com // In the case there is no read request to go next, 130510206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 130610206Sandreas.hansson@arm.com // if we are draining) 130710206Sandreas.hansson@arm.com if (!writeQueue.empty() && 130810206Sandreas.hansson@arm.com (drainManager || writeQueue.size() > writeLowThreshold)) { 130910206Sandreas.hansson@arm.com 131010206Sandreas.hansson@arm.com switch_to_writes = true; 131110206Sandreas.hansson@arm.com } else { 131210206Sandreas.hansson@arm.com // check if we are drained 131310206Sandreas.hansson@arm.com if (respQueue.empty () && drainManager) { 131410509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 131510206Sandreas.hansson@arm.com drainManager->signalDrainDone(); 131610206Sandreas.hansson@arm.com drainManager = NULL; 131710206Sandreas.hansson@arm.com } 131810206Sandreas.hansson@arm.com 131910206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 132010206Sandreas.hansson@arm.com // event for the next request 132110206Sandreas.hansson@arm.com return; 132210206Sandreas.hansson@arm.com } 132310206Sandreas.hansson@arm.com } else { 132410618SOmar.Naji@arm.com // bool to check if there is a read to a free rank 132510618SOmar.Naji@arm.com bool found_read = false; 132610618SOmar.Naji@arm.com 132710206Sandreas.hansson@arm.com // Figure out which read request goes next, and move it to the 132810206Sandreas.hansson@arm.com // front of the read queue 132910618SOmar.Naji@arm.com found_read = chooseNext(readQueue, switched_cmd_type); 133010618SOmar.Naji@arm.com 133110618SOmar.Naji@arm.com // if no read to an available rank is found then return 133210618SOmar.Naji@arm.com // at this point. There could be writes to the available ranks 133310618SOmar.Naji@arm.com // which are above the required threshold. However, to 133410618SOmar.Naji@arm.com // avoid adding more complexity to the code, return and wait 133510618SOmar.Naji@arm.com // for a refresh event to kick things into action again. 133610618SOmar.Naji@arm.com if (!found_read) 133710618SOmar.Naji@arm.com return; 133810206Sandreas.hansson@arm.com 133910215Sandreas.hansson@arm.com DRAMPacket* dram_pkt = readQueue.front(); 134010618SOmar.Naji@arm.com assert(dram_pkt->rankRef.isAvailable()); 134110393Swendy.elsasser@arm.com // here we get a bit creative and shift the bus busy time not 134210393Swendy.elsasser@arm.com // just the tWTR, but also a CAS latency to capture the fact 134310393Swendy.elsasser@arm.com // that we are allowed to prepare a new bank, but not issue a 134410393Swendy.elsasser@arm.com // read command until after tWTR, in essence we capture a 134510393Swendy.elsasser@arm.com // bubble on the data bus that is tWTR + tCL 134610394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 134710394Swendy.elsasser@arm.com busBusyUntil += tWTR + tCL; 134810393Swendy.elsasser@arm.com } 134910393Swendy.elsasser@arm.com 135010215Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 135110206Sandreas.hansson@arm.com 135210206Sandreas.hansson@arm.com // At this point we're done dealing with the request 135310215Sandreas.hansson@arm.com readQueue.pop_front(); 135410215Sandreas.hansson@arm.com 135510215Sandreas.hansson@arm.com // sanity check 135610215Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 135710215Sandreas.hansson@arm.com assert(dram_pkt->readyTime >= curTick()); 135810215Sandreas.hansson@arm.com 135910215Sandreas.hansson@arm.com // Insert into response queue. It will be sent back to the 136010215Sandreas.hansson@arm.com // requestor at its readyTime 136110215Sandreas.hansson@arm.com if (respQueue.empty()) { 136210215Sandreas.hansson@arm.com assert(!respondEvent.scheduled()); 136310215Sandreas.hansson@arm.com schedule(respondEvent, dram_pkt->readyTime); 136410215Sandreas.hansson@arm.com } else { 136510215Sandreas.hansson@arm.com assert(respQueue.back()->readyTime <= dram_pkt->readyTime); 136610215Sandreas.hansson@arm.com assert(respondEvent.scheduled()); 136710215Sandreas.hansson@arm.com } 136810215Sandreas.hansson@arm.com 136910215Sandreas.hansson@arm.com respQueue.push_back(dram_pkt); 137010206Sandreas.hansson@arm.com 137110206Sandreas.hansson@arm.com // we have so many writes that we have to transition 137210206Sandreas.hansson@arm.com if (writeQueue.size() > writeHighThreshold) { 137310206Sandreas.hansson@arm.com switch_to_writes = true; 137410206Sandreas.hansson@arm.com } 137510206Sandreas.hansson@arm.com } 137610206Sandreas.hansson@arm.com 137710206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 137810206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 137910206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 138010206Sandreas.hansson@arm.com if (switch_to_writes) { 138110206Sandreas.hansson@arm.com // transition to writing 138210206Sandreas.hansson@arm.com busState = READ_TO_WRITE; 138310206Sandreas.hansson@arm.com } 13849352SN/A } else { 138510618SOmar.Naji@arm.com // bool to check if write to free rank is found 138610618SOmar.Naji@arm.com bool found_write = false; 138710618SOmar.Naji@arm.com 138810618SOmar.Naji@arm.com found_write = chooseNext(writeQueue, switched_cmd_type); 138910618SOmar.Naji@arm.com 139010618SOmar.Naji@arm.com // if no writes to an available rank are found then return. 139110618SOmar.Naji@arm.com // There could be reads to the available ranks. However, to avoid 139210618SOmar.Naji@arm.com // adding more complexity to the code, return at this point and wait 139310618SOmar.Naji@arm.com // for a refresh event to kick things into action again. 139410618SOmar.Naji@arm.com if (!found_write) 139510618SOmar.Naji@arm.com return; 139610618SOmar.Naji@arm.com 139710206Sandreas.hansson@arm.com DRAMPacket* dram_pkt = writeQueue.front(); 139810618SOmar.Naji@arm.com assert(dram_pkt->rankRef.isAvailable()); 139910206Sandreas.hansson@arm.com // sanity check 140010206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 140110393Swendy.elsasser@arm.com 140210394Swendy.elsasser@arm.com // add a bubble to the data bus, as defined by the 140310394Swendy.elsasser@arm.com // tRTW when access is to the same rank as previous burst 140410394Swendy.elsasser@arm.com // Different rank timing is handled with tCS, which is 140510394Swendy.elsasser@arm.com // applied to colAllowedAt 140610394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 140710394Swendy.elsasser@arm.com busBusyUntil += tRTW; 140810393Swendy.elsasser@arm.com } 140910393Swendy.elsasser@arm.com 141010206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 141110206Sandreas.hansson@arm.com 141210206Sandreas.hansson@arm.com writeQueue.pop_front(); 141310206Sandreas.hansson@arm.com delete dram_pkt; 141410206Sandreas.hansson@arm.com 141510206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 141610206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 141710206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 141810206Sandreas.hansson@arm.com // writes, then switch to reads. 141910206Sandreas.hansson@arm.com if (writeQueue.empty() || 142010206Sandreas.hansson@arm.com (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 142110206Sandreas.hansson@arm.com !drainManager) || 142210206Sandreas.hansson@arm.com (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 142310206Sandreas.hansson@arm.com // turn the bus back around for reads again 142410206Sandreas.hansson@arm.com busState = WRITE_TO_READ; 142510206Sandreas.hansson@arm.com 142610206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 142710206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 142810206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 142910206Sandreas.hansson@arm.com // nothing to do 143010206Sandreas.hansson@arm.com } 143110206Sandreas.hansson@arm.com } 143210618SOmar.Naji@arm.com // It is possible that a refresh to another rank kicks things back into 143310618SOmar.Naji@arm.com // action before reaching this point. 143410618SOmar.Naji@arm.com if (!nextReqEvent.scheduled()) 143510618SOmar.Naji@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 143610206Sandreas.hansson@arm.com 143710206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 143810206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 143910206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 144010206Sandreas.hansson@arm.com // the next request processing 144110206Sandreas.hansson@arm.com if (retryWrReq && writeQueue.size() < writeBufferSize) { 144210206Sandreas.hansson@arm.com retryWrReq = false; 144310206Sandreas.hansson@arm.com port.sendRetry(); 14449352SN/A } 14459243SN/A} 14469243SN/A 14479967SN/Auint64_t 144810393Swendy.elsasser@arm.comDRAMCtrl::minBankPrep(const deque<DRAMPacket*>& queue, 144910393Swendy.elsasser@arm.com bool switched_cmd_type) const 14509967SN/A{ 14519967SN/A uint64_t bank_mask = 0; 145210211Sandreas.hansson@arm.com Tick min_act_at = MaxTick; 14539967SN/A 145410393Swendy.elsasser@arm.com uint64_t bank_mask_same_rank = 0; 145510393Swendy.elsasser@arm.com Tick min_act_at_same_rank = MaxTick; 145610393Swendy.elsasser@arm.com 145710393Swendy.elsasser@arm.com // Give precedence to commands that access same rank as previous command 145810393Swendy.elsasser@arm.com bool same_rank_match = false; 145910393Swendy.elsasser@arm.com 146010393Swendy.elsasser@arm.com // determine if we have queued transactions targetting the 14619967SN/A // bank in question 14629967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 146310618SOmar.Naji@arm.com for (const auto& p : queue) { 146410618SOmar.Naji@arm.com if(p->rankRef.isAvailable()) 146510618SOmar.Naji@arm.com got_waiting[p->bankId] = true; 14669967SN/A } 14679967SN/A 14689967SN/A for (int i = 0; i < ranksPerChannel; i++) { 14699967SN/A for (int j = 0; j < banksPerRank; j++) { 147010618SOmar.Naji@arm.com uint16_t bank_id = i * banksPerRank + j; 147110211Sandreas.hansson@arm.com 14729967SN/A // if we have waiting requests for the bank, and it is 14739967SN/A // amongst the first available, update the mask 147410211Sandreas.hansson@arm.com if (got_waiting[bank_id]) { 147510618SOmar.Naji@arm.com // make sure this rank is not currently refreshing. 147610618SOmar.Naji@arm.com assert(ranks[i]->isAvailable()); 147710211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue 147810211Sandreas.hansson@arm.com // an activate, ignoring any rank-to-rank switching 147910393Swendy.elsasser@arm.com // cost in this calculation 148010618SOmar.Naji@arm.com Tick act_at = ranks[i]->banks[j].openRow == Bank::NO_ROW ? 148110618SOmar.Naji@arm.com ranks[i]->banks[j].actAllowedAt : 148210618SOmar.Naji@arm.com std::max(ranks[i]->banks[j].preAllowedAt, curTick()) + tRP; 148310211Sandreas.hansson@arm.com 148410393Swendy.elsasser@arm.com // prioritize commands that access the 148510393Swendy.elsasser@arm.com // same rank as previous burst 148610393Swendy.elsasser@arm.com // Calculate bank mask separately for the case and 148710393Swendy.elsasser@arm.com // evaluate after loop iterations complete 148810393Swendy.elsasser@arm.com if (i == activeRank && ranksPerChannel > 1) { 148910393Swendy.elsasser@arm.com if (act_at <= min_act_at_same_rank) { 149010393Swendy.elsasser@arm.com // reset same rank bank mask if new minimum is found 149110393Swendy.elsasser@arm.com // and previous minimum could not immediately send ACT 149210393Swendy.elsasser@arm.com if (act_at < min_act_at_same_rank && 149310393Swendy.elsasser@arm.com min_act_at_same_rank > curTick()) 149410393Swendy.elsasser@arm.com bank_mask_same_rank = 0; 149510393Swendy.elsasser@arm.com 149610393Swendy.elsasser@arm.com // Set flag indicating that a same rank 149710393Swendy.elsasser@arm.com // opportunity was found 149810393Swendy.elsasser@arm.com same_rank_match = true; 149910393Swendy.elsasser@arm.com 150010393Swendy.elsasser@arm.com // set the bit corresponding to the available bank 150110393Swendy.elsasser@arm.com replaceBits(bank_mask_same_rank, bank_id, bank_id, 1); 150210393Swendy.elsasser@arm.com min_act_at_same_rank = act_at; 150310393Swendy.elsasser@arm.com } 150410393Swendy.elsasser@arm.com } else { 150510393Swendy.elsasser@arm.com if (act_at <= min_act_at) { 150610393Swendy.elsasser@arm.com // reset bank mask if new minimum is found 150710393Swendy.elsasser@arm.com // and either previous minimum could not immediately send ACT 150810393Swendy.elsasser@arm.com if (act_at < min_act_at && min_act_at > curTick()) 150910393Swendy.elsasser@arm.com bank_mask = 0; 151010393Swendy.elsasser@arm.com // set the bit corresponding to the available bank 151110393Swendy.elsasser@arm.com replaceBits(bank_mask, bank_id, bank_id, 1); 151210393Swendy.elsasser@arm.com min_act_at = act_at; 151310393Swendy.elsasser@arm.com } 151410211Sandreas.hansson@arm.com } 15159967SN/A } 15169967SN/A } 15179967SN/A } 151810211Sandreas.hansson@arm.com 151910393Swendy.elsasser@arm.com // Determine the earliest time when the next burst can issue based 152010393Swendy.elsasser@arm.com // on the current busBusyUntil delay. 152110393Swendy.elsasser@arm.com // Offset by tRCD to correlate with ACT timing variables 152210393Swendy.elsasser@arm.com Tick min_cmd_at = busBusyUntil - tCL - tRCD; 152310393Swendy.elsasser@arm.com 152410617SOmar.Naji@arm.com // if we have multiple ranks and all 152510617SOmar.Naji@arm.com // waiting packets are accessing a rank which was previously active 152610617SOmar.Naji@arm.com // then bank_mask_same_rank will be set to a value while bank_mask will 152710617SOmar.Naji@arm.com // remain 0. In this case, the function should return the value of 152810617SOmar.Naji@arm.com // bank_mask_same_rank. 152910617SOmar.Naji@arm.com // else if waiting packets access a rank which was previously active and 153010617SOmar.Naji@arm.com // other ranks, prioritize same rank accesses that can issue B2B 153110393Swendy.elsasser@arm.com // Only optimize for same ranks when the command type 153210393Swendy.elsasser@arm.com // does not change; do not want to unnecessarily incur tWTR 153310393Swendy.elsasser@arm.com // 153410393Swendy.elsasser@arm.com // Resulting FCFS prioritization Order is: 153510393Swendy.elsasser@arm.com // 1) Commands that access the same rank as previous burst 153610393Swendy.elsasser@arm.com // and can prep the bank seamlessly. 153710393Swendy.elsasser@arm.com // 2) Commands (any rank) with earliest bank prep 153810617SOmar.Naji@arm.com if ((bank_mask == 0) || (!switched_cmd_type && same_rank_match && 153910617SOmar.Naji@arm.com min_act_at_same_rank <= min_cmd_at)) { 154010393Swendy.elsasser@arm.com bank_mask = bank_mask_same_rank; 154110393Swendy.elsasser@arm.com } 154210393Swendy.elsasser@arm.com 15439967SN/A return bank_mask; 15449967SN/A} 15459967SN/A 154610618SOmar.Naji@arm.comDRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p) 154710618SOmar.Naji@arm.com : EventManager(&_memory), memory(_memory), 154810618SOmar.Naji@arm.com pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), pwrStateTick(0), 154910618SOmar.Naji@arm.com refreshState(REF_IDLE), refreshDueAt(0), 155010618SOmar.Naji@arm.com power(_p, false), numBanksActive(0), 155110618SOmar.Naji@arm.com activateEvent(*this), prechargeEvent(*this), 155210618SOmar.Naji@arm.com refreshEvent(*this), powerEvent(*this) 155310618SOmar.Naji@arm.com{ } 155410618SOmar.Naji@arm.com 15559243SN/Avoid 155610618SOmar.Naji@arm.comDRAMCtrl::Rank::startup(Tick ref_tick) 155710618SOmar.Naji@arm.com{ 155810618SOmar.Naji@arm.com assert(ref_tick > curTick()); 155910618SOmar.Naji@arm.com 156010618SOmar.Naji@arm.com pwrStateTick = curTick(); 156110618SOmar.Naji@arm.com 156210618SOmar.Naji@arm.com // kick off the refresh, and give ourselves enough time to 156310618SOmar.Naji@arm.com // precharge 156410618SOmar.Naji@arm.com schedule(refreshEvent, ref_tick); 156510618SOmar.Naji@arm.com} 156610618SOmar.Naji@arm.com 156710618SOmar.Naji@arm.comvoid 156810619Sandreas.hansson@arm.comDRAMCtrl::Rank::suspend() 156910619Sandreas.hansson@arm.com{ 157010619Sandreas.hansson@arm.com deschedule(refreshEvent); 157110619Sandreas.hansson@arm.com} 157210619Sandreas.hansson@arm.com 157310619Sandreas.hansson@arm.comvoid 157410618SOmar.Naji@arm.comDRAMCtrl::Rank::checkDrainDone() 157510618SOmar.Naji@arm.com{ 157610618SOmar.Naji@arm.com // if this rank was waiting to drain it is now able to proceed to 157710618SOmar.Naji@arm.com // precharge 157810618SOmar.Naji@arm.com if (refreshState == REF_DRAIN) { 157910618SOmar.Naji@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 158010618SOmar.Naji@arm.com 158110618SOmar.Naji@arm.com refreshState = REF_PRE; 158210618SOmar.Naji@arm.com 158310618SOmar.Naji@arm.com // hand control back to the refresh event loop 158410618SOmar.Naji@arm.com schedule(refreshEvent, curTick()); 158510618SOmar.Naji@arm.com } 158610618SOmar.Naji@arm.com} 158710618SOmar.Naji@arm.com 158810618SOmar.Naji@arm.comvoid 158910618SOmar.Naji@arm.comDRAMCtrl::Rank::processActivateEvent() 159010618SOmar.Naji@arm.com{ 159110618SOmar.Naji@arm.com // we should transition to the active state as soon as any bank is active 159210618SOmar.Naji@arm.com if (pwrState != PWR_ACT) 159310618SOmar.Naji@arm.com // note that at this point numBanksActive could be back at 159410618SOmar.Naji@arm.com // zero again due to a precharge scheduled in the future 159510618SOmar.Naji@arm.com schedulePowerEvent(PWR_ACT, curTick()); 159610618SOmar.Naji@arm.com} 159710618SOmar.Naji@arm.com 159810618SOmar.Naji@arm.comvoid 159910618SOmar.Naji@arm.comDRAMCtrl::Rank::processPrechargeEvent() 160010618SOmar.Naji@arm.com{ 160110618SOmar.Naji@arm.com // if we reached zero, then special conditions apply as we track 160210618SOmar.Naji@arm.com // if all banks are precharged for the power models 160310618SOmar.Naji@arm.com if (numBanksActive == 0) { 160410618SOmar.Naji@arm.com // we should transition to the idle state when the last bank 160510618SOmar.Naji@arm.com // is precharged 160610618SOmar.Naji@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 160710618SOmar.Naji@arm.com } 160810618SOmar.Naji@arm.com} 160910618SOmar.Naji@arm.com 161010618SOmar.Naji@arm.comvoid 161110618SOmar.Naji@arm.comDRAMCtrl::Rank::processRefreshEvent() 16129243SN/A{ 161310207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 161410207Sandreas.hansson@arm.com if (refreshState == REF_IDLE) { 161510207Sandreas.hansson@arm.com // remember when the refresh is due 161610207Sandreas.hansson@arm.com refreshDueAt = curTick(); 16179243SN/A 161810207Sandreas.hansson@arm.com // proceed to drain 161910207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 16209243SN/A 162110207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 162210207Sandreas.hansson@arm.com } 162310207Sandreas.hansson@arm.com 162410618SOmar.Naji@arm.com // let any scheduled read or write to the same rank go ahead, 162510618SOmar.Naji@arm.com // after which it will 162610207Sandreas.hansson@arm.com // hand control back to this event loop 162710207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 162810618SOmar.Naji@arm.com // if a request is at the moment being handled and this request is 162910618SOmar.Naji@arm.com // accessing the current rank then wait for it to finish 163010618SOmar.Naji@arm.com if ((rank == memory.activeRank) 163110618SOmar.Naji@arm.com && (memory.nextReqEvent.scheduled())) { 163210207Sandreas.hansson@arm.com // hand control over to the request loop until it is 163310207Sandreas.hansson@arm.com // evaluated next 163410207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 163510207Sandreas.hansson@arm.com 163610207Sandreas.hansson@arm.com return; 163710207Sandreas.hansson@arm.com } else { 163810207Sandreas.hansson@arm.com refreshState = REF_PRE; 163910207Sandreas.hansson@arm.com } 164010207Sandreas.hansson@arm.com } 164110207Sandreas.hansson@arm.com 164210207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 164310207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 164410208Sandreas.hansson@arm.com // precharge any active bank if we are not already in the idle 164510208Sandreas.hansson@arm.com // state 164610208Sandreas.hansson@arm.com if (pwrState != PWR_IDLE) { 164710214Sandreas.hansson@arm.com // at the moment, we use a precharge all even if there is 164810214Sandreas.hansson@arm.com // only a single bank open 164910208Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 165010214Sandreas.hansson@arm.com 165110214Sandreas.hansson@arm.com // first determine when we can precharge 165210214Sandreas.hansson@arm.com Tick pre_at = curTick(); 165310618SOmar.Naji@arm.com 165410618SOmar.Naji@arm.com for (auto &b : banks) { 165510618SOmar.Naji@arm.com // respect both causality and any existing bank 165610618SOmar.Naji@arm.com // constraints, some banks could already have a 165710618SOmar.Naji@arm.com // (auto) precharge scheduled 165810618SOmar.Naji@arm.com pre_at = std::max(b.preAllowedAt, pre_at); 165910618SOmar.Naji@arm.com } 166010618SOmar.Naji@arm.com 166110618SOmar.Naji@arm.com // make sure all banks per rank are precharged, and for those that 166210618SOmar.Naji@arm.com // already are, update their availability 166310618SOmar.Naji@arm.com Tick act_allowed_at = pre_at + memory.tRP; 166410618SOmar.Naji@arm.com 166510618SOmar.Naji@arm.com for (auto &b : banks) { 166610618SOmar.Naji@arm.com if (b.openRow != Bank::NO_ROW) { 166710618SOmar.Naji@arm.com memory.prechargeBank(*this, b, pre_at, false); 166810618SOmar.Naji@arm.com } else { 166910618SOmar.Naji@arm.com b.actAllowedAt = std::max(b.actAllowedAt, act_allowed_at); 167010618SOmar.Naji@arm.com b.preAllowedAt = std::max(b.preAllowedAt, pre_at); 167110214Sandreas.hansson@arm.com } 167210214Sandreas.hansson@arm.com } 167310214Sandreas.hansson@arm.com 167410618SOmar.Naji@arm.com // precharge all banks in rank 167510618SOmar.Naji@arm.com power.powerlib.doCommand(MemCommand::PREA, 0, 167610618SOmar.Naji@arm.com divCeil(pre_at, memory.tCK) - 167710618SOmar.Naji@arm.com memory.timeStampOffset); 167810214Sandreas.hansson@arm.com 167910618SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PREA,0,%d\n", 168010618SOmar.Naji@arm.com divCeil(pre_at, memory.tCK) - 168110618SOmar.Naji@arm.com memory.timeStampOffset, rank); 168210208Sandreas.hansson@arm.com } else { 168310208Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 168410208Sandreas.hansson@arm.com 168510208Sandreas.hansson@arm.com // go ahead and kick the power state machine into gear if 168610208Sandreas.hansson@arm.com // we are already idle 168710208Sandreas.hansson@arm.com schedulePowerEvent(PWR_REF, curTick()); 16889975SN/A } 16899975SN/A 169010208Sandreas.hansson@arm.com refreshState = REF_RUN; 169110208Sandreas.hansson@arm.com assert(numBanksActive == 0); 16929243SN/A 169310208Sandreas.hansson@arm.com // wait for all banks to be precharged, at which point the 169410208Sandreas.hansson@arm.com // power state machine will transition to the idle state, and 169510208Sandreas.hansson@arm.com // automatically move to a refresh, at that point it will also 169610208Sandreas.hansson@arm.com // call this method to get the refresh event loop going again 169710207Sandreas.hansson@arm.com return; 169810207Sandreas.hansson@arm.com } 169910207Sandreas.hansson@arm.com 170010207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 170110207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 170210207Sandreas.hansson@arm.com // should never get here with any banks active 170310207Sandreas.hansson@arm.com assert(numBanksActive == 0); 170410208Sandreas.hansson@arm.com assert(pwrState == PWR_REF); 170510207Sandreas.hansson@arm.com 170610618SOmar.Naji@arm.com Tick ref_done_at = curTick() + memory.tRFC; 170710207Sandreas.hansson@arm.com 170810618SOmar.Naji@arm.com for (auto &b : banks) { 170910618SOmar.Naji@arm.com b.actAllowedAt = ref_done_at; 171010618SOmar.Naji@arm.com } 171110247Sandreas.hansson@arm.com 171210618SOmar.Naji@arm.com // at the moment this affects all ranks 171310618SOmar.Naji@arm.com power.powerlib.doCommand(MemCommand::REF, 0, 171410618SOmar.Naji@arm.com divCeil(curTick(), memory.tCK) - 171510618SOmar.Naji@arm.com memory.timeStampOffset); 171610432SOmar.Naji@arm.com 171710618SOmar.Naji@arm.com // at the moment sort the list of commands and update the counters 171810618SOmar.Naji@arm.com // for DRAMPower libray when doing a refresh 171910618SOmar.Naji@arm.com sort(power.powerlib.cmdList.begin(), 172010618SOmar.Naji@arm.com power.powerlib.cmdList.end(), DRAMCtrl::sortTime); 172110432SOmar.Naji@arm.com 172210618SOmar.Naji@arm.com // update the counters for DRAMPower, passing false to 172310618SOmar.Naji@arm.com // indicate that this is not the last command in the 172410618SOmar.Naji@arm.com // list. DRAMPower requires this information for the 172510618SOmar.Naji@arm.com // correct calculation of the background energy at the end 172610618SOmar.Naji@arm.com // of the simulation. Ideally we would want to call this 172710618SOmar.Naji@arm.com // function with true once at the end of the 172810618SOmar.Naji@arm.com // simulation. However, the discarded energy is extremly 172910618SOmar.Naji@arm.com // small and does not effect the final results. 173010618SOmar.Naji@arm.com power.powerlib.updateCounters(false); 173110432SOmar.Naji@arm.com 173210618SOmar.Naji@arm.com // call the energy function 173310618SOmar.Naji@arm.com power.powerlib.calcEnergy(); 173410432SOmar.Naji@arm.com 173510618SOmar.Naji@arm.com // Update the stats 173610618SOmar.Naji@arm.com updatePowerStats(); 173710432SOmar.Naji@arm.com 173810618SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), memory.tCK) - 173910618SOmar.Naji@arm.com memory.timeStampOffset, rank); 174010207Sandreas.hansson@arm.com 174110207Sandreas.hansson@arm.com // make sure we did not wait so long that we cannot make up 174210207Sandreas.hansson@arm.com // for it 174310618SOmar.Naji@arm.com if (refreshDueAt + memory.tREFI < ref_done_at) { 174410207Sandreas.hansson@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 174510207Sandreas.hansson@arm.com } 174610207Sandreas.hansson@arm.com 174710207Sandreas.hansson@arm.com // compensate for the delay in actually performing the refresh 174810207Sandreas.hansson@arm.com // when scheduling the next one 174910618SOmar.Naji@arm.com schedule(refreshEvent, refreshDueAt + memory.tREFI - memory.tRP); 175010207Sandreas.hansson@arm.com 175110208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 175210207Sandreas.hansson@arm.com 175310208Sandreas.hansson@arm.com // move to the idle power state once the refresh is done, this 175410208Sandreas.hansson@arm.com // will also move the refresh state machine to the refresh 175510208Sandreas.hansson@arm.com // idle state 175610211Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, ref_done_at); 175710207Sandreas.hansson@arm.com 175810208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n", 175910618SOmar.Naji@arm.com ref_done_at, refreshDueAt + memory.tREFI); 176010208Sandreas.hansson@arm.com } 176110208Sandreas.hansson@arm.com} 176210208Sandreas.hansson@arm.com 176310208Sandreas.hansson@arm.comvoid 176410618SOmar.Naji@arm.comDRAMCtrl::Rank::schedulePowerEvent(PowerState pwr_state, Tick tick) 176510208Sandreas.hansson@arm.com{ 176610208Sandreas.hansson@arm.com // respect causality 176710208Sandreas.hansson@arm.com assert(tick >= curTick()); 176810208Sandreas.hansson@arm.com 176910208Sandreas.hansson@arm.com if (!powerEvent.scheduled()) { 177010208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 177110208Sandreas.hansson@arm.com tick, pwr_state); 177210208Sandreas.hansson@arm.com 177310208Sandreas.hansson@arm.com // insert the new transition 177410208Sandreas.hansson@arm.com pwrStateTrans = pwr_state; 177510208Sandreas.hansson@arm.com 177610208Sandreas.hansson@arm.com schedule(powerEvent, tick); 177710208Sandreas.hansson@arm.com } else { 177810208Sandreas.hansson@arm.com panic("Scheduled power event at %llu to state %d, " 177910208Sandreas.hansson@arm.com "with scheduled event at %llu to %d\n", tick, pwr_state, 178010208Sandreas.hansson@arm.com powerEvent.when(), pwrStateTrans); 178110208Sandreas.hansson@arm.com } 178210208Sandreas.hansson@arm.com} 178310208Sandreas.hansson@arm.com 178410208Sandreas.hansson@arm.comvoid 178510618SOmar.Naji@arm.comDRAMCtrl::Rank::processPowerEvent() 178610208Sandreas.hansson@arm.com{ 178710208Sandreas.hansson@arm.com // remember where we were, and for how long 178810208Sandreas.hansson@arm.com Tick duration = curTick() - pwrStateTick; 178910208Sandreas.hansson@arm.com PowerState prev_state = pwrState; 179010208Sandreas.hansson@arm.com 179110208Sandreas.hansson@arm.com // update the accounting 179210208Sandreas.hansson@arm.com pwrStateTime[prev_state] += duration; 179310208Sandreas.hansson@arm.com 179410208Sandreas.hansson@arm.com pwrState = pwrStateTrans; 179510208Sandreas.hansson@arm.com pwrStateTick = curTick(); 179610208Sandreas.hansson@arm.com 179710208Sandreas.hansson@arm.com if (pwrState == PWR_IDLE) { 179810208Sandreas.hansson@arm.com DPRINTF(DRAMState, "All banks precharged\n"); 179910208Sandreas.hansson@arm.com 180010208Sandreas.hansson@arm.com // if we were refreshing, make sure we start scheduling requests again 180110208Sandreas.hansson@arm.com if (prev_state == PWR_REF) { 180210208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 180310208Sandreas.hansson@arm.com assert(pwrState == PWR_IDLE); 180410208Sandreas.hansson@arm.com 180510208Sandreas.hansson@arm.com // kick things into action again 180610208Sandreas.hansson@arm.com refreshState = REF_IDLE; 180710618SOmar.Naji@arm.com // a request event could be already scheduled by the state 180810618SOmar.Naji@arm.com // machine of the other rank 180910618SOmar.Naji@arm.com if (!memory.nextReqEvent.scheduled()) 181010618SOmar.Naji@arm.com schedule(memory.nextReqEvent, curTick()); 181110208Sandreas.hansson@arm.com } else { 181210208Sandreas.hansson@arm.com assert(prev_state == PWR_ACT); 181310208Sandreas.hansson@arm.com 181410208Sandreas.hansson@arm.com // if we have a pending refresh, and are now moving to 181510208Sandreas.hansson@arm.com // the idle state, direclty transition to a refresh 181610208Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 181710208Sandreas.hansson@arm.com // there should be nothing waiting at this point 181810208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 181910208Sandreas.hansson@arm.com 182010208Sandreas.hansson@arm.com // update the state in zero time and proceed below 182110208Sandreas.hansson@arm.com pwrState = PWR_REF; 182210208Sandreas.hansson@arm.com } 182310208Sandreas.hansson@arm.com } 182410208Sandreas.hansson@arm.com } 182510208Sandreas.hansson@arm.com 182610208Sandreas.hansson@arm.com // we transition to the refresh state, let the refresh state 182710208Sandreas.hansson@arm.com // machine know of this state update and let it deal with the 182810208Sandreas.hansson@arm.com // scheduling of the next power state transition as well as the 182910208Sandreas.hansson@arm.com // following refresh 183010208Sandreas.hansson@arm.com if (pwrState == PWR_REF) { 183110208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refreshing\n"); 183210208Sandreas.hansson@arm.com // kick the refresh event loop into action again, and that 183310208Sandreas.hansson@arm.com // in turn will schedule a transition to the idle power 183410208Sandreas.hansson@arm.com // state once the refresh is done 183510208Sandreas.hansson@arm.com assert(refreshState == REF_RUN); 183610208Sandreas.hansson@arm.com processRefreshEvent(); 183710207Sandreas.hansson@arm.com } 18389243SN/A} 18399243SN/A 18409243SN/Avoid 184110618SOmar.Naji@arm.comDRAMCtrl::Rank::updatePowerStats() 184210432SOmar.Naji@arm.com{ 184310432SOmar.Naji@arm.com // Get the energy and power from DRAMPower 184410432SOmar.Naji@arm.com Data::MemoryPowerModel::Energy energy = 184510618SOmar.Naji@arm.com power.powerlib.getEnergy(); 184610618SOmar.Naji@arm.com Data::MemoryPowerModel::Power rank_power = 184710618SOmar.Naji@arm.com power.powerlib.getPower(); 184810432SOmar.Naji@arm.com 184910618SOmar.Naji@arm.com actEnergy = energy.act_energy * memory.devicesPerRank; 185010618SOmar.Naji@arm.com preEnergy = energy.pre_energy * memory.devicesPerRank; 185110618SOmar.Naji@arm.com readEnergy = energy.read_energy * memory.devicesPerRank; 185210618SOmar.Naji@arm.com writeEnergy = energy.write_energy * memory.devicesPerRank; 185310618SOmar.Naji@arm.com refreshEnergy = energy.ref_energy * memory.devicesPerRank; 185410618SOmar.Naji@arm.com actBackEnergy = energy.act_stdby_energy * memory.devicesPerRank; 185510618SOmar.Naji@arm.com preBackEnergy = energy.pre_stdby_energy * memory.devicesPerRank; 185610618SOmar.Naji@arm.com totalEnergy = energy.total_energy * memory.devicesPerRank; 185710618SOmar.Naji@arm.com averagePower = rank_power.average_power * memory.devicesPerRank; 185810432SOmar.Naji@arm.com} 185910432SOmar.Naji@arm.com 186010432SOmar.Naji@arm.comvoid 186110618SOmar.Naji@arm.comDRAMCtrl::Rank::regStats() 186210618SOmar.Naji@arm.com{ 186310618SOmar.Naji@arm.com using namespace Stats; 186410618SOmar.Naji@arm.com 186510618SOmar.Naji@arm.com pwrStateTime 186610618SOmar.Naji@arm.com .init(5) 186710618SOmar.Naji@arm.com .name(name() + ".memoryStateTime") 186810618SOmar.Naji@arm.com .desc("Time in different power states"); 186910618SOmar.Naji@arm.com pwrStateTime.subname(0, "IDLE"); 187010618SOmar.Naji@arm.com pwrStateTime.subname(1, "REF"); 187110618SOmar.Naji@arm.com pwrStateTime.subname(2, "PRE_PDN"); 187210618SOmar.Naji@arm.com pwrStateTime.subname(3, "ACT"); 187310618SOmar.Naji@arm.com pwrStateTime.subname(4, "ACT_PDN"); 187410618SOmar.Naji@arm.com 187510618SOmar.Naji@arm.com actEnergy 187610618SOmar.Naji@arm.com .name(name() + ".actEnergy") 187710618SOmar.Naji@arm.com .desc("Energy for activate commands per rank (pJ)"); 187810618SOmar.Naji@arm.com 187910618SOmar.Naji@arm.com preEnergy 188010618SOmar.Naji@arm.com .name(name() + ".preEnergy") 188110618SOmar.Naji@arm.com .desc("Energy for precharge commands per rank (pJ)"); 188210618SOmar.Naji@arm.com 188310618SOmar.Naji@arm.com readEnergy 188410618SOmar.Naji@arm.com .name(name() + ".readEnergy") 188510618SOmar.Naji@arm.com .desc("Energy for read commands per rank (pJ)"); 188610618SOmar.Naji@arm.com 188710618SOmar.Naji@arm.com writeEnergy 188810618SOmar.Naji@arm.com .name(name() + ".writeEnergy") 188910618SOmar.Naji@arm.com .desc("Energy for write commands per rank (pJ)"); 189010618SOmar.Naji@arm.com 189110618SOmar.Naji@arm.com refreshEnergy 189210618SOmar.Naji@arm.com .name(name() + ".refreshEnergy") 189310618SOmar.Naji@arm.com .desc("Energy for refresh commands per rank (pJ)"); 189410618SOmar.Naji@arm.com 189510618SOmar.Naji@arm.com actBackEnergy 189610618SOmar.Naji@arm.com .name(name() + ".actBackEnergy") 189710618SOmar.Naji@arm.com .desc("Energy for active background per rank (pJ)"); 189810618SOmar.Naji@arm.com 189910618SOmar.Naji@arm.com preBackEnergy 190010618SOmar.Naji@arm.com .name(name() + ".preBackEnergy") 190110618SOmar.Naji@arm.com .desc("Energy for precharge background per rank (pJ)"); 190210618SOmar.Naji@arm.com 190310618SOmar.Naji@arm.com totalEnergy 190410618SOmar.Naji@arm.com .name(name() + ".totalEnergy") 190510618SOmar.Naji@arm.com .desc("Total energy per rank (pJ)"); 190610618SOmar.Naji@arm.com 190710618SOmar.Naji@arm.com averagePower 190810618SOmar.Naji@arm.com .name(name() + ".averagePower") 190910618SOmar.Naji@arm.com .desc("Core power per rank (mW)"); 191010618SOmar.Naji@arm.com} 191110618SOmar.Naji@arm.comvoid 191210146Sandreas.hansson@arm.comDRAMCtrl::regStats() 19139243SN/A{ 19149243SN/A using namespace Stats; 19159243SN/A 19169243SN/A AbstractMemory::regStats(); 19179243SN/A 191810618SOmar.Naji@arm.com for (auto r : ranks) { 191910618SOmar.Naji@arm.com r->regStats(); 192010618SOmar.Naji@arm.com } 192110618SOmar.Naji@arm.com 19229243SN/A readReqs 19239243SN/A .name(name() + ".readReqs") 19249977SN/A .desc("Number of read requests accepted"); 19259243SN/A 19269243SN/A writeReqs 19279243SN/A .name(name() + ".writeReqs") 19289977SN/A .desc("Number of write requests accepted"); 19299831SN/A 19309831SN/A readBursts 19319831SN/A .name(name() + ".readBursts") 19329977SN/A .desc("Number of DRAM read bursts, " 19339977SN/A "including those serviced by the write queue"); 19349831SN/A 19359831SN/A writeBursts 19369831SN/A .name(name() + ".writeBursts") 19379977SN/A .desc("Number of DRAM write bursts, " 19389977SN/A "including those merged in the write queue"); 19399243SN/A 19409243SN/A servicedByWrQ 19419243SN/A .name(name() + ".servicedByWrQ") 19429977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 19439977SN/A 19449977SN/A mergedWrBursts 19459977SN/A .name(name() + ".mergedWrBursts") 19469977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 19479243SN/A 19489243SN/A neitherReadNorWrite 19499977SN/A .name(name() + ".neitherReadNorWriteReqs") 19509977SN/A .desc("Number of requests that are neither read nor write"); 19519243SN/A 19529977SN/A perBankRdBursts 19539243SN/A .init(banksPerRank * ranksPerChannel) 19549977SN/A .name(name() + ".perBankRdBursts") 19559977SN/A .desc("Per bank write bursts"); 19569243SN/A 19579977SN/A perBankWrBursts 19589243SN/A .init(banksPerRank * ranksPerChannel) 19599977SN/A .name(name() + ".perBankWrBursts") 19609977SN/A .desc("Per bank write bursts"); 19619243SN/A 19629243SN/A avgRdQLen 19639243SN/A .name(name() + ".avgRdQLen") 19649977SN/A .desc("Average read queue length when enqueuing") 19659243SN/A .precision(2); 19669243SN/A 19679243SN/A avgWrQLen 19689243SN/A .name(name() + ".avgWrQLen") 19699977SN/A .desc("Average write queue length when enqueuing") 19709243SN/A .precision(2); 19719243SN/A 19729243SN/A totQLat 19739243SN/A .name(name() + ".totQLat") 19749977SN/A .desc("Total ticks spent queuing"); 19759243SN/A 19769243SN/A totBusLat 19779243SN/A .name(name() + ".totBusLat") 19789977SN/A .desc("Total ticks spent in databus transfers"); 19799243SN/A 19809243SN/A totMemAccLat 19819243SN/A .name(name() + ".totMemAccLat") 19829977SN/A .desc("Total ticks spent from burst creation until serviced " 19839977SN/A "by the DRAM"); 19849243SN/A 19859243SN/A avgQLat 19869243SN/A .name(name() + ".avgQLat") 19879977SN/A .desc("Average queueing delay per DRAM burst") 19889243SN/A .precision(2); 19899243SN/A 19909831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 19919243SN/A 19929243SN/A avgBusLat 19939243SN/A .name(name() + ".avgBusLat") 19949977SN/A .desc("Average bus latency per DRAM burst") 19959243SN/A .precision(2); 19969243SN/A 19979831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 19989243SN/A 19999243SN/A avgMemAccLat 20009243SN/A .name(name() + ".avgMemAccLat") 20019977SN/A .desc("Average memory access latency per DRAM burst") 20029243SN/A .precision(2); 20039243SN/A 20049831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 20059243SN/A 20069243SN/A numRdRetry 20079243SN/A .name(name() + ".numRdRetry") 20089977SN/A .desc("Number of times read queue was full causing retry"); 20099243SN/A 20109243SN/A numWrRetry 20119243SN/A .name(name() + ".numWrRetry") 20129977SN/A .desc("Number of times write queue was full causing retry"); 20139243SN/A 20149243SN/A readRowHits 20159243SN/A .name(name() + ".readRowHits") 20169243SN/A .desc("Number of row buffer hits during reads"); 20179243SN/A 20189243SN/A writeRowHits 20199243SN/A .name(name() + ".writeRowHits") 20209243SN/A .desc("Number of row buffer hits during writes"); 20219243SN/A 20229243SN/A readRowHitRate 20239243SN/A .name(name() + ".readRowHitRate") 20249243SN/A .desc("Row buffer hit rate for reads") 20259243SN/A .precision(2); 20269243SN/A 20279831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 20289243SN/A 20299243SN/A writeRowHitRate 20309243SN/A .name(name() + ".writeRowHitRate") 20319243SN/A .desc("Row buffer hit rate for writes") 20329243SN/A .precision(2); 20339243SN/A 20349977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 20359243SN/A 20369243SN/A readPktSize 20379831SN/A .init(ceilLog2(burstSize) + 1) 20389243SN/A .name(name() + ".readPktSize") 20399977SN/A .desc("Read request sizes (log2)"); 20409243SN/A 20419243SN/A writePktSize 20429831SN/A .init(ceilLog2(burstSize) + 1) 20439243SN/A .name(name() + ".writePktSize") 20449977SN/A .desc("Write request sizes (log2)"); 20459243SN/A 20469243SN/A rdQLenPdf 20479567SN/A .init(readBufferSize) 20489243SN/A .name(name() + ".rdQLenPdf") 20499243SN/A .desc("What read queue length does an incoming req see"); 20509243SN/A 20519243SN/A wrQLenPdf 20529567SN/A .init(writeBufferSize) 20539243SN/A .name(name() + ".wrQLenPdf") 20549243SN/A .desc("What write queue length does an incoming req see"); 20559243SN/A 20569727SN/A bytesPerActivate 205710141SN/A .init(maxAccessesPerRow) 20589727SN/A .name(name() + ".bytesPerActivate") 20599727SN/A .desc("Bytes accessed per row activation") 20609727SN/A .flags(nozero); 20619243SN/A 206210147Sandreas.hansson@arm.com rdPerTurnAround 206310147Sandreas.hansson@arm.com .init(readBufferSize) 206410147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 206510147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 206610147Sandreas.hansson@arm.com .flags(nozero); 206710147Sandreas.hansson@arm.com 206810147Sandreas.hansson@arm.com wrPerTurnAround 206910147Sandreas.hansson@arm.com .init(writeBufferSize) 207010147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 207110147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 207210147Sandreas.hansson@arm.com .flags(nozero); 207310147Sandreas.hansson@arm.com 20749975SN/A bytesReadDRAM 20759975SN/A .name(name() + ".bytesReadDRAM") 20769975SN/A .desc("Total number of bytes read from DRAM"); 20779975SN/A 20789975SN/A bytesReadWrQ 20799975SN/A .name(name() + ".bytesReadWrQ") 20809975SN/A .desc("Total number of bytes read from write queue"); 20819243SN/A 20829243SN/A bytesWritten 20839243SN/A .name(name() + ".bytesWritten") 20849977SN/A .desc("Total number of bytes written to DRAM"); 20859243SN/A 20869977SN/A bytesReadSys 20879977SN/A .name(name() + ".bytesReadSys") 20889977SN/A .desc("Total read bytes from the system interface side"); 20899243SN/A 20909977SN/A bytesWrittenSys 20919977SN/A .name(name() + ".bytesWrittenSys") 20929977SN/A .desc("Total written bytes from the system interface side"); 20939243SN/A 20949243SN/A avgRdBW 20959243SN/A .name(name() + ".avgRdBW") 20969977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 20979243SN/A .precision(2); 20989243SN/A 20999977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 21009243SN/A 21019243SN/A avgWrBW 21029243SN/A .name(name() + ".avgWrBW") 21039977SN/A .desc("Average achieved write bandwidth in MiByte/s") 21049243SN/A .precision(2); 21059243SN/A 21069243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 21079243SN/A 21089977SN/A avgRdBWSys 21099977SN/A .name(name() + ".avgRdBWSys") 21109977SN/A .desc("Average system read bandwidth in MiByte/s") 21119243SN/A .precision(2); 21129243SN/A 21139977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 21149243SN/A 21159977SN/A avgWrBWSys 21169977SN/A .name(name() + ".avgWrBWSys") 21179977SN/A .desc("Average system write bandwidth in MiByte/s") 21189243SN/A .precision(2); 21199243SN/A 21209977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 21219243SN/A 21229243SN/A peakBW 21239243SN/A .name(name() + ".peakBW") 21249977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 21259243SN/A .precision(2); 21269243SN/A 21279831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 21289243SN/A 21299243SN/A busUtil 21309243SN/A .name(name() + ".busUtil") 21319243SN/A .desc("Data bus utilization in percentage") 21329243SN/A .precision(2); 21339243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 21349243SN/A 21359243SN/A totGap 21369243SN/A .name(name() + ".totGap") 21379243SN/A .desc("Total gap between requests"); 21389243SN/A 21399243SN/A avgGap 21409243SN/A .name(name() + ".avgGap") 21419243SN/A .desc("Average gap between requests") 21429243SN/A .precision(2); 21439243SN/A 21449243SN/A avgGap = totGap / (readReqs + writeReqs); 21459975SN/A 21469975SN/A // Stats for DRAM Power calculation based on Micron datasheet 21479975SN/A busUtilRead 21489975SN/A .name(name() + ".busUtilRead") 21499975SN/A .desc("Data bus utilization in percentage for reads") 21509975SN/A .precision(2); 21519975SN/A 21529975SN/A busUtilRead = avgRdBW / peakBW * 100; 21539975SN/A 21549975SN/A busUtilWrite 21559975SN/A .name(name() + ".busUtilWrite") 21569975SN/A .desc("Data bus utilization in percentage for writes") 21579975SN/A .precision(2); 21589975SN/A 21599975SN/A busUtilWrite = avgWrBW / peakBW * 100; 21609975SN/A 21619975SN/A pageHitRate 21629975SN/A .name(name() + ".pageHitRate") 21639975SN/A .desc("Row buffer hit rate, read and write combined") 21649975SN/A .precision(2); 21659975SN/A 21669977SN/A pageHitRate = (writeRowHits + readRowHits) / 21679977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 21689243SN/A} 21699243SN/A 21709243SN/Avoid 217110146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 21729243SN/A{ 21739243SN/A // rely on the abstract memory 21749243SN/A functionalAccess(pkt); 21759243SN/A} 21769243SN/A 21779294SN/ABaseSlavePort& 217810146Sandreas.hansson@arm.comDRAMCtrl::getSlavePort(const string &if_name, PortID idx) 21799243SN/A{ 21809243SN/A if (if_name != "port") { 21819243SN/A return MemObject::getSlavePort(if_name, idx); 21829243SN/A } else { 21839243SN/A return port; 21849243SN/A } 21859243SN/A} 21869243SN/A 21879243SN/Aunsigned int 218810146Sandreas.hansson@arm.comDRAMCtrl::drain(DrainManager *dm) 21899243SN/A{ 21909342SN/A unsigned int count = port.drain(dm); 21919243SN/A 21929243SN/A // if there is anything in any of our internal queues, keep track 21939243SN/A // of that as well 21949567SN/A if (!(writeQueue.empty() && readQueue.empty() && 21959567SN/A respQueue.empty())) { 21969352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 21979567SN/A " resp: %d\n", writeQueue.size(), readQueue.size(), 21989567SN/A respQueue.size()); 21999243SN/A ++count; 22009342SN/A drainManager = dm; 220110206Sandreas.hansson@arm.com 22029352SN/A // the only part that is not drained automatically over time 220310206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 220410206Sandreas.hansson@arm.com if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 220510206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 220610206Sandreas.hansson@arm.com } 22079243SN/A } 22089243SN/A 22099243SN/A if (count) 22109342SN/A setDrainState(Drainable::Draining); 22119243SN/A else 22129342SN/A setDrainState(Drainable::Drained); 22139243SN/A return count; 22149243SN/A} 22159243SN/A 221610619Sandreas.hansson@arm.comvoid 221710619Sandreas.hansson@arm.comDRAMCtrl::drainResume() 221810619Sandreas.hansson@arm.com{ 221910619Sandreas.hansson@arm.com if (!isTimingMode && system()->isTimingMode()) { 222010619Sandreas.hansson@arm.com // if we switched to timing mode, kick things into action, 222110619Sandreas.hansson@arm.com // and behave as if we restored from a checkpoint 222210619Sandreas.hansson@arm.com startup(); 222310619Sandreas.hansson@arm.com } else if (isTimingMode && !system()->isTimingMode()) { 222410619Sandreas.hansson@arm.com // if we switch from timing mode, stop the refresh events to 222510619Sandreas.hansson@arm.com // not cause issues with KVM 222610619Sandreas.hansson@arm.com for (auto r : ranks) { 222710619Sandreas.hansson@arm.com r->suspend(); 222810619Sandreas.hansson@arm.com } 222910619Sandreas.hansson@arm.com } 223010619Sandreas.hansson@arm.com 223110619Sandreas.hansson@arm.com // update the mode 223210619Sandreas.hansson@arm.com isTimingMode = system()->isTimingMode(); 223310619Sandreas.hansson@arm.com} 223410619Sandreas.hansson@arm.com 223510146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 22369243SN/A : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 22379243SN/A memory(_memory) 22389243SN/A{ } 22399243SN/A 22409243SN/AAddrRangeList 224110146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 22429243SN/A{ 22439243SN/A AddrRangeList ranges; 22449243SN/A ranges.push_back(memory.getAddrRange()); 22459243SN/A return ranges; 22469243SN/A} 22479243SN/A 22489243SN/Avoid 224910146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 22509243SN/A{ 22519243SN/A pkt->pushLabel(memory.name()); 22529243SN/A 22539243SN/A if (!queue.checkFunctional(pkt)) { 22549243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 22559243SN/A // calls recvAtomic() and throws away the latency; we can save a 22569243SN/A // little here by just not calculating the latency. 22579243SN/A memory.recvFunctional(pkt); 22589243SN/A } 22599243SN/A 22609243SN/A pkt->popLabel(); 22619243SN/A} 22629243SN/A 22639243SN/ATick 226410146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 22659243SN/A{ 22669243SN/A return memory.recvAtomic(pkt); 22679243SN/A} 22689243SN/A 22699243SN/Abool 227010146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 22719243SN/A{ 22729243SN/A // pass it to the memory controller 22739243SN/A return memory.recvTimingReq(pkt); 22749243SN/A} 22759243SN/A 227610146Sandreas.hansson@arm.comDRAMCtrl* 227710146Sandreas.hansson@arm.comDRAMCtrlParams::create() 22789243SN/A{ 227910146Sandreas.hansson@arm.com return new DRAMCtrl(this); 22809243SN/A} 2281