dram_ctrl.cc revision 10619
19243SN/A/* 210206Sandreas.hansson@arm.com * Copyright (c) 2010-2014 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 4310618SOmar.Naji@arm.com * Omar Naji 449243SN/A */ 459243SN/A 4610146Sandreas.hansson@arm.com#include "base/bitfield.hh" 479356SN/A#include "base/trace.hh" 4810146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 4910247Sandreas.hansson@arm.com#include "debug/DRAMPower.hh" 5010208Sandreas.hansson@arm.com#include "debug/DRAMState.hh" 519352SN/A#include "debug/Drain.hh" 5210146Sandreas.hansson@arm.com#include "mem/dram_ctrl.hh" 539814SN/A#include "sim/system.hh" 549243SN/A 559243SN/Ausing namespace std; 5610432SOmar.Naji@arm.comusing namespace Data; 579243SN/A 5810146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 599243SN/A AbstractMemory(p), 6010619Sandreas.hansson@arm.com port(name() + ".port", *this), isTimingMode(false), 619243SN/A retryRdReq(false), retryWrReq(false), 6210211Sandreas.hansson@arm.com busState(READ), 6310618SOmar.Naji@arm.com nextReqEvent(this), respondEvent(this), 6410208Sandreas.hansson@arm.com drainManager(NULL), 6510489SOmar.Naji@arm.com deviceSize(p->device_size), 669831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 679831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 689831SN/A devicesPerRank(p->devices_per_rank), 699831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 709831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 7110140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 7210286Sandreas.hansson@arm.com columnsPerStripe(range.granularity() / burstSize), 739243SN/A ranksPerChannel(p->ranks_per_channel), 7410394Swendy.elsasser@arm.com bankGroupsPerRank(p->bank_groups_per_rank), 7510394Swendy.elsasser@arm.com bankGroupArch(p->bank_groups_per_rank > 0), 769566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 779243SN/A readBufferSize(p->read_buffer_size), 789243SN/A writeBufferSize(p->write_buffer_size), 7910140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 8010140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 8110147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 8210147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 8310393Swendy.elsasser@arm.com tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST), 8410394Swendy.elsasser@arm.com tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), 8510394Swendy.elsasser@arm.com tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 8610394Swendy.elsasser@arm.com tRRD_L(p->tRRD_L), tXAW(p->tXAW), activationLimit(p->activation_limit), 879243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 889243SN/A pageMgmt(p->page_policy), 8910141SN/A maxAccessesPerRow(p->max_accesses_per_row), 909726SN/A frontendLatency(p->static_frontend_latency), 919726SN/A backendLatency(p->static_backend_latency), 9210618SOmar.Naji@arm.com busBusyUntil(0), prevArrival(0), 9310618SOmar.Naji@arm.com nextReqTime(0), activeRank(0), timeStampOffset(0) 949243SN/A{ 9510618SOmar.Naji@arm.com for (int i = 0; i < ranksPerChannel; i++) { 9610618SOmar.Naji@arm.com Rank* rank = new Rank(*this, p); 9710618SOmar.Naji@arm.com ranks.push_back(rank); 9810432SOmar.Naji@arm.com 9910618SOmar.Naji@arm.com rank->actTicks.resize(activationLimit, 0); 10010618SOmar.Naji@arm.com rank->banks.resize(banksPerRank); 10110618SOmar.Naji@arm.com rank->rank = i; 10210432SOmar.Naji@arm.com 10310246Sandreas.hansson@arm.com for (int b = 0; b < banksPerRank; b++) { 10410618SOmar.Naji@arm.com rank->banks[b].bank = b; 10510561SOmar.Naji@arm.com // GDDR addressing of banks to BG is linear. 10610561SOmar.Naji@arm.com // Here we assume that all DRAM generations address bank groups as 10710561SOmar.Naji@arm.com // follows: 10810394Swendy.elsasser@arm.com if (bankGroupArch) { 10910394Swendy.elsasser@arm.com // Simply assign lower bits to bank group in order to 11010394Swendy.elsasser@arm.com // rotate across bank groups as banks are incremented 11110394Swendy.elsasser@arm.com // e.g. with 4 banks per bank group and 16 banks total: 11210394Swendy.elsasser@arm.com // banks 0,4,8,12 are in bank group 0 11310394Swendy.elsasser@arm.com // banks 1,5,9,13 are in bank group 1 11410394Swendy.elsasser@arm.com // banks 2,6,10,14 are in bank group 2 11510394Swendy.elsasser@arm.com // banks 3,7,11,15 are in bank group 3 11610618SOmar.Naji@arm.com rank->banks[b].bankgr = b % bankGroupsPerRank; 11710394Swendy.elsasser@arm.com } else { 11810394Swendy.elsasser@arm.com // No bank groups; simply assign to bank number 11910618SOmar.Naji@arm.com rank->banks[b].bankgr = b; 12010394Swendy.elsasser@arm.com } 12110246Sandreas.hansson@arm.com } 12210246Sandreas.hansson@arm.com } 12310246Sandreas.hansson@arm.com 12410140SN/A // perform a basic check of the write thresholds 12510140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 12610140SN/A fatal("Write buffer low threshold %d must be smaller than the " 12710140SN/A "high threshold %d\n", p->write_low_thresh_perc, 12810140SN/A p->write_high_thresh_perc); 1299243SN/A 1309243SN/A // determine the rows per bank by looking at the total capacity 1319567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1329243SN/A 13310489SOmar.Naji@arm.com // determine the dram actual capacity from the DRAM config in Mbytes 13410489SOmar.Naji@arm.com uint64_t deviceCapacity = deviceSize / (1024 * 1024) * devicesPerRank * 13510489SOmar.Naji@arm.com ranksPerChannel; 13610489SOmar.Naji@arm.com 13710489SOmar.Naji@arm.com // if actual DRAM size does not match memory capacity in system warn! 13810489SOmar.Naji@arm.com if (deviceCapacity != capacity / (1024 * 1024)) 13910489SOmar.Naji@arm.com warn("DRAM device capacity (%d Mbytes) does not match the " 14010489SOmar.Naji@arm.com "address range assigned (%d Mbytes)\n", deviceCapacity, 14110489SOmar.Naji@arm.com capacity / (1024 * 1024)); 14210489SOmar.Naji@arm.com 1439243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1449243SN/A AbstractMemory::size()); 1459831SN/A 1469831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1479831SN/A rowBufferSize, columnsPerRowBuffer); 1489831SN/A 1499831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1509243SN/A 15110286Sandreas.hansson@arm.com // a bit of sanity checks on the interleaving 1529566SN/A if (range.interleaved()) { 1539566SN/A if (channels != range.stripes()) 15410143SN/A fatal("%s has %d interleaved address stripes but %d channel(s)\n", 1559566SN/A name(), range.stripes(), channels); 1569566SN/A 15710136SN/A if (addrMapping == Enums::RoRaBaChCo) { 1589831SN/A if (rowBufferSize != range.granularity()) { 15910286Sandreas.hansson@arm.com fatal("Channel interleaving of %s doesn't match RoRaBaChCo " 16010136SN/A "address map\n", name()); 1619566SN/A } 16210286Sandreas.hansson@arm.com } else if (addrMapping == Enums::RoRaBaCoCh || 16310286Sandreas.hansson@arm.com addrMapping == Enums::RoCoRaBaCh) { 16410286Sandreas.hansson@arm.com // for the interleavings with channel bits in the bottom, 16510286Sandreas.hansson@arm.com // if the system uses a channel striping granularity that 16610286Sandreas.hansson@arm.com // is larger than the DRAM burst size, then map the 16710286Sandreas.hansson@arm.com // sequential accesses within a stripe to a number of 16810286Sandreas.hansson@arm.com // columns in the DRAM, effectively placing some of the 16910286Sandreas.hansson@arm.com // lower-order column bits as the least-significant bits 17010286Sandreas.hansson@arm.com // of the address (above the ones denoting the burst size) 17110286Sandreas.hansson@arm.com assert(columnsPerStripe >= 1); 17210286Sandreas.hansson@arm.com 17310286Sandreas.hansson@arm.com // channel striping has to be done at a granularity that 17410286Sandreas.hansson@arm.com // is equal or larger to a cache line 17510286Sandreas.hansson@arm.com if (system()->cacheLineSize() > range.granularity()) { 17610286Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at least as large " 17710286Sandreas.hansson@arm.com "as the cache line size\n", name()); 1789669SN/A } 17910286Sandreas.hansson@arm.com 18010286Sandreas.hansson@arm.com // ...and equal or smaller than the row-buffer size 18110286Sandreas.hansson@arm.com if (rowBufferSize < range.granularity()) { 18210286Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at most as large " 18310286Sandreas.hansson@arm.com "as the row-buffer size\n", name()); 18410286Sandreas.hansson@arm.com } 18510286Sandreas.hansson@arm.com // this is essentially the check above, so just to be sure 18610286Sandreas.hansson@arm.com assert(columnsPerStripe <= columnsPerRowBuffer); 1879566SN/A } 1889566SN/A } 18910207Sandreas.hansson@arm.com 19010207Sandreas.hansson@arm.com // some basic sanity checks 19110207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 19210207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 19310207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 19410207Sandreas.hansson@arm.com } 19510394Swendy.elsasser@arm.com 19610394Swendy.elsasser@arm.com // basic bank group architecture checks -> 19710394Swendy.elsasser@arm.com if (bankGroupArch) { 19810394Swendy.elsasser@arm.com // must have at least one bank per bank group 19910394Swendy.elsasser@arm.com if (bankGroupsPerRank > banksPerRank) { 20010394Swendy.elsasser@arm.com fatal("banks per rank (%d) must be equal to or larger than " 20110394Swendy.elsasser@arm.com "banks groups per rank (%d)\n", 20210394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 20310394Swendy.elsasser@arm.com } 20410394Swendy.elsasser@arm.com // must have same number of banks in each bank group 20510394Swendy.elsasser@arm.com if ((banksPerRank % bankGroupsPerRank) != 0) { 20610394Swendy.elsasser@arm.com fatal("Banks per rank (%d) must be evenly divisible by bank groups " 20710394Swendy.elsasser@arm.com "per rank (%d) for equal banks per bank group\n", 20810394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 20910394Swendy.elsasser@arm.com } 21010394Swendy.elsasser@arm.com // tCCD_L should be greater than minimal, back-to-back burst delay 21110394Swendy.elsasser@arm.com if (tCCD_L <= tBURST) { 21210394Swendy.elsasser@arm.com fatal("tCCD_L (%d) should be larger than tBURST (%d) when " 21310394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 21410394Swendy.elsasser@arm.com tCCD_L, tBURST, bankGroupsPerRank); 21510394Swendy.elsasser@arm.com } 21610394Swendy.elsasser@arm.com // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay 21710561SOmar.Naji@arm.com // some datasheets might specify it equal to tRRD 21810561SOmar.Naji@arm.com if (tRRD_L < tRRD) { 21910394Swendy.elsasser@arm.com fatal("tRRD_L (%d) should be larger than tRRD (%d) when " 22010394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 22110394Swendy.elsasser@arm.com tRRD_L, tRRD, bankGroupsPerRank); 22210394Swendy.elsasser@arm.com } 22310394Swendy.elsasser@arm.com } 22410394Swendy.elsasser@arm.com 2259243SN/A} 2269243SN/A 2279243SN/Avoid 22810146Sandreas.hansson@arm.comDRAMCtrl::init() 22910140SN/A{ 23010466Sandreas.hansson@arm.com AbstractMemory::init(); 23110466Sandreas.hansson@arm.com 23210466Sandreas.hansson@arm.com if (!port.isConnected()) { 23310146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 23410140SN/A } else { 23510140SN/A port.sendRangeChange(); 23610140SN/A } 23710140SN/A} 23810140SN/A 23910140SN/Avoid 24010146Sandreas.hansson@arm.comDRAMCtrl::startup() 2419243SN/A{ 24210619Sandreas.hansson@arm.com // remember the memory system mode of operation 24310619Sandreas.hansson@arm.com isTimingMode = system()->isTimingMode(); 24410618SOmar.Naji@arm.com 24510619Sandreas.hansson@arm.com if (isTimingMode) { 24610619Sandreas.hansson@arm.com // timestamp offset should be in clock cycles for DRAMPower 24710619Sandreas.hansson@arm.com timeStampOffset = divCeil(curTick(), tCK); 24810619Sandreas.hansson@arm.com 24910619Sandreas.hansson@arm.com // update the start tick for the precharge accounting to the 25010619Sandreas.hansson@arm.com // current tick 25110619Sandreas.hansson@arm.com for (auto r : ranks) { 25210619Sandreas.hansson@arm.com r->startup(curTick() + tREFI - tRP); 25310619Sandreas.hansson@arm.com } 25410619Sandreas.hansson@arm.com 25510619Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 25610619Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 25710619Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 25810619Sandreas.hansson@arm.com // start of simulation 25910619Sandreas.hansson@arm.com busBusyUntil = curTick() + tRP + tRCD + tCL; 26010618SOmar.Naji@arm.com } 2619243SN/A} 2629243SN/A 2639243SN/ATick 26410146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 2659243SN/A{ 2669243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 2679243SN/A 2689243SN/A // do the actual memory access and turn the packet into a response 2699243SN/A access(pkt); 2709243SN/A 2719243SN/A Tick latency = 0; 2729243SN/A if (!pkt->memInhibitAsserted() && pkt->hasData()) { 2739243SN/A // this value is not supposed to be accurate, just enough to 2749243SN/A // keep things going, mimic a closed page 2759243SN/A latency = tRP + tRCD + tCL; 2769243SN/A } 2779243SN/A return latency; 2789243SN/A} 2799243SN/A 2809243SN/Abool 28110146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 2829243SN/A{ 2839831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 2849831SN/A readBufferSize, readQueue.size() + respQueue.size(), 2859831SN/A neededEntries); 2869243SN/A 2879831SN/A return 2889831SN/A (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 2899243SN/A} 2909243SN/A 2919243SN/Abool 29210146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 2939243SN/A{ 2949831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 2959831SN/A writeBufferSize, writeQueue.size(), neededEntries); 2969831SN/A return (writeQueue.size() + neededEntries) > writeBufferSize; 2979243SN/A} 2989243SN/A 29910146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 30010146Sandreas.hansson@arm.comDRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 30110143SN/A bool isRead) 3029243SN/A{ 3039669SN/A // decode the address based on the address mapping scheme, with 30410136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 30510136SN/A // channel, respectively 3069243SN/A uint8_t rank; 3079967SN/A uint8_t bank; 30810245Sandreas.hansson@arm.com // use a 64-bit unsigned during the computations as the row is 30910245Sandreas.hansson@arm.com // always the top bits, and check before creating the DRAMPacket 31010245Sandreas.hansson@arm.com uint64_t row; 3119243SN/A 31210286Sandreas.hansson@arm.com // truncate the address to a DRAM burst, which makes it unique to 31310286Sandreas.hansson@arm.com // a specific column, row, bank, rank and channel 3149831SN/A Addr addr = dramPktAddr / burstSize; 3159243SN/A 3169491SN/A // we have removed the lowest order address bits that denote the 3179831SN/A // position within the column 31810136SN/A if (addrMapping == Enums::RoRaBaChCo) { 3199491SN/A // the lowest order bits denote the column to ensure that 3209491SN/A // sequential cache lines occupy the same row 3219831SN/A addr = addr / columnsPerRowBuffer; 3229243SN/A 3239669SN/A // take out the channel part of the address 3249566SN/A addr = addr / channels; 3259566SN/A 3269669SN/A // after the channel bits, get the bank bits to interleave 3279669SN/A // over the banks 3289669SN/A bank = addr % banksPerRank; 3299669SN/A addr = addr / banksPerRank; 3309669SN/A 3319669SN/A // after the bank, we get the rank bits which thus interleaves 3329669SN/A // over the ranks 3339669SN/A rank = addr % ranksPerChannel; 3349669SN/A addr = addr / ranksPerChannel; 3359669SN/A 3369669SN/A // lastly, get the row bits 3379669SN/A row = addr % rowsPerBank; 3389669SN/A addr = addr / rowsPerBank; 33910136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 34010286Sandreas.hansson@arm.com // take out the lower-order column bits 34110286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 34210286Sandreas.hansson@arm.com 3439669SN/A // take out the channel part of the address 3449669SN/A addr = addr / channels; 3459669SN/A 34610286Sandreas.hansson@arm.com // next, the higher-order column bites 34710286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3489669SN/A 3499669SN/A // after the column bits, we get the bank bits to interleave 3509491SN/A // over the banks 3519243SN/A bank = addr % banksPerRank; 3529243SN/A addr = addr / banksPerRank; 3539243SN/A 3549491SN/A // after the bank, we get the rank bits which thus interleaves 3559491SN/A // over the ranks 3569243SN/A rank = addr % ranksPerChannel; 3579243SN/A addr = addr / ranksPerChannel; 3589243SN/A 3599491SN/A // lastly, get the row bits 3609243SN/A row = addr % rowsPerBank; 3619243SN/A addr = addr / rowsPerBank; 36210136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 3639491SN/A // optimise for closed page mode and utilise maximum 3649491SN/A // parallelism of the DRAM (at the cost of power) 3659491SN/A 36610286Sandreas.hansson@arm.com // take out the lower-order column bits 36710286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 36810286Sandreas.hansson@arm.com 3699566SN/A // take out the channel part of the address, not that this has 3709566SN/A // to match with how accesses are interleaved between the 3719566SN/A // controllers in the address mapping 3729566SN/A addr = addr / channels; 3739566SN/A 3749491SN/A // start with the bank bits, as this provides the maximum 3759491SN/A // opportunity for parallelism between requests 3769243SN/A bank = addr % banksPerRank; 3779243SN/A addr = addr / banksPerRank; 3789243SN/A 3799491SN/A // next get the rank bits 3809243SN/A rank = addr % ranksPerChannel; 3819243SN/A addr = addr / ranksPerChannel; 3829243SN/A 38310286Sandreas.hansson@arm.com // next, the higher-order column bites 38410286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3859243SN/A 3869491SN/A // lastly, get the row bits 3879243SN/A row = addr % rowsPerBank; 3889243SN/A addr = addr / rowsPerBank; 3899243SN/A } else 3909243SN/A panic("Unknown address mapping policy chosen!"); 3919243SN/A 3929243SN/A assert(rank < ranksPerChannel); 3939243SN/A assert(bank < banksPerRank); 3949243SN/A assert(row < rowsPerBank); 39510245Sandreas.hansson@arm.com assert(row < Bank::NO_ROW); 3969243SN/A 3979243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 3989831SN/A dramPktAddr, rank, bank, row); 3999243SN/A 4009243SN/A // create the corresponding DRAM packet with the entry time and 4019567SN/A // ready time set to the current tick, the latter will be updated 4029567SN/A // later 4039967SN/A uint16_t bank_id = banksPerRank * rank + bank; 4049967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 40510618SOmar.Naji@arm.com size, ranks[rank]->banks[bank], *ranks[rank]); 4069243SN/A} 4079243SN/A 4089243SN/Avoid 40910146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 4109243SN/A{ 4119243SN/A // only add to the read queue here. whenever the request is 4129243SN/A // eventually done, set the readyTime, and call schedule() 4139243SN/A assert(!pkt->isWrite()); 4149243SN/A 4159831SN/A assert(pktCount != 0); 4169831SN/A 4179831SN/A // if the request size is larger than burst size, the pkt is split into 4189831SN/A // multiple DRAM packets 4199831SN/A // Note if the pkt starting address is not aligened to burst size, the 4209831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 4219831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 4229831SN/A // check read packets against packets in write queue. 4239243SN/A Addr addr = pkt->getAddr(); 4249831SN/A unsigned pktsServicedByWrQ = 0; 4259831SN/A BurstHelper* burst_helper = NULL; 4269831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4279831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4289831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4299831SN/A readPktSize[ceilLog2(size)]++; 4309831SN/A readBursts++; 4319243SN/A 4329831SN/A // First check write buffer to see if the data is already at 4339831SN/A // the controller 4349831SN/A bool foundInWrQ = false; 4359833SN/A for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) { 4369832SN/A // check if the read is subsumed in the write entry we are 4379832SN/A // looking at 4389832SN/A if ((*i)->addr <= addr && 4399832SN/A (addr + size) <= ((*i)->addr + (*i)->size)) { 4409831SN/A foundInWrQ = true; 4419831SN/A servicedByWrQ++; 4429831SN/A pktsServicedByWrQ++; 4439831SN/A DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 4449831SN/A "write queue\n", addr, size); 4459975SN/A bytesReadWrQ += burstSize; 4469831SN/A break; 4479831SN/A } 4489243SN/A } 4499831SN/A 4509831SN/A // If not found in the write q, make a DRAM packet and 4519831SN/A // push it onto the read queue 4529831SN/A if (!foundInWrQ) { 4539831SN/A 4549831SN/A // Make the burst helper for split packets 4559831SN/A if (pktCount > 1 && burst_helper == NULL) { 4569831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 4579831SN/A "dram requests\n", pkt->getAddr(), pktCount); 4589831SN/A burst_helper = new BurstHelper(pktCount); 4599831SN/A } 4609831SN/A 4619966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 4629831SN/A dram_pkt->burstHelper = burst_helper; 4639831SN/A 4649831SN/A assert(!readQueueFull(1)); 4659831SN/A rdQLenPdf[readQueue.size() + respQueue.size()]++; 4669831SN/A 4679831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 4689831SN/A 4699831SN/A readQueue.push_back(dram_pkt); 4709831SN/A 4719831SN/A // Update stats 4729831SN/A avgRdQLen = readQueue.size() + respQueue.size(); 4739831SN/A } 4749831SN/A 4759831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 4769831SN/A addr = (addr | (burstSize - 1)) + 1; 4779243SN/A } 4789243SN/A 4799831SN/A // If all packets are serviced by write queue, we send the repsonse back 4809831SN/A if (pktsServicedByWrQ == pktCount) { 4819831SN/A accessAndRespond(pkt, frontendLatency); 4829831SN/A return; 4839831SN/A } 4849243SN/A 4859831SN/A // Update how many split packets are serviced by write queue 4869831SN/A if (burst_helper != NULL) 4879831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 4889243SN/A 48910206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 49010206Sandreas.hansson@arm.com // queue, do so now 49110206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 4929567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 4939567SN/A schedule(nextReqEvent, curTick()); 4949243SN/A } 4959243SN/A} 4969243SN/A 4979243SN/Avoid 49810146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 4999243SN/A{ 5009243SN/A // only add to the write queue here. whenever the request is 5019243SN/A // eventually done, set the readyTime, and call schedule() 5029243SN/A assert(pkt->isWrite()); 5039243SN/A 5049831SN/A // if the request size is larger than burst size, the pkt is split into 5059831SN/A // multiple DRAM packets 5069831SN/A Addr addr = pkt->getAddr(); 5079831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 5089831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 5099831SN/A pkt->getAddr() + pkt->getSize()) - addr; 5109831SN/A writePktSize[ceilLog2(size)]++; 5119831SN/A writeBursts++; 5129243SN/A 5139832SN/A // see if we can merge with an existing item in the write 5149838SN/A // queue and keep track of whether we have merged or not so we 5159838SN/A // can stop at that point and also avoid enqueueing a new 5169838SN/A // request 5179832SN/A bool merged = false; 5189832SN/A auto w = writeQueue.begin(); 5199243SN/A 5209832SN/A while(!merged && w != writeQueue.end()) { 5219832SN/A // either of the two could be first, if they are the same 5229832SN/A // it does not matter which way we go 5239832SN/A if ((*w)->addr >= addr) { 5249838SN/A // the existing one starts after the new one, figure 5259838SN/A // out where the new one ends with respect to the 5269838SN/A // existing one 5279832SN/A if ((addr + size) >= ((*w)->addr + (*w)->size)) { 5289832SN/A // check if the existing one is completely 5299832SN/A // subsumed in the new one 5309832SN/A DPRINTF(DRAM, "Merging write covering existing burst\n"); 5319832SN/A merged = true; 5329832SN/A // update both the address and the size 5339832SN/A (*w)->addr = addr; 5349832SN/A (*w)->size = size; 5359832SN/A } else if ((addr + size) >= (*w)->addr && 5369832SN/A ((*w)->addr + (*w)->size - addr) <= burstSize) { 5379832SN/A // the new one is just before or partially 5389832SN/A // overlapping with the existing one, and together 5399832SN/A // they fit within a burst 5409832SN/A DPRINTF(DRAM, "Merging write before existing burst\n"); 5419832SN/A merged = true; 5429832SN/A // the existing queue item needs to be adjusted with 5439832SN/A // respect to both address and size 54410047SN/A (*w)->size = (*w)->addr + (*w)->size - addr; 5459832SN/A (*w)->addr = addr; 5469832SN/A } 5479832SN/A } else { 5489838SN/A // the new one starts after the current one, figure 5499838SN/A // out where the existing one ends with respect to the 5509838SN/A // new one 5519832SN/A if (((*w)->addr + (*w)->size) >= (addr + size)) { 5529832SN/A // check if the new one is completely subsumed in the 5539832SN/A // existing one 5549832SN/A DPRINTF(DRAM, "Merging write into existing burst\n"); 5559832SN/A merged = true; 5569832SN/A // no adjustments necessary 5579832SN/A } else if (((*w)->addr + (*w)->size) >= addr && 5589832SN/A (addr + size - (*w)->addr) <= burstSize) { 5599832SN/A // the existing one is just before or partially 5609832SN/A // overlapping with the new one, and together 5619832SN/A // they fit within a burst 5629832SN/A DPRINTF(DRAM, "Merging write after existing burst\n"); 5639832SN/A merged = true; 5649832SN/A // the address is right, and only the size has 5659832SN/A // to be adjusted 5669832SN/A (*w)->size = addr + size - (*w)->addr; 5679832SN/A } 5689832SN/A } 5699832SN/A ++w; 5709832SN/A } 5719243SN/A 5729832SN/A // if the item was not merged we need to create a new write 5739832SN/A // and enqueue it 5749832SN/A if (!merged) { 5759966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 5769243SN/A 5779832SN/A assert(writeQueue.size() < writeBufferSize); 5789832SN/A wrQLenPdf[writeQueue.size()]++; 5799243SN/A 5809832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 5819831SN/A 5829832SN/A writeQueue.push_back(dram_pkt); 5839831SN/A 5849832SN/A // Update stats 5859832SN/A avgWrQLen = writeQueue.size(); 5869977SN/A } else { 5879977SN/A // keep track of the fact that this burst effectively 5889977SN/A // disappeared as it was merged with an existing one 5899977SN/A mergedWrBursts++; 5909832SN/A } 5919832SN/A 5929831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 5939831SN/A addr = (addr | (burstSize - 1)) + 1; 5949831SN/A } 5959243SN/A 5969243SN/A // we do not wait for the writes to be send to the actual memory, 5979243SN/A // but instead take responsibility for the consistency here and 5989243SN/A // snoop the write queue for any upcoming reads 5999831SN/A // @todo, if a pkt size is larger than burst size, we might need a 6009831SN/A // different front end latency 6019726SN/A accessAndRespond(pkt, frontendLatency); 6029243SN/A 60310206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 60410206Sandreas.hansson@arm.com // queue, do so now 60510206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 60610206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 60710206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 6089243SN/A } 6099243SN/A} 6109243SN/A 6119243SN/Avoid 61210146Sandreas.hansson@arm.comDRAMCtrl::printQs() const { 6139243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 6149833SN/A for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 6159243SN/A DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 6169243SN/A } 6179243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 6189833SN/A for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 6199243SN/A DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 6209243SN/A } 6219243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 6229833SN/A for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 6239243SN/A DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 6249243SN/A } 6259243SN/A} 6269243SN/A 6279243SN/Abool 62810146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 6299243SN/A{ 6309349SN/A /// @todo temporary hack to deal with memory corruption issues until 6319349SN/A /// 4-phase transactions are complete 6329349SN/A for (int x = 0; x < pendingDelete.size(); x++) 6339349SN/A delete pendingDelete[x]; 6349349SN/A pendingDelete.clear(); 6359349SN/A 6369243SN/A // This is where we enter from the outside world 6379567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 6389831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 6399243SN/A 6409567SN/A // simply drop inhibited packets for now 6419567SN/A if (pkt->memInhibitAsserted()) { 64210143SN/A DPRINTF(DRAM, "Inhibited packet -- Dropping it now\n"); 6439567SN/A pendingDelete.push_back(pkt); 6449567SN/A return true; 6459567SN/A } 6469243SN/A 6479243SN/A // Calc avg gap between requests 6489243SN/A if (prevArrival != 0) { 6499243SN/A totGap += curTick() - prevArrival; 6509243SN/A } 6519243SN/A prevArrival = curTick(); 6529243SN/A 6539831SN/A 6549831SN/A // Find out how many dram packets a pkt translates to 6559831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 6569831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 6579831SN/A // multiple dram packets 6589243SN/A unsigned size = pkt->getSize(); 6599831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 6609831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 6619243SN/A 6629243SN/A // check local buffers and do not accept if full 6639243SN/A if (pkt->isRead()) { 6649567SN/A assert(size != 0); 6659831SN/A if (readQueueFull(dram_pkt_count)) { 6669567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 6679243SN/A // remember that we have to retry this port 6689243SN/A retryRdReq = true; 6699243SN/A numRdRetry++; 6709243SN/A return false; 6719243SN/A } else { 6729831SN/A addToReadQueue(pkt, dram_pkt_count); 6739243SN/A readReqs++; 6749977SN/A bytesReadSys += size; 6759243SN/A } 6769243SN/A } else if (pkt->isWrite()) { 6779567SN/A assert(size != 0); 6789831SN/A if (writeQueueFull(dram_pkt_count)) { 6799567SN/A DPRINTF(DRAM, "Write queue full, not accepting\n"); 6809243SN/A // remember that we have to retry this port 6819243SN/A retryWrReq = true; 6829243SN/A numWrRetry++; 6839243SN/A return false; 6849243SN/A } else { 6859831SN/A addToWriteQueue(pkt, dram_pkt_count); 6869243SN/A writeReqs++; 6879977SN/A bytesWrittenSys += size; 6889243SN/A } 6899243SN/A } else { 6909243SN/A DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 6919243SN/A neitherReadNorWrite++; 6929726SN/A accessAndRespond(pkt, 1); 6939243SN/A } 6949243SN/A 6959243SN/A return true; 6969243SN/A} 6979243SN/A 6989243SN/Avoid 69910146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 7009243SN/A{ 7019243SN/A DPRINTF(DRAM, 7029243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 7039243SN/A 7049831SN/A DRAMPacket* dram_pkt = respQueue.front(); 7059243SN/A 7069831SN/A if (dram_pkt->burstHelper) { 7079831SN/A // it is a split packet 7089831SN/A dram_pkt->burstHelper->burstsServiced++; 7099831SN/A if (dram_pkt->burstHelper->burstsServiced == 71010143SN/A dram_pkt->burstHelper->burstCount) { 7119831SN/A // we have now serviced all children packets of a system packet 7129831SN/A // so we can now respond to the requester 7139831SN/A // @todo we probably want to have a different front end and back 7149831SN/A // end latency for split packets 7159831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7169831SN/A delete dram_pkt->burstHelper; 7179831SN/A dram_pkt->burstHelper = NULL; 7189831SN/A } 7199831SN/A } else { 7209831SN/A // it is not a split packet 7219831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7229831SN/A } 7239243SN/A 7249831SN/A delete respQueue.front(); 7259831SN/A respQueue.pop_front(); 7269243SN/A 7279831SN/A if (!respQueue.empty()) { 7289831SN/A assert(respQueue.front()->readyTime >= curTick()); 7299831SN/A assert(!respondEvent.scheduled()); 7309831SN/A schedule(respondEvent, respQueue.front()->readyTime); 7319831SN/A } else { 7329831SN/A // if there is nothing left in any queue, signal a drain 7339831SN/A if (writeQueue.empty() && readQueue.empty() && 7349831SN/A drainManager) { 73510509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 7369831SN/A drainManager->signalDrainDone(); 7379831SN/A drainManager = NULL; 7389831SN/A } 7399831SN/A } 7409567SN/A 7419831SN/A // We have made a location in the queue available at this point, 7429831SN/A // so if there is a read that was forced to wait, retry now 7439831SN/A if (retryRdReq) { 7449831SN/A retryRdReq = false; 7459831SN/A port.sendRetry(); 7469831SN/A } 7479243SN/A} 7489243SN/A 74910618SOmar.Naji@arm.combool 75010393Swendy.elsasser@arm.comDRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue, bool switched_cmd_type) 7519243SN/A{ 75210206Sandreas.hansson@arm.com // This method does the arbitration between requests. The chosen 75310206Sandreas.hansson@arm.com // packet is simply moved to the head of the queue. The other 75410206Sandreas.hansson@arm.com // methods know that this is the place to look. For example, with 75510206Sandreas.hansson@arm.com // FCFS, this method does nothing 75610206Sandreas.hansson@arm.com assert(!queue.empty()); 7579243SN/A 75810618SOmar.Naji@arm.com // bool to indicate if a packet to an available rank is found 75910618SOmar.Naji@arm.com bool found_packet = false; 76010206Sandreas.hansson@arm.com if (queue.size() == 1) { 76110618SOmar.Naji@arm.com DRAMPacket* dram_pkt = queue.front(); 76210618SOmar.Naji@arm.com // available rank corresponds to state refresh idle 76310618SOmar.Naji@arm.com if (ranks[dram_pkt->rank]->isAvailable()) { 76410618SOmar.Naji@arm.com found_packet = true; 76510618SOmar.Naji@arm.com DPRINTF(DRAM, "Single request, going to a free rank\n"); 76610618SOmar.Naji@arm.com } else { 76710618SOmar.Naji@arm.com DPRINTF(DRAM, "Single request, going to a busy rank\n"); 76810618SOmar.Naji@arm.com } 76910618SOmar.Naji@arm.com return found_packet; 7709243SN/A } 7719243SN/A 7729243SN/A if (memSchedPolicy == Enums::fcfs) { 77310618SOmar.Naji@arm.com // check if there is a packet going to a free rank 77410618SOmar.Naji@arm.com for(auto i = queue.begin(); i != queue.end() ; ++i) { 77510618SOmar.Naji@arm.com DRAMPacket* dram_pkt = *i; 77610618SOmar.Naji@arm.com if (ranks[dram_pkt->rank]->isAvailable()) { 77710618SOmar.Naji@arm.com queue.erase(i); 77810618SOmar.Naji@arm.com queue.push_front(dram_pkt); 77910618SOmar.Naji@arm.com found_packet = true; 78010618SOmar.Naji@arm.com break; 78110618SOmar.Naji@arm.com } 78210618SOmar.Naji@arm.com } 7839243SN/A } else if (memSchedPolicy == Enums::frfcfs) { 78410618SOmar.Naji@arm.com found_packet = reorderQueue(queue, switched_cmd_type); 7859243SN/A } else 7869243SN/A panic("No scheduling policy chosen\n"); 78710618SOmar.Naji@arm.com return found_packet; 7889243SN/A} 7899243SN/A 79010618SOmar.Naji@arm.combool 79110393Swendy.elsasser@arm.comDRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue, bool switched_cmd_type) 7929974SN/A{ 7939974SN/A // Only determine this when needed 7949974SN/A uint64_t earliest_banks = 0; 7959974SN/A 7969974SN/A // Search for row hits first, if no row hit is found then schedule the 7979974SN/A // packet to one of the earliest banks available 79810618SOmar.Naji@arm.com bool found_packet = false; 7999974SN/A bool found_earliest_pkt = false; 80010393Swendy.elsasser@arm.com bool found_prepped_diff_rank_pkt = false; 80110618SOmar.Naji@arm.com auto selected_pkt_it = queue.end(); 8029974SN/A 8039974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 8049974SN/A DRAMPacket* dram_pkt = *i; 8059974SN/A const Bank& bank = dram_pkt->bankRef; 80610618SOmar.Naji@arm.com // check if rank is busy. If this is the case jump to the next packet 8079974SN/A // Check if it is a row hit 80810618SOmar.Naji@arm.com if (dram_pkt->rankRef.isAvailable()) { 80910618SOmar.Naji@arm.com if (bank.openRow == dram_pkt->row) { 81010618SOmar.Naji@arm.com if (dram_pkt->rank == activeRank || switched_cmd_type) { 81110618SOmar.Naji@arm.com // FCFS within the hits, giving priority to commands 81210618SOmar.Naji@arm.com // that access the same rank as the previous burst 81310618SOmar.Naji@arm.com // to minimize bus turnaround delays 81410618SOmar.Naji@arm.com // Only give rank prioity when command type is 81510618SOmar.Naji@arm.com // not changing 81610618SOmar.Naji@arm.com DPRINTF(DRAM, "Row buffer hit\n"); 81710618SOmar.Naji@arm.com selected_pkt_it = i; 81810618SOmar.Naji@arm.com break; 81910618SOmar.Naji@arm.com } else if (!found_prepped_diff_rank_pkt) { 82010618SOmar.Naji@arm.com // found row hit for command on different rank 82110618SOmar.Naji@arm.com // than prev burst 82210618SOmar.Naji@arm.com selected_pkt_it = i; 82310618SOmar.Naji@arm.com found_prepped_diff_rank_pkt = true; 82410618SOmar.Naji@arm.com } 82510618SOmar.Naji@arm.com } else if (!found_earliest_pkt & !found_prepped_diff_rank_pkt) { 82610618SOmar.Naji@arm.com // packet going to a rank which is currently not waiting for a 82710618SOmar.Naji@arm.com // refresh, No row hit and 82810618SOmar.Naji@arm.com // haven't found an entry with a row hit to a new rank 82910618SOmar.Naji@arm.com if (earliest_banks == 0) 83010618SOmar.Naji@arm.com // Determine entries with earliest bank prep delay 83110618SOmar.Naji@arm.com // Function will give priority to commands that access the 83210618SOmar.Naji@arm.com // same rank as previous burst and can prep 83310618SOmar.Naji@arm.com // the bank seamlessly 83410618SOmar.Naji@arm.com earliest_banks = minBankPrep(queue, switched_cmd_type); 83510211Sandreas.hansson@arm.com 83610618SOmar.Naji@arm.com // FCFS - Bank is first available bank 83710618SOmar.Naji@arm.com if (bits(earliest_banks, dram_pkt->bankId, 83810618SOmar.Naji@arm.com dram_pkt->bankId)) { 83910618SOmar.Naji@arm.com // Remember the packet to be scheduled to one of 84010618SOmar.Naji@arm.com // the earliest banks available, FCFS amongst the 84110618SOmar.Naji@arm.com // earliest banks 84210618SOmar.Naji@arm.com selected_pkt_it = i; 84310618SOmar.Naji@arm.com //if the packet found is going to a rank that is currently 84410618SOmar.Naji@arm.com //not busy then update the found_packet to true 84510618SOmar.Naji@arm.com found_earliest_pkt = true; 84610618SOmar.Naji@arm.com } 8479974SN/A } 8489974SN/A } 8499974SN/A } 8509974SN/A 85110618SOmar.Naji@arm.com if (selected_pkt_it != queue.end()) { 85210618SOmar.Naji@arm.com DRAMPacket* selected_pkt = *selected_pkt_it; 85310618SOmar.Naji@arm.com queue.erase(selected_pkt_it); 85410618SOmar.Naji@arm.com queue.push_front(selected_pkt); 85510618SOmar.Naji@arm.com found_packet = true; 85610618SOmar.Naji@arm.com } 85710618SOmar.Naji@arm.com return found_packet; 8589974SN/A} 8599974SN/A 8609974SN/Avoid 86110146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 8629243SN/A{ 8639243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 8649243SN/A 8659243SN/A bool needsResponse = pkt->needsResponse(); 8669243SN/A // do the actual memory access which also turns the packet into a 8679243SN/A // response 8689243SN/A access(pkt); 8699243SN/A 8709243SN/A // turn packet around to go back to requester if response expected 8719243SN/A if (needsResponse) { 8729243SN/A // access already turned the packet into a response 8739243SN/A assert(pkt->isResponse()); 8749243SN/A 8759549SN/A // @todo someone should pay for this 87610405Sandreas.hansson@arm.com pkt->firstWordDelay = pkt->lastWordDelay = 0; 8779549SN/A 8789726SN/A // queue the packet in the response queue to be sent out after 8799726SN/A // the static latency has passed 8809726SN/A port.schedTimingResp(pkt, curTick() + static_latency); 8819243SN/A } else { 8829587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 8839587SN/A // is still having a pointer to it 8849587SN/A pendingDelete.push_back(pkt); 8859243SN/A } 8869243SN/A 8879243SN/A DPRINTF(DRAM, "Done\n"); 8889243SN/A 8899243SN/A return; 8909243SN/A} 8919243SN/A 8929243SN/Avoid 89310618SOmar.Naji@arm.comDRAMCtrl::activateBank(Rank& rank_ref, Bank& bank_ref, 89410618SOmar.Naji@arm.com Tick act_tick, uint32_t row) 8959488SN/A{ 89610618SOmar.Naji@arm.com assert(rank_ref.actTicks.size() == activationLimit); 8979488SN/A 8989488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 8999488SN/A 90010207Sandreas.hansson@arm.com // update the open row 90110618SOmar.Naji@arm.com assert(bank_ref.openRow == Bank::NO_ROW); 90210618SOmar.Naji@arm.com bank_ref.openRow = row; 90310207Sandreas.hansson@arm.com 90410207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 90510207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 90610207Sandreas.hansson@arm.com // precharge 90710618SOmar.Naji@arm.com bank_ref.bytesAccessed = 0; 90810618SOmar.Naji@arm.com bank_ref.rowAccesses = 0; 90910207Sandreas.hansson@arm.com 91010618SOmar.Naji@arm.com ++rank_ref.numBanksActive; 91110618SOmar.Naji@arm.com assert(rank_ref.numBanksActive <= banksPerRank); 91210207Sandreas.hansson@arm.com 91310247Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n", 91410618SOmar.Naji@arm.com bank_ref.bank, rank_ref.rank, act_tick, 91510618SOmar.Naji@arm.com ranks[rank_ref.rank]->numBanksActive); 91610247Sandreas.hansson@arm.com 91710618SOmar.Naji@arm.com rank_ref.power.powerlib.doCommand(MemCommand::ACT, bank_ref.bank, 91810618SOmar.Naji@arm.com divCeil(act_tick, tCK) - 91910618SOmar.Naji@arm.com timeStampOffset); 92010432SOmar.Naji@arm.com 92110432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK) - 92210618SOmar.Naji@arm.com timeStampOffset, bank_ref.bank, rank_ref.rank); 9239975SN/A 92410211Sandreas.hansson@arm.com // The next access has to respect tRAS for this bank 92510618SOmar.Naji@arm.com bank_ref.preAllowedAt = act_tick + tRAS; 92610211Sandreas.hansson@arm.com 92710211Sandreas.hansson@arm.com // Respect the row-to-column command delay 92810618SOmar.Naji@arm.com bank_ref.colAllowedAt = std::max(act_tick + tRCD, bank_ref.colAllowedAt); 92910211Sandreas.hansson@arm.com 9309971SN/A // start by enforcing tRRD 9319971SN/A for(int i = 0; i < banksPerRank; i++) { 93210210Sandreas.hansson@arm.com // next activate to any bank in this rank must not happen 93310210Sandreas.hansson@arm.com // before tRRD 93410618SOmar.Naji@arm.com if (bankGroupArch && (bank_ref.bankgr == rank_ref.banks[i].bankgr)) { 93510394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 93610394Swendy.elsasser@arm.com // ACT commands within the same bank group. Use tRRD_L 93710394Swendy.elsasser@arm.com // in this case 93810618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD_L, 93910618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt); 94010394Swendy.elsasser@arm.com } else { 94110394Swendy.elsasser@arm.com // use shorter tRRD value when either 94210394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 94310394Swendy.elsasser@arm.com // 2) bank is in a different bank group 94410618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD, 94510618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt); 94610394Swendy.elsasser@arm.com } 9479971SN/A } 94810208Sandreas.hansson@arm.com 9499971SN/A // next, we deal with tXAW, if the activation limit is disabled 95010492SOmar.Naji@arm.com // then we directly schedule an activate power event 95110618SOmar.Naji@arm.com if (!rank_ref.actTicks.empty()) { 95210492SOmar.Naji@arm.com // sanity check 95310618SOmar.Naji@arm.com if (rank_ref.actTicks.back() && 95410618SOmar.Naji@arm.com (act_tick - rank_ref.actTicks.back()) < tXAW) { 95510492SOmar.Naji@arm.com panic("Got %d activates in window %d (%llu - %llu) which " 95610492SOmar.Naji@arm.com "is smaller than %llu\n", activationLimit, act_tick - 95710618SOmar.Naji@arm.com rank_ref.actTicks.back(), act_tick, 95810618SOmar.Naji@arm.com rank_ref.actTicks.back(), tXAW); 95910492SOmar.Naji@arm.com } 9609824SN/A 96110492SOmar.Naji@arm.com // shift the times used for the book keeping, the last element 96210492SOmar.Naji@arm.com // (highest index) is the oldest one and hence the lowest value 96310618SOmar.Naji@arm.com rank_ref.actTicks.pop_back(); 9649488SN/A 96510492SOmar.Naji@arm.com // record an new activation (in the future) 96610618SOmar.Naji@arm.com rank_ref.actTicks.push_front(act_tick); 9679488SN/A 96810492SOmar.Naji@arm.com // cannot activate more than X times in time window tXAW, push the 96910492SOmar.Naji@arm.com // next one (the X + 1'st activate) to be tXAW away from the 97010492SOmar.Naji@arm.com // oldest in our window of X 97110618SOmar.Naji@arm.com if (rank_ref.actTicks.back() && 97210618SOmar.Naji@arm.com (act_tick - rank_ref.actTicks.back()) < tXAW) { 97310492SOmar.Naji@arm.com DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate " 97410492SOmar.Naji@arm.com "no earlier than %llu\n", activationLimit, 97510618SOmar.Naji@arm.com rank_ref.actTicks.back() + tXAW); 9769488SN/A for(int j = 0; j < banksPerRank; j++) 9779488SN/A // next activate must not happen before end of window 97810618SOmar.Naji@arm.com rank_ref.banks[j].actAllowedAt = 97910618SOmar.Naji@arm.com std::max(rank_ref.actTicks.back() + tXAW, 98010618SOmar.Naji@arm.com rank_ref.banks[j].actAllowedAt); 98110492SOmar.Naji@arm.com } 9829488SN/A } 98310208Sandreas.hansson@arm.com 98410208Sandreas.hansson@arm.com // at the point when this activate takes place, make sure we 98510208Sandreas.hansson@arm.com // transition to the active power state 98610618SOmar.Naji@arm.com if (!rank_ref.activateEvent.scheduled()) 98710618SOmar.Naji@arm.com schedule(rank_ref.activateEvent, act_tick); 98810618SOmar.Naji@arm.com else if (rank_ref.activateEvent.when() > act_tick) 98910208Sandreas.hansson@arm.com // move it sooner in time 99010618SOmar.Naji@arm.com reschedule(rank_ref.activateEvent, act_tick); 99110208Sandreas.hansson@arm.com} 99210208Sandreas.hansson@arm.com 99310208Sandreas.hansson@arm.comvoid 99410618SOmar.Naji@arm.comDRAMCtrl::prechargeBank(Rank& rank_ref, Bank& bank, Tick pre_at, bool trace) 99510207Sandreas.hansson@arm.com{ 99610207Sandreas.hansson@arm.com // make sure the bank has an open row 99710207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 99810207Sandreas.hansson@arm.com 99910207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 100010207Sandreas.hansson@arm.com // the page 100110207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 100210207Sandreas.hansson@arm.com 100310207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 100410207Sandreas.hansson@arm.com 100510214Sandreas.hansson@arm.com // no precharge allowed before this one 100610214Sandreas.hansson@arm.com bank.preAllowedAt = pre_at; 100710214Sandreas.hansson@arm.com 100810211Sandreas.hansson@arm.com Tick pre_done_at = pre_at + tRP; 100910211Sandreas.hansson@arm.com 101010211Sandreas.hansson@arm.com bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at); 101110207Sandreas.hansson@arm.com 101210618SOmar.Naji@arm.com assert(rank_ref.numBanksActive != 0); 101310618SOmar.Naji@arm.com --rank_ref.numBanksActive; 101410207Sandreas.hansson@arm.com 101510247Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got " 101610618SOmar.Naji@arm.com "%d active\n", bank.bank, rank_ref.rank, pre_at, 101710618SOmar.Naji@arm.com rank_ref.numBanksActive); 101810247Sandreas.hansson@arm.com 101910432SOmar.Naji@arm.com if (trace) { 102010207Sandreas.hansson@arm.com 102110618SOmar.Naji@arm.com rank_ref.power.powerlib.doCommand(MemCommand::PRE, bank.bank, 102210432SOmar.Naji@arm.com divCeil(pre_at, tCK) - 102310432SOmar.Naji@arm.com timeStampOffset); 102410432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK) - 102510618SOmar.Naji@arm.com timeStampOffset, bank.bank, rank_ref.rank); 102610432SOmar.Naji@arm.com } 102710208Sandreas.hansson@arm.com // if we look at the current number of active banks we might be 102810208Sandreas.hansson@arm.com // tempted to think the DRAM is now idle, however this can be 102910208Sandreas.hansson@arm.com // undone by an activate that is scheduled to happen before we 103010208Sandreas.hansson@arm.com // would have reached the idle state, so schedule an event and 103110208Sandreas.hansson@arm.com // rather check once we actually make it to the point in time when 103210208Sandreas.hansson@arm.com // the (last) precharge takes place 103310618SOmar.Naji@arm.com if (!rank_ref.prechargeEvent.scheduled()) 103410618SOmar.Naji@arm.com schedule(rank_ref.prechargeEvent, pre_done_at); 103510618SOmar.Naji@arm.com else if (rank_ref.prechargeEvent.when() < pre_done_at) 103610618SOmar.Naji@arm.com reschedule(rank_ref.prechargeEvent, pre_done_at); 103710207Sandreas.hansson@arm.com} 103810207Sandreas.hansson@arm.com 103910207Sandreas.hansson@arm.comvoid 104010146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 10419243SN/A{ 10429243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 10439243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 10449243SN/A 104510618SOmar.Naji@arm.com // get the rank 104610618SOmar.Naji@arm.com Rank& rank = dram_pkt->rankRef; 104710618SOmar.Naji@arm.com 104810211Sandreas.hansson@arm.com // get the bank 10499967SN/A Bank& bank = dram_pkt->bankRef; 10509243SN/A 105110211Sandreas.hansson@arm.com // for the state we need to track if it is a row hit or not 105210211Sandreas.hansson@arm.com bool row_hit = true; 105310211Sandreas.hansson@arm.com 105410211Sandreas.hansson@arm.com // respect any constraints on the command (e.g. tRCD or tCCD) 105510211Sandreas.hansson@arm.com Tick cmd_at = std::max(bank.colAllowedAt, curTick()); 105610211Sandreas.hansson@arm.com 105710211Sandreas.hansson@arm.com // Determine the access latency and update the bank state 105810211Sandreas.hansson@arm.com if (bank.openRow == dram_pkt->row) { 105910211Sandreas.hansson@arm.com // nothing to do 106010209Sandreas.hansson@arm.com } else { 106110211Sandreas.hansson@arm.com row_hit = false; 106210211Sandreas.hansson@arm.com 106310209Sandreas.hansson@arm.com // If there is a page open, precharge it. 106410209Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 106510618SOmar.Naji@arm.com prechargeBank(rank, bank, std::max(bank.preAllowedAt, curTick())); 10669488SN/A } 10679973SN/A 106810211Sandreas.hansson@arm.com // next we need to account for the delay in activating the 106910211Sandreas.hansson@arm.com // page 107010211Sandreas.hansson@arm.com Tick act_tick = std::max(bank.actAllowedAt, curTick()); 10719973SN/A 107210210Sandreas.hansson@arm.com // Record the activation and deal with all the global timing 107310210Sandreas.hansson@arm.com // constraints caused be a new activation (tRRD and tXAW) 107410618SOmar.Naji@arm.com activateBank(rank, bank, act_tick, dram_pkt->row); 107510210Sandreas.hansson@arm.com 107610211Sandreas.hansson@arm.com // issue the command as early as possible 107710211Sandreas.hansson@arm.com cmd_at = bank.colAllowedAt; 107810209Sandreas.hansson@arm.com } 107910209Sandreas.hansson@arm.com 108010211Sandreas.hansson@arm.com // we need to wait until the bus is available before we can issue 108110211Sandreas.hansson@arm.com // the command 108210211Sandreas.hansson@arm.com cmd_at = std::max(cmd_at, busBusyUntil - tCL); 108310211Sandreas.hansson@arm.com 108410211Sandreas.hansson@arm.com // update the packet ready time 108510211Sandreas.hansson@arm.com dram_pkt->readyTime = cmd_at + tCL + tBURST; 108610211Sandreas.hansson@arm.com 108710211Sandreas.hansson@arm.com // only one burst can use the bus at any one point in time 108810211Sandreas.hansson@arm.com assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 108910211Sandreas.hansson@arm.com 109010394Swendy.elsasser@arm.com // update the time for the next read/write burst for each 109110394Swendy.elsasser@arm.com // bank (add a max with tCCD/tCCD_L here) 109210394Swendy.elsasser@arm.com Tick cmd_dly; 109310394Swendy.elsasser@arm.com for(int j = 0; j < ranksPerChannel; j++) { 109410394Swendy.elsasser@arm.com for(int i = 0; i < banksPerRank; i++) { 109510394Swendy.elsasser@arm.com // next burst to same bank group in this rank must not happen 109610394Swendy.elsasser@arm.com // before tCCD_L. Different bank group timing requirement is 109710394Swendy.elsasser@arm.com // tBURST; Add tCS for different ranks 109810394Swendy.elsasser@arm.com if (dram_pkt->rank == j) { 109910618SOmar.Naji@arm.com if (bankGroupArch && 110010618SOmar.Naji@arm.com (bank.bankgr == ranks[j]->banks[i].bankgr)) { 110110394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 110210394Swendy.elsasser@arm.com // RD/WR burst commands to the same bank group. 110310394Swendy.elsasser@arm.com // Use tCCD_L in this case 110410394Swendy.elsasser@arm.com cmd_dly = tCCD_L; 110510394Swendy.elsasser@arm.com } else { 110610394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), the shorter 110710394Swendy.elsasser@arm.com // cas-to-cas delay value, when either: 110810394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 110910394Swendy.elsasser@arm.com // 2) bank is in a different bank group 111010394Swendy.elsasser@arm.com cmd_dly = tBURST; 111110394Swendy.elsasser@arm.com } 111210394Swendy.elsasser@arm.com } else { 111310394Swendy.elsasser@arm.com // different rank is by default in a different bank group 111410394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), which is the shorter 111510394Swendy.elsasser@arm.com // cas-to-cas delay in this case 111610394Swendy.elsasser@arm.com // Add tCS to account for rank-to-rank bus delay requirements 111710394Swendy.elsasser@arm.com cmd_dly = tBURST + tCS; 111810394Swendy.elsasser@arm.com } 111910618SOmar.Naji@arm.com ranks[j]->banks[i].colAllowedAt = std::max(cmd_at + cmd_dly, 112010618SOmar.Naji@arm.com ranks[j]->banks[i].colAllowedAt); 112110394Swendy.elsasser@arm.com } 112210394Swendy.elsasser@arm.com } 112310211Sandreas.hansson@arm.com 112410393Swendy.elsasser@arm.com // Save rank of current access 112510393Swendy.elsasser@arm.com activeRank = dram_pkt->rank; 112610393Swendy.elsasser@arm.com 112710212Sandreas.hansson@arm.com // If this is a write, we also need to respect the write recovery 112810212Sandreas.hansson@arm.com // time before a precharge, in the case of a read, respect the 112910212Sandreas.hansson@arm.com // read to precharge constraint 113010212Sandreas.hansson@arm.com bank.preAllowedAt = std::max(bank.preAllowedAt, 113110212Sandreas.hansson@arm.com dram_pkt->isRead ? cmd_at + tRTP : 113210212Sandreas.hansson@arm.com dram_pkt->readyTime + tWR); 113310210Sandreas.hansson@arm.com 113410209Sandreas.hansson@arm.com // increment the bytes accessed and the accesses per row 113510209Sandreas.hansson@arm.com bank.bytesAccessed += burstSize; 113610209Sandreas.hansson@arm.com ++bank.rowAccesses; 113710209Sandreas.hansson@arm.com 113810209Sandreas.hansson@arm.com // if we reached the max, then issue with an auto-precharge 113910209Sandreas.hansson@arm.com bool auto_precharge = pageMgmt == Enums::close || 114010209Sandreas.hansson@arm.com bank.rowAccesses == maxAccessesPerRow; 114110209Sandreas.hansson@arm.com 114210209Sandreas.hansson@arm.com // if we did not hit the limit, we might still want to 114310209Sandreas.hansson@arm.com // auto-precharge 114410209Sandreas.hansson@arm.com if (!auto_precharge && 114510209Sandreas.hansson@arm.com (pageMgmt == Enums::open_adaptive || 114610209Sandreas.hansson@arm.com pageMgmt == Enums::close_adaptive)) { 114710209Sandreas.hansson@arm.com // a twist on the open and close page policies: 114810209Sandreas.hansson@arm.com // 1) open_adaptive page policy does not blindly keep the 114910209Sandreas.hansson@arm.com // page open, but close it if there are no row hits, and there 115010209Sandreas.hansson@arm.com // are bank conflicts in the queue 115110209Sandreas.hansson@arm.com // 2) close_adaptive page policy does not blindly close the 115210209Sandreas.hansson@arm.com // page, but closes it only if there are no row hits in the queue. 115310209Sandreas.hansson@arm.com // In this case, only force an auto precharge when there 115410209Sandreas.hansson@arm.com // are no same page hits in the queue 115510209Sandreas.hansson@arm.com bool got_more_hits = false; 115610209Sandreas.hansson@arm.com bool got_bank_conflict = false; 115710209Sandreas.hansson@arm.com 115810209Sandreas.hansson@arm.com // either look at the read queue or write queue 115910209Sandreas.hansson@arm.com const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 116010209Sandreas.hansson@arm.com writeQueue; 116110209Sandreas.hansson@arm.com auto p = queue.begin(); 116210209Sandreas.hansson@arm.com // make sure we are not considering the packet that we are 116310209Sandreas.hansson@arm.com // currently dealing with (which is the head of the queue) 116410209Sandreas.hansson@arm.com ++p; 116510209Sandreas.hansson@arm.com 116610209Sandreas.hansson@arm.com // keep on looking until we have found required condition or 116710209Sandreas.hansson@arm.com // reached the end 116810209Sandreas.hansson@arm.com while (!(got_more_hits && 116910209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive)) && 117010209Sandreas.hansson@arm.com p != queue.end()) { 117110209Sandreas.hansson@arm.com bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 117210209Sandreas.hansson@arm.com (dram_pkt->bank == (*p)->bank); 117310209Sandreas.hansson@arm.com bool same_row = dram_pkt->row == (*p)->row; 117410209Sandreas.hansson@arm.com got_more_hits |= same_rank_bank && same_row; 117510209Sandreas.hansson@arm.com got_bank_conflict |= same_rank_bank && !same_row; 11769973SN/A ++p; 117710141SN/A } 117810141SN/A 117910209Sandreas.hansson@arm.com // auto pre-charge when either 118010209Sandreas.hansson@arm.com // 1) open_adaptive policy, we have not got any more hits, and 118110209Sandreas.hansson@arm.com // have a bank conflict 118210209Sandreas.hansson@arm.com // 2) close_adaptive policy and we have not got any more hits 118310209Sandreas.hansson@arm.com auto_precharge = !got_more_hits && 118410209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive); 118510209Sandreas.hansson@arm.com } 118610142SN/A 118710247Sandreas.hansson@arm.com // DRAMPower trace command to be written 118810247Sandreas.hansson@arm.com std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR"; 118910247Sandreas.hansson@arm.com 119010432SOmar.Naji@arm.com // MemCommand required for DRAMPower library 119110432SOmar.Naji@arm.com MemCommand::cmds command = (mem_cmd == "RD") ? MemCommand::RD : 119210432SOmar.Naji@arm.com MemCommand::WR; 119310432SOmar.Naji@arm.com 119410209Sandreas.hansson@arm.com // if this access should use auto-precharge, then we are 119510209Sandreas.hansson@arm.com // closing the row 119610209Sandreas.hansson@arm.com if (auto_precharge) { 119710432SOmar.Naji@arm.com // if auto-precharge push a PRE command at the correct tick to the 119810432SOmar.Naji@arm.com // list used by DRAMPower library to calculate power 119910618SOmar.Naji@arm.com prechargeBank(rank, bank, std::max(curTick(), bank.preAllowedAt)); 12009973SN/A 120110209Sandreas.hansson@arm.com DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 120210209Sandreas.hansson@arm.com } 12039963SN/A 12049243SN/A // Update bus state 12059243SN/A busBusyUntil = dram_pkt->readyTime; 12069243SN/A 120710211Sandreas.hansson@arm.com DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n", 120810211Sandreas.hansson@arm.com dram_pkt->addr, dram_pkt->readyTime, busBusyUntil); 12099243SN/A 121010618SOmar.Naji@arm.com dram_pkt->rankRef.power.powerlib.doCommand(command, dram_pkt->bank, 121110432SOmar.Naji@arm.com divCeil(cmd_at, tCK) - 121210432SOmar.Naji@arm.com timeStampOffset); 121310432SOmar.Naji@arm.com 121410432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK) - 121510432SOmar.Naji@arm.com timeStampOffset, mem_cmd, dram_pkt->bank, dram_pkt->rank); 121610247Sandreas.hansson@arm.com 121710206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 121810206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 121910206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 122010206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 122110206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 12229972SN/A 122310206Sandreas.hansson@arm.com // Update the stats and schedule the next request 12249977SN/A if (dram_pkt->isRead) { 122510147Sandreas.hansson@arm.com ++readsThisTime; 122610211Sandreas.hansson@arm.com if (row_hit) 12279977SN/A readRowHits++; 12289977SN/A bytesReadDRAM += burstSize; 12299977SN/A perBankRdBursts[dram_pkt->bankId]++; 123010206Sandreas.hansson@arm.com 123110206Sandreas.hansson@arm.com // Update latency stats 123210206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 123310206Sandreas.hansson@arm.com totBusLat += tBURST; 123410211Sandreas.hansson@arm.com totQLat += cmd_at - dram_pkt->entryTime; 12359977SN/A } else { 123610147Sandreas.hansson@arm.com ++writesThisTime; 123710211Sandreas.hansson@arm.com if (row_hit) 12389977SN/A writeRowHits++; 12399977SN/A bytesWritten += burstSize; 12409977SN/A perBankWrBursts[dram_pkt->bankId]++; 12419243SN/A } 12429243SN/A} 12439243SN/A 12449243SN/Avoid 124510206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 12469243SN/A{ 124710618SOmar.Naji@arm.com int busyRanks = 0; 124810618SOmar.Naji@arm.com for (auto r : ranks) { 124910618SOmar.Naji@arm.com if (!r->isAvailable()) { 125010618SOmar.Naji@arm.com // rank is busy refreshing 125110618SOmar.Naji@arm.com busyRanks++; 125210618SOmar.Naji@arm.com 125310618SOmar.Naji@arm.com // let the rank know that if it was waiting to drain, it 125410618SOmar.Naji@arm.com // is now done and ready to proceed 125510618SOmar.Naji@arm.com r->checkDrainDone(); 125610618SOmar.Naji@arm.com } 125710618SOmar.Naji@arm.com } 125810618SOmar.Naji@arm.com 125910618SOmar.Naji@arm.com if (busyRanks == ranksPerChannel) { 126010618SOmar.Naji@arm.com // if all ranks are refreshing wait for them to finish 126110618SOmar.Naji@arm.com // and stall this state machine without taking any further 126210618SOmar.Naji@arm.com // action, and do not schedule a new nextReqEvent 126310618SOmar.Naji@arm.com return; 126410618SOmar.Naji@arm.com } 126510618SOmar.Naji@arm.com 126610393Swendy.elsasser@arm.com // pre-emptively set to false. Overwrite if in READ_TO_WRITE 126710393Swendy.elsasser@arm.com // or WRITE_TO_READ state 126810393Swendy.elsasser@arm.com bool switched_cmd_type = false; 126910206Sandreas.hansson@arm.com if (busState == READ_TO_WRITE) { 127010206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 127110206Sandreas.hansson@arm.com "waiting\n", readsThisTime, readQueue.size()); 12729243SN/A 127310206Sandreas.hansson@arm.com // sample and reset the read-related stats as we are now 127410206Sandreas.hansson@arm.com // transitioning to writes, and all reads are done 127510206Sandreas.hansson@arm.com rdPerTurnAround.sample(readsThisTime); 127610206Sandreas.hansson@arm.com readsThisTime = 0; 127710206Sandreas.hansson@arm.com 127810206Sandreas.hansson@arm.com // now proceed to do the actual writes 127910206Sandreas.hansson@arm.com busState = WRITE; 128010393Swendy.elsasser@arm.com switched_cmd_type = true; 128110206Sandreas.hansson@arm.com } else if (busState == WRITE_TO_READ) { 128210206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 128310206Sandreas.hansson@arm.com "waiting\n", writesThisTime, writeQueue.size()); 128410206Sandreas.hansson@arm.com 128510206Sandreas.hansson@arm.com wrPerTurnAround.sample(writesThisTime); 128610206Sandreas.hansson@arm.com writesThisTime = 0; 128710206Sandreas.hansson@arm.com 128810206Sandreas.hansson@arm.com busState = READ; 128910393Swendy.elsasser@arm.com switched_cmd_type = true; 129010206Sandreas.hansson@arm.com } 129110206Sandreas.hansson@arm.com 129210206Sandreas.hansson@arm.com // when we get here it is either a read or a write 129310206Sandreas.hansson@arm.com if (busState == READ) { 129410206Sandreas.hansson@arm.com 129510206Sandreas.hansson@arm.com // track if we should switch or not 129610206Sandreas.hansson@arm.com bool switch_to_writes = false; 129710206Sandreas.hansson@arm.com 129810206Sandreas.hansson@arm.com if (readQueue.empty()) { 129910206Sandreas.hansson@arm.com // In the case there is no read request to go next, 130010206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 130110206Sandreas.hansson@arm.com // if we are draining) 130210206Sandreas.hansson@arm.com if (!writeQueue.empty() && 130310206Sandreas.hansson@arm.com (drainManager || writeQueue.size() > writeLowThreshold)) { 130410206Sandreas.hansson@arm.com 130510206Sandreas.hansson@arm.com switch_to_writes = true; 130610206Sandreas.hansson@arm.com } else { 130710206Sandreas.hansson@arm.com // check if we are drained 130810206Sandreas.hansson@arm.com if (respQueue.empty () && drainManager) { 130910509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 131010206Sandreas.hansson@arm.com drainManager->signalDrainDone(); 131110206Sandreas.hansson@arm.com drainManager = NULL; 131210206Sandreas.hansson@arm.com } 131310206Sandreas.hansson@arm.com 131410206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 131510206Sandreas.hansson@arm.com // event for the next request 131610206Sandreas.hansson@arm.com return; 131710206Sandreas.hansson@arm.com } 131810206Sandreas.hansson@arm.com } else { 131910618SOmar.Naji@arm.com // bool to check if there is a read to a free rank 132010618SOmar.Naji@arm.com bool found_read = false; 132110618SOmar.Naji@arm.com 132210206Sandreas.hansson@arm.com // Figure out which read request goes next, and move it to the 132310206Sandreas.hansson@arm.com // front of the read queue 132410618SOmar.Naji@arm.com found_read = chooseNext(readQueue, switched_cmd_type); 132510618SOmar.Naji@arm.com 132610618SOmar.Naji@arm.com // if no read to an available rank is found then return 132710618SOmar.Naji@arm.com // at this point. There could be writes to the available ranks 132810618SOmar.Naji@arm.com // which are above the required threshold. However, to 132910618SOmar.Naji@arm.com // avoid adding more complexity to the code, return and wait 133010618SOmar.Naji@arm.com // for a refresh event to kick things into action again. 133110618SOmar.Naji@arm.com if (!found_read) 133210618SOmar.Naji@arm.com return; 133310206Sandreas.hansson@arm.com 133410215Sandreas.hansson@arm.com DRAMPacket* dram_pkt = readQueue.front(); 133510618SOmar.Naji@arm.com assert(dram_pkt->rankRef.isAvailable()); 133610393Swendy.elsasser@arm.com // here we get a bit creative and shift the bus busy time not 133710393Swendy.elsasser@arm.com // just the tWTR, but also a CAS latency to capture the fact 133810393Swendy.elsasser@arm.com // that we are allowed to prepare a new bank, but not issue a 133910393Swendy.elsasser@arm.com // read command until after tWTR, in essence we capture a 134010393Swendy.elsasser@arm.com // bubble on the data bus that is tWTR + tCL 134110394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 134210394Swendy.elsasser@arm.com busBusyUntil += tWTR + tCL; 134310393Swendy.elsasser@arm.com } 134410393Swendy.elsasser@arm.com 134510215Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 134610206Sandreas.hansson@arm.com 134710206Sandreas.hansson@arm.com // At this point we're done dealing with the request 134810215Sandreas.hansson@arm.com readQueue.pop_front(); 134910215Sandreas.hansson@arm.com 135010215Sandreas.hansson@arm.com // sanity check 135110215Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 135210215Sandreas.hansson@arm.com assert(dram_pkt->readyTime >= curTick()); 135310215Sandreas.hansson@arm.com 135410215Sandreas.hansson@arm.com // Insert into response queue. It will be sent back to the 135510215Sandreas.hansson@arm.com // requestor at its readyTime 135610215Sandreas.hansson@arm.com if (respQueue.empty()) { 135710215Sandreas.hansson@arm.com assert(!respondEvent.scheduled()); 135810215Sandreas.hansson@arm.com schedule(respondEvent, dram_pkt->readyTime); 135910215Sandreas.hansson@arm.com } else { 136010215Sandreas.hansson@arm.com assert(respQueue.back()->readyTime <= dram_pkt->readyTime); 136110215Sandreas.hansson@arm.com assert(respondEvent.scheduled()); 136210215Sandreas.hansson@arm.com } 136310215Sandreas.hansson@arm.com 136410215Sandreas.hansson@arm.com respQueue.push_back(dram_pkt); 136510206Sandreas.hansson@arm.com 136610206Sandreas.hansson@arm.com // we have so many writes that we have to transition 136710206Sandreas.hansson@arm.com if (writeQueue.size() > writeHighThreshold) { 136810206Sandreas.hansson@arm.com switch_to_writes = true; 136910206Sandreas.hansson@arm.com } 137010206Sandreas.hansson@arm.com } 137110206Sandreas.hansson@arm.com 137210206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 137310206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 137410206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 137510206Sandreas.hansson@arm.com if (switch_to_writes) { 137610206Sandreas.hansson@arm.com // transition to writing 137710206Sandreas.hansson@arm.com busState = READ_TO_WRITE; 137810206Sandreas.hansson@arm.com } 13799352SN/A } else { 138010618SOmar.Naji@arm.com // bool to check if write to free rank is found 138110618SOmar.Naji@arm.com bool found_write = false; 138210618SOmar.Naji@arm.com 138310618SOmar.Naji@arm.com found_write = chooseNext(writeQueue, switched_cmd_type); 138410618SOmar.Naji@arm.com 138510618SOmar.Naji@arm.com // if no writes to an available rank are found then return. 138610618SOmar.Naji@arm.com // There could be reads to the available ranks. However, to avoid 138710618SOmar.Naji@arm.com // adding more complexity to the code, return at this point and wait 138810618SOmar.Naji@arm.com // for a refresh event to kick things into action again. 138910618SOmar.Naji@arm.com if (!found_write) 139010618SOmar.Naji@arm.com return; 139110618SOmar.Naji@arm.com 139210206Sandreas.hansson@arm.com DRAMPacket* dram_pkt = writeQueue.front(); 139310618SOmar.Naji@arm.com assert(dram_pkt->rankRef.isAvailable()); 139410206Sandreas.hansson@arm.com // sanity check 139510206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 139610393Swendy.elsasser@arm.com 139710394Swendy.elsasser@arm.com // add a bubble to the data bus, as defined by the 139810394Swendy.elsasser@arm.com // tRTW when access is to the same rank as previous burst 139910394Swendy.elsasser@arm.com // Different rank timing is handled with tCS, which is 140010394Swendy.elsasser@arm.com // applied to colAllowedAt 140110394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 140210394Swendy.elsasser@arm.com busBusyUntil += tRTW; 140310393Swendy.elsasser@arm.com } 140410393Swendy.elsasser@arm.com 140510206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 140610206Sandreas.hansson@arm.com 140710206Sandreas.hansson@arm.com writeQueue.pop_front(); 140810206Sandreas.hansson@arm.com delete dram_pkt; 140910206Sandreas.hansson@arm.com 141010206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 141110206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 141210206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 141310206Sandreas.hansson@arm.com // writes, then switch to reads. 141410206Sandreas.hansson@arm.com if (writeQueue.empty() || 141510206Sandreas.hansson@arm.com (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 141610206Sandreas.hansson@arm.com !drainManager) || 141710206Sandreas.hansson@arm.com (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 141810206Sandreas.hansson@arm.com // turn the bus back around for reads again 141910206Sandreas.hansson@arm.com busState = WRITE_TO_READ; 142010206Sandreas.hansson@arm.com 142110206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 142210206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 142310206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 142410206Sandreas.hansson@arm.com // nothing to do 142510206Sandreas.hansson@arm.com } 142610206Sandreas.hansson@arm.com } 142710618SOmar.Naji@arm.com // It is possible that a refresh to another rank kicks things back into 142810618SOmar.Naji@arm.com // action before reaching this point. 142910618SOmar.Naji@arm.com if (!nextReqEvent.scheduled()) 143010618SOmar.Naji@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 143110206Sandreas.hansson@arm.com 143210206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 143310206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 143410206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 143510206Sandreas.hansson@arm.com // the next request processing 143610206Sandreas.hansson@arm.com if (retryWrReq && writeQueue.size() < writeBufferSize) { 143710206Sandreas.hansson@arm.com retryWrReq = false; 143810206Sandreas.hansson@arm.com port.sendRetry(); 14399352SN/A } 14409243SN/A} 14419243SN/A 14429967SN/Auint64_t 144310393Swendy.elsasser@arm.comDRAMCtrl::minBankPrep(const deque<DRAMPacket*>& queue, 144410393Swendy.elsasser@arm.com bool switched_cmd_type) const 14459967SN/A{ 14469967SN/A uint64_t bank_mask = 0; 144710211Sandreas.hansson@arm.com Tick min_act_at = MaxTick; 14489967SN/A 144910393Swendy.elsasser@arm.com uint64_t bank_mask_same_rank = 0; 145010393Swendy.elsasser@arm.com Tick min_act_at_same_rank = MaxTick; 145110393Swendy.elsasser@arm.com 145210393Swendy.elsasser@arm.com // Give precedence to commands that access same rank as previous command 145310393Swendy.elsasser@arm.com bool same_rank_match = false; 145410393Swendy.elsasser@arm.com 145510393Swendy.elsasser@arm.com // determine if we have queued transactions targetting the 14569967SN/A // bank in question 14579967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 145810618SOmar.Naji@arm.com for (const auto& p : queue) { 145910618SOmar.Naji@arm.com if(p->rankRef.isAvailable()) 146010618SOmar.Naji@arm.com got_waiting[p->bankId] = true; 14619967SN/A } 14629967SN/A 14639967SN/A for (int i = 0; i < ranksPerChannel; i++) { 14649967SN/A for (int j = 0; j < banksPerRank; j++) { 146510618SOmar.Naji@arm.com uint16_t bank_id = i * banksPerRank + j; 146610211Sandreas.hansson@arm.com 14679967SN/A // if we have waiting requests for the bank, and it is 14689967SN/A // amongst the first available, update the mask 146910211Sandreas.hansson@arm.com if (got_waiting[bank_id]) { 147010618SOmar.Naji@arm.com // make sure this rank is not currently refreshing. 147110618SOmar.Naji@arm.com assert(ranks[i]->isAvailable()); 147210211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue 147310211Sandreas.hansson@arm.com // an activate, ignoring any rank-to-rank switching 147410393Swendy.elsasser@arm.com // cost in this calculation 147510618SOmar.Naji@arm.com Tick act_at = ranks[i]->banks[j].openRow == Bank::NO_ROW ? 147610618SOmar.Naji@arm.com ranks[i]->banks[j].actAllowedAt : 147710618SOmar.Naji@arm.com std::max(ranks[i]->banks[j].preAllowedAt, curTick()) + tRP; 147810211Sandreas.hansson@arm.com 147910393Swendy.elsasser@arm.com // prioritize commands that access the 148010393Swendy.elsasser@arm.com // same rank as previous burst 148110393Swendy.elsasser@arm.com // Calculate bank mask separately for the case and 148210393Swendy.elsasser@arm.com // evaluate after loop iterations complete 148310393Swendy.elsasser@arm.com if (i == activeRank && ranksPerChannel > 1) { 148410393Swendy.elsasser@arm.com if (act_at <= min_act_at_same_rank) { 148510393Swendy.elsasser@arm.com // reset same rank bank mask if new minimum is found 148610393Swendy.elsasser@arm.com // and previous minimum could not immediately send ACT 148710393Swendy.elsasser@arm.com if (act_at < min_act_at_same_rank && 148810393Swendy.elsasser@arm.com min_act_at_same_rank > curTick()) 148910393Swendy.elsasser@arm.com bank_mask_same_rank = 0; 149010393Swendy.elsasser@arm.com 149110393Swendy.elsasser@arm.com // Set flag indicating that a same rank 149210393Swendy.elsasser@arm.com // opportunity was found 149310393Swendy.elsasser@arm.com same_rank_match = true; 149410393Swendy.elsasser@arm.com 149510393Swendy.elsasser@arm.com // set the bit corresponding to the available bank 149610393Swendy.elsasser@arm.com replaceBits(bank_mask_same_rank, bank_id, bank_id, 1); 149710393Swendy.elsasser@arm.com min_act_at_same_rank = act_at; 149810393Swendy.elsasser@arm.com } 149910393Swendy.elsasser@arm.com } else { 150010393Swendy.elsasser@arm.com if (act_at <= min_act_at) { 150110393Swendy.elsasser@arm.com // reset bank mask if new minimum is found 150210393Swendy.elsasser@arm.com // and either previous minimum could not immediately send ACT 150310393Swendy.elsasser@arm.com if (act_at < min_act_at && min_act_at > curTick()) 150410393Swendy.elsasser@arm.com bank_mask = 0; 150510393Swendy.elsasser@arm.com // set the bit corresponding to the available bank 150610393Swendy.elsasser@arm.com replaceBits(bank_mask, bank_id, bank_id, 1); 150710393Swendy.elsasser@arm.com min_act_at = act_at; 150810393Swendy.elsasser@arm.com } 150910211Sandreas.hansson@arm.com } 15109967SN/A } 15119967SN/A } 15129967SN/A } 151310211Sandreas.hansson@arm.com 151410393Swendy.elsasser@arm.com // Determine the earliest time when the next burst can issue based 151510393Swendy.elsasser@arm.com // on the current busBusyUntil delay. 151610393Swendy.elsasser@arm.com // Offset by tRCD to correlate with ACT timing variables 151710393Swendy.elsasser@arm.com Tick min_cmd_at = busBusyUntil - tCL - tRCD; 151810393Swendy.elsasser@arm.com 151910617SOmar.Naji@arm.com // if we have multiple ranks and all 152010617SOmar.Naji@arm.com // waiting packets are accessing a rank which was previously active 152110617SOmar.Naji@arm.com // then bank_mask_same_rank will be set to a value while bank_mask will 152210617SOmar.Naji@arm.com // remain 0. In this case, the function should return the value of 152310617SOmar.Naji@arm.com // bank_mask_same_rank. 152410617SOmar.Naji@arm.com // else if waiting packets access a rank which was previously active and 152510617SOmar.Naji@arm.com // other ranks, prioritize same rank accesses that can issue B2B 152610393Swendy.elsasser@arm.com // Only optimize for same ranks when the command type 152710393Swendy.elsasser@arm.com // does not change; do not want to unnecessarily incur tWTR 152810393Swendy.elsasser@arm.com // 152910393Swendy.elsasser@arm.com // Resulting FCFS prioritization Order is: 153010393Swendy.elsasser@arm.com // 1) Commands that access the same rank as previous burst 153110393Swendy.elsasser@arm.com // and can prep the bank seamlessly. 153210393Swendy.elsasser@arm.com // 2) Commands (any rank) with earliest bank prep 153310617SOmar.Naji@arm.com if ((bank_mask == 0) || (!switched_cmd_type && same_rank_match && 153410617SOmar.Naji@arm.com min_act_at_same_rank <= min_cmd_at)) { 153510393Swendy.elsasser@arm.com bank_mask = bank_mask_same_rank; 153610393Swendy.elsasser@arm.com } 153710393Swendy.elsasser@arm.com 15389967SN/A return bank_mask; 15399967SN/A} 15409967SN/A 154110618SOmar.Naji@arm.comDRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p) 154210618SOmar.Naji@arm.com : EventManager(&_memory), memory(_memory), 154310618SOmar.Naji@arm.com pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), pwrStateTick(0), 154410618SOmar.Naji@arm.com refreshState(REF_IDLE), refreshDueAt(0), 154510618SOmar.Naji@arm.com power(_p, false), numBanksActive(0), 154610618SOmar.Naji@arm.com activateEvent(*this), prechargeEvent(*this), 154710618SOmar.Naji@arm.com refreshEvent(*this), powerEvent(*this) 154810618SOmar.Naji@arm.com{ } 154910618SOmar.Naji@arm.com 15509243SN/Avoid 155110618SOmar.Naji@arm.comDRAMCtrl::Rank::startup(Tick ref_tick) 155210618SOmar.Naji@arm.com{ 155310618SOmar.Naji@arm.com assert(ref_tick > curTick()); 155410618SOmar.Naji@arm.com 155510618SOmar.Naji@arm.com pwrStateTick = curTick(); 155610618SOmar.Naji@arm.com 155710618SOmar.Naji@arm.com // kick off the refresh, and give ourselves enough time to 155810618SOmar.Naji@arm.com // precharge 155910618SOmar.Naji@arm.com schedule(refreshEvent, ref_tick); 156010618SOmar.Naji@arm.com} 156110618SOmar.Naji@arm.com 156210618SOmar.Naji@arm.comvoid 156310619Sandreas.hansson@arm.comDRAMCtrl::Rank::suspend() 156410619Sandreas.hansson@arm.com{ 156510619Sandreas.hansson@arm.com deschedule(refreshEvent); 156610619Sandreas.hansson@arm.com} 156710619Sandreas.hansson@arm.com 156810619Sandreas.hansson@arm.comvoid 156910618SOmar.Naji@arm.comDRAMCtrl::Rank::checkDrainDone() 157010618SOmar.Naji@arm.com{ 157110618SOmar.Naji@arm.com // if this rank was waiting to drain it is now able to proceed to 157210618SOmar.Naji@arm.com // precharge 157310618SOmar.Naji@arm.com if (refreshState == REF_DRAIN) { 157410618SOmar.Naji@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 157510618SOmar.Naji@arm.com 157610618SOmar.Naji@arm.com refreshState = REF_PRE; 157710618SOmar.Naji@arm.com 157810618SOmar.Naji@arm.com // hand control back to the refresh event loop 157910618SOmar.Naji@arm.com schedule(refreshEvent, curTick()); 158010618SOmar.Naji@arm.com } 158110618SOmar.Naji@arm.com} 158210618SOmar.Naji@arm.com 158310618SOmar.Naji@arm.comvoid 158410618SOmar.Naji@arm.comDRAMCtrl::Rank::processActivateEvent() 158510618SOmar.Naji@arm.com{ 158610618SOmar.Naji@arm.com // we should transition to the active state as soon as any bank is active 158710618SOmar.Naji@arm.com if (pwrState != PWR_ACT) 158810618SOmar.Naji@arm.com // note that at this point numBanksActive could be back at 158910618SOmar.Naji@arm.com // zero again due to a precharge scheduled in the future 159010618SOmar.Naji@arm.com schedulePowerEvent(PWR_ACT, curTick()); 159110618SOmar.Naji@arm.com} 159210618SOmar.Naji@arm.com 159310618SOmar.Naji@arm.comvoid 159410618SOmar.Naji@arm.comDRAMCtrl::Rank::processPrechargeEvent() 159510618SOmar.Naji@arm.com{ 159610618SOmar.Naji@arm.com // if we reached zero, then special conditions apply as we track 159710618SOmar.Naji@arm.com // if all banks are precharged for the power models 159810618SOmar.Naji@arm.com if (numBanksActive == 0) { 159910618SOmar.Naji@arm.com // we should transition to the idle state when the last bank 160010618SOmar.Naji@arm.com // is precharged 160110618SOmar.Naji@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 160210618SOmar.Naji@arm.com } 160310618SOmar.Naji@arm.com} 160410618SOmar.Naji@arm.com 160510618SOmar.Naji@arm.comvoid 160610618SOmar.Naji@arm.comDRAMCtrl::Rank::processRefreshEvent() 16079243SN/A{ 160810207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 160910207Sandreas.hansson@arm.com if (refreshState == REF_IDLE) { 161010207Sandreas.hansson@arm.com // remember when the refresh is due 161110207Sandreas.hansson@arm.com refreshDueAt = curTick(); 16129243SN/A 161310207Sandreas.hansson@arm.com // proceed to drain 161410207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 16159243SN/A 161610207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 161710207Sandreas.hansson@arm.com } 161810207Sandreas.hansson@arm.com 161910618SOmar.Naji@arm.com // let any scheduled read or write to the same rank go ahead, 162010618SOmar.Naji@arm.com // after which it will 162110207Sandreas.hansson@arm.com // hand control back to this event loop 162210207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 162310618SOmar.Naji@arm.com // if a request is at the moment being handled and this request is 162410618SOmar.Naji@arm.com // accessing the current rank then wait for it to finish 162510618SOmar.Naji@arm.com if ((rank == memory.activeRank) 162610618SOmar.Naji@arm.com && (memory.nextReqEvent.scheduled())) { 162710207Sandreas.hansson@arm.com // hand control over to the request loop until it is 162810207Sandreas.hansson@arm.com // evaluated next 162910207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 163010207Sandreas.hansson@arm.com 163110207Sandreas.hansson@arm.com return; 163210207Sandreas.hansson@arm.com } else { 163310207Sandreas.hansson@arm.com refreshState = REF_PRE; 163410207Sandreas.hansson@arm.com } 163510207Sandreas.hansson@arm.com } 163610207Sandreas.hansson@arm.com 163710207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 163810207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 163910208Sandreas.hansson@arm.com // precharge any active bank if we are not already in the idle 164010208Sandreas.hansson@arm.com // state 164110208Sandreas.hansson@arm.com if (pwrState != PWR_IDLE) { 164210214Sandreas.hansson@arm.com // at the moment, we use a precharge all even if there is 164310214Sandreas.hansson@arm.com // only a single bank open 164410208Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 164510214Sandreas.hansson@arm.com 164610214Sandreas.hansson@arm.com // first determine when we can precharge 164710214Sandreas.hansson@arm.com Tick pre_at = curTick(); 164810618SOmar.Naji@arm.com 164910618SOmar.Naji@arm.com for (auto &b : banks) { 165010618SOmar.Naji@arm.com // respect both causality and any existing bank 165110618SOmar.Naji@arm.com // constraints, some banks could already have a 165210618SOmar.Naji@arm.com // (auto) precharge scheduled 165310618SOmar.Naji@arm.com pre_at = std::max(b.preAllowedAt, pre_at); 165410618SOmar.Naji@arm.com } 165510618SOmar.Naji@arm.com 165610618SOmar.Naji@arm.com // make sure all banks per rank are precharged, and for those that 165710618SOmar.Naji@arm.com // already are, update their availability 165810618SOmar.Naji@arm.com Tick act_allowed_at = pre_at + memory.tRP; 165910618SOmar.Naji@arm.com 166010618SOmar.Naji@arm.com for (auto &b : banks) { 166110618SOmar.Naji@arm.com if (b.openRow != Bank::NO_ROW) { 166210618SOmar.Naji@arm.com memory.prechargeBank(*this, b, pre_at, false); 166310618SOmar.Naji@arm.com } else { 166410618SOmar.Naji@arm.com b.actAllowedAt = std::max(b.actAllowedAt, act_allowed_at); 166510618SOmar.Naji@arm.com b.preAllowedAt = std::max(b.preAllowedAt, pre_at); 166610214Sandreas.hansson@arm.com } 166710214Sandreas.hansson@arm.com } 166810214Sandreas.hansson@arm.com 166910618SOmar.Naji@arm.com // precharge all banks in rank 167010618SOmar.Naji@arm.com power.powerlib.doCommand(MemCommand::PREA, 0, 167110618SOmar.Naji@arm.com divCeil(pre_at, memory.tCK) - 167210618SOmar.Naji@arm.com memory.timeStampOffset); 167310214Sandreas.hansson@arm.com 167410618SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PREA,0,%d\n", 167510618SOmar.Naji@arm.com divCeil(pre_at, memory.tCK) - 167610618SOmar.Naji@arm.com memory.timeStampOffset, rank); 167710208Sandreas.hansson@arm.com } else { 167810208Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 167910208Sandreas.hansson@arm.com 168010208Sandreas.hansson@arm.com // go ahead and kick the power state machine into gear if 168110208Sandreas.hansson@arm.com // we are already idle 168210208Sandreas.hansson@arm.com schedulePowerEvent(PWR_REF, curTick()); 16839975SN/A } 16849975SN/A 168510208Sandreas.hansson@arm.com refreshState = REF_RUN; 168610208Sandreas.hansson@arm.com assert(numBanksActive == 0); 16879243SN/A 168810208Sandreas.hansson@arm.com // wait for all banks to be precharged, at which point the 168910208Sandreas.hansson@arm.com // power state machine will transition to the idle state, and 169010208Sandreas.hansson@arm.com // automatically move to a refresh, at that point it will also 169110208Sandreas.hansson@arm.com // call this method to get the refresh event loop going again 169210207Sandreas.hansson@arm.com return; 169310207Sandreas.hansson@arm.com } 169410207Sandreas.hansson@arm.com 169510207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 169610207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 169710207Sandreas.hansson@arm.com // should never get here with any banks active 169810207Sandreas.hansson@arm.com assert(numBanksActive == 0); 169910208Sandreas.hansson@arm.com assert(pwrState == PWR_REF); 170010207Sandreas.hansson@arm.com 170110618SOmar.Naji@arm.com Tick ref_done_at = curTick() + memory.tRFC; 170210207Sandreas.hansson@arm.com 170310618SOmar.Naji@arm.com for (auto &b : banks) { 170410618SOmar.Naji@arm.com b.actAllowedAt = ref_done_at; 170510618SOmar.Naji@arm.com } 170610247Sandreas.hansson@arm.com 170710618SOmar.Naji@arm.com // at the moment this affects all ranks 170810618SOmar.Naji@arm.com power.powerlib.doCommand(MemCommand::REF, 0, 170910618SOmar.Naji@arm.com divCeil(curTick(), memory.tCK) - 171010618SOmar.Naji@arm.com memory.timeStampOffset); 171110432SOmar.Naji@arm.com 171210618SOmar.Naji@arm.com // at the moment sort the list of commands and update the counters 171310618SOmar.Naji@arm.com // for DRAMPower libray when doing a refresh 171410618SOmar.Naji@arm.com sort(power.powerlib.cmdList.begin(), 171510618SOmar.Naji@arm.com power.powerlib.cmdList.end(), DRAMCtrl::sortTime); 171610432SOmar.Naji@arm.com 171710618SOmar.Naji@arm.com // update the counters for DRAMPower, passing false to 171810618SOmar.Naji@arm.com // indicate that this is not the last command in the 171910618SOmar.Naji@arm.com // list. DRAMPower requires this information for the 172010618SOmar.Naji@arm.com // correct calculation of the background energy at the end 172110618SOmar.Naji@arm.com // of the simulation. Ideally we would want to call this 172210618SOmar.Naji@arm.com // function with true once at the end of the 172310618SOmar.Naji@arm.com // simulation. However, the discarded energy is extremly 172410618SOmar.Naji@arm.com // small and does not effect the final results. 172510618SOmar.Naji@arm.com power.powerlib.updateCounters(false); 172610432SOmar.Naji@arm.com 172710618SOmar.Naji@arm.com // call the energy function 172810618SOmar.Naji@arm.com power.powerlib.calcEnergy(); 172910432SOmar.Naji@arm.com 173010618SOmar.Naji@arm.com // Update the stats 173110618SOmar.Naji@arm.com updatePowerStats(); 173210432SOmar.Naji@arm.com 173310618SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), memory.tCK) - 173410618SOmar.Naji@arm.com memory.timeStampOffset, rank); 173510207Sandreas.hansson@arm.com 173610207Sandreas.hansson@arm.com // make sure we did not wait so long that we cannot make up 173710207Sandreas.hansson@arm.com // for it 173810618SOmar.Naji@arm.com if (refreshDueAt + memory.tREFI < ref_done_at) { 173910207Sandreas.hansson@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 174010207Sandreas.hansson@arm.com } 174110207Sandreas.hansson@arm.com 174210207Sandreas.hansson@arm.com // compensate for the delay in actually performing the refresh 174310207Sandreas.hansson@arm.com // when scheduling the next one 174410618SOmar.Naji@arm.com schedule(refreshEvent, refreshDueAt + memory.tREFI - memory.tRP); 174510207Sandreas.hansson@arm.com 174610208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 174710207Sandreas.hansson@arm.com 174810208Sandreas.hansson@arm.com // move to the idle power state once the refresh is done, this 174910208Sandreas.hansson@arm.com // will also move the refresh state machine to the refresh 175010208Sandreas.hansson@arm.com // idle state 175110211Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, ref_done_at); 175210207Sandreas.hansson@arm.com 175310208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n", 175410618SOmar.Naji@arm.com ref_done_at, refreshDueAt + memory.tREFI); 175510208Sandreas.hansson@arm.com } 175610208Sandreas.hansson@arm.com} 175710208Sandreas.hansson@arm.com 175810208Sandreas.hansson@arm.comvoid 175910618SOmar.Naji@arm.comDRAMCtrl::Rank::schedulePowerEvent(PowerState pwr_state, Tick tick) 176010208Sandreas.hansson@arm.com{ 176110208Sandreas.hansson@arm.com // respect causality 176210208Sandreas.hansson@arm.com assert(tick >= curTick()); 176310208Sandreas.hansson@arm.com 176410208Sandreas.hansson@arm.com if (!powerEvent.scheduled()) { 176510208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 176610208Sandreas.hansson@arm.com tick, pwr_state); 176710208Sandreas.hansson@arm.com 176810208Sandreas.hansson@arm.com // insert the new transition 176910208Sandreas.hansson@arm.com pwrStateTrans = pwr_state; 177010208Sandreas.hansson@arm.com 177110208Sandreas.hansson@arm.com schedule(powerEvent, tick); 177210208Sandreas.hansson@arm.com } else { 177310208Sandreas.hansson@arm.com panic("Scheduled power event at %llu to state %d, " 177410208Sandreas.hansson@arm.com "with scheduled event at %llu to %d\n", tick, pwr_state, 177510208Sandreas.hansson@arm.com powerEvent.when(), pwrStateTrans); 177610208Sandreas.hansson@arm.com } 177710208Sandreas.hansson@arm.com} 177810208Sandreas.hansson@arm.com 177910208Sandreas.hansson@arm.comvoid 178010618SOmar.Naji@arm.comDRAMCtrl::Rank::processPowerEvent() 178110208Sandreas.hansson@arm.com{ 178210208Sandreas.hansson@arm.com // remember where we were, and for how long 178310208Sandreas.hansson@arm.com Tick duration = curTick() - pwrStateTick; 178410208Sandreas.hansson@arm.com PowerState prev_state = pwrState; 178510208Sandreas.hansson@arm.com 178610208Sandreas.hansson@arm.com // update the accounting 178710208Sandreas.hansson@arm.com pwrStateTime[prev_state] += duration; 178810208Sandreas.hansson@arm.com 178910208Sandreas.hansson@arm.com pwrState = pwrStateTrans; 179010208Sandreas.hansson@arm.com pwrStateTick = curTick(); 179110208Sandreas.hansson@arm.com 179210208Sandreas.hansson@arm.com if (pwrState == PWR_IDLE) { 179310208Sandreas.hansson@arm.com DPRINTF(DRAMState, "All banks precharged\n"); 179410208Sandreas.hansson@arm.com 179510208Sandreas.hansson@arm.com // if we were refreshing, make sure we start scheduling requests again 179610208Sandreas.hansson@arm.com if (prev_state == PWR_REF) { 179710208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 179810208Sandreas.hansson@arm.com assert(pwrState == PWR_IDLE); 179910208Sandreas.hansson@arm.com 180010208Sandreas.hansson@arm.com // kick things into action again 180110208Sandreas.hansson@arm.com refreshState = REF_IDLE; 180210618SOmar.Naji@arm.com // a request event could be already scheduled by the state 180310618SOmar.Naji@arm.com // machine of the other rank 180410618SOmar.Naji@arm.com if (!memory.nextReqEvent.scheduled()) 180510618SOmar.Naji@arm.com schedule(memory.nextReqEvent, curTick()); 180610208Sandreas.hansson@arm.com } else { 180710208Sandreas.hansson@arm.com assert(prev_state == PWR_ACT); 180810208Sandreas.hansson@arm.com 180910208Sandreas.hansson@arm.com // if we have a pending refresh, and are now moving to 181010208Sandreas.hansson@arm.com // the idle state, direclty transition to a refresh 181110208Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 181210208Sandreas.hansson@arm.com // there should be nothing waiting at this point 181310208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 181410208Sandreas.hansson@arm.com 181510208Sandreas.hansson@arm.com // update the state in zero time and proceed below 181610208Sandreas.hansson@arm.com pwrState = PWR_REF; 181710208Sandreas.hansson@arm.com } 181810208Sandreas.hansson@arm.com } 181910208Sandreas.hansson@arm.com } 182010208Sandreas.hansson@arm.com 182110208Sandreas.hansson@arm.com // we transition to the refresh state, let the refresh state 182210208Sandreas.hansson@arm.com // machine know of this state update and let it deal with the 182310208Sandreas.hansson@arm.com // scheduling of the next power state transition as well as the 182410208Sandreas.hansson@arm.com // following refresh 182510208Sandreas.hansson@arm.com if (pwrState == PWR_REF) { 182610208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refreshing\n"); 182710208Sandreas.hansson@arm.com // kick the refresh event loop into action again, and that 182810208Sandreas.hansson@arm.com // in turn will schedule a transition to the idle power 182910208Sandreas.hansson@arm.com // state once the refresh is done 183010208Sandreas.hansson@arm.com assert(refreshState == REF_RUN); 183110208Sandreas.hansson@arm.com processRefreshEvent(); 183210207Sandreas.hansson@arm.com } 18339243SN/A} 18349243SN/A 18359243SN/Avoid 183610618SOmar.Naji@arm.comDRAMCtrl::Rank::updatePowerStats() 183710432SOmar.Naji@arm.com{ 183810432SOmar.Naji@arm.com // Get the energy and power from DRAMPower 183910432SOmar.Naji@arm.com Data::MemoryPowerModel::Energy energy = 184010618SOmar.Naji@arm.com power.powerlib.getEnergy(); 184110618SOmar.Naji@arm.com Data::MemoryPowerModel::Power rank_power = 184210618SOmar.Naji@arm.com power.powerlib.getPower(); 184310432SOmar.Naji@arm.com 184410618SOmar.Naji@arm.com actEnergy = energy.act_energy * memory.devicesPerRank; 184510618SOmar.Naji@arm.com preEnergy = energy.pre_energy * memory.devicesPerRank; 184610618SOmar.Naji@arm.com readEnergy = energy.read_energy * memory.devicesPerRank; 184710618SOmar.Naji@arm.com writeEnergy = energy.write_energy * memory.devicesPerRank; 184810618SOmar.Naji@arm.com refreshEnergy = energy.ref_energy * memory.devicesPerRank; 184910618SOmar.Naji@arm.com actBackEnergy = energy.act_stdby_energy * memory.devicesPerRank; 185010618SOmar.Naji@arm.com preBackEnergy = energy.pre_stdby_energy * memory.devicesPerRank; 185110618SOmar.Naji@arm.com totalEnergy = energy.total_energy * memory.devicesPerRank; 185210618SOmar.Naji@arm.com averagePower = rank_power.average_power * memory.devicesPerRank; 185310432SOmar.Naji@arm.com} 185410432SOmar.Naji@arm.com 185510432SOmar.Naji@arm.comvoid 185610618SOmar.Naji@arm.comDRAMCtrl::Rank::regStats() 185710618SOmar.Naji@arm.com{ 185810618SOmar.Naji@arm.com using namespace Stats; 185910618SOmar.Naji@arm.com 186010618SOmar.Naji@arm.com pwrStateTime 186110618SOmar.Naji@arm.com .init(5) 186210618SOmar.Naji@arm.com .name(name() + ".memoryStateTime") 186310618SOmar.Naji@arm.com .desc("Time in different power states"); 186410618SOmar.Naji@arm.com pwrStateTime.subname(0, "IDLE"); 186510618SOmar.Naji@arm.com pwrStateTime.subname(1, "REF"); 186610618SOmar.Naji@arm.com pwrStateTime.subname(2, "PRE_PDN"); 186710618SOmar.Naji@arm.com pwrStateTime.subname(3, "ACT"); 186810618SOmar.Naji@arm.com pwrStateTime.subname(4, "ACT_PDN"); 186910618SOmar.Naji@arm.com 187010618SOmar.Naji@arm.com actEnergy 187110618SOmar.Naji@arm.com .name(name() + ".actEnergy") 187210618SOmar.Naji@arm.com .desc("Energy for activate commands per rank (pJ)"); 187310618SOmar.Naji@arm.com 187410618SOmar.Naji@arm.com preEnergy 187510618SOmar.Naji@arm.com .name(name() + ".preEnergy") 187610618SOmar.Naji@arm.com .desc("Energy for precharge commands per rank (pJ)"); 187710618SOmar.Naji@arm.com 187810618SOmar.Naji@arm.com readEnergy 187910618SOmar.Naji@arm.com .name(name() + ".readEnergy") 188010618SOmar.Naji@arm.com .desc("Energy for read commands per rank (pJ)"); 188110618SOmar.Naji@arm.com 188210618SOmar.Naji@arm.com writeEnergy 188310618SOmar.Naji@arm.com .name(name() + ".writeEnergy") 188410618SOmar.Naji@arm.com .desc("Energy for write commands per rank (pJ)"); 188510618SOmar.Naji@arm.com 188610618SOmar.Naji@arm.com refreshEnergy 188710618SOmar.Naji@arm.com .name(name() + ".refreshEnergy") 188810618SOmar.Naji@arm.com .desc("Energy for refresh commands per rank (pJ)"); 188910618SOmar.Naji@arm.com 189010618SOmar.Naji@arm.com actBackEnergy 189110618SOmar.Naji@arm.com .name(name() + ".actBackEnergy") 189210618SOmar.Naji@arm.com .desc("Energy for active background per rank (pJ)"); 189310618SOmar.Naji@arm.com 189410618SOmar.Naji@arm.com preBackEnergy 189510618SOmar.Naji@arm.com .name(name() + ".preBackEnergy") 189610618SOmar.Naji@arm.com .desc("Energy for precharge background per rank (pJ)"); 189710618SOmar.Naji@arm.com 189810618SOmar.Naji@arm.com totalEnergy 189910618SOmar.Naji@arm.com .name(name() + ".totalEnergy") 190010618SOmar.Naji@arm.com .desc("Total energy per rank (pJ)"); 190110618SOmar.Naji@arm.com 190210618SOmar.Naji@arm.com averagePower 190310618SOmar.Naji@arm.com .name(name() + ".averagePower") 190410618SOmar.Naji@arm.com .desc("Core power per rank (mW)"); 190510618SOmar.Naji@arm.com} 190610618SOmar.Naji@arm.comvoid 190710146Sandreas.hansson@arm.comDRAMCtrl::regStats() 19089243SN/A{ 19099243SN/A using namespace Stats; 19109243SN/A 19119243SN/A AbstractMemory::regStats(); 19129243SN/A 191310618SOmar.Naji@arm.com for (auto r : ranks) { 191410618SOmar.Naji@arm.com r->regStats(); 191510618SOmar.Naji@arm.com } 191610618SOmar.Naji@arm.com 19179243SN/A readReqs 19189243SN/A .name(name() + ".readReqs") 19199977SN/A .desc("Number of read requests accepted"); 19209243SN/A 19219243SN/A writeReqs 19229243SN/A .name(name() + ".writeReqs") 19239977SN/A .desc("Number of write requests accepted"); 19249831SN/A 19259831SN/A readBursts 19269831SN/A .name(name() + ".readBursts") 19279977SN/A .desc("Number of DRAM read bursts, " 19289977SN/A "including those serviced by the write queue"); 19299831SN/A 19309831SN/A writeBursts 19319831SN/A .name(name() + ".writeBursts") 19329977SN/A .desc("Number of DRAM write bursts, " 19339977SN/A "including those merged in the write queue"); 19349243SN/A 19359243SN/A servicedByWrQ 19369243SN/A .name(name() + ".servicedByWrQ") 19379977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 19389977SN/A 19399977SN/A mergedWrBursts 19409977SN/A .name(name() + ".mergedWrBursts") 19419977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 19429243SN/A 19439243SN/A neitherReadNorWrite 19449977SN/A .name(name() + ".neitherReadNorWriteReqs") 19459977SN/A .desc("Number of requests that are neither read nor write"); 19469243SN/A 19479977SN/A perBankRdBursts 19489243SN/A .init(banksPerRank * ranksPerChannel) 19499977SN/A .name(name() + ".perBankRdBursts") 19509977SN/A .desc("Per bank write bursts"); 19519243SN/A 19529977SN/A perBankWrBursts 19539243SN/A .init(banksPerRank * ranksPerChannel) 19549977SN/A .name(name() + ".perBankWrBursts") 19559977SN/A .desc("Per bank write bursts"); 19569243SN/A 19579243SN/A avgRdQLen 19589243SN/A .name(name() + ".avgRdQLen") 19599977SN/A .desc("Average read queue length when enqueuing") 19609243SN/A .precision(2); 19619243SN/A 19629243SN/A avgWrQLen 19639243SN/A .name(name() + ".avgWrQLen") 19649977SN/A .desc("Average write queue length when enqueuing") 19659243SN/A .precision(2); 19669243SN/A 19679243SN/A totQLat 19689243SN/A .name(name() + ".totQLat") 19699977SN/A .desc("Total ticks spent queuing"); 19709243SN/A 19719243SN/A totBusLat 19729243SN/A .name(name() + ".totBusLat") 19739977SN/A .desc("Total ticks spent in databus transfers"); 19749243SN/A 19759243SN/A totMemAccLat 19769243SN/A .name(name() + ".totMemAccLat") 19779977SN/A .desc("Total ticks spent from burst creation until serviced " 19789977SN/A "by the DRAM"); 19799243SN/A 19809243SN/A avgQLat 19819243SN/A .name(name() + ".avgQLat") 19829977SN/A .desc("Average queueing delay per DRAM burst") 19839243SN/A .precision(2); 19849243SN/A 19859831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 19869243SN/A 19879243SN/A avgBusLat 19889243SN/A .name(name() + ".avgBusLat") 19899977SN/A .desc("Average bus latency per DRAM burst") 19909243SN/A .precision(2); 19919243SN/A 19929831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 19939243SN/A 19949243SN/A avgMemAccLat 19959243SN/A .name(name() + ".avgMemAccLat") 19969977SN/A .desc("Average memory access latency per DRAM burst") 19979243SN/A .precision(2); 19989243SN/A 19999831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 20009243SN/A 20019243SN/A numRdRetry 20029243SN/A .name(name() + ".numRdRetry") 20039977SN/A .desc("Number of times read queue was full causing retry"); 20049243SN/A 20059243SN/A numWrRetry 20069243SN/A .name(name() + ".numWrRetry") 20079977SN/A .desc("Number of times write queue was full causing retry"); 20089243SN/A 20099243SN/A readRowHits 20109243SN/A .name(name() + ".readRowHits") 20119243SN/A .desc("Number of row buffer hits during reads"); 20129243SN/A 20139243SN/A writeRowHits 20149243SN/A .name(name() + ".writeRowHits") 20159243SN/A .desc("Number of row buffer hits during writes"); 20169243SN/A 20179243SN/A readRowHitRate 20189243SN/A .name(name() + ".readRowHitRate") 20199243SN/A .desc("Row buffer hit rate for reads") 20209243SN/A .precision(2); 20219243SN/A 20229831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 20239243SN/A 20249243SN/A writeRowHitRate 20259243SN/A .name(name() + ".writeRowHitRate") 20269243SN/A .desc("Row buffer hit rate for writes") 20279243SN/A .precision(2); 20289243SN/A 20299977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 20309243SN/A 20319243SN/A readPktSize 20329831SN/A .init(ceilLog2(burstSize) + 1) 20339243SN/A .name(name() + ".readPktSize") 20349977SN/A .desc("Read request sizes (log2)"); 20359243SN/A 20369243SN/A writePktSize 20379831SN/A .init(ceilLog2(burstSize) + 1) 20389243SN/A .name(name() + ".writePktSize") 20399977SN/A .desc("Write request sizes (log2)"); 20409243SN/A 20419243SN/A rdQLenPdf 20429567SN/A .init(readBufferSize) 20439243SN/A .name(name() + ".rdQLenPdf") 20449243SN/A .desc("What read queue length does an incoming req see"); 20459243SN/A 20469243SN/A wrQLenPdf 20479567SN/A .init(writeBufferSize) 20489243SN/A .name(name() + ".wrQLenPdf") 20499243SN/A .desc("What write queue length does an incoming req see"); 20509243SN/A 20519727SN/A bytesPerActivate 205210141SN/A .init(maxAccessesPerRow) 20539727SN/A .name(name() + ".bytesPerActivate") 20549727SN/A .desc("Bytes accessed per row activation") 20559727SN/A .flags(nozero); 20569243SN/A 205710147Sandreas.hansson@arm.com rdPerTurnAround 205810147Sandreas.hansson@arm.com .init(readBufferSize) 205910147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 206010147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 206110147Sandreas.hansson@arm.com .flags(nozero); 206210147Sandreas.hansson@arm.com 206310147Sandreas.hansson@arm.com wrPerTurnAround 206410147Sandreas.hansson@arm.com .init(writeBufferSize) 206510147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 206610147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 206710147Sandreas.hansson@arm.com .flags(nozero); 206810147Sandreas.hansson@arm.com 20699975SN/A bytesReadDRAM 20709975SN/A .name(name() + ".bytesReadDRAM") 20719975SN/A .desc("Total number of bytes read from DRAM"); 20729975SN/A 20739975SN/A bytesReadWrQ 20749975SN/A .name(name() + ".bytesReadWrQ") 20759975SN/A .desc("Total number of bytes read from write queue"); 20769243SN/A 20779243SN/A bytesWritten 20789243SN/A .name(name() + ".bytesWritten") 20799977SN/A .desc("Total number of bytes written to DRAM"); 20809243SN/A 20819977SN/A bytesReadSys 20829977SN/A .name(name() + ".bytesReadSys") 20839977SN/A .desc("Total read bytes from the system interface side"); 20849243SN/A 20859977SN/A bytesWrittenSys 20869977SN/A .name(name() + ".bytesWrittenSys") 20879977SN/A .desc("Total written bytes from the system interface side"); 20889243SN/A 20899243SN/A avgRdBW 20909243SN/A .name(name() + ".avgRdBW") 20919977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 20929243SN/A .precision(2); 20939243SN/A 20949977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 20959243SN/A 20969243SN/A avgWrBW 20979243SN/A .name(name() + ".avgWrBW") 20989977SN/A .desc("Average achieved write bandwidth in MiByte/s") 20999243SN/A .precision(2); 21009243SN/A 21019243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 21029243SN/A 21039977SN/A avgRdBWSys 21049977SN/A .name(name() + ".avgRdBWSys") 21059977SN/A .desc("Average system read bandwidth in MiByte/s") 21069243SN/A .precision(2); 21079243SN/A 21089977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 21099243SN/A 21109977SN/A avgWrBWSys 21119977SN/A .name(name() + ".avgWrBWSys") 21129977SN/A .desc("Average system write bandwidth in MiByte/s") 21139243SN/A .precision(2); 21149243SN/A 21159977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 21169243SN/A 21179243SN/A peakBW 21189243SN/A .name(name() + ".peakBW") 21199977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 21209243SN/A .precision(2); 21219243SN/A 21229831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 21239243SN/A 21249243SN/A busUtil 21259243SN/A .name(name() + ".busUtil") 21269243SN/A .desc("Data bus utilization in percentage") 21279243SN/A .precision(2); 21289243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 21299243SN/A 21309243SN/A totGap 21319243SN/A .name(name() + ".totGap") 21329243SN/A .desc("Total gap between requests"); 21339243SN/A 21349243SN/A avgGap 21359243SN/A .name(name() + ".avgGap") 21369243SN/A .desc("Average gap between requests") 21379243SN/A .precision(2); 21389243SN/A 21399243SN/A avgGap = totGap / (readReqs + writeReqs); 21409975SN/A 21419975SN/A // Stats for DRAM Power calculation based on Micron datasheet 21429975SN/A busUtilRead 21439975SN/A .name(name() + ".busUtilRead") 21449975SN/A .desc("Data bus utilization in percentage for reads") 21459975SN/A .precision(2); 21469975SN/A 21479975SN/A busUtilRead = avgRdBW / peakBW * 100; 21489975SN/A 21499975SN/A busUtilWrite 21509975SN/A .name(name() + ".busUtilWrite") 21519975SN/A .desc("Data bus utilization in percentage for writes") 21529975SN/A .precision(2); 21539975SN/A 21549975SN/A busUtilWrite = avgWrBW / peakBW * 100; 21559975SN/A 21569975SN/A pageHitRate 21579975SN/A .name(name() + ".pageHitRate") 21589975SN/A .desc("Row buffer hit rate, read and write combined") 21599975SN/A .precision(2); 21609975SN/A 21619977SN/A pageHitRate = (writeRowHits + readRowHits) / 21629977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 21639243SN/A} 21649243SN/A 21659243SN/Avoid 216610146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 21679243SN/A{ 21689243SN/A // rely on the abstract memory 21699243SN/A functionalAccess(pkt); 21709243SN/A} 21719243SN/A 21729294SN/ABaseSlavePort& 217310146Sandreas.hansson@arm.comDRAMCtrl::getSlavePort(const string &if_name, PortID idx) 21749243SN/A{ 21759243SN/A if (if_name != "port") { 21769243SN/A return MemObject::getSlavePort(if_name, idx); 21779243SN/A } else { 21789243SN/A return port; 21799243SN/A } 21809243SN/A} 21819243SN/A 21829243SN/Aunsigned int 218310146Sandreas.hansson@arm.comDRAMCtrl::drain(DrainManager *dm) 21849243SN/A{ 21859342SN/A unsigned int count = port.drain(dm); 21869243SN/A 21879243SN/A // if there is anything in any of our internal queues, keep track 21889243SN/A // of that as well 21899567SN/A if (!(writeQueue.empty() && readQueue.empty() && 21909567SN/A respQueue.empty())) { 21919352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 21929567SN/A " resp: %d\n", writeQueue.size(), readQueue.size(), 21939567SN/A respQueue.size()); 21949243SN/A ++count; 21959342SN/A drainManager = dm; 219610206Sandreas.hansson@arm.com 21979352SN/A // the only part that is not drained automatically over time 219810206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 219910206Sandreas.hansson@arm.com if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 220010206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 220110206Sandreas.hansson@arm.com } 22029243SN/A } 22039243SN/A 22049243SN/A if (count) 22059342SN/A setDrainState(Drainable::Draining); 22069243SN/A else 22079342SN/A setDrainState(Drainable::Drained); 22089243SN/A return count; 22099243SN/A} 22109243SN/A 221110619Sandreas.hansson@arm.comvoid 221210619Sandreas.hansson@arm.comDRAMCtrl::drainResume() 221310619Sandreas.hansson@arm.com{ 221410619Sandreas.hansson@arm.com if (!isTimingMode && system()->isTimingMode()) { 221510619Sandreas.hansson@arm.com // if we switched to timing mode, kick things into action, 221610619Sandreas.hansson@arm.com // and behave as if we restored from a checkpoint 221710619Sandreas.hansson@arm.com startup(); 221810619Sandreas.hansson@arm.com } else if (isTimingMode && !system()->isTimingMode()) { 221910619Sandreas.hansson@arm.com // if we switch from timing mode, stop the refresh events to 222010619Sandreas.hansson@arm.com // not cause issues with KVM 222110619Sandreas.hansson@arm.com for (auto r : ranks) { 222210619Sandreas.hansson@arm.com r->suspend(); 222310619Sandreas.hansson@arm.com } 222410619Sandreas.hansson@arm.com } 222510619Sandreas.hansson@arm.com 222610619Sandreas.hansson@arm.com // update the mode 222710619Sandreas.hansson@arm.com isTimingMode = system()->isTimingMode(); 222810619Sandreas.hansson@arm.com} 222910619Sandreas.hansson@arm.com 223010146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 22319243SN/A : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 22329243SN/A memory(_memory) 22339243SN/A{ } 22349243SN/A 22359243SN/AAddrRangeList 223610146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 22379243SN/A{ 22389243SN/A AddrRangeList ranges; 22399243SN/A ranges.push_back(memory.getAddrRange()); 22409243SN/A return ranges; 22419243SN/A} 22429243SN/A 22439243SN/Avoid 224410146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 22459243SN/A{ 22469243SN/A pkt->pushLabel(memory.name()); 22479243SN/A 22489243SN/A if (!queue.checkFunctional(pkt)) { 22499243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 22509243SN/A // calls recvAtomic() and throws away the latency; we can save a 22519243SN/A // little here by just not calculating the latency. 22529243SN/A memory.recvFunctional(pkt); 22539243SN/A } 22549243SN/A 22559243SN/A pkt->popLabel(); 22569243SN/A} 22579243SN/A 22589243SN/ATick 225910146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 22609243SN/A{ 22619243SN/A return memory.recvAtomic(pkt); 22629243SN/A} 22639243SN/A 22649243SN/Abool 226510146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 22669243SN/A{ 22679243SN/A // pass it to the memory controller 22689243SN/A return memory.recvTimingReq(pkt); 22699243SN/A} 22709243SN/A 227110146Sandreas.hansson@arm.comDRAMCtrl* 227210146Sandreas.hansson@arm.comDRAMCtrlParams::create() 22739243SN/A{ 227410146Sandreas.hansson@arm.com return new DRAMCtrl(this); 22759243SN/A} 2276