dram_ctrl.cc revision 10509
19243SN/A/* 210206Sandreas.hansson@arm.com * Copyright (c) 2010-2014 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 439243SN/A */ 449243SN/A 4510146Sandreas.hansson@arm.com#include "base/bitfield.hh" 469356SN/A#include "base/trace.hh" 4710146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 4810247Sandreas.hansson@arm.com#include "debug/DRAMPower.hh" 4910208Sandreas.hansson@arm.com#include "debug/DRAMState.hh" 509352SN/A#include "debug/Drain.hh" 5110146Sandreas.hansson@arm.com#include "mem/dram_ctrl.hh" 529814SN/A#include "sim/system.hh" 539243SN/A 549243SN/Ausing namespace std; 5510432SOmar.Naji@arm.comusing namespace Data; 569243SN/A 5710146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 589243SN/A AbstractMemory(p), 599243SN/A port(name() + ".port", *this), 609243SN/A retryRdReq(false), retryWrReq(false), 6110211Sandreas.hansson@arm.com busState(READ), 6210208Sandreas.hansson@arm.com nextReqEvent(this), respondEvent(this), activateEvent(this), 6310208Sandreas.hansson@arm.com prechargeEvent(this), refreshEvent(this), powerEvent(this), 6410208Sandreas.hansson@arm.com drainManager(NULL), 6510489SOmar.Naji@arm.com deviceSize(p->device_size), 669831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 679831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 689831SN/A devicesPerRank(p->devices_per_rank), 699831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 709831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 7110140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 7210286Sandreas.hansson@arm.com columnsPerStripe(range.granularity() / burstSize), 739243SN/A ranksPerChannel(p->ranks_per_channel), 7410394Swendy.elsasser@arm.com bankGroupsPerRank(p->bank_groups_per_rank), 7510394Swendy.elsasser@arm.com bankGroupArch(p->bank_groups_per_rank > 0), 769566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 779243SN/A readBufferSize(p->read_buffer_size), 789243SN/A writeBufferSize(p->write_buffer_size), 7910140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 8010140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 8110147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 8210147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 8310393Swendy.elsasser@arm.com tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST), 8410394Swendy.elsasser@arm.com tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), 8510394Swendy.elsasser@arm.com tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 8610394Swendy.elsasser@arm.com tRRD_L(p->tRRD_L), tXAW(p->tXAW), activationLimit(p->activation_limit), 879243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 889243SN/A pageMgmt(p->page_policy), 8910141SN/A maxAccessesPerRow(p->max_accesses_per_row), 909726SN/A frontendLatency(p->static_frontend_latency), 919726SN/A backendLatency(p->static_backend_latency), 9210208Sandreas.hansson@arm.com busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE), 9310208Sandreas.hansson@arm.com pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), prevArrival(0), 9410393Swendy.elsasser@arm.com nextReqTime(0), pwrStateTick(0), numBanksActive(0), 9510432SOmar.Naji@arm.com activeRank(0), timeStampOffset(0) 969243SN/A{ 979243SN/A // create the bank states based on the dimensions of the ranks and 989243SN/A // banks 999243SN/A banks.resize(ranksPerChannel); 10010432SOmar.Naji@arm.com 10110432SOmar.Naji@arm.com //create list of drampower objects. For each rank 1 drampower instance. 10210432SOmar.Naji@arm.com for (int i = 0; i < ranksPerChannel; i++) { 10310432SOmar.Naji@arm.com DRAMPower drampower = DRAMPower(p, false); 10410432SOmar.Naji@arm.com rankPower.emplace_back(drampower); 10510432SOmar.Naji@arm.com } 10610432SOmar.Naji@arm.com 1079969SN/A actTicks.resize(ranksPerChannel); 1089243SN/A for (size_t c = 0; c < ranksPerChannel; ++c) { 1099243SN/A banks[c].resize(banksPerRank); 1109969SN/A actTicks[c].resize(activationLimit, 0); 1119243SN/A } 1129243SN/A 11310246Sandreas.hansson@arm.com // set the bank indices 11410246Sandreas.hansson@arm.com for (int r = 0; r < ranksPerChannel; r++) { 11510246Sandreas.hansson@arm.com for (int b = 0; b < banksPerRank; b++) { 11610246Sandreas.hansson@arm.com banks[r][b].rank = r; 11710246Sandreas.hansson@arm.com banks[r][b].bank = b; 11810394Swendy.elsasser@arm.com if (bankGroupArch) { 11910394Swendy.elsasser@arm.com // Simply assign lower bits to bank group in order to 12010394Swendy.elsasser@arm.com // rotate across bank groups as banks are incremented 12110394Swendy.elsasser@arm.com // e.g. with 4 banks per bank group and 16 banks total: 12210394Swendy.elsasser@arm.com // banks 0,4,8,12 are in bank group 0 12310394Swendy.elsasser@arm.com // banks 1,5,9,13 are in bank group 1 12410394Swendy.elsasser@arm.com // banks 2,6,10,14 are in bank group 2 12510394Swendy.elsasser@arm.com // banks 3,7,11,15 are in bank group 3 12610394Swendy.elsasser@arm.com banks[r][b].bankgr = b % bankGroupsPerRank; 12710394Swendy.elsasser@arm.com } else { 12810394Swendy.elsasser@arm.com // No bank groups; simply assign to bank number 12910394Swendy.elsasser@arm.com banks[r][b].bankgr = b; 13010394Swendy.elsasser@arm.com } 13110246Sandreas.hansson@arm.com } 13210246Sandreas.hansson@arm.com } 13310246Sandreas.hansson@arm.com 13410140SN/A // perform a basic check of the write thresholds 13510140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 13610140SN/A fatal("Write buffer low threshold %d must be smaller than the " 13710140SN/A "high threshold %d\n", p->write_low_thresh_perc, 13810140SN/A p->write_high_thresh_perc); 1399243SN/A 1409243SN/A // determine the rows per bank by looking at the total capacity 1419567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1429243SN/A 14310489SOmar.Naji@arm.com // determine the dram actual capacity from the DRAM config in Mbytes 14410489SOmar.Naji@arm.com uint64_t deviceCapacity = deviceSize / (1024 * 1024) * devicesPerRank * 14510489SOmar.Naji@arm.com ranksPerChannel; 14610489SOmar.Naji@arm.com 14710489SOmar.Naji@arm.com // if actual DRAM size does not match memory capacity in system warn! 14810489SOmar.Naji@arm.com if (deviceCapacity != capacity / (1024 * 1024)) 14910489SOmar.Naji@arm.com warn("DRAM device capacity (%d Mbytes) does not match the " 15010489SOmar.Naji@arm.com "address range assigned (%d Mbytes)\n", deviceCapacity, 15110489SOmar.Naji@arm.com capacity / (1024 * 1024)); 15210489SOmar.Naji@arm.com 1539243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1549243SN/A AbstractMemory::size()); 1559831SN/A 1569831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1579831SN/A rowBufferSize, columnsPerRowBuffer); 1589831SN/A 1599831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1609243SN/A 16110286Sandreas.hansson@arm.com // a bit of sanity checks on the interleaving 1629566SN/A if (range.interleaved()) { 1639566SN/A if (channels != range.stripes()) 16410143SN/A fatal("%s has %d interleaved address stripes but %d channel(s)\n", 1659566SN/A name(), range.stripes(), channels); 1669566SN/A 16710136SN/A if (addrMapping == Enums::RoRaBaChCo) { 1689831SN/A if (rowBufferSize != range.granularity()) { 16910286Sandreas.hansson@arm.com fatal("Channel interleaving of %s doesn't match RoRaBaChCo " 17010136SN/A "address map\n", name()); 1719566SN/A } 17210286Sandreas.hansson@arm.com } else if (addrMapping == Enums::RoRaBaCoCh || 17310286Sandreas.hansson@arm.com addrMapping == Enums::RoCoRaBaCh) { 17410286Sandreas.hansson@arm.com // for the interleavings with channel bits in the bottom, 17510286Sandreas.hansson@arm.com // if the system uses a channel striping granularity that 17610286Sandreas.hansson@arm.com // is larger than the DRAM burst size, then map the 17710286Sandreas.hansson@arm.com // sequential accesses within a stripe to a number of 17810286Sandreas.hansson@arm.com // columns in the DRAM, effectively placing some of the 17910286Sandreas.hansson@arm.com // lower-order column bits as the least-significant bits 18010286Sandreas.hansson@arm.com // of the address (above the ones denoting the burst size) 18110286Sandreas.hansson@arm.com assert(columnsPerStripe >= 1); 18210286Sandreas.hansson@arm.com 18310286Sandreas.hansson@arm.com // channel striping has to be done at a granularity that 18410286Sandreas.hansson@arm.com // is equal or larger to a cache line 18510286Sandreas.hansson@arm.com if (system()->cacheLineSize() > range.granularity()) { 18610286Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at least as large " 18710286Sandreas.hansson@arm.com "as the cache line size\n", name()); 1889669SN/A } 18910286Sandreas.hansson@arm.com 19010286Sandreas.hansson@arm.com // ...and equal or smaller than the row-buffer size 19110286Sandreas.hansson@arm.com if (rowBufferSize < range.granularity()) { 19210286Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at most as large " 19310286Sandreas.hansson@arm.com "as the row-buffer size\n", name()); 19410286Sandreas.hansson@arm.com } 19510286Sandreas.hansson@arm.com // this is essentially the check above, so just to be sure 19610286Sandreas.hansson@arm.com assert(columnsPerStripe <= columnsPerRowBuffer); 1979566SN/A } 1989566SN/A } 19910207Sandreas.hansson@arm.com 20010207Sandreas.hansson@arm.com // some basic sanity checks 20110207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 20210207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 20310207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 20410207Sandreas.hansson@arm.com } 20510394Swendy.elsasser@arm.com 20610394Swendy.elsasser@arm.com // basic bank group architecture checks -> 20710394Swendy.elsasser@arm.com if (bankGroupArch) { 20810394Swendy.elsasser@arm.com // must have at least one bank per bank group 20910394Swendy.elsasser@arm.com if (bankGroupsPerRank > banksPerRank) { 21010394Swendy.elsasser@arm.com fatal("banks per rank (%d) must be equal to or larger than " 21110394Swendy.elsasser@arm.com "banks groups per rank (%d)\n", 21210394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 21310394Swendy.elsasser@arm.com } 21410394Swendy.elsasser@arm.com // must have same number of banks in each bank group 21510394Swendy.elsasser@arm.com if ((banksPerRank % bankGroupsPerRank) != 0) { 21610394Swendy.elsasser@arm.com fatal("Banks per rank (%d) must be evenly divisible by bank groups " 21710394Swendy.elsasser@arm.com "per rank (%d) for equal banks per bank group\n", 21810394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 21910394Swendy.elsasser@arm.com } 22010394Swendy.elsasser@arm.com // tCCD_L should be greater than minimal, back-to-back burst delay 22110394Swendy.elsasser@arm.com if (tCCD_L <= tBURST) { 22210394Swendy.elsasser@arm.com fatal("tCCD_L (%d) should be larger than tBURST (%d) when " 22310394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 22410394Swendy.elsasser@arm.com tCCD_L, tBURST, bankGroupsPerRank); 22510394Swendy.elsasser@arm.com } 22610394Swendy.elsasser@arm.com // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay 22710394Swendy.elsasser@arm.com if (tRRD_L <= tRRD) { 22810394Swendy.elsasser@arm.com fatal("tRRD_L (%d) should be larger than tRRD (%d) when " 22910394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 23010394Swendy.elsasser@arm.com tRRD_L, tRRD, bankGroupsPerRank); 23110394Swendy.elsasser@arm.com } 23210394Swendy.elsasser@arm.com } 23310394Swendy.elsasser@arm.com 2349243SN/A} 2359243SN/A 2369243SN/Avoid 23710146Sandreas.hansson@arm.comDRAMCtrl::init() 23810140SN/A{ 23910466Sandreas.hansson@arm.com AbstractMemory::init(); 24010466Sandreas.hansson@arm.com 24110466Sandreas.hansson@arm.com if (!port.isConnected()) { 24210146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 24310140SN/A } else { 24410140SN/A port.sendRangeChange(); 24510140SN/A } 24610140SN/A} 24710140SN/A 24810140SN/Avoid 24910146Sandreas.hansson@arm.comDRAMCtrl::startup() 2509243SN/A{ 25110432SOmar.Naji@arm.com // timestamp offset should be in clock cycles for DRAMPower 25210432SOmar.Naji@arm.com timeStampOffset = divCeil(curTick(), tCK); 25310143SN/A // update the start tick for the precharge accounting to the 25410143SN/A // current tick 25510208Sandreas.hansson@arm.com pwrStateTick = curTick(); 25610143SN/A 25710206Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 25810206Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 25910206Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 26010206Sandreas.hansson@arm.com // start of simulation 26110206Sandreas.hansson@arm.com busBusyUntil = curTick() + tRP + tRCD + tCL; 26210206Sandreas.hansson@arm.com 26310207Sandreas.hansson@arm.com // kick off the refresh, and give ourselves enough time to 26410207Sandreas.hansson@arm.com // precharge 26510207Sandreas.hansson@arm.com schedule(refreshEvent, curTick() + tREFI - tRP); 2669243SN/A} 2679243SN/A 2689243SN/ATick 26910146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 2709243SN/A{ 2719243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 2729243SN/A 2739243SN/A // do the actual memory access and turn the packet into a response 2749243SN/A access(pkt); 2759243SN/A 2769243SN/A Tick latency = 0; 2779243SN/A if (!pkt->memInhibitAsserted() && pkt->hasData()) { 2789243SN/A // this value is not supposed to be accurate, just enough to 2799243SN/A // keep things going, mimic a closed page 2809243SN/A latency = tRP + tRCD + tCL; 2819243SN/A } 2829243SN/A return latency; 2839243SN/A} 2849243SN/A 2859243SN/Abool 28610146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 2879243SN/A{ 2889831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 2899831SN/A readBufferSize, readQueue.size() + respQueue.size(), 2909831SN/A neededEntries); 2919243SN/A 2929831SN/A return 2939831SN/A (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 2949243SN/A} 2959243SN/A 2969243SN/Abool 29710146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 2989243SN/A{ 2999831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 3009831SN/A writeBufferSize, writeQueue.size(), neededEntries); 3019831SN/A return (writeQueue.size() + neededEntries) > writeBufferSize; 3029243SN/A} 3039243SN/A 30410146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 30510146Sandreas.hansson@arm.comDRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 30610143SN/A bool isRead) 3079243SN/A{ 3089669SN/A // decode the address based on the address mapping scheme, with 30910136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 31010136SN/A // channel, respectively 3119243SN/A uint8_t rank; 3129967SN/A uint8_t bank; 31310245Sandreas.hansson@arm.com // use a 64-bit unsigned during the computations as the row is 31410245Sandreas.hansson@arm.com // always the top bits, and check before creating the DRAMPacket 31510245Sandreas.hansson@arm.com uint64_t row; 3169243SN/A 31710286Sandreas.hansson@arm.com // truncate the address to a DRAM burst, which makes it unique to 31810286Sandreas.hansson@arm.com // a specific column, row, bank, rank and channel 3199831SN/A Addr addr = dramPktAddr / burstSize; 3209243SN/A 3219491SN/A // we have removed the lowest order address bits that denote the 3229831SN/A // position within the column 32310136SN/A if (addrMapping == Enums::RoRaBaChCo) { 3249491SN/A // the lowest order bits denote the column to ensure that 3259491SN/A // sequential cache lines occupy the same row 3269831SN/A addr = addr / columnsPerRowBuffer; 3279243SN/A 3289669SN/A // take out the channel part of the address 3299566SN/A addr = addr / channels; 3309566SN/A 3319669SN/A // after the channel bits, get the bank bits to interleave 3329669SN/A // over the banks 3339669SN/A bank = addr % banksPerRank; 3349669SN/A addr = addr / banksPerRank; 3359669SN/A 3369669SN/A // after the bank, we get the rank bits which thus interleaves 3379669SN/A // over the ranks 3389669SN/A rank = addr % ranksPerChannel; 3399669SN/A addr = addr / ranksPerChannel; 3409669SN/A 3419669SN/A // lastly, get the row bits 3429669SN/A row = addr % rowsPerBank; 3439669SN/A addr = addr / rowsPerBank; 34410136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 34510286Sandreas.hansson@arm.com // take out the lower-order column bits 34610286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 34710286Sandreas.hansson@arm.com 3489669SN/A // take out the channel part of the address 3499669SN/A addr = addr / channels; 3509669SN/A 35110286Sandreas.hansson@arm.com // next, the higher-order column bites 35210286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3539669SN/A 3549669SN/A // after the column bits, we get the bank bits to interleave 3559491SN/A // over the banks 3569243SN/A bank = addr % banksPerRank; 3579243SN/A addr = addr / banksPerRank; 3589243SN/A 3599491SN/A // after the bank, we get the rank bits which thus interleaves 3609491SN/A // over the ranks 3619243SN/A rank = addr % ranksPerChannel; 3629243SN/A addr = addr / ranksPerChannel; 3639243SN/A 3649491SN/A // lastly, get the row bits 3659243SN/A row = addr % rowsPerBank; 3669243SN/A addr = addr / rowsPerBank; 36710136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 3689491SN/A // optimise for closed page mode and utilise maximum 3699491SN/A // parallelism of the DRAM (at the cost of power) 3709491SN/A 37110286Sandreas.hansson@arm.com // take out the lower-order column bits 37210286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 37310286Sandreas.hansson@arm.com 3749566SN/A // take out the channel part of the address, not that this has 3759566SN/A // to match with how accesses are interleaved between the 3769566SN/A // controllers in the address mapping 3779566SN/A addr = addr / channels; 3789566SN/A 3799491SN/A // start with the bank bits, as this provides the maximum 3809491SN/A // opportunity for parallelism between requests 3819243SN/A bank = addr % banksPerRank; 3829243SN/A addr = addr / banksPerRank; 3839243SN/A 3849491SN/A // next get the rank bits 3859243SN/A rank = addr % ranksPerChannel; 3869243SN/A addr = addr / ranksPerChannel; 3879243SN/A 38810286Sandreas.hansson@arm.com // next, the higher-order column bites 38910286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3909243SN/A 3919491SN/A // lastly, get the row bits 3929243SN/A row = addr % rowsPerBank; 3939243SN/A addr = addr / rowsPerBank; 3949243SN/A } else 3959243SN/A panic("Unknown address mapping policy chosen!"); 3969243SN/A 3979243SN/A assert(rank < ranksPerChannel); 3989243SN/A assert(bank < banksPerRank); 3999243SN/A assert(row < rowsPerBank); 40010245Sandreas.hansson@arm.com assert(row < Bank::NO_ROW); 4019243SN/A 4029243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 4039831SN/A dramPktAddr, rank, bank, row); 4049243SN/A 4059243SN/A // create the corresponding DRAM packet with the entry time and 4069567SN/A // ready time set to the current tick, the latter will be updated 4079567SN/A // later 4089967SN/A uint16_t bank_id = banksPerRank * rank + bank; 4099967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 4109967SN/A size, banks[rank][bank]); 4119243SN/A} 4129243SN/A 4139243SN/Avoid 41410146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 4159243SN/A{ 4169243SN/A // only add to the read queue here. whenever the request is 4179243SN/A // eventually done, set the readyTime, and call schedule() 4189243SN/A assert(!pkt->isWrite()); 4199243SN/A 4209831SN/A assert(pktCount != 0); 4219831SN/A 4229831SN/A // if the request size is larger than burst size, the pkt is split into 4239831SN/A // multiple DRAM packets 4249831SN/A // Note if the pkt starting address is not aligened to burst size, the 4259831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 4269831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 4279831SN/A // check read packets against packets in write queue. 4289243SN/A Addr addr = pkt->getAddr(); 4299831SN/A unsigned pktsServicedByWrQ = 0; 4309831SN/A BurstHelper* burst_helper = NULL; 4319831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4329831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4339831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4349831SN/A readPktSize[ceilLog2(size)]++; 4359831SN/A readBursts++; 4369243SN/A 4379831SN/A // First check write buffer to see if the data is already at 4389831SN/A // the controller 4399831SN/A bool foundInWrQ = false; 4409833SN/A for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) { 4419832SN/A // check if the read is subsumed in the write entry we are 4429832SN/A // looking at 4439832SN/A if ((*i)->addr <= addr && 4449832SN/A (addr + size) <= ((*i)->addr + (*i)->size)) { 4459831SN/A foundInWrQ = true; 4469831SN/A servicedByWrQ++; 4479831SN/A pktsServicedByWrQ++; 4489831SN/A DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 4499831SN/A "write queue\n", addr, size); 4509975SN/A bytesReadWrQ += burstSize; 4519831SN/A break; 4529831SN/A } 4539243SN/A } 4549831SN/A 4559831SN/A // If not found in the write q, make a DRAM packet and 4569831SN/A // push it onto the read queue 4579831SN/A if (!foundInWrQ) { 4589831SN/A 4599831SN/A // Make the burst helper for split packets 4609831SN/A if (pktCount > 1 && burst_helper == NULL) { 4619831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 4629831SN/A "dram requests\n", pkt->getAddr(), pktCount); 4639831SN/A burst_helper = new BurstHelper(pktCount); 4649831SN/A } 4659831SN/A 4669966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 4679831SN/A dram_pkt->burstHelper = burst_helper; 4689831SN/A 4699831SN/A assert(!readQueueFull(1)); 4709831SN/A rdQLenPdf[readQueue.size() + respQueue.size()]++; 4719831SN/A 4729831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 4739831SN/A 4749831SN/A readQueue.push_back(dram_pkt); 4759831SN/A 4769831SN/A // Update stats 4779831SN/A avgRdQLen = readQueue.size() + respQueue.size(); 4789831SN/A } 4799831SN/A 4809831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 4819831SN/A addr = (addr | (burstSize - 1)) + 1; 4829243SN/A } 4839243SN/A 4849831SN/A // If all packets are serviced by write queue, we send the repsonse back 4859831SN/A if (pktsServicedByWrQ == pktCount) { 4869831SN/A accessAndRespond(pkt, frontendLatency); 4879831SN/A return; 4889831SN/A } 4899243SN/A 4909831SN/A // Update how many split packets are serviced by write queue 4919831SN/A if (burst_helper != NULL) 4929831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 4939243SN/A 49410206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 49510206Sandreas.hansson@arm.com // queue, do so now 49610206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 4979567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 4989567SN/A schedule(nextReqEvent, curTick()); 4999243SN/A } 5009243SN/A} 5019243SN/A 5029243SN/Avoid 50310146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 5049243SN/A{ 5059243SN/A // only add to the write queue here. whenever the request is 5069243SN/A // eventually done, set the readyTime, and call schedule() 5079243SN/A assert(pkt->isWrite()); 5089243SN/A 5099831SN/A // if the request size is larger than burst size, the pkt is split into 5109831SN/A // multiple DRAM packets 5119831SN/A Addr addr = pkt->getAddr(); 5129831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 5139831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 5149831SN/A pkt->getAddr() + pkt->getSize()) - addr; 5159831SN/A writePktSize[ceilLog2(size)]++; 5169831SN/A writeBursts++; 5179243SN/A 5189832SN/A // see if we can merge with an existing item in the write 5199838SN/A // queue and keep track of whether we have merged or not so we 5209838SN/A // can stop at that point and also avoid enqueueing a new 5219838SN/A // request 5229832SN/A bool merged = false; 5239832SN/A auto w = writeQueue.begin(); 5249243SN/A 5259832SN/A while(!merged && w != writeQueue.end()) { 5269832SN/A // either of the two could be first, if they are the same 5279832SN/A // it does not matter which way we go 5289832SN/A if ((*w)->addr >= addr) { 5299838SN/A // the existing one starts after the new one, figure 5309838SN/A // out where the new one ends with respect to the 5319838SN/A // existing one 5329832SN/A if ((addr + size) >= ((*w)->addr + (*w)->size)) { 5339832SN/A // check if the existing one is completely 5349832SN/A // subsumed in the new one 5359832SN/A DPRINTF(DRAM, "Merging write covering existing burst\n"); 5369832SN/A merged = true; 5379832SN/A // update both the address and the size 5389832SN/A (*w)->addr = addr; 5399832SN/A (*w)->size = size; 5409832SN/A } else if ((addr + size) >= (*w)->addr && 5419832SN/A ((*w)->addr + (*w)->size - addr) <= burstSize) { 5429832SN/A // the new one is just before or partially 5439832SN/A // overlapping with the existing one, and together 5449832SN/A // they fit within a burst 5459832SN/A DPRINTF(DRAM, "Merging write before existing burst\n"); 5469832SN/A merged = true; 5479832SN/A // the existing queue item needs to be adjusted with 5489832SN/A // respect to both address and size 54910047SN/A (*w)->size = (*w)->addr + (*w)->size - addr; 5509832SN/A (*w)->addr = addr; 5519832SN/A } 5529832SN/A } else { 5539838SN/A // the new one starts after the current one, figure 5549838SN/A // out where the existing one ends with respect to the 5559838SN/A // new one 5569832SN/A if (((*w)->addr + (*w)->size) >= (addr + size)) { 5579832SN/A // check if the new one is completely subsumed in the 5589832SN/A // existing one 5599832SN/A DPRINTF(DRAM, "Merging write into existing burst\n"); 5609832SN/A merged = true; 5619832SN/A // no adjustments necessary 5629832SN/A } else if (((*w)->addr + (*w)->size) >= addr && 5639832SN/A (addr + size - (*w)->addr) <= burstSize) { 5649832SN/A // the existing one is just before or partially 5659832SN/A // overlapping with the new one, and together 5669832SN/A // they fit within a burst 5679832SN/A DPRINTF(DRAM, "Merging write after existing burst\n"); 5689832SN/A merged = true; 5699832SN/A // the address is right, and only the size has 5709832SN/A // to be adjusted 5719832SN/A (*w)->size = addr + size - (*w)->addr; 5729832SN/A } 5739832SN/A } 5749832SN/A ++w; 5759832SN/A } 5769243SN/A 5779832SN/A // if the item was not merged we need to create a new write 5789832SN/A // and enqueue it 5799832SN/A if (!merged) { 5809966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 5819243SN/A 5829832SN/A assert(writeQueue.size() < writeBufferSize); 5839832SN/A wrQLenPdf[writeQueue.size()]++; 5849243SN/A 5859832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 5869831SN/A 5879832SN/A writeQueue.push_back(dram_pkt); 5889831SN/A 5899832SN/A // Update stats 5909832SN/A avgWrQLen = writeQueue.size(); 5919977SN/A } else { 5929977SN/A // keep track of the fact that this burst effectively 5939977SN/A // disappeared as it was merged with an existing one 5949977SN/A mergedWrBursts++; 5959832SN/A } 5969832SN/A 5979831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 5989831SN/A addr = (addr | (burstSize - 1)) + 1; 5999831SN/A } 6009243SN/A 6019243SN/A // we do not wait for the writes to be send to the actual memory, 6029243SN/A // but instead take responsibility for the consistency here and 6039243SN/A // snoop the write queue for any upcoming reads 6049831SN/A // @todo, if a pkt size is larger than burst size, we might need a 6059831SN/A // different front end latency 6069726SN/A accessAndRespond(pkt, frontendLatency); 6079243SN/A 60810206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 60910206Sandreas.hansson@arm.com // queue, do so now 61010206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 61110206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 61210206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 6139243SN/A } 6149243SN/A} 6159243SN/A 6169243SN/Avoid 61710146Sandreas.hansson@arm.comDRAMCtrl::printQs() const { 6189243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 6199833SN/A for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 6209243SN/A DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 6219243SN/A } 6229243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 6239833SN/A for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 6249243SN/A DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 6259243SN/A } 6269243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 6279833SN/A for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 6289243SN/A DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 6299243SN/A } 6309243SN/A} 6319243SN/A 6329243SN/Abool 63310146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 6349243SN/A{ 6359349SN/A /// @todo temporary hack to deal with memory corruption issues until 6369349SN/A /// 4-phase transactions are complete 6379349SN/A for (int x = 0; x < pendingDelete.size(); x++) 6389349SN/A delete pendingDelete[x]; 6399349SN/A pendingDelete.clear(); 6409349SN/A 6419243SN/A // This is where we enter from the outside world 6429567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 6439831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 6449243SN/A 6459567SN/A // simply drop inhibited packets for now 6469567SN/A if (pkt->memInhibitAsserted()) { 64710143SN/A DPRINTF(DRAM, "Inhibited packet -- Dropping it now\n"); 6489567SN/A pendingDelete.push_back(pkt); 6499567SN/A return true; 6509567SN/A } 6519243SN/A 6529243SN/A // Calc avg gap between requests 6539243SN/A if (prevArrival != 0) { 6549243SN/A totGap += curTick() - prevArrival; 6559243SN/A } 6569243SN/A prevArrival = curTick(); 6579243SN/A 6589831SN/A 6599831SN/A // Find out how many dram packets a pkt translates to 6609831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 6619831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 6629831SN/A // multiple dram packets 6639243SN/A unsigned size = pkt->getSize(); 6649831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 6659831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 6669243SN/A 6679243SN/A // check local buffers and do not accept if full 6689243SN/A if (pkt->isRead()) { 6699567SN/A assert(size != 0); 6709831SN/A if (readQueueFull(dram_pkt_count)) { 6719567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 6729243SN/A // remember that we have to retry this port 6739243SN/A retryRdReq = true; 6749243SN/A numRdRetry++; 6759243SN/A return false; 6769243SN/A } else { 6779831SN/A addToReadQueue(pkt, dram_pkt_count); 6789243SN/A readReqs++; 6799977SN/A bytesReadSys += size; 6809243SN/A } 6819243SN/A } else if (pkt->isWrite()) { 6829567SN/A assert(size != 0); 6839831SN/A if (writeQueueFull(dram_pkt_count)) { 6849567SN/A DPRINTF(DRAM, "Write queue full, not accepting\n"); 6859243SN/A // remember that we have to retry this port 6869243SN/A retryWrReq = true; 6879243SN/A numWrRetry++; 6889243SN/A return false; 6899243SN/A } else { 6909831SN/A addToWriteQueue(pkt, dram_pkt_count); 6919243SN/A writeReqs++; 6929977SN/A bytesWrittenSys += size; 6939243SN/A } 6949243SN/A } else { 6959243SN/A DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 6969243SN/A neitherReadNorWrite++; 6979726SN/A accessAndRespond(pkt, 1); 6989243SN/A } 6999243SN/A 7009243SN/A return true; 7019243SN/A} 7029243SN/A 7039243SN/Avoid 70410146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 7059243SN/A{ 7069243SN/A DPRINTF(DRAM, 7079243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 7089243SN/A 7099831SN/A DRAMPacket* dram_pkt = respQueue.front(); 7109243SN/A 7119831SN/A if (dram_pkt->burstHelper) { 7129831SN/A // it is a split packet 7139831SN/A dram_pkt->burstHelper->burstsServiced++; 7149831SN/A if (dram_pkt->burstHelper->burstsServiced == 71510143SN/A dram_pkt->burstHelper->burstCount) { 7169831SN/A // we have now serviced all children packets of a system packet 7179831SN/A // so we can now respond to the requester 7189831SN/A // @todo we probably want to have a different front end and back 7199831SN/A // end latency for split packets 7209831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7219831SN/A delete dram_pkt->burstHelper; 7229831SN/A dram_pkt->burstHelper = NULL; 7239831SN/A } 7249831SN/A } else { 7259831SN/A // it is not a split packet 7269831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7279831SN/A } 7289243SN/A 7299831SN/A delete respQueue.front(); 7309831SN/A respQueue.pop_front(); 7319243SN/A 7329831SN/A if (!respQueue.empty()) { 7339831SN/A assert(respQueue.front()->readyTime >= curTick()); 7349831SN/A assert(!respondEvent.scheduled()); 7359831SN/A schedule(respondEvent, respQueue.front()->readyTime); 7369831SN/A } else { 7379831SN/A // if there is nothing left in any queue, signal a drain 7389831SN/A if (writeQueue.empty() && readQueue.empty() && 7399831SN/A drainManager) { 74010509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 7419831SN/A drainManager->signalDrainDone(); 7429831SN/A drainManager = NULL; 7439831SN/A } 7449831SN/A } 7459567SN/A 7469831SN/A // We have made a location in the queue available at this point, 7479831SN/A // so if there is a read that was forced to wait, retry now 7489831SN/A if (retryRdReq) { 7499831SN/A retryRdReq = false; 7509831SN/A port.sendRetry(); 7519831SN/A } 7529243SN/A} 7539243SN/A 7549243SN/Avoid 75510393Swendy.elsasser@arm.comDRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue, bool switched_cmd_type) 7569243SN/A{ 75710206Sandreas.hansson@arm.com // This method does the arbitration between requests. The chosen 75810206Sandreas.hansson@arm.com // packet is simply moved to the head of the queue. The other 75910206Sandreas.hansson@arm.com // methods know that this is the place to look. For example, with 76010206Sandreas.hansson@arm.com // FCFS, this method does nothing 76110206Sandreas.hansson@arm.com assert(!queue.empty()); 7629243SN/A 76310206Sandreas.hansson@arm.com if (queue.size() == 1) { 76410206Sandreas.hansson@arm.com DPRINTF(DRAM, "Single request, nothing to do\n"); 7659243SN/A return; 7669243SN/A } 7679243SN/A 7689243SN/A if (memSchedPolicy == Enums::fcfs) { 7699243SN/A // Do nothing, since the correct request is already head 7709243SN/A } else if (memSchedPolicy == Enums::frfcfs) { 77110393Swendy.elsasser@arm.com reorderQueue(queue, switched_cmd_type); 7729243SN/A } else 7739243SN/A panic("No scheduling policy chosen\n"); 7749243SN/A} 7759243SN/A 7769243SN/Avoid 77710393Swendy.elsasser@arm.comDRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue, bool switched_cmd_type) 7789974SN/A{ 7799974SN/A // Only determine this when needed 7809974SN/A uint64_t earliest_banks = 0; 7819974SN/A 7829974SN/A // Search for row hits first, if no row hit is found then schedule the 7839974SN/A // packet to one of the earliest banks available 7849974SN/A bool found_earliest_pkt = false; 78510393Swendy.elsasser@arm.com bool found_prepped_diff_rank_pkt = false; 7869974SN/A auto selected_pkt_it = queue.begin(); 7879974SN/A 7889974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 7899974SN/A DRAMPacket* dram_pkt = *i; 7909974SN/A const Bank& bank = dram_pkt->bankRef; 7919974SN/A // Check if it is a row hit 7929974SN/A if (bank.openRow == dram_pkt->row) { 79310393Swendy.elsasser@arm.com if (dram_pkt->rank == activeRank || switched_cmd_type) { 79410393Swendy.elsasser@arm.com // FCFS within the hits, giving priority to commands 79510393Swendy.elsasser@arm.com // that access the same rank as the previous burst 79610393Swendy.elsasser@arm.com // to minimize bus turnaround delays 79710393Swendy.elsasser@arm.com // Only give rank prioity when command type is not changing 79810393Swendy.elsasser@arm.com DPRINTF(DRAM, "Row buffer hit\n"); 79910393Swendy.elsasser@arm.com selected_pkt_it = i; 80010393Swendy.elsasser@arm.com break; 80110393Swendy.elsasser@arm.com } else if (!found_prepped_diff_rank_pkt) { 80210393Swendy.elsasser@arm.com // found row hit for command on different rank than prev burst 80310393Swendy.elsasser@arm.com selected_pkt_it = i; 80410393Swendy.elsasser@arm.com found_prepped_diff_rank_pkt = true; 80510393Swendy.elsasser@arm.com } 80610393Swendy.elsasser@arm.com } else if (!found_earliest_pkt & !found_prepped_diff_rank_pkt) { 80710393Swendy.elsasser@arm.com // No row hit and 80810393Swendy.elsasser@arm.com // haven't found an entry with a row hit to a new rank 8099974SN/A if (earliest_banks == 0) 81010393Swendy.elsasser@arm.com // Determine entries with earliest bank prep delay 81110393Swendy.elsasser@arm.com // Function will give priority to commands that access the 81210393Swendy.elsasser@arm.com // same rank as previous burst and can prep the bank seamlessly 81310393Swendy.elsasser@arm.com earliest_banks = minBankPrep(queue, switched_cmd_type); 81410211Sandreas.hansson@arm.com 81510393Swendy.elsasser@arm.com // FCFS - Bank is first available bank 81610393Swendy.elsasser@arm.com if (bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) { 8179974SN/A // Remember the packet to be scheduled to one of the earliest 81810211Sandreas.hansson@arm.com // banks available, FCFS amongst the earliest banks 8199974SN/A selected_pkt_it = i; 8209974SN/A found_earliest_pkt = true; 8219974SN/A } 8229974SN/A } 8239974SN/A } 8249974SN/A 8259974SN/A DRAMPacket* selected_pkt = *selected_pkt_it; 8269974SN/A queue.erase(selected_pkt_it); 8279974SN/A queue.push_front(selected_pkt); 8289974SN/A} 8299974SN/A 8309974SN/Avoid 83110146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 8329243SN/A{ 8339243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 8349243SN/A 8359243SN/A bool needsResponse = pkt->needsResponse(); 8369243SN/A // do the actual memory access which also turns the packet into a 8379243SN/A // response 8389243SN/A access(pkt); 8399243SN/A 8409243SN/A // turn packet around to go back to requester if response expected 8419243SN/A if (needsResponse) { 8429243SN/A // access already turned the packet into a response 8439243SN/A assert(pkt->isResponse()); 8449243SN/A 8459549SN/A // @todo someone should pay for this 84610405Sandreas.hansson@arm.com pkt->firstWordDelay = pkt->lastWordDelay = 0; 8479549SN/A 8489726SN/A // queue the packet in the response queue to be sent out after 8499726SN/A // the static latency has passed 8509726SN/A port.schedTimingResp(pkt, curTick() + static_latency); 8519243SN/A } else { 8529587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 8539587SN/A // is still having a pointer to it 8549587SN/A pendingDelete.push_back(pkt); 8559243SN/A } 8569243SN/A 8579243SN/A DPRINTF(DRAM, "Done\n"); 8589243SN/A 8599243SN/A return; 8609243SN/A} 8619243SN/A 8629243SN/Avoid 86310246Sandreas.hansson@arm.comDRAMCtrl::activateBank(Bank& bank, Tick act_tick, uint32_t row) 8649488SN/A{ 86510246Sandreas.hansson@arm.com // get the rank index from the bank 86610246Sandreas.hansson@arm.com uint8_t rank = bank.rank; 86710246Sandreas.hansson@arm.com 8689969SN/A assert(actTicks[rank].size() == activationLimit); 8699488SN/A 8709488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 8719488SN/A 87210207Sandreas.hansson@arm.com // update the open row 87310246Sandreas.hansson@arm.com assert(bank.openRow == Bank::NO_ROW); 87410246Sandreas.hansson@arm.com bank.openRow = row; 87510207Sandreas.hansson@arm.com 87610207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 87710207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 87810207Sandreas.hansson@arm.com // precharge 87910246Sandreas.hansson@arm.com bank.bytesAccessed = 0; 88010246Sandreas.hansson@arm.com bank.rowAccesses = 0; 88110207Sandreas.hansson@arm.com 88210207Sandreas.hansson@arm.com ++numBanksActive; 88310207Sandreas.hansson@arm.com assert(numBanksActive <= banksPerRank * ranksPerChannel); 88410207Sandreas.hansson@arm.com 88510247Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n", 88610247Sandreas.hansson@arm.com bank.bank, bank.rank, act_tick, numBanksActive); 88710247Sandreas.hansson@arm.com 88810432SOmar.Naji@arm.com rankPower[bank.rank].powerlib.doCommand(MemCommand::ACT, bank.bank, 88910432SOmar.Naji@arm.com divCeil(act_tick, tCK) - 89010432SOmar.Naji@arm.com timeStampOffset); 89110432SOmar.Naji@arm.com 89210432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK) - 89310432SOmar.Naji@arm.com timeStampOffset, bank.bank, bank.rank); 8949975SN/A 89510211Sandreas.hansson@arm.com // The next access has to respect tRAS for this bank 89610246Sandreas.hansson@arm.com bank.preAllowedAt = act_tick + tRAS; 89710211Sandreas.hansson@arm.com 89810211Sandreas.hansson@arm.com // Respect the row-to-column command delay 89910394Swendy.elsasser@arm.com bank.colAllowedAt = std::max(act_tick + tRCD, bank.colAllowedAt); 90010211Sandreas.hansson@arm.com 9019971SN/A // start by enforcing tRRD 9029971SN/A for(int i = 0; i < banksPerRank; i++) { 90310210Sandreas.hansson@arm.com // next activate to any bank in this rank must not happen 90410210Sandreas.hansson@arm.com // before tRRD 90510394Swendy.elsasser@arm.com if (bankGroupArch && (bank.bankgr == banks[rank][i].bankgr)) { 90610394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 90710394Swendy.elsasser@arm.com // ACT commands within the same bank group. Use tRRD_L 90810394Swendy.elsasser@arm.com // in this case 90910394Swendy.elsasser@arm.com banks[rank][i].actAllowedAt = std::max(act_tick + tRRD_L, 91010394Swendy.elsasser@arm.com banks[rank][i].actAllowedAt); 91110394Swendy.elsasser@arm.com } else { 91210394Swendy.elsasser@arm.com // use shorter tRRD value when either 91310394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 91410394Swendy.elsasser@arm.com // 2) bank is in a different bank group 91510394Swendy.elsasser@arm.com banks[rank][i].actAllowedAt = std::max(act_tick + tRRD, 91610394Swendy.elsasser@arm.com banks[rank][i].actAllowedAt); 91710394Swendy.elsasser@arm.com } 9189971SN/A } 91910208Sandreas.hansson@arm.com 9209971SN/A // next, we deal with tXAW, if the activation limit is disabled 92110492SOmar.Naji@arm.com // then we directly schedule an activate power event 92210492SOmar.Naji@arm.com if (!actTicks[rank].empty()) { 92310492SOmar.Naji@arm.com // sanity check 92410492SOmar.Naji@arm.com if (actTicks[rank].back() && 92510492SOmar.Naji@arm.com (act_tick - actTicks[rank].back()) < tXAW) { 92610492SOmar.Naji@arm.com panic("Got %d activates in window %d (%llu - %llu) which " 92710492SOmar.Naji@arm.com "is smaller than %llu\n", activationLimit, act_tick - 92810492SOmar.Naji@arm.com actTicks[rank].back(), act_tick, actTicks[rank].back(), 92910492SOmar.Naji@arm.com tXAW); 93010492SOmar.Naji@arm.com } 9319824SN/A 93210492SOmar.Naji@arm.com // shift the times used for the book keeping, the last element 93310492SOmar.Naji@arm.com // (highest index) is the oldest one and hence the lowest value 93410492SOmar.Naji@arm.com actTicks[rank].pop_back(); 9359488SN/A 93610492SOmar.Naji@arm.com // record an new activation (in the future) 93710492SOmar.Naji@arm.com actTicks[rank].push_front(act_tick); 9389488SN/A 93910492SOmar.Naji@arm.com // cannot activate more than X times in time window tXAW, push the 94010492SOmar.Naji@arm.com // next one (the X + 1'st activate) to be tXAW away from the 94110492SOmar.Naji@arm.com // oldest in our window of X 94210492SOmar.Naji@arm.com if (actTicks[rank].back() && 94310492SOmar.Naji@arm.com (act_tick - actTicks[rank].back()) < tXAW) { 94410492SOmar.Naji@arm.com DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate " 94510492SOmar.Naji@arm.com "no earlier than %llu\n", activationLimit, 94610492SOmar.Naji@arm.com actTicks[rank].back() + tXAW); 9479488SN/A for(int j = 0; j < banksPerRank; j++) 9489488SN/A // next activate must not happen before end of window 94910210Sandreas.hansson@arm.com banks[rank][j].actAllowedAt = 95010210Sandreas.hansson@arm.com std::max(actTicks[rank].back() + tXAW, 95110210Sandreas.hansson@arm.com banks[rank][j].actAllowedAt); 95210492SOmar.Naji@arm.com } 9539488SN/A } 95410208Sandreas.hansson@arm.com 95510208Sandreas.hansson@arm.com // at the point when this activate takes place, make sure we 95610208Sandreas.hansson@arm.com // transition to the active power state 95710208Sandreas.hansson@arm.com if (!activateEvent.scheduled()) 95810208Sandreas.hansson@arm.com schedule(activateEvent, act_tick); 95910208Sandreas.hansson@arm.com else if (activateEvent.when() > act_tick) 96010208Sandreas.hansson@arm.com // move it sooner in time 96110208Sandreas.hansson@arm.com reschedule(activateEvent, act_tick); 96210208Sandreas.hansson@arm.com} 96310208Sandreas.hansson@arm.com 96410208Sandreas.hansson@arm.comvoid 96510208Sandreas.hansson@arm.comDRAMCtrl::processActivateEvent() 96610208Sandreas.hansson@arm.com{ 96710208Sandreas.hansson@arm.com // we should transition to the active state as soon as any bank is active 96810208Sandreas.hansson@arm.com if (pwrState != PWR_ACT) 96910208Sandreas.hansson@arm.com // note that at this point numBanksActive could be back at 97010208Sandreas.hansson@arm.com // zero again due to a precharge scheduled in the future 97110208Sandreas.hansson@arm.com schedulePowerEvent(PWR_ACT, curTick()); 9729488SN/A} 9739488SN/A 9749488SN/Avoid 97510247Sandreas.hansson@arm.comDRAMCtrl::prechargeBank(Bank& bank, Tick pre_at, bool trace) 97610207Sandreas.hansson@arm.com{ 97710207Sandreas.hansson@arm.com // make sure the bank has an open row 97810207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 97910207Sandreas.hansson@arm.com 98010207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 98110207Sandreas.hansson@arm.com // the page 98210207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 98310207Sandreas.hansson@arm.com 98410207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 98510207Sandreas.hansson@arm.com 98610214Sandreas.hansson@arm.com // no precharge allowed before this one 98710214Sandreas.hansson@arm.com bank.preAllowedAt = pre_at; 98810214Sandreas.hansson@arm.com 98910211Sandreas.hansson@arm.com Tick pre_done_at = pre_at + tRP; 99010211Sandreas.hansson@arm.com 99110211Sandreas.hansson@arm.com bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at); 99210207Sandreas.hansson@arm.com 99310207Sandreas.hansson@arm.com assert(numBanksActive != 0); 99410207Sandreas.hansson@arm.com --numBanksActive; 99510207Sandreas.hansson@arm.com 99610247Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got " 99710247Sandreas.hansson@arm.com "%d active\n", bank.bank, bank.rank, pre_at, numBanksActive); 99810247Sandreas.hansson@arm.com 99910432SOmar.Naji@arm.com if (trace) { 100010207Sandreas.hansson@arm.com 100110432SOmar.Naji@arm.com rankPower[bank.rank].powerlib.doCommand(MemCommand::PRE, bank.bank, 100210432SOmar.Naji@arm.com divCeil(pre_at, tCK) - 100310432SOmar.Naji@arm.com timeStampOffset); 100410432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK) - 100510432SOmar.Naji@arm.com timeStampOffset, bank.bank, bank.rank); 100610432SOmar.Naji@arm.com } 100710208Sandreas.hansson@arm.com // if we look at the current number of active banks we might be 100810208Sandreas.hansson@arm.com // tempted to think the DRAM is now idle, however this can be 100910208Sandreas.hansson@arm.com // undone by an activate that is scheduled to happen before we 101010208Sandreas.hansson@arm.com // would have reached the idle state, so schedule an event and 101110208Sandreas.hansson@arm.com // rather check once we actually make it to the point in time when 101210208Sandreas.hansson@arm.com // the (last) precharge takes place 101310208Sandreas.hansson@arm.com if (!prechargeEvent.scheduled()) 101410211Sandreas.hansson@arm.com schedule(prechargeEvent, pre_done_at); 101510211Sandreas.hansson@arm.com else if (prechargeEvent.when() < pre_done_at) 101610211Sandreas.hansson@arm.com reschedule(prechargeEvent, pre_done_at); 101710208Sandreas.hansson@arm.com} 101810208Sandreas.hansson@arm.com 101910208Sandreas.hansson@arm.comvoid 102010208Sandreas.hansson@arm.comDRAMCtrl::processPrechargeEvent() 102110208Sandreas.hansson@arm.com{ 102210207Sandreas.hansson@arm.com // if we reached zero, then special conditions apply as we track 102310207Sandreas.hansson@arm.com // if all banks are precharged for the power models 102410207Sandreas.hansson@arm.com if (numBanksActive == 0) { 102510208Sandreas.hansson@arm.com // we should transition to the idle state when the last bank 102610208Sandreas.hansson@arm.com // is precharged 102710208Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 102810207Sandreas.hansson@arm.com } 102910207Sandreas.hansson@arm.com} 103010207Sandreas.hansson@arm.com 103110207Sandreas.hansson@arm.comvoid 103210146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 10339243SN/A{ 10349243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 10359243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 10369243SN/A 103710211Sandreas.hansson@arm.com // get the bank 10389967SN/A Bank& bank = dram_pkt->bankRef; 10399243SN/A 104010211Sandreas.hansson@arm.com // for the state we need to track if it is a row hit or not 104110211Sandreas.hansson@arm.com bool row_hit = true; 104210211Sandreas.hansson@arm.com 104310211Sandreas.hansson@arm.com // respect any constraints on the command (e.g. tRCD or tCCD) 104410211Sandreas.hansson@arm.com Tick cmd_at = std::max(bank.colAllowedAt, curTick()); 104510211Sandreas.hansson@arm.com 104610211Sandreas.hansson@arm.com // Determine the access latency and update the bank state 104710211Sandreas.hansson@arm.com if (bank.openRow == dram_pkt->row) { 104810211Sandreas.hansson@arm.com // nothing to do 104910209Sandreas.hansson@arm.com } else { 105010211Sandreas.hansson@arm.com row_hit = false; 105110211Sandreas.hansson@arm.com 105210209Sandreas.hansson@arm.com // If there is a page open, precharge it. 105310209Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 105410211Sandreas.hansson@arm.com prechargeBank(bank, std::max(bank.preAllowedAt, curTick())); 10559488SN/A } 10569973SN/A 105710211Sandreas.hansson@arm.com // next we need to account for the delay in activating the 105810211Sandreas.hansson@arm.com // page 105910211Sandreas.hansson@arm.com Tick act_tick = std::max(bank.actAllowedAt, curTick()); 10609973SN/A 106110210Sandreas.hansson@arm.com // Record the activation and deal with all the global timing 106210210Sandreas.hansson@arm.com // constraints caused be a new activation (tRRD and tXAW) 106310246Sandreas.hansson@arm.com activateBank(bank, act_tick, dram_pkt->row); 106410210Sandreas.hansson@arm.com 106510211Sandreas.hansson@arm.com // issue the command as early as possible 106610211Sandreas.hansson@arm.com cmd_at = bank.colAllowedAt; 106710209Sandreas.hansson@arm.com } 106810209Sandreas.hansson@arm.com 106910211Sandreas.hansson@arm.com // we need to wait until the bus is available before we can issue 107010211Sandreas.hansson@arm.com // the command 107110211Sandreas.hansson@arm.com cmd_at = std::max(cmd_at, busBusyUntil - tCL); 107210211Sandreas.hansson@arm.com 107310211Sandreas.hansson@arm.com // update the packet ready time 107410211Sandreas.hansson@arm.com dram_pkt->readyTime = cmd_at + tCL + tBURST; 107510211Sandreas.hansson@arm.com 107610211Sandreas.hansson@arm.com // only one burst can use the bus at any one point in time 107710211Sandreas.hansson@arm.com assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 107810211Sandreas.hansson@arm.com 107910394Swendy.elsasser@arm.com // update the time for the next read/write burst for each 108010394Swendy.elsasser@arm.com // bank (add a max with tCCD/tCCD_L here) 108110394Swendy.elsasser@arm.com Tick cmd_dly; 108210394Swendy.elsasser@arm.com for(int j = 0; j < ranksPerChannel; j++) { 108310394Swendy.elsasser@arm.com for(int i = 0; i < banksPerRank; i++) { 108410394Swendy.elsasser@arm.com // next burst to same bank group in this rank must not happen 108510394Swendy.elsasser@arm.com // before tCCD_L. Different bank group timing requirement is 108610394Swendy.elsasser@arm.com // tBURST; Add tCS for different ranks 108710394Swendy.elsasser@arm.com if (dram_pkt->rank == j) { 108810394Swendy.elsasser@arm.com if (bankGroupArch && (bank.bankgr == banks[j][i].bankgr)) { 108910394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 109010394Swendy.elsasser@arm.com // RD/WR burst commands to the same bank group. 109110394Swendy.elsasser@arm.com // Use tCCD_L in this case 109210394Swendy.elsasser@arm.com cmd_dly = tCCD_L; 109310394Swendy.elsasser@arm.com } else { 109410394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), the shorter 109510394Swendy.elsasser@arm.com // cas-to-cas delay value, when either: 109610394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 109710394Swendy.elsasser@arm.com // 2) bank is in a different bank group 109810394Swendy.elsasser@arm.com cmd_dly = tBURST; 109910394Swendy.elsasser@arm.com } 110010394Swendy.elsasser@arm.com } else { 110110394Swendy.elsasser@arm.com // different rank is by default in a different bank group 110210394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), which is the shorter 110310394Swendy.elsasser@arm.com // cas-to-cas delay in this case 110410394Swendy.elsasser@arm.com // Add tCS to account for rank-to-rank bus delay requirements 110510394Swendy.elsasser@arm.com cmd_dly = tBURST + tCS; 110610394Swendy.elsasser@arm.com } 110710394Swendy.elsasser@arm.com banks[j][i].colAllowedAt = std::max(cmd_at + cmd_dly, 110810394Swendy.elsasser@arm.com banks[j][i].colAllowedAt); 110910394Swendy.elsasser@arm.com } 111010394Swendy.elsasser@arm.com } 111110211Sandreas.hansson@arm.com 111210393Swendy.elsasser@arm.com // Save rank of current access 111310393Swendy.elsasser@arm.com activeRank = dram_pkt->rank; 111410393Swendy.elsasser@arm.com 111510212Sandreas.hansson@arm.com // If this is a write, we also need to respect the write recovery 111610212Sandreas.hansson@arm.com // time before a precharge, in the case of a read, respect the 111710212Sandreas.hansson@arm.com // read to precharge constraint 111810212Sandreas.hansson@arm.com bank.preAllowedAt = std::max(bank.preAllowedAt, 111910212Sandreas.hansson@arm.com dram_pkt->isRead ? cmd_at + tRTP : 112010212Sandreas.hansson@arm.com dram_pkt->readyTime + tWR); 112110210Sandreas.hansson@arm.com 112210209Sandreas.hansson@arm.com // increment the bytes accessed and the accesses per row 112310209Sandreas.hansson@arm.com bank.bytesAccessed += burstSize; 112410209Sandreas.hansson@arm.com ++bank.rowAccesses; 112510209Sandreas.hansson@arm.com 112610209Sandreas.hansson@arm.com // if we reached the max, then issue with an auto-precharge 112710209Sandreas.hansson@arm.com bool auto_precharge = pageMgmt == Enums::close || 112810209Sandreas.hansson@arm.com bank.rowAccesses == maxAccessesPerRow; 112910209Sandreas.hansson@arm.com 113010209Sandreas.hansson@arm.com // if we did not hit the limit, we might still want to 113110209Sandreas.hansson@arm.com // auto-precharge 113210209Sandreas.hansson@arm.com if (!auto_precharge && 113310209Sandreas.hansson@arm.com (pageMgmt == Enums::open_adaptive || 113410209Sandreas.hansson@arm.com pageMgmt == Enums::close_adaptive)) { 113510209Sandreas.hansson@arm.com // a twist on the open and close page policies: 113610209Sandreas.hansson@arm.com // 1) open_adaptive page policy does not blindly keep the 113710209Sandreas.hansson@arm.com // page open, but close it if there are no row hits, and there 113810209Sandreas.hansson@arm.com // are bank conflicts in the queue 113910209Sandreas.hansson@arm.com // 2) close_adaptive page policy does not blindly close the 114010209Sandreas.hansson@arm.com // page, but closes it only if there are no row hits in the queue. 114110209Sandreas.hansson@arm.com // In this case, only force an auto precharge when there 114210209Sandreas.hansson@arm.com // are no same page hits in the queue 114310209Sandreas.hansson@arm.com bool got_more_hits = false; 114410209Sandreas.hansson@arm.com bool got_bank_conflict = false; 114510209Sandreas.hansson@arm.com 114610209Sandreas.hansson@arm.com // either look at the read queue or write queue 114710209Sandreas.hansson@arm.com const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 114810209Sandreas.hansson@arm.com writeQueue; 114910209Sandreas.hansson@arm.com auto p = queue.begin(); 115010209Sandreas.hansson@arm.com // make sure we are not considering the packet that we are 115110209Sandreas.hansson@arm.com // currently dealing with (which is the head of the queue) 115210209Sandreas.hansson@arm.com ++p; 115310209Sandreas.hansson@arm.com 115410209Sandreas.hansson@arm.com // keep on looking until we have found required condition or 115510209Sandreas.hansson@arm.com // reached the end 115610209Sandreas.hansson@arm.com while (!(got_more_hits && 115710209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive)) && 115810209Sandreas.hansson@arm.com p != queue.end()) { 115910209Sandreas.hansson@arm.com bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 116010209Sandreas.hansson@arm.com (dram_pkt->bank == (*p)->bank); 116110209Sandreas.hansson@arm.com bool same_row = dram_pkt->row == (*p)->row; 116210209Sandreas.hansson@arm.com got_more_hits |= same_rank_bank && same_row; 116310209Sandreas.hansson@arm.com got_bank_conflict |= same_rank_bank && !same_row; 11649973SN/A ++p; 116510141SN/A } 116610141SN/A 116710209Sandreas.hansson@arm.com // auto pre-charge when either 116810209Sandreas.hansson@arm.com // 1) open_adaptive policy, we have not got any more hits, and 116910209Sandreas.hansson@arm.com // have a bank conflict 117010209Sandreas.hansson@arm.com // 2) close_adaptive policy and we have not got any more hits 117110209Sandreas.hansson@arm.com auto_precharge = !got_more_hits && 117210209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive); 117310209Sandreas.hansson@arm.com } 117410142SN/A 117510247Sandreas.hansson@arm.com // DRAMPower trace command to be written 117610247Sandreas.hansson@arm.com std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR"; 117710247Sandreas.hansson@arm.com 117810432SOmar.Naji@arm.com // MemCommand required for DRAMPower library 117910432SOmar.Naji@arm.com MemCommand::cmds command = (mem_cmd == "RD") ? MemCommand::RD : 118010432SOmar.Naji@arm.com MemCommand::WR; 118110432SOmar.Naji@arm.com 118210209Sandreas.hansson@arm.com // if this access should use auto-precharge, then we are 118310209Sandreas.hansson@arm.com // closing the row 118410209Sandreas.hansson@arm.com if (auto_precharge) { 118510432SOmar.Naji@arm.com // if auto-precharge push a PRE command at the correct tick to the 118610432SOmar.Naji@arm.com // list used by DRAMPower library to calculate power 118710432SOmar.Naji@arm.com prechargeBank(bank, std::max(curTick(), bank.preAllowedAt)); 11889973SN/A 118910209Sandreas.hansson@arm.com DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 119010209Sandreas.hansson@arm.com } 11919963SN/A 11929243SN/A // Update bus state 11939243SN/A busBusyUntil = dram_pkt->readyTime; 11949243SN/A 119510211Sandreas.hansson@arm.com DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n", 119610211Sandreas.hansson@arm.com dram_pkt->addr, dram_pkt->readyTime, busBusyUntil); 11979243SN/A 119810432SOmar.Naji@arm.com rankPower[dram_pkt->rank].powerlib.doCommand(command, dram_pkt->bank, 119910432SOmar.Naji@arm.com divCeil(cmd_at, tCK) - 120010432SOmar.Naji@arm.com timeStampOffset); 120110432SOmar.Naji@arm.com 120210432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK) - 120310432SOmar.Naji@arm.com timeStampOffset, mem_cmd, dram_pkt->bank, dram_pkt->rank); 120410247Sandreas.hansson@arm.com 120510206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 120610206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 120710206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 120810206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 120910206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 12109972SN/A 121110206Sandreas.hansson@arm.com // Update the stats and schedule the next request 12129977SN/A if (dram_pkt->isRead) { 121310147Sandreas.hansson@arm.com ++readsThisTime; 121410211Sandreas.hansson@arm.com if (row_hit) 12159977SN/A readRowHits++; 12169977SN/A bytesReadDRAM += burstSize; 12179977SN/A perBankRdBursts[dram_pkt->bankId]++; 121810206Sandreas.hansson@arm.com 121910206Sandreas.hansson@arm.com // Update latency stats 122010206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 122110206Sandreas.hansson@arm.com totBusLat += tBURST; 122210211Sandreas.hansson@arm.com totQLat += cmd_at - dram_pkt->entryTime; 12239977SN/A } else { 122410147Sandreas.hansson@arm.com ++writesThisTime; 122510211Sandreas.hansson@arm.com if (row_hit) 12269977SN/A writeRowHits++; 12279977SN/A bytesWritten += burstSize; 12289977SN/A perBankWrBursts[dram_pkt->bankId]++; 12299243SN/A } 12309243SN/A} 12319243SN/A 12329243SN/Avoid 123310206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 12349243SN/A{ 123510393Swendy.elsasser@arm.com // pre-emptively set to false. Overwrite if in READ_TO_WRITE 123610393Swendy.elsasser@arm.com // or WRITE_TO_READ state 123710393Swendy.elsasser@arm.com bool switched_cmd_type = false; 123810206Sandreas.hansson@arm.com if (busState == READ_TO_WRITE) { 123910206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 124010206Sandreas.hansson@arm.com "waiting\n", readsThisTime, readQueue.size()); 12419243SN/A 124210206Sandreas.hansson@arm.com // sample and reset the read-related stats as we are now 124310206Sandreas.hansson@arm.com // transitioning to writes, and all reads are done 124410206Sandreas.hansson@arm.com rdPerTurnAround.sample(readsThisTime); 124510206Sandreas.hansson@arm.com readsThisTime = 0; 124610206Sandreas.hansson@arm.com 124710206Sandreas.hansson@arm.com // now proceed to do the actual writes 124810206Sandreas.hansson@arm.com busState = WRITE; 124910393Swendy.elsasser@arm.com switched_cmd_type = true; 125010206Sandreas.hansson@arm.com } else if (busState == WRITE_TO_READ) { 125110206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 125210206Sandreas.hansson@arm.com "waiting\n", writesThisTime, writeQueue.size()); 125310206Sandreas.hansson@arm.com 125410206Sandreas.hansson@arm.com wrPerTurnAround.sample(writesThisTime); 125510206Sandreas.hansson@arm.com writesThisTime = 0; 125610206Sandreas.hansson@arm.com 125710206Sandreas.hansson@arm.com busState = READ; 125810393Swendy.elsasser@arm.com switched_cmd_type = true; 125910206Sandreas.hansson@arm.com } 126010206Sandreas.hansson@arm.com 126110207Sandreas.hansson@arm.com if (refreshState != REF_IDLE) { 126210207Sandreas.hansson@arm.com // if a refresh waiting for this event loop to finish, then hand 126310207Sandreas.hansson@arm.com // over now, and do not schedule a new nextReqEvent 126410207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 126510207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 126610207Sandreas.hansson@arm.com 126710207Sandreas.hansson@arm.com refreshState = REF_PRE; 126810207Sandreas.hansson@arm.com 126910207Sandreas.hansson@arm.com // hand control back to the refresh event loop 127010207Sandreas.hansson@arm.com schedule(refreshEvent, curTick()); 127110207Sandreas.hansson@arm.com } 127210207Sandreas.hansson@arm.com 127310207Sandreas.hansson@arm.com // let the refresh finish before issuing any further requests 127410207Sandreas.hansson@arm.com return; 127510207Sandreas.hansson@arm.com } 127610207Sandreas.hansson@arm.com 127710206Sandreas.hansson@arm.com // when we get here it is either a read or a write 127810206Sandreas.hansson@arm.com if (busState == READ) { 127910206Sandreas.hansson@arm.com 128010206Sandreas.hansson@arm.com // track if we should switch or not 128110206Sandreas.hansson@arm.com bool switch_to_writes = false; 128210206Sandreas.hansson@arm.com 128310206Sandreas.hansson@arm.com if (readQueue.empty()) { 128410206Sandreas.hansson@arm.com // In the case there is no read request to go next, 128510206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 128610206Sandreas.hansson@arm.com // if we are draining) 128710206Sandreas.hansson@arm.com if (!writeQueue.empty() && 128810206Sandreas.hansson@arm.com (drainManager || writeQueue.size() > writeLowThreshold)) { 128910206Sandreas.hansson@arm.com 129010206Sandreas.hansson@arm.com switch_to_writes = true; 129110206Sandreas.hansson@arm.com } else { 129210206Sandreas.hansson@arm.com // check if we are drained 129310206Sandreas.hansson@arm.com if (respQueue.empty () && drainManager) { 129410509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 129510206Sandreas.hansson@arm.com drainManager->signalDrainDone(); 129610206Sandreas.hansson@arm.com drainManager = NULL; 129710206Sandreas.hansson@arm.com } 129810206Sandreas.hansson@arm.com 129910206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 130010206Sandreas.hansson@arm.com // event for the next request 130110206Sandreas.hansson@arm.com return; 130210206Sandreas.hansson@arm.com } 130310206Sandreas.hansson@arm.com } else { 130410206Sandreas.hansson@arm.com // Figure out which read request goes next, and move it to the 130510206Sandreas.hansson@arm.com // front of the read queue 130610393Swendy.elsasser@arm.com chooseNext(readQueue, switched_cmd_type); 130710206Sandreas.hansson@arm.com 130810215Sandreas.hansson@arm.com DRAMPacket* dram_pkt = readQueue.front(); 130910215Sandreas.hansson@arm.com 131010393Swendy.elsasser@arm.com // here we get a bit creative and shift the bus busy time not 131110393Swendy.elsasser@arm.com // just the tWTR, but also a CAS latency to capture the fact 131210393Swendy.elsasser@arm.com // that we are allowed to prepare a new bank, but not issue a 131310393Swendy.elsasser@arm.com // read command until after tWTR, in essence we capture a 131410393Swendy.elsasser@arm.com // bubble on the data bus that is tWTR + tCL 131510394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 131610394Swendy.elsasser@arm.com busBusyUntil += tWTR + tCL; 131710393Swendy.elsasser@arm.com } 131810393Swendy.elsasser@arm.com 131910215Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 132010206Sandreas.hansson@arm.com 132110206Sandreas.hansson@arm.com // At this point we're done dealing with the request 132210215Sandreas.hansson@arm.com readQueue.pop_front(); 132310215Sandreas.hansson@arm.com 132410215Sandreas.hansson@arm.com // sanity check 132510215Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 132610215Sandreas.hansson@arm.com assert(dram_pkt->readyTime >= curTick()); 132710215Sandreas.hansson@arm.com 132810215Sandreas.hansson@arm.com // Insert into response queue. It will be sent back to the 132910215Sandreas.hansson@arm.com // requestor at its readyTime 133010215Sandreas.hansson@arm.com if (respQueue.empty()) { 133110215Sandreas.hansson@arm.com assert(!respondEvent.scheduled()); 133210215Sandreas.hansson@arm.com schedule(respondEvent, dram_pkt->readyTime); 133310215Sandreas.hansson@arm.com } else { 133410215Sandreas.hansson@arm.com assert(respQueue.back()->readyTime <= dram_pkt->readyTime); 133510215Sandreas.hansson@arm.com assert(respondEvent.scheduled()); 133610215Sandreas.hansson@arm.com } 133710215Sandreas.hansson@arm.com 133810215Sandreas.hansson@arm.com respQueue.push_back(dram_pkt); 133910206Sandreas.hansson@arm.com 134010206Sandreas.hansson@arm.com // we have so many writes that we have to transition 134110206Sandreas.hansson@arm.com if (writeQueue.size() > writeHighThreshold) { 134210206Sandreas.hansson@arm.com switch_to_writes = true; 134310206Sandreas.hansson@arm.com } 134410206Sandreas.hansson@arm.com } 134510206Sandreas.hansson@arm.com 134610206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 134710206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 134810206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 134910206Sandreas.hansson@arm.com if (switch_to_writes) { 135010206Sandreas.hansson@arm.com // transition to writing 135110206Sandreas.hansson@arm.com busState = READ_TO_WRITE; 135210206Sandreas.hansson@arm.com } 13539352SN/A } else { 135410393Swendy.elsasser@arm.com chooseNext(writeQueue, switched_cmd_type); 135510206Sandreas.hansson@arm.com DRAMPacket* dram_pkt = writeQueue.front(); 135610206Sandreas.hansson@arm.com // sanity check 135710206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 135810393Swendy.elsasser@arm.com 135910394Swendy.elsasser@arm.com // add a bubble to the data bus, as defined by the 136010394Swendy.elsasser@arm.com // tRTW when access is to the same rank as previous burst 136110394Swendy.elsasser@arm.com // Different rank timing is handled with tCS, which is 136210394Swendy.elsasser@arm.com // applied to colAllowedAt 136310394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 136410394Swendy.elsasser@arm.com busBusyUntil += tRTW; 136510393Swendy.elsasser@arm.com } 136610393Swendy.elsasser@arm.com 136710206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 136810206Sandreas.hansson@arm.com 136910206Sandreas.hansson@arm.com writeQueue.pop_front(); 137010206Sandreas.hansson@arm.com delete dram_pkt; 137110206Sandreas.hansson@arm.com 137210206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 137310206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 137410206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 137510206Sandreas.hansson@arm.com // writes, then switch to reads. 137610206Sandreas.hansson@arm.com if (writeQueue.empty() || 137710206Sandreas.hansson@arm.com (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 137810206Sandreas.hansson@arm.com !drainManager) || 137910206Sandreas.hansson@arm.com (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 138010206Sandreas.hansson@arm.com // turn the bus back around for reads again 138110206Sandreas.hansson@arm.com busState = WRITE_TO_READ; 138210206Sandreas.hansson@arm.com 138310206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 138410206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 138510206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 138610206Sandreas.hansson@arm.com // nothing to do 138710206Sandreas.hansson@arm.com } 138810206Sandreas.hansson@arm.com } 138910206Sandreas.hansson@arm.com 139010206Sandreas.hansson@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 139110206Sandreas.hansson@arm.com 139210206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 139310206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 139410206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 139510206Sandreas.hansson@arm.com // the next request processing 139610206Sandreas.hansson@arm.com if (retryWrReq && writeQueue.size() < writeBufferSize) { 139710206Sandreas.hansson@arm.com retryWrReq = false; 139810206Sandreas.hansson@arm.com port.sendRetry(); 13999352SN/A } 14009243SN/A} 14019243SN/A 14029967SN/Auint64_t 140310393Swendy.elsasser@arm.comDRAMCtrl::minBankPrep(const deque<DRAMPacket*>& queue, 140410393Swendy.elsasser@arm.com bool switched_cmd_type) const 14059967SN/A{ 14069967SN/A uint64_t bank_mask = 0; 140710211Sandreas.hansson@arm.com Tick min_act_at = MaxTick; 14089967SN/A 140910393Swendy.elsasser@arm.com uint64_t bank_mask_same_rank = 0; 141010393Swendy.elsasser@arm.com Tick min_act_at_same_rank = MaxTick; 141110393Swendy.elsasser@arm.com 141210393Swendy.elsasser@arm.com // Give precedence to commands that access same rank as previous command 141310393Swendy.elsasser@arm.com bool same_rank_match = false; 141410393Swendy.elsasser@arm.com 141510393Swendy.elsasser@arm.com // determine if we have queued transactions targetting the 14169967SN/A // bank in question 14179967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 14189967SN/A for (auto p = queue.begin(); p != queue.end(); ++p) { 14199967SN/A got_waiting[(*p)->bankId] = true; 14209967SN/A } 14219967SN/A 14229967SN/A for (int i = 0; i < ranksPerChannel; i++) { 14239967SN/A for (int j = 0; j < banksPerRank; j++) { 142410211Sandreas.hansson@arm.com uint8_t bank_id = i * banksPerRank + j; 142510211Sandreas.hansson@arm.com 14269967SN/A // if we have waiting requests for the bank, and it is 14279967SN/A // amongst the first available, update the mask 142810211Sandreas.hansson@arm.com if (got_waiting[bank_id]) { 142910211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue 143010211Sandreas.hansson@arm.com // an activate, ignoring any rank-to-rank switching 143110393Swendy.elsasser@arm.com // cost in this calculation 143210211Sandreas.hansson@arm.com Tick act_at = banks[i][j].openRow == Bank::NO_ROW ? 143310211Sandreas.hansson@arm.com banks[i][j].actAllowedAt : 143410211Sandreas.hansson@arm.com std::max(banks[i][j].preAllowedAt, curTick()) + tRP; 143510211Sandreas.hansson@arm.com 143610393Swendy.elsasser@arm.com // prioritize commands that access the 143710393Swendy.elsasser@arm.com // same rank as previous burst 143810393Swendy.elsasser@arm.com // Calculate bank mask separately for the case and 143910393Swendy.elsasser@arm.com // evaluate after loop iterations complete 144010393Swendy.elsasser@arm.com if (i == activeRank && ranksPerChannel > 1) { 144110393Swendy.elsasser@arm.com if (act_at <= min_act_at_same_rank) { 144210393Swendy.elsasser@arm.com // reset same rank bank mask if new minimum is found 144310393Swendy.elsasser@arm.com // and previous minimum could not immediately send ACT 144410393Swendy.elsasser@arm.com if (act_at < min_act_at_same_rank && 144510393Swendy.elsasser@arm.com min_act_at_same_rank > curTick()) 144610393Swendy.elsasser@arm.com bank_mask_same_rank = 0; 144710393Swendy.elsasser@arm.com 144810393Swendy.elsasser@arm.com // Set flag indicating that a same rank 144910393Swendy.elsasser@arm.com // opportunity was found 145010393Swendy.elsasser@arm.com same_rank_match = true; 145110393Swendy.elsasser@arm.com 145210393Swendy.elsasser@arm.com // set the bit corresponding to the available bank 145310393Swendy.elsasser@arm.com replaceBits(bank_mask_same_rank, bank_id, bank_id, 1); 145410393Swendy.elsasser@arm.com min_act_at_same_rank = act_at; 145510393Swendy.elsasser@arm.com } 145610393Swendy.elsasser@arm.com } else { 145710393Swendy.elsasser@arm.com if (act_at <= min_act_at) { 145810393Swendy.elsasser@arm.com // reset bank mask if new minimum is found 145910393Swendy.elsasser@arm.com // and either previous minimum could not immediately send ACT 146010393Swendy.elsasser@arm.com if (act_at < min_act_at && min_act_at > curTick()) 146110393Swendy.elsasser@arm.com bank_mask = 0; 146210393Swendy.elsasser@arm.com // set the bit corresponding to the available bank 146310393Swendy.elsasser@arm.com replaceBits(bank_mask, bank_id, bank_id, 1); 146410393Swendy.elsasser@arm.com min_act_at = act_at; 146510393Swendy.elsasser@arm.com } 146610211Sandreas.hansson@arm.com } 14679967SN/A } 14689967SN/A } 14699967SN/A } 147010211Sandreas.hansson@arm.com 147110393Swendy.elsasser@arm.com // Determine the earliest time when the next burst can issue based 147210393Swendy.elsasser@arm.com // on the current busBusyUntil delay. 147310393Swendy.elsasser@arm.com // Offset by tRCD to correlate with ACT timing variables 147410393Swendy.elsasser@arm.com Tick min_cmd_at = busBusyUntil - tCL - tRCD; 147510393Swendy.elsasser@arm.com 147610393Swendy.elsasser@arm.com // Prioritize same rank accesses that can issue B2B 147710393Swendy.elsasser@arm.com // Only optimize for same ranks when the command type 147810393Swendy.elsasser@arm.com // does not change; do not want to unnecessarily incur tWTR 147910393Swendy.elsasser@arm.com // 148010393Swendy.elsasser@arm.com // Resulting FCFS prioritization Order is: 148110393Swendy.elsasser@arm.com // 1) Commands that access the same rank as previous burst 148210393Swendy.elsasser@arm.com // and can prep the bank seamlessly. 148310393Swendy.elsasser@arm.com // 2) Commands (any rank) with earliest bank prep 148410393Swendy.elsasser@arm.com if (!switched_cmd_type && same_rank_match && 148510393Swendy.elsasser@arm.com min_act_at_same_rank <= min_cmd_at) { 148610393Swendy.elsasser@arm.com bank_mask = bank_mask_same_rank; 148710393Swendy.elsasser@arm.com } 148810393Swendy.elsasser@arm.com 14899967SN/A return bank_mask; 14909967SN/A} 14919967SN/A 14929243SN/Avoid 149310146Sandreas.hansson@arm.comDRAMCtrl::processRefreshEvent() 14949243SN/A{ 149510207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 149610207Sandreas.hansson@arm.com if (refreshState == REF_IDLE) { 149710207Sandreas.hansson@arm.com // remember when the refresh is due 149810207Sandreas.hansson@arm.com refreshDueAt = curTick(); 14999243SN/A 150010207Sandreas.hansson@arm.com // proceed to drain 150110207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 15029243SN/A 150310207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 150410207Sandreas.hansson@arm.com } 150510207Sandreas.hansson@arm.com 150610207Sandreas.hansson@arm.com // let any scheduled read or write go ahead, after which it will 150710207Sandreas.hansson@arm.com // hand control back to this event loop 150810207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 150910207Sandreas.hansson@arm.com if (nextReqEvent.scheduled()) { 151010207Sandreas.hansson@arm.com // hand control over to the request loop until it is 151110207Sandreas.hansson@arm.com // evaluated next 151210207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 151310207Sandreas.hansson@arm.com 151410207Sandreas.hansson@arm.com return; 151510207Sandreas.hansson@arm.com } else { 151610207Sandreas.hansson@arm.com refreshState = REF_PRE; 151710207Sandreas.hansson@arm.com } 151810207Sandreas.hansson@arm.com } 151910207Sandreas.hansson@arm.com 152010207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 152110207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 152210208Sandreas.hansson@arm.com // precharge any active bank if we are not already in the idle 152310208Sandreas.hansson@arm.com // state 152410208Sandreas.hansson@arm.com if (pwrState != PWR_IDLE) { 152510214Sandreas.hansson@arm.com // at the moment, we use a precharge all even if there is 152610214Sandreas.hansson@arm.com // only a single bank open 152710208Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 152810214Sandreas.hansson@arm.com 152910214Sandreas.hansson@arm.com // first determine when we can precharge 153010214Sandreas.hansson@arm.com Tick pre_at = curTick(); 153110214Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 153210214Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 153310214Sandreas.hansson@arm.com // respect both causality and any existing bank 153410214Sandreas.hansson@arm.com // constraints, some banks could already have a 153510214Sandreas.hansson@arm.com // (auto) precharge scheduled 153610214Sandreas.hansson@arm.com pre_at = std::max(banks[i][j].preAllowedAt, pre_at); 153710214Sandreas.hansson@arm.com } 153810214Sandreas.hansson@arm.com } 153910214Sandreas.hansson@arm.com 154010214Sandreas.hansson@arm.com // make sure all banks are precharged, and for those that 154110214Sandreas.hansson@arm.com // already are, update their availability 154210214Sandreas.hansson@arm.com Tick act_allowed_at = pre_at + tRP; 154310214Sandreas.hansson@arm.com 154410208Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 154510208Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 154610208Sandreas.hansson@arm.com if (banks[i][j].openRow != Bank::NO_ROW) { 154710247Sandreas.hansson@arm.com prechargeBank(banks[i][j], pre_at, false); 154810214Sandreas.hansson@arm.com } else { 154910214Sandreas.hansson@arm.com banks[i][j].actAllowedAt = 155010214Sandreas.hansson@arm.com std::max(banks[i][j].actAllowedAt, act_allowed_at); 155110214Sandreas.hansson@arm.com banks[i][j].preAllowedAt = 155210214Sandreas.hansson@arm.com std::max(banks[i][j].preAllowedAt, pre_at); 155310208Sandreas.hansson@arm.com } 155410207Sandreas.hansson@arm.com } 155510247Sandreas.hansson@arm.com 155610247Sandreas.hansson@arm.com // at the moment this affects all ranks 155710432SOmar.Naji@arm.com rankPower[i].powerlib.doCommand(MemCommand::PREA, 0, 155810432SOmar.Naji@arm.com divCeil(pre_at, tCK) - 155910432SOmar.Naji@arm.com timeStampOffset); 156010432SOmar.Naji@arm.com 156110432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PREA,0,%d\n", divCeil(pre_at, tCK) - 156210432SOmar.Naji@arm.com timeStampOffset, i); 156310207Sandreas.hansson@arm.com } 156410208Sandreas.hansson@arm.com } else { 156510208Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 156610208Sandreas.hansson@arm.com 156710208Sandreas.hansson@arm.com // go ahead and kick the power state machine into gear if 156810208Sandreas.hansson@arm.com // we are already idle 156910208Sandreas.hansson@arm.com schedulePowerEvent(PWR_REF, curTick()); 15709975SN/A } 15719975SN/A 157210208Sandreas.hansson@arm.com refreshState = REF_RUN; 157310208Sandreas.hansson@arm.com assert(numBanksActive == 0); 15749243SN/A 157510208Sandreas.hansson@arm.com // wait for all banks to be precharged, at which point the 157610208Sandreas.hansson@arm.com // power state machine will transition to the idle state, and 157710208Sandreas.hansson@arm.com // automatically move to a refresh, at that point it will also 157810208Sandreas.hansson@arm.com // call this method to get the refresh event loop going again 157910207Sandreas.hansson@arm.com return; 158010207Sandreas.hansson@arm.com } 158110207Sandreas.hansson@arm.com 158210207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 158310207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 158410207Sandreas.hansson@arm.com // should never get here with any banks active 158510207Sandreas.hansson@arm.com assert(numBanksActive == 0); 158610208Sandreas.hansson@arm.com assert(pwrState == PWR_REF); 158710207Sandreas.hansson@arm.com 158810211Sandreas.hansson@arm.com Tick ref_done_at = curTick() + tRFC; 158910207Sandreas.hansson@arm.com 159010207Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 159110207Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 159210211Sandreas.hansson@arm.com banks[i][j].actAllowedAt = ref_done_at; 159310207Sandreas.hansson@arm.com } 159410247Sandreas.hansson@arm.com 159510247Sandreas.hansson@arm.com // at the moment this affects all ranks 159610432SOmar.Naji@arm.com rankPower[i].powerlib.doCommand(MemCommand::REF, 0, 159710432SOmar.Naji@arm.com divCeil(curTick(), tCK) - 159810432SOmar.Naji@arm.com timeStampOffset); 159910432SOmar.Naji@arm.com 160010432SOmar.Naji@arm.com // at the moment sort the list of commands and update the counters 160110432SOmar.Naji@arm.com // for DRAMPower libray when doing a refresh 160210432SOmar.Naji@arm.com sort(rankPower[i].powerlib.cmdList.begin(), 160310432SOmar.Naji@arm.com rankPower[i].powerlib.cmdList.end(), DRAMCtrl::sortTime); 160410432SOmar.Naji@arm.com 160510432SOmar.Naji@arm.com // update the counters for DRAMPower, passing false to 160610432SOmar.Naji@arm.com // indicate that this is not the last command in the 160710432SOmar.Naji@arm.com // list. DRAMPower requires this information for the 160810432SOmar.Naji@arm.com // correct calculation of the background energy at the end 160910432SOmar.Naji@arm.com // of the simulation. Ideally we would want to call this 161010432SOmar.Naji@arm.com // function with true once at the end of the 161110432SOmar.Naji@arm.com // simulation. However, the discarded energy is extremly 161210432SOmar.Naji@arm.com // small and does not effect the final results. 161310432SOmar.Naji@arm.com rankPower[i].powerlib.updateCounters(false); 161410432SOmar.Naji@arm.com 161510432SOmar.Naji@arm.com // call the energy function 161610432SOmar.Naji@arm.com rankPower[i].powerlib.calcEnergy(); 161710432SOmar.Naji@arm.com 161810432SOmar.Naji@arm.com // Update the stats 161910432SOmar.Naji@arm.com updatePowerStats(i); 162010432SOmar.Naji@arm.com 162110432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), tCK) - 162210432SOmar.Naji@arm.com timeStampOffset, i); 162310207Sandreas.hansson@arm.com } 162410207Sandreas.hansson@arm.com 162510207Sandreas.hansson@arm.com // make sure we did not wait so long that we cannot make up 162610207Sandreas.hansson@arm.com // for it 162710211Sandreas.hansson@arm.com if (refreshDueAt + tREFI < ref_done_at) { 162810207Sandreas.hansson@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 162910207Sandreas.hansson@arm.com } 163010207Sandreas.hansson@arm.com 163110207Sandreas.hansson@arm.com // compensate for the delay in actually performing the refresh 163210207Sandreas.hansson@arm.com // when scheduling the next one 163310207Sandreas.hansson@arm.com schedule(refreshEvent, refreshDueAt + tREFI - tRP); 163410207Sandreas.hansson@arm.com 163510208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 163610207Sandreas.hansson@arm.com 163710208Sandreas.hansson@arm.com // move to the idle power state once the refresh is done, this 163810208Sandreas.hansson@arm.com // will also move the refresh state machine to the refresh 163910208Sandreas.hansson@arm.com // idle state 164010211Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, ref_done_at); 164110207Sandreas.hansson@arm.com 164210208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n", 164310211Sandreas.hansson@arm.com ref_done_at, refreshDueAt + tREFI); 164410208Sandreas.hansson@arm.com } 164510208Sandreas.hansson@arm.com} 164610208Sandreas.hansson@arm.com 164710208Sandreas.hansson@arm.comvoid 164810208Sandreas.hansson@arm.comDRAMCtrl::schedulePowerEvent(PowerState pwr_state, Tick tick) 164910208Sandreas.hansson@arm.com{ 165010208Sandreas.hansson@arm.com // respect causality 165110208Sandreas.hansson@arm.com assert(tick >= curTick()); 165210208Sandreas.hansson@arm.com 165310208Sandreas.hansson@arm.com if (!powerEvent.scheduled()) { 165410208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 165510208Sandreas.hansson@arm.com tick, pwr_state); 165610208Sandreas.hansson@arm.com 165710208Sandreas.hansson@arm.com // insert the new transition 165810208Sandreas.hansson@arm.com pwrStateTrans = pwr_state; 165910208Sandreas.hansson@arm.com 166010208Sandreas.hansson@arm.com schedule(powerEvent, tick); 166110208Sandreas.hansson@arm.com } else { 166210208Sandreas.hansson@arm.com panic("Scheduled power event at %llu to state %d, " 166310208Sandreas.hansson@arm.com "with scheduled event at %llu to %d\n", tick, pwr_state, 166410208Sandreas.hansson@arm.com powerEvent.when(), pwrStateTrans); 166510208Sandreas.hansson@arm.com } 166610208Sandreas.hansson@arm.com} 166710208Sandreas.hansson@arm.com 166810208Sandreas.hansson@arm.comvoid 166910208Sandreas.hansson@arm.comDRAMCtrl::processPowerEvent() 167010208Sandreas.hansson@arm.com{ 167110208Sandreas.hansson@arm.com // remember where we were, and for how long 167210208Sandreas.hansson@arm.com Tick duration = curTick() - pwrStateTick; 167310208Sandreas.hansson@arm.com PowerState prev_state = pwrState; 167410208Sandreas.hansson@arm.com 167510208Sandreas.hansson@arm.com // update the accounting 167610208Sandreas.hansson@arm.com pwrStateTime[prev_state] += duration; 167710208Sandreas.hansson@arm.com 167810208Sandreas.hansson@arm.com pwrState = pwrStateTrans; 167910208Sandreas.hansson@arm.com pwrStateTick = curTick(); 168010208Sandreas.hansson@arm.com 168110208Sandreas.hansson@arm.com if (pwrState == PWR_IDLE) { 168210208Sandreas.hansson@arm.com DPRINTF(DRAMState, "All banks precharged\n"); 168310208Sandreas.hansson@arm.com 168410208Sandreas.hansson@arm.com // if we were refreshing, make sure we start scheduling requests again 168510208Sandreas.hansson@arm.com if (prev_state == PWR_REF) { 168610208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 168710208Sandreas.hansson@arm.com assert(pwrState == PWR_IDLE); 168810208Sandreas.hansson@arm.com 168910208Sandreas.hansson@arm.com // kick things into action again 169010208Sandreas.hansson@arm.com refreshState = REF_IDLE; 169110208Sandreas.hansson@arm.com assert(!nextReqEvent.scheduled()); 169210208Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 169310208Sandreas.hansson@arm.com } else { 169410208Sandreas.hansson@arm.com assert(prev_state == PWR_ACT); 169510208Sandreas.hansson@arm.com 169610208Sandreas.hansson@arm.com // if we have a pending refresh, and are now moving to 169710208Sandreas.hansson@arm.com // the idle state, direclty transition to a refresh 169810208Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 169910208Sandreas.hansson@arm.com // there should be nothing waiting at this point 170010208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 170110208Sandreas.hansson@arm.com 170210208Sandreas.hansson@arm.com // update the state in zero time and proceed below 170310208Sandreas.hansson@arm.com pwrState = PWR_REF; 170410208Sandreas.hansson@arm.com } 170510208Sandreas.hansson@arm.com } 170610208Sandreas.hansson@arm.com } 170710208Sandreas.hansson@arm.com 170810208Sandreas.hansson@arm.com // we transition to the refresh state, let the refresh state 170910208Sandreas.hansson@arm.com // machine know of this state update and let it deal with the 171010208Sandreas.hansson@arm.com // scheduling of the next power state transition as well as the 171110208Sandreas.hansson@arm.com // following refresh 171210208Sandreas.hansson@arm.com if (pwrState == PWR_REF) { 171310208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refreshing\n"); 171410208Sandreas.hansson@arm.com // kick the refresh event loop into action again, and that 171510208Sandreas.hansson@arm.com // in turn will schedule a transition to the idle power 171610208Sandreas.hansson@arm.com // state once the refresh is done 171710208Sandreas.hansson@arm.com assert(refreshState == REF_RUN); 171810208Sandreas.hansson@arm.com processRefreshEvent(); 171910207Sandreas.hansson@arm.com } 17209243SN/A} 17219243SN/A 17229243SN/Avoid 172310432SOmar.Naji@arm.comDRAMCtrl::updatePowerStats(uint8_t rank) 172410432SOmar.Naji@arm.com{ 172510432SOmar.Naji@arm.com // Get the energy and power from DRAMPower 172610432SOmar.Naji@arm.com Data::MemoryPowerModel::Energy energy = 172710432SOmar.Naji@arm.com rankPower[rank].powerlib.getEnergy(); 172810432SOmar.Naji@arm.com Data::MemoryPowerModel::Power power = 172910432SOmar.Naji@arm.com rankPower[rank].powerlib.getPower(); 173010432SOmar.Naji@arm.com 173110432SOmar.Naji@arm.com actEnergy[rank] = energy.act_energy * devicesPerRank; 173210432SOmar.Naji@arm.com preEnergy[rank] = energy.pre_energy * devicesPerRank; 173310432SOmar.Naji@arm.com readEnergy[rank] = energy.read_energy * devicesPerRank; 173410432SOmar.Naji@arm.com writeEnergy[rank] = energy.write_energy * devicesPerRank; 173510432SOmar.Naji@arm.com refreshEnergy[rank] = energy.ref_energy * devicesPerRank; 173610432SOmar.Naji@arm.com actBackEnergy[rank] = energy.act_stdby_energy * devicesPerRank; 173710432SOmar.Naji@arm.com preBackEnergy[rank] = energy.pre_stdby_energy * devicesPerRank; 173810432SOmar.Naji@arm.com totalEnergy[rank] = energy.total_energy * devicesPerRank; 173910432SOmar.Naji@arm.com averagePower[rank] = power.average_power * devicesPerRank; 174010432SOmar.Naji@arm.com} 174110432SOmar.Naji@arm.com 174210432SOmar.Naji@arm.comvoid 174310146Sandreas.hansson@arm.comDRAMCtrl::regStats() 17449243SN/A{ 17459243SN/A using namespace Stats; 17469243SN/A 17479243SN/A AbstractMemory::regStats(); 17489243SN/A 17499243SN/A readReqs 17509243SN/A .name(name() + ".readReqs") 17519977SN/A .desc("Number of read requests accepted"); 17529243SN/A 17539243SN/A writeReqs 17549243SN/A .name(name() + ".writeReqs") 17559977SN/A .desc("Number of write requests accepted"); 17569831SN/A 17579831SN/A readBursts 17589831SN/A .name(name() + ".readBursts") 17599977SN/A .desc("Number of DRAM read bursts, " 17609977SN/A "including those serviced by the write queue"); 17619831SN/A 17629831SN/A writeBursts 17639831SN/A .name(name() + ".writeBursts") 17649977SN/A .desc("Number of DRAM write bursts, " 17659977SN/A "including those merged in the write queue"); 17669243SN/A 17679243SN/A servicedByWrQ 17689243SN/A .name(name() + ".servicedByWrQ") 17699977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 17709977SN/A 17719977SN/A mergedWrBursts 17729977SN/A .name(name() + ".mergedWrBursts") 17739977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 17749243SN/A 17759243SN/A neitherReadNorWrite 17769977SN/A .name(name() + ".neitherReadNorWriteReqs") 17779977SN/A .desc("Number of requests that are neither read nor write"); 17789243SN/A 17799977SN/A perBankRdBursts 17809243SN/A .init(banksPerRank * ranksPerChannel) 17819977SN/A .name(name() + ".perBankRdBursts") 17829977SN/A .desc("Per bank write bursts"); 17839243SN/A 17849977SN/A perBankWrBursts 17859243SN/A .init(banksPerRank * ranksPerChannel) 17869977SN/A .name(name() + ".perBankWrBursts") 17879977SN/A .desc("Per bank write bursts"); 17889243SN/A 17899243SN/A avgRdQLen 17909243SN/A .name(name() + ".avgRdQLen") 17919977SN/A .desc("Average read queue length when enqueuing") 17929243SN/A .precision(2); 17939243SN/A 17949243SN/A avgWrQLen 17959243SN/A .name(name() + ".avgWrQLen") 17969977SN/A .desc("Average write queue length when enqueuing") 17979243SN/A .precision(2); 17989243SN/A 17999243SN/A totQLat 18009243SN/A .name(name() + ".totQLat") 18019977SN/A .desc("Total ticks spent queuing"); 18029243SN/A 18039243SN/A totBusLat 18049243SN/A .name(name() + ".totBusLat") 18059977SN/A .desc("Total ticks spent in databus transfers"); 18069243SN/A 18079243SN/A totMemAccLat 18089243SN/A .name(name() + ".totMemAccLat") 18099977SN/A .desc("Total ticks spent from burst creation until serviced " 18109977SN/A "by the DRAM"); 18119243SN/A 18129243SN/A avgQLat 18139243SN/A .name(name() + ".avgQLat") 18149977SN/A .desc("Average queueing delay per DRAM burst") 18159243SN/A .precision(2); 18169243SN/A 18179831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 18189243SN/A 18199243SN/A avgBusLat 18209243SN/A .name(name() + ".avgBusLat") 18219977SN/A .desc("Average bus latency per DRAM burst") 18229243SN/A .precision(2); 18239243SN/A 18249831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 18259243SN/A 18269243SN/A avgMemAccLat 18279243SN/A .name(name() + ".avgMemAccLat") 18289977SN/A .desc("Average memory access latency per DRAM burst") 18299243SN/A .precision(2); 18309243SN/A 18319831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 18329243SN/A 18339243SN/A numRdRetry 18349243SN/A .name(name() + ".numRdRetry") 18359977SN/A .desc("Number of times read queue was full causing retry"); 18369243SN/A 18379243SN/A numWrRetry 18389243SN/A .name(name() + ".numWrRetry") 18399977SN/A .desc("Number of times write queue was full causing retry"); 18409243SN/A 18419243SN/A readRowHits 18429243SN/A .name(name() + ".readRowHits") 18439243SN/A .desc("Number of row buffer hits during reads"); 18449243SN/A 18459243SN/A writeRowHits 18469243SN/A .name(name() + ".writeRowHits") 18479243SN/A .desc("Number of row buffer hits during writes"); 18489243SN/A 18499243SN/A readRowHitRate 18509243SN/A .name(name() + ".readRowHitRate") 18519243SN/A .desc("Row buffer hit rate for reads") 18529243SN/A .precision(2); 18539243SN/A 18549831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 18559243SN/A 18569243SN/A writeRowHitRate 18579243SN/A .name(name() + ".writeRowHitRate") 18589243SN/A .desc("Row buffer hit rate for writes") 18599243SN/A .precision(2); 18609243SN/A 18619977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 18629243SN/A 18639243SN/A readPktSize 18649831SN/A .init(ceilLog2(burstSize) + 1) 18659243SN/A .name(name() + ".readPktSize") 18669977SN/A .desc("Read request sizes (log2)"); 18679243SN/A 18689243SN/A writePktSize 18699831SN/A .init(ceilLog2(burstSize) + 1) 18709243SN/A .name(name() + ".writePktSize") 18719977SN/A .desc("Write request sizes (log2)"); 18729243SN/A 18739243SN/A rdQLenPdf 18749567SN/A .init(readBufferSize) 18759243SN/A .name(name() + ".rdQLenPdf") 18769243SN/A .desc("What read queue length does an incoming req see"); 18779243SN/A 18789243SN/A wrQLenPdf 18799567SN/A .init(writeBufferSize) 18809243SN/A .name(name() + ".wrQLenPdf") 18819243SN/A .desc("What write queue length does an incoming req see"); 18829243SN/A 18839727SN/A bytesPerActivate 188410141SN/A .init(maxAccessesPerRow) 18859727SN/A .name(name() + ".bytesPerActivate") 18869727SN/A .desc("Bytes accessed per row activation") 18879727SN/A .flags(nozero); 18889243SN/A 188910147Sandreas.hansson@arm.com rdPerTurnAround 189010147Sandreas.hansson@arm.com .init(readBufferSize) 189110147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 189210147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 189310147Sandreas.hansson@arm.com .flags(nozero); 189410147Sandreas.hansson@arm.com 189510147Sandreas.hansson@arm.com wrPerTurnAround 189610147Sandreas.hansson@arm.com .init(writeBufferSize) 189710147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 189810147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 189910147Sandreas.hansson@arm.com .flags(nozero); 190010147Sandreas.hansson@arm.com 19019975SN/A bytesReadDRAM 19029975SN/A .name(name() + ".bytesReadDRAM") 19039975SN/A .desc("Total number of bytes read from DRAM"); 19049975SN/A 19059975SN/A bytesReadWrQ 19069975SN/A .name(name() + ".bytesReadWrQ") 19079975SN/A .desc("Total number of bytes read from write queue"); 19089243SN/A 19099243SN/A bytesWritten 19109243SN/A .name(name() + ".bytesWritten") 19119977SN/A .desc("Total number of bytes written to DRAM"); 19129243SN/A 19139977SN/A bytesReadSys 19149977SN/A .name(name() + ".bytesReadSys") 19159977SN/A .desc("Total read bytes from the system interface side"); 19169243SN/A 19179977SN/A bytesWrittenSys 19189977SN/A .name(name() + ".bytesWrittenSys") 19199977SN/A .desc("Total written bytes from the system interface side"); 19209243SN/A 19219243SN/A avgRdBW 19229243SN/A .name(name() + ".avgRdBW") 19239977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 19249243SN/A .precision(2); 19259243SN/A 19269977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 19279243SN/A 19289243SN/A avgWrBW 19299243SN/A .name(name() + ".avgWrBW") 19309977SN/A .desc("Average achieved write bandwidth in MiByte/s") 19319243SN/A .precision(2); 19329243SN/A 19339243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 19349243SN/A 19359977SN/A avgRdBWSys 19369977SN/A .name(name() + ".avgRdBWSys") 19379977SN/A .desc("Average system read bandwidth in MiByte/s") 19389243SN/A .precision(2); 19399243SN/A 19409977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 19419243SN/A 19429977SN/A avgWrBWSys 19439977SN/A .name(name() + ".avgWrBWSys") 19449977SN/A .desc("Average system write bandwidth in MiByte/s") 19459243SN/A .precision(2); 19469243SN/A 19479977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 19489243SN/A 19499243SN/A peakBW 19509243SN/A .name(name() + ".peakBW") 19519977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 19529243SN/A .precision(2); 19539243SN/A 19549831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 19559243SN/A 19569243SN/A busUtil 19579243SN/A .name(name() + ".busUtil") 19589243SN/A .desc("Data bus utilization in percentage") 19599243SN/A .precision(2); 19609243SN/A 19619243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 19629243SN/A 19639243SN/A totGap 19649243SN/A .name(name() + ".totGap") 19659243SN/A .desc("Total gap between requests"); 19669243SN/A 19679243SN/A avgGap 19689243SN/A .name(name() + ".avgGap") 19699243SN/A .desc("Average gap between requests") 19709243SN/A .precision(2); 19719243SN/A 19729243SN/A avgGap = totGap / (readReqs + writeReqs); 19739975SN/A 19749975SN/A // Stats for DRAM Power calculation based on Micron datasheet 19759975SN/A busUtilRead 19769975SN/A .name(name() + ".busUtilRead") 19779975SN/A .desc("Data bus utilization in percentage for reads") 19789975SN/A .precision(2); 19799975SN/A 19809975SN/A busUtilRead = avgRdBW / peakBW * 100; 19819975SN/A 19829975SN/A busUtilWrite 19839975SN/A .name(name() + ".busUtilWrite") 19849975SN/A .desc("Data bus utilization in percentage for writes") 19859975SN/A .precision(2); 19869975SN/A 19879975SN/A busUtilWrite = avgWrBW / peakBW * 100; 19889975SN/A 19899975SN/A pageHitRate 19909975SN/A .name(name() + ".pageHitRate") 19919975SN/A .desc("Row buffer hit rate, read and write combined") 19929975SN/A .precision(2); 19939975SN/A 19949977SN/A pageHitRate = (writeRowHits + readRowHits) / 19959977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 19969975SN/A 199710208Sandreas.hansson@arm.com pwrStateTime 199810208Sandreas.hansson@arm.com .init(5) 199910208Sandreas.hansson@arm.com .name(name() + ".memoryStateTime") 200010208Sandreas.hansson@arm.com .desc("Time in different power states"); 200110208Sandreas.hansson@arm.com pwrStateTime.subname(0, "IDLE"); 200210208Sandreas.hansson@arm.com pwrStateTime.subname(1, "REF"); 200310208Sandreas.hansson@arm.com pwrStateTime.subname(2, "PRE_PDN"); 200410208Sandreas.hansson@arm.com pwrStateTime.subname(3, "ACT"); 200510208Sandreas.hansson@arm.com pwrStateTime.subname(4, "ACT_PDN"); 200610432SOmar.Naji@arm.com 200710432SOmar.Naji@arm.com actEnergy 200810432SOmar.Naji@arm.com .init(ranksPerChannel) 200910432SOmar.Naji@arm.com .name(name() + ".actEnergy") 201010432SOmar.Naji@arm.com .desc("Energy for activate commands per rank (pJ)"); 201110432SOmar.Naji@arm.com 201210432SOmar.Naji@arm.com preEnergy 201310432SOmar.Naji@arm.com .init(ranksPerChannel) 201410432SOmar.Naji@arm.com .name(name() + ".preEnergy") 201510432SOmar.Naji@arm.com .desc("Energy for precharge commands per rank (pJ)"); 201610432SOmar.Naji@arm.com 201710432SOmar.Naji@arm.com readEnergy 201810432SOmar.Naji@arm.com .init(ranksPerChannel) 201910432SOmar.Naji@arm.com .name(name() + ".readEnergy") 202010432SOmar.Naji@arm.com .desc("Energy for read commands per rank (pJ)"); 202110432SOmar.Naji@arm.com 202210432SOmar.Naji@arm.com writeEnergy 202310432SOmar.Naji@arm.com .init(ranksPerChannel) 202410432SOmar.Naji@arm.com .name(name() + ".writeEnergy") 202510432SOmar.Naji@arm.com .desc("Energy for write commands per rank (pJ)"); 202610432SOmar.Naji@arm.com 202710432SOmar.Naji@arm.com refreshEnergy 202810432SOmar.Naji@arm.com .init(ranksPerChannel) 202910432SOmar.Naji@arm.com .name(name() + ".refreshEnergy") 203010432SOmar.Naji@arm.com .desc("Energy for refresh commands per rank (pJ)"); 203110432SOmar.Naji@arm.com 203210432SOmar.Naji@arm.com actBackEnergy 203310432SOmar.Naji@arm.com .init(ranksPerChannel) 203410432SOmar.Naji@arm.com .name(name() + ".actBackEnergy") 203510432SOmar.Naji@arm.com .desc("Energy for active background per rank (pJ)"); 203610432SOmar.Naji@arm.com 203710432SOmar.Naji@arm.com preBackEnergy 203810432SOmar.Naji@arm.com .init(ranksPerChannel) 203910432SOmar.Naji@arm.com .name(name() + ".preBackEnergy") 204010432SOmar.Naji@arm.com .desc("Energy for precharge background per rank (pJ)"); 204110432SOmar.Naji@arm.com 204210432SOmar.Naji@arm.com totalEnergy 204310432SOmar.Naji@arm.com .init(ranksPerChannel) 204410432SOmar.Naji@arm.com .name(name() + ".totalEnergy") 204510432SOmar.Naji@arm.com .desc("Total energy per rank (pJ)"); 204610432SOmar.Naji@arm.com 204710432SOmar.Naji@arm.com averagePower 204810432SOmar.Naji@arm.com .init(ranksPerChannel) 204910432SOmar.Naji@arm.com .name(name() + ".averagePower") 205010432SOmar.Naji@arm.com .desc("Core power per rank (mW)"); 20519243SN/A} 20529243SN/A 20539243SN/Avoid 205410146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 20559243SN/A{ 20569243SN/A // rely on the abstract memory 20579243SN/A functionalAccess(pkt); 20589243SN/A} 20599243SN/A 20609294SN/ABaseSlavePort& 206110146Sandreas.hansson@arm.comDRAMCtrl::getSlavePort(const string &if_name, PortID idx) 20629243SN/A{ 20639243SN/A if (if_name != "port") { 20649243SN/A return MemObject::getSlavePort(if_name, idx); 20659243SN/A } else { 20669243SN/A return port; 20679243SN/A } 20689243SN/A} 20699243SN/A 20709243SN/Aunsigned int 207110146Sandreas.hansson@arm.comDRAMCtrl::drain(DrainManager *dm) 20729243SN/A{ 20739342SN/A unsigned int count = port.drain(dm); 20749243SN/A 20759243SN/A // if there is anything in any of our internal queues, keep track 20769243SN/A // of that as well 20779567SN/A if (!(writeQueue.empty() && readQueue.empty() && 20789567SN/A respQueue.empty())) { 20799352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 20809567SN/A " resp: %d\n", writeQueue.size(), readQueue.size(), 20819567SN/A respQueue.size()); 20829243SN/A ++count; 20839342SN/A drainManager = dm; 208410206Sandreas.hansson@arm.com 20859352SN/A // the only part that is not drained automatically over time 208610206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 208710206Sandreas.hansson@arm.com if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 208810206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 208910206Sandreas.hansson@arm.com } 20909243SN/A } 20919243SN/A 20929243SN/A if (count) 20939342SN/A setDrainState(Drainable::Draining); 20949243SN/A else 20959342SN/A setDrainState(Drainable::Drained); 20969243SN/A return count; 20979243SN/A} 20989243SN/A 209910146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 21009243SN/A : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 21019243SN/A memory(_memory) 21029243SN/A{ } 21039243SN/A 21049243SN/AAddrRangeList 210510146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 21069243SN/A{ 21079243SN/A AddrRangeList ranges; 21089243SN/A ranges.push_back(memory.getAddrRange()); 21099243SN/A return ranges; 21109243SN/A} 21119243SN/A 21129243SN/Avoid 211310146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 21149243SN/A{ 21159243SN/A pkt->pushLabel(memory.name()); 21169243SN/A 21179243SN/A if (!queue.checkFunctional(pkt)) { 21189243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 21199243SN/A // calls recvAtomic() and throws away the latency; we can save a 21209243SN/A // little here by just not calculating the latency. 21219243SN/A memory.recvFunctional(pkt); 21229243SN/A } 21239243SN/A 21249243SN/A pkt->popLabel(); 21259243SN/A} 21269243SN/A 21279243SN/ATick 212810146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 21299243SN/A{ 21309243SN/A return memory.recvAtomic(pkt); 21319243SN/A} 21329243SN/A 21339243SN/Abool 213410146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 21359243SN/A{ 21369243SN/A // pass it to the memory controller 21379243SN/A return memory.recvTimingReq(pkt); 21389243SN/A} 21399243SN/A 214010146Sandreas.hansson@arm.comDRAMCtrl* 214110146Sandreas.hansson@arm.comDRAMCtrlParams::create() 21429243SN/A{ 214310146Sandreas.hansson@arm.com return new DRAMCtrl(this); 21449243SN/A} 2145