dram_ctrl.cc revision 10466
19243SN/A/* 210206Sandreas.hansson@arm.com * Copyright (c) 2010-2014 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 439243SN/A */ 449243SN/A 4510146Sandreas.hansson@arm.com#include "base/bitfield.hh" 469356SN/A#include "base/trace.hh" 4710146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 4810247Sandreas.hansson@arm.com#include "debug/DRAMPower.hh" 4910208Sandreas.hansson@arm.com#include "debug/DRAMState.hh" 509352SN/A#include "debug/Drain.hh" 5110146Sandreas.hansson@arm.com#include "mem/dram_ctrl.hh" 529814SN/A#include "sim/system.hh" 539243SN/A 549243SN/Ausing namespace std; 5510432SOmar.Naji@arm.comusing namespace Data; 569243SN/A 5710146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 589243SN/A AbstractMemory(p), 599243SN/A port(name() + ".port", *this), 609243SN/A retryRdReq(false), retryWrReq(false), 6110211Sandreas.hansson@arm.com busState(READ), 6210208Sandreas.hansson@arm.com nextReqEvent(this), respondEvent(this), activateEvent(this), 6310208Sandreas.hansson@arm.com prechargeEvent(this), refreshEvent(this), powerEvent(this), 6410208Sandreas.hansson@arm.com drainManager(NULL), 659831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 669831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 679831SN/A devicesPerRank(p->devices_per_rank), 689831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 699831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 7010140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 7110286Sandreas.hansson@arm.com columnsPerStripe(range.granularity() / burstSize), 729243SN/A ranksPerChannel(p->ranks_per_channel), 7310394Swendy.elsasser@arm.com bankGroupsPerRank(p->bank_groups_per_rank), 7410394Swendy.elsasser@arm.com bankGroupArch(p->bank_groups_per_rank > 0), 759566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 769243SN/A readBufferSize(p->read_buffer_size), 779243SN/A writeBufferSize(p->write_buffer_size), 7810140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 7910140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 8010147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 8110147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 8210393Swendy.elsasser@arm.com tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST), 8310394Swendy.elsasser@arm.com tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), 8410394Swendy.elsasser@arm.com tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 8510394Swendy.elsasser@arm.com tRRD_L(p->tRRD_L), tXAW(p->tXAW), activationLimit(p->activation_limit), 869243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 879243SN/A pageMgmt(p->page_policy), 8810141SN/A maxAccessesPerRow(p->max_accesses_per_row), 899726SN/A frontendLatency(p->static_frontend_latency), 909726SN/A backendLatency(p->static_backend_latency), 9110208Sandreas.hansson@arm.com busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE), 9210208Sandreas.hansson@arm.com pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), prevArrival(0), 9310393Swendy.elsasser@arm.com nextReqTime(0), pwrStateTick(0), numBanksActive(0), 9410432SOmar.Naji@arm.com activeRank(0), timeStampOffset(0) 959243SN/A{ 969243SN/A // create the bank states based on the dimensions of the ranks and 979243SN/A // banks 989243SN/A banks.resize(ranksPerChannel); 9910432SOmar.Naji@arm.com 10010432SOmar.Naji@arm.com //create list of drampower objects. For each rank 1 drampower instance. 10110432SOmar.Naji@arm.com for (int i = 0; i < ranksPerChannel; i++) { 10210432SOmar.Naji@arm.com DRAMPower drampower = DRAMPower(p, false); 10310432SOmar.Naji@arm.com rankPower.emplace_back(drampower); 10410432SOmar.Naji@arm.com } 10510432SOmar.Naji@arm.com 1069969SN/A actTicks.resize(ranksPerChannel); 1079243SN/A for (size_t c = 0; c < ranksPerChannel; ++c) { 1089243SN/A banks[c].resize(banksPerRank); 1099969SN/A actTicks[c].resize(activationLimit, 0); 1109243SN/A } 1119243SN/A 11210246Sandreas.hansson@arm.com // set the bank indices 11310246Sandreas.hansson@arm.com for (int r = 0; r < ranksPerChannel; r++) { 11410246Sandreas.hansson@arm.com for (int b = 0; b < banksPerRank; b++) { 11510246Sandreas.hansson@arm.com banks[r][b].rank = r; 11610246Sandreas.hansson@arm.com banks[r][b].bank = b; 11710394Swendy.elsasser@arm.com if (bankGroupArch) { 11810394Swendy.elsasser@arm.com // Simply assign lower bits to bank group in order to 11910394Swendy.elsasser@arm.com // rotate across bank groups as banks are incremented 12010394Swendy.elsasser@arm.com // e.g. with 4 banks per bank group and 16 banks total: 12110394Swendy.elsasser@arm.com // banks 0,4,8,12 are in bank group 0 12210394Swendy.elsasser@arm.com // banks 1,5,9,13 are in bank group 1 12310394Swendy.elsasser@arm.com // banks 2,6,10,14 are in bank group 2 12410394Swendy.elsasser@arm.com // banks 3,7,11,15 are in bank group 3 12510394Swendy.elsasser@arm.com banks[r][b].bankgr = b % bankGroupsPerRank; 12610394Swendy.elsasser@arm.com } else { 12710394Swendy.elsasser@arm.com // No bank groups; simply assign to bank number 12810394Swendy.elsasser@arm.com banks[r][b].bankgr = b; 12910394Swendy.elsasser@arm.com } 13010246Sandreas.hansson@arm.com } 13110246Sandreas.hansson@arm.com } 13210246Sandreas.hansson@arm.com 13310140SN/A // perform a basic check of the write thresholds 13410140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 13510140SN/A fatal("Write buffer low threshold %d must be smaller than the " 13610140SN/A "high threshold %d\n", p->write_low_thresh_perc, 13710140SN/A p->write_high_thresh_perc); 1389243SN/A 1399243SN/A // determine the rows per bank by looking at the total capacity 1409567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1419243SN/A 1429243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1439243SN/A AbstractMemory::size()); 1449831SN/A 1459831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1469831SN/A rowBufferSize, columnsPerRowBuffer); 1479831SN/A 1489831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1499243SN/A 15010286Sandreas.hansson@arm.com // a bit of sanity checks on the interleaving 1519566SN/A if (range.interleaved()) { 1529566SN/A if (channels != range.stripes()) 15310143SN/A fatal("%s has %d interleaved address stripes but %d channel(s)\n", 1549566SN/A name(), range.stripes(), channels); 1559566SN/A 15610136SN/A if (addrMapping == Enums::RoRaBaChCo) { 1579831SN/A if (rowBufferSize != range.granularity()) { 15810286Sandreas.hansson@arm.com fatal("Channel interleaving of %s doesn't match RoRaBaChCo " 15910136SN/A "address map\n", name()); 1609566SN/A } 16110286Sandreas.hansson@arm.com } else if (addrMapping == Enums::RoRaBaCoCh || 16210286Sandreas.hansson@arm.com addrMapping == Enums::RoCoRaBaCh) { 16310286Sandreas.hansson@arm.com // for the interleavings with channel bits in the bottom, 16410286Sandreas.hansson@arm.com // if the system uses a channel striping granularity that 16510286Sandreas.hansson@arm.com // is larger than the DRAM burst size, then map the 16610286Sandreas.hansson@arm.com // sequential accesses within a stripe to a number of 16710286Sandreas.hansson@arm.com // columns in the DRAM, effectively placing some of the 16810286Sandreas.hansson@arm.com // lower-order column bits as the least-significant bits 16910286Sandreas.hansson@arm.com // of the address (above the ones denoting the burst size) 17010286Sandreas.hansson@arm.com assert(columnsPerStripe >= 1); 17110286Sandreas.hansson@arm.com 17210286Sandreas.hansson@arm.com // channel striping has to be done at a granularity that 17310286Sandreas.hansson@arm.com // is equal or larger to a cache line 17410286Sandreas.hansson@arm.com if (system()->cacheLineSize() > range.granularity()) { 17510286Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at least as large " 17610286Sandreas.hansson@arm.com "as the cache line size\n", name()); 1779669SN/A } 17810286Sandreas.hansson@arm.com 17910286Sandreas.hansson@arm.com // ...and equal or smaller than the row-buffer size 18010286Sandreas.hansson@arm.com if (rowBufferSize < range.granularity()) { 18110286Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at most as large " 18210286Sandreas.hansson@arm.com "as the row-buffer size\n", name()); 18310286Sandreas.hansson@arm.com } 18410286Sandreas.hansson@arm.com // this is essentially the check above, so just to be sure 18510286Sandreas.hansson@arm.com assert(columnsPerStripe <= columnsPerRowBuffer); 1869566SN/A } 1879566SN/A } 18810207Sandreas.hansson@arm.com 18910207Sandreas.hansson@arm.com // some basic sanity checks 19010207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 19110207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 19210207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 19310207Sandreas.hansson@arm.com } 19410394Swendy.elsasser@arm.com 19510394Swendy.elsasser@arm.com // basic bank group architecture checks -> 19610394Swendy.elsasser@arm.com if (bankGroupArch) { 19710394Swendy.elsasser@arm.com // must have at least one bank per bank group 19810394Swendy.elsasser@arm.com if (bankGroupsPerRank > banksPerRank) { 19910394Swendy.elsasser@arm.com fatal("banks per rank (%d) must be equal to or larger than " 20010394Swendy.elsasser@arm.com "banks groups per rank (%d)\n", 20110394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 20210394Swendy.elsasser@arm.com } 20310394Swendy.elsasser@arm.com // must have same number of banks in each bank group 20410394Swendy.elsasser@arm.com if ((banksPerRank % bankGroupsPerRank) != 0) { 20510394Swendy.elsasser@arm.com fatal("Banks per rank (%d) must be evenly divisible by bank groups " 20610394Swendy.elsasser@arm.com "per rank (%d) for equal banks per bank group\n", 20710394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 20810394Swendy.elsasser@arm.com } 20910394Swendy.elsasser@arm.com // tCCD_L should be greater than minimal, back-to-back burst delay 21010394Swendy.elsasser@arm.com if (tCCD_L <= tBURST) { 21110394Swendy.elsasser@arm.com fatal("tCCD_L (%d) should be larger than tBURST (%d) when " 21210394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 21310394Swendy.elsasser@arm.com tCCD_L, tBURST, bankGroupsPerRank); 21410394Swendy.elsasser@arm.com } 21510394Swendy.elsasser@arm.com // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay 21610394Swendy.elsasser@arm.com if (tRRD_L <= tRRD) { 21710394Swendy.elsasser@arm.com fatal("tRRD_L (%d) should be larger than tRRD (%d) when " 21810394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 21910394Swendy.elsasser@arm.com tRRD_L, tRRD, bankGroupsPerRank); 22010394Swendy.elsasser@arm.com } 22110394Swendy.elsasser@arm.com } 22210394Swendy.elsasser@arm.com 2239243SN/A} 2249243SN/A 2259243SN/Avoid 22610146Sandreas.hansson@arm.comDRAMCtrl::init() 22710140SN/A{ 22810466Sandreas.hansson@arm.com AbstractMemory::init(); 22910466Sandreas.hansson@arm.com 23010466Sandreas.hansson@arm.com if (!port.isConnected()) { 23110146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 23210140SN/A } else { 23310140SN/A port.sendRangeChange(); 23410140SN/A } 23510140SN/A} 23610140SN/A 23710140SN/Avoid 23810146Sandreas.hansson@arm.comDRAMCtrl::startup() 2399243SN/A{ 24010432SOmar.Naji@arm.com // timestamp offset should be in clock cycles for DRAMPower 24110432SOmar.Naji@arm.com timeStampOffset = divCeil(curTick(), tCK); 24210143SN/A // update the start tick for the precharge accounting to the 24310143SN/A // current tick 24410208Sandreas.hansson@arm.com pwrStateTick = curTick(); 24510143SN/A 24610206Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 24710206Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 24810206Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 24910206Sandreas.hansson@arm.com // start of simulation 25010206Sandreas.hansson@arm.com busBusyUntil = curTick() + tRP + tRCD + tCL; 25110206Sandreas.hansson@arm.com 25210207Sandreas.hansson@arm.com // kick off the refresh, and give ourselves enough time to 25310207Sandreas.hansson@arm.com // precharge 25410207Sandreas.hansson@arm.com schedule(refreshEvent, curTick() + tREFI - tRP); 2559243SN/A} 2569243SN/A 2579243SN/ATick 25810146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 2599243SN/A{ 2609243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 2619243SN/A 2629243SN/A // do the actual memory access and turn the packet into a response 2639243SN/A access(pkt); 2649243SN/A 2659243SN/A Tick latency = 0; 2669243SN/A if (!pkt->memInhibitAsserted() && pkt->hasData()) { 2679243SN/A // this value is not supposed to be accurate, just enough to 2689243SN/A // keep things going, mimic a closed page 2699243SN/A latency = tRP + tRCD + tCL; 2709243SN/A } 2719243SN/A return latency; 2729243SN/A} 2739243SN/A 2749243SN/Abool 27510146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 2769243SN/A{ 2779831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 2789831SN/A readBufferSize, readQueue.size() + respQueue.size(), 2799831SN/A neededEntries); 2809243SN/A 2819831SN/A return 2829831SN/A (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 2839243SN/A} 2849243SN/A 2859243SN/Abool 28610146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 2879243SN/A{ 2889831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 2899831SN/A writeBufferSize, writeQueue.size(), neededEntries); 2909831SN/A return (writeQueue.size() + neededEntries) > writeBufferSize; 2919243SN/A} 2929243SN/A 29310146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 29410146Sandreas.hansson@arm.comDRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 29510143SN/A bool isRead) 2969243SN/A{ 2979669SN/A // decode the address based on the address mapping scheme, with 29810136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 29910136SN/A // channel, respectively 3009243SN/A uint8_t rank; 3019967SN/A uint8_t bank; 30210245Sandreas.hansson@arm.com // use a 64-bit unsigned during the computations as the row is 30310245Sandreas.hansson@arm.com // always the top bits, and check before creating the DRAMPacket 30410245Sandreas.hansson@arm.com uint64_t row; 3059243SN/A 30610286Sandreas.hansson@arm.com // truncate the address to a DRAM burst, which makes it unique to 30710286Sandreas.hansson@arm.com // a specific column, row, bank, rank and channel 3089831SN/A Addr addr = dramPktAddr / burstSize; 3099243SN/A 3109491SN/A // we have removed the lowest order address bits that denote the 3119831SN/A // position within the column 31210136SN/A if (addrMapping == Enums::RoRaBaChCo) { 3139491SN/A // the lowest order bits denote the column to ensure that 3149491SN/A // sequential cache lines occupy the same row 3159831SN/A addr = addr / columnsPerRowBuffer; 3169243SN/A 3179669SN/A // take out the channel part of the address 3189566SN/A addr = addr / channels; 3199566SN/A 3209669SN/A // after the channel bits, get the bank bits to interleave 3219669SN/A // over the banks 3229669SN/A bank = addr % banksPerRank; 3239669SN/A addr = addr / banksPerRank; 3249669SN/A 3259669SN/A // after the bank, we get the rank bits which thus interleaves 3269669SN/A // over the ranks 3279669SN/A rank = addr % ranksPerChannel; 3289669SN/A addr = addr / ranksPerChannel; 3299669SN/A 3309669SN/A // lastly, get the row bits 3319669SN/A row = addr % rowsPerBank; 3329669SN/A addr = addr / rowsPerBank; 33310136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 33410286Sandreas.hansson@arm.com // take out the lower-order column bits 33510286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 33610286Sandreas.hansson@arm.com 3379669SN/A // take out the channel part of the address 3389669SN/A addr = addr / channels; 3399669SN/A 34010286Sandreas.hansson@arm.com // next, the higher-order column bites 34110286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3429669SN/A 3439669SN/A // after the column bits, we get the bank bits to interleave 3449491SN/A // over the banks 3459243SN/A bank = addr % banksPerRank; 3469243SN/A addr = addr / banksPerRank; 3479243SN/A 3489491SN/A // after the bank, we get the rank bits which thus interleaves 3499491SN/A // over the ranks 3509243SN/A rank = addr % ranksPerChannel; 3519243SN/A addr = addr / ranksPerChannel; 3529243SN/A 3539491SN/A // lastly, get the row bits 3549243SN/A row = addr % rowsPerBank; 3559243SN/A addr = addr / rowsPerBank; 35610136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 3579491SN/A // optimise for closed page mode and utilise maximum 3589491SN/A // parallelism of the DRAM (at the cost of power) 3599491SN/A 36010286Sandreas.hansson@arm.com // take out the lower-order column bits 36110286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 36210286Sandreas.hansson@arm.com 3639566SN/A // take out the channel part of the address, not that this has 3649566SN/A // to match with how accesses are interleaved between the 3659566SN/A // controllers in the address mapping 3669566SN/A addr = addr / channels; 3679566SN/A 3689491SN/A // start with the bank bits, as this provides the maximum 3699491SN/A // opportunity for parallelism between requests 3709243SN/A bank = addr % banksPerRank; 3719243SN/A addr = addr / banksPerRank; 3729243SN/A 3739491SN/A // next get the rank bits 3749243SN/A rank = addr % ranksPerChannel; 3759243SN/A addr = addr / ranksPerChannel; 3769243SN/A 37710286Sandreas.hansson@arm.com // next, the higher-order column bites 37810286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3799243SN/A 3809491SN/A // lastly, get the row bits 3819243SN/A row = addr % rowsPerBank; 3829243SN/A addr = addr / rowsPerBank; 3839243SN/A } else 3849243SN/A panic("Unknown address mapping policy chosen!"); 3859243SN/A 3869243SN/A assert(rank < ranksPerChannel); 3879243SN/A assert(bank < banksPerRank); 3889243SN/A assert(row < rowsPerBank); 38910245Sandreas.hansson@arm.com assert(row < Bank::NO_ROW); 3909243SN/A 3919243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 3929831SN/A dramPktAddr, rank, bank, row); 3939243SN/A 3949243SN/A // create the corresponding DRAM packet with the entry time and 3959567SN/A // ready time set to the current tick, the latter will be updated 3969567SN/A // later 3979967SN/A uint16_t bank_id = banksPerRank * rank + bank; 3989967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 3999967SN/A size, banks[rank][bank]); 4009243SN/A} 4019243SN/A 4029243SN/Avoid 40310146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 4049243SN/A{ 4059243SN/A // only add to the read queue here. whenever the request is 4069243SN/A // eventually done, set the readyTime, and call schedule() 4079243SN/A assert(!pkt->isWrite()); 4089243SN/A 4099831SN/A assert(pktCount != 0); 4109831SN/A 4119831SN/A // if the request size is larger than burst size, the pkt is split into 4129831SN/A // multiple DRAM packets 4139831SN/A // Note if the pkt starting address is not aligened to burst size, the 4149831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 4159831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 4169831SN/A // check read packets against packets in write queue. 4179243SN/A Addr addr = pkt->getAddr(); 4189831SN/A unsigned pktsServicedByWrQ = 0; 4199831SN/A BurstHelper* burst_helper = NULL; 4209831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4219831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4229831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4239831SN/A readPktSize[ceilLog2(size)]++; 4249831SN/A readBursts++; 4259243SN/A 4269831SN/A // First check write buffer to see if the data is already at 4279831SN/A // the controller 4289831SN/A bool foundInWrQ = false; 4299833SN/A for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) { 4309832SN/A // check if the read is subsumed in the write entry we are 4319832SN/A // looking at 4329832SN/A if ((*i)->addr <= addr && 4339832SN/A (addr + size) <= ((*i)->addr + (*i)->size)) { 4349831SN/A foundInWrQ = true; 4359831SN/A servicedByWrQ++; 4369831SN/A pktsServicedByWrQ++; 4379831SN/A DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 4389831SN/A "write queue\n", addr, size); 4399975SN/A bytesReadWrQ += burstSize; 4409831SN/A break; 4419831SN/A } 4429243SN/A } 4439831SN/A 4449831SN/A // If not found in the write q, make a DRAM packet and 4459831SN/A // push it onto the read queue 4469831SN/A if (!foundInWrQ) { 4479831SN/A 4489831SN/A // Make the burst helper for split packets 4499831SN/A if (pktCount > 1 && burst_helper == NULL) { 4509831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 4519831SN/A "dram requests\n", pkt->getAddr(), pktCount); 4529831SN/A burst_helper = new BurstHelper(pktCount); 4539831SN/A } 4549831SN/A 4559966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 4569831SN/A dram_pkt->burstHelper = burst_helper; 4579831SN/A 4589831SN/A assert(!readQueueFull(1)); 4599831SN/A rdQLenPdf[readQueue.size() + respQueue.size()]++; 4609831SN/A 4619831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 4629831SN/A 4639831SN/A readQueue.push_back(dram_pkt); 4649831SN/A 4659831SN/A // Update stats 4669831SN/A avgRdQLen = readQueue.size() + respQueue.size(); 4679831SN/A } 4689831SN/A 4699831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 4709831SN/A addr = (addr | (burstSize - 1)) + 1; 4719243SN/A } 4729243SN/A 4739831SN/A // If all packets are serviced by write queue, we send the repsonse back 4749831SN/A if (pktsServicedByWrQ == pktCount) { 4759831SN/A accessAndRespond(pkt, frontendLatency); 4769831SN/A return; 4779831SN/A } 4789243SN/A 4799831SN/A // Update how many split packets are serviced by write queue 4809831SN/A if (burst_helper != NULL) 4819831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 4829243SN/A 48310206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 48410206Sandreas.hansson@arm.com // queue, do so now 48510206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 4869567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 4879567SN/A schedule(nextReqEvent, curTick()); 4889243SN/A } 4899243SN/A} 4909243SN/A 4919243SN/Avoid 49210146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 4939243SN/A{ 4949243SN/A // only add to the write queue here. whenever the request is 4959243SN/A // eventually done, set the readyTime, and call schedule() 4969243SN/A assert(pkt->isWrite()); 4979243SN/A 4989831SN/A // if the request size is larger than burst size, the pkt is split into 4999831SN/A // multiple DRAM packets 5009831SN/A Addr addr = pkt->getAddr(); 5019831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 5029831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 5039831SN/A pkt->getAddr() + pkt->getSize()) - addr; 5049831SN/A writePktSize[ceilLog2(size)]++; 5059831SN/A writeBursts++; 5069243SN/A 5079832SN/A // see if we can merge with an existing item in the write 5089838SN/A // queue and keep track of whether we have merged or not so we 5099838SN/A // can stop at that point and also avoid enqueueing a new 5109838SN/A // request 5119832SN/A bool merged = false; 5129832SN/A auto w = writeQueue.begin(); 5139243SN/A 5149832SN/A while(!merged && w != writeQueue.end()) { 5159832SN/A // either of the two could be first, if they are the same 5169832SN/A // it does not matter which way we go 5179832SN/A if ((*w)->addr >= addr) { 5189838SN/A // the existing one starts after the new one, figure 5199838SN/A // out where the new one ends with respect to the 5209838SN/A // existing one 5219832SN/A if ((addr + size) >= ((*w)->addr + (*w)->size)) { 5229832SN/A // check if the existing one is completely 5239832SN/A // subsumed in the new one 5249832SN/A DPRINTF(DRAM, "Merging write covering existing burst\n"); 5259832SN/A merged = true; 5269832SN/A // update both the address and the size 5279832SN/A (*w)->addr = addr; 5289832SN/A (*w)->size = size; 5299832SN/A } else if ((addr + size) >= (*w)->addr && 5309832SN/A ((*w)->addr + (*w)->size - addr) <= burstSize) { 5319832SN/A // the new one is just before or partially 5329832SN/A // overlapping with the existing one, and together 5339832SN/A // they fit within a burst 5349832SN/A DPRINTF(DRAM, "Merging write before existing burst\n"); 5359832SN/A merged = true; 5369832SN/A // the existing queue item needs to be adjusted with 5379832SN/A // respect to both address and size 53810047SN/A (*w)->size = (*w)->addr + (*w)->size - addr; 5399832SN/A (*w)->addr = addr; 5409832SN/A } 5419832SN/A } else { 5429838SN/A // the new one starts after the current one, figure 5439838SN/A // out where the existing one ends with respect to the 5449838SN/A // new one 5459832SN/A if (((*w)->addr + (*w)->size) >= (addr + size)) { 5469832SN/A // check if the new one is completely subsumed in the 5479832SN/A // existing one 5489832SN/A DPRINTF(DRAM, "Merging write into existing burst\n"); 5499832SN/A merged = true; 5509832SN/A // no adjustments necessary 5519832SN/A } else if (((*w)->addr + (*w)->size) >= addr && 5529832SN/A (addr + size - (*w)->addr) <= burstSize) { 5539832SN/A // the existing one is just before or partially 5549832SN/A // overlapping with the new one, and together 5559832SN/A // they fit within a burst 5569832SN/A DPRINTF(DRAM, "Merging write after existing burst\n"); 5579832SN/A merged = true; 5589832SN/A // the address is right, and only the size has 5599832SN/A // to be adjusted 5609832SN/A (*w)->size = addr + size - (*w)->addr; 5619832SN/A } 5629832SN/A } 5639832SN/A ++w; 5649832SN/A } 5659243SN/A 5669832SN/A // if the item was not merged we need to create a new write 5679832SN/A // and enqueue it 5689832SN/A if (!merged) { 5699966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 5709243SN/A 5719832SN/A assert(writeQueue.size() < writeBufferSize); 5729832SN/A wrQLenPdf[writeQueue.size()]++; 5739243SN/A 5749832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 5759831SN/A 5769832SN/A writeQueue.push_back(dram_pkt); 5779831SN/A 5789832SN/A // Update stats 5799832SN/A avgWrQLen = writeQueue.size(); 5809977SN/A } else { 5819977SN/A // keep track of the fact that this burst effectively 5829977SN/A // disappeared as it was merged with an existing one 5839977SN/A mergedWrBursts++; 5849832SN/A } 5859832SN/A 5869831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 5879831SN/A addr = (addr | (burstSize - 1)) + 1; 5889831SN/A } 5899243SN/A 5909243SN/A // we do not wait for the writes to be send to the actual memory, 5919243SN/A // but instead take responsibility for the consistency here and 5929243SN/A // snoop the write queue for any upcoming reads 5939831SN/A // @todo, if a pkt size is larger than burst size, we might need a 5949831SN/A // different front end latency 5959726SN/A accessAndRespond(pkt, frontendLatency); 5969243SN/A 59710206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 59810206Sandreas.hansson@arm.com // queue, do so now 59910206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 60010206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 60110206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 6029243SN/A } 6039243SN/A} 6049243SN/A 6059243SN/Avoid 60610146Sandreas.hansson@arm.comDRAMCtrl::printQs() const { 6079243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 6089833SN/A for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 6099243SN/A DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 6109243SN/A } 6119243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 6129833SN/A for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 6139243SN/A DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 6149243SN/A } 6159243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 6169833SN/A for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 6179243SN/A DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 6189243SN/A } 6199243SN/A} 6209243SN/A 6219243SN/Abool 62210146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 6239243SN/A{ 6249349SN/A /// @todo temporary hack to deal with memory corruption issues until 6259349SN/A /// 4-phase transactions are complete 6269349SN/A for (int x = 0; x < pendingDelete.size(); x++) 6279349SN/A delete pendingDelete[x]; 6289349SN/A pendingDelete.clear(); 6299349SN/A 6309243SN/A // This is where we enter from the outside world 6319567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 6329831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 6339243SN/A 6349567SN/A // simply drop inhibited packets for now 6359567SN/A if (pkt->memInhibitAsserted()) { 63610143SN/A DPRINTF(DRAM, "Inhibited packet -- Dropping it now\n"); 6379567SN/A pendingDelete.push_back(pkt); 6389567SN/A return true; 6399567SN/A } 6409243SN/A 6419243SN/A // Calc avg gap between requests 6429243SN/A if (prevArrival != 0) { 6439243SN/A totGap += curTick() - prevArrival; 6449243SN/A } 6459243SN/A prevArrival = curTick(); 6469243SN/A 6479831SN/A 6489831SN/A // Find out how many dram packets a pkt translates to 6499831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 6509831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 6519831SN/A // multiple dram packets 6529243SN/A unsigned size = pkt->getSize(); 6539831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 6549831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 6559243SN/A 6569243SN/A // check local buffers and do not accept if full 6579243SN/A if (pkt->isRead()) { 6589567SN/A assert(size != 0); 6599831SN/A if (readQueueFull(dram_pkt_count)) { 6609567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 6619243SN/A // remember that we have to retry this port 6629243SN/A retryRdReq = true; 6639243SN/A numRdRetry++; 6649243SN/A return false; 6659243SN/A } else { 6669831SN/A addToReadQueue(pkt, dram_pkt_count); 6679243SN/A readReqs++; 6689977SN/A bytesReadSys += size; 6699243SN/A } 6709243SN/A } else if (pkt->isWrite()) { 6719567SN/A assert(size != 0); 6729831SN/A if (writeQueueFull(dram_pkt_count)) { 6739567SN/A DPRINTF(DRAM, "Write queue full, not accepting\n"); 6749243SN/A // remember that we have to retry this port 6759243SN/A retryWrReq = true; 6769243SN/A numWrRetry++; 6779243SN/A return false; 6789243SN/A } else { 6799831SN/A addToWriteQueue(pkt, dram_pkt_count); 6809243SN/A writeReqs++; 6819977SN/A bytesWrittenSys += size; 6829243SN/A } 6839243SN/A } else { 6849243SN/A DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 6859243SN/A neitherReadNorWrite++; 6869726SN/A accessAndRespond(pkt, 1); 6879243SN/A } 6889243SN/A 6899243SN/A return true; 6909243SN/A} 6919243SN/A 6929243SN/Avoid 69310146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 6949243SN/A{ 6959243SN/A DPRINTF(DRAM, 6969243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 6979243SN/A 6989831SN/A DRAMPacket* dram_pkt = respQueue.front(); 6999243SN/A 7009831SN/A if (dram_pkt->burstHelper) { 7019831SN/A // it is a split packet 7029831SN/A dram_pkt->burstHelper->burstsServiced++; 7039831SN/A if (dram_pkt->burstHelper->burstsServiced == 70410143SN/A dram_pkt->burstHelper->burstCount) { 7059831SN/A // we have now serviced all children packets of a system packet 7069831SN/A // so we can now respond to the requester 7079831SN/A // @todo we probably want to have a different front end and back 7089831SN/A // end latency for split packets 7099831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7109831SN/A delete dram_pkt->burstHelper; 7119831SN/A dram_pkt->burstHelper = NULL; 7129831SN/A } 7139831SN/A } else { 7149831SN/A // it is not a split packet 7159831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7169831SN/A } 7179243SN/A 7189831SN/A delete respQueue.front(); 7199831SN/A respQueue.pop_front(); 7209243SN/A 7219831SN/A if (!respQueue.empty()) { 7229831SN/A assert(respQueue.front()->readyTime >= curTick()); 7239831SN/A assert(!respondEvent.scheduled()); 7249831SN/A schedule(respondEvent, respQueue.front()->readyTime); 7259831SN/A } else { 7269831SN/A // if there is nothing left in any queue, signal a drain 7279831SN/A if (writeQueue.empty() && readQueue.empty() && 7289831SN/A drainManager) { 7299831SN/A drainManager->signalDrainDone(); 7309831SN/A drainManager = NULL; 7319831SN/A } 7329831SN/A } 7339567SN/A 7349831SN/A // We have made a location in the queue available at this point, 7359831SN/A // so if there is a read that was forced to wait, retry now 7369831SN/A if (retryRdReq) { 7379831SN/A retryRdReq = false; 7389831SN/A port.sendRetry(); 7399831SN/A } 7409243SN/A} 7419243SN/A 7429243SN/Avoid 74310393Swendy.elsasser@arm.comDRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue, bool switched_cmd_type) 7449243SN/A{ 74510206Sandreas.hansson@arm.com // This method does the arbitration between requests. The chosen 74610206Sandreas.hansson@arm.com // packet is simply moved to the head of the queue. The other 74710206Sandreas.hansson@arm.com // methods know that this is the place to look. For example, with 74810206Sandreas.hansson@arm.com // FCFS, this method does nothing 74910206Sandreas.hansson@arm.com assert(!queue.empty()); 7509243SN/A 75110206Sandreas.hansson@arm.com if (queue.size() == 1) { 75210206Sandreas.hansson@arm.com DPRINTF(DRAM, "Single request, nothing to do\n"); 7539243SN/A return; 7549243SN/A } 7559243SN/A 7569243SN/A if (memSchedPolicy == Enums::fcfs) { 7579243SN/A // Do nothing, since the correct request is already head 7589243SN/A } else if (memSchedPolicy == Enums::frfcfs) { 75910393Swendy.elsasser@arm.com reorderQueue(queue, switched_cmd_type); 7609243SN/A } else 7619243SN/A panic("No scheduling policy chosen\n"); 7629243SN/A} 7639243SN/A 7649243SN/Avoid 76510393Swendy.elsasser@arm.comDRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue, bool switched_cmd_type) 7669974SN/A{ 7679974SN/A // Only determine this when needed 7689974SN/A uint64_t earliest_banks = 0; 7699974SN/A 7709974SN/A // Search for row hits first, if no row hit is found then schedule the 7719974SN/A // packet to one of the earliest banks available 7729974SN/A bool found_earliest_pkt = false; 77310393Swendy.elsasser@arm.com bool found_prepped_diff_rank_pkt = false; 7749974SN/A auto selected_pkt_it = queue.begin(); 7759974SN/A 7769974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 7779974SN/A DRAMPacket* dram_pkt = *i; 7789974SN/A const Bank& bank = dram_pkt->bankRef; 7799974SN/A // Check if it is a row hit 7809974SN/A if (bank.openRow == dram_pkt->row) { 78110393Swendy.elsasser@arm.com if (dram_pkt->rank == activeRank || switched_cmd_type) { 78210393Swendy.elsasser@arm.com // FCFS within the hits, giving priority to commands 78310393Swendy.elsasser@arm.com // that access the same rank as the previous burst 78410393Swendy.elsasser@arm.com // to minimize bus turnaround delays 78510393Swendy.elsasser@arm.com // Only give rank prioity when command type is not changing 78610393Swendy.elsasser@arm.com DPRINTF(DRAM, "Row buffer hit\n"); 78710393Swendy.elsasser@arm.com selected_pkt_it = i; 78810393Swendy.elsasser@arm.com break; 78910393Swendy.elsasser@arm.com } else if (!found_prepped_diff_rank_pkt) { 79010393Swendy.elsasser@arm.com // found row hit for command on different rank than prev burst 79110393Swendy.elsasser@arm.com selected_pkt_it = i; 79210393Swendy.elsasser@arm.com found_prepped_diff_rank_pkt = true; 79310393Swendy.elsasser@arm.com } 79410393Swendy.elsasser@arm.com } else if (!found_earliest_pkt & !found_prepped_diff_rank_pkt) { 79510393Swendy.elsasser@arm.com // No row hit and 79610393Swendy.elsasser@arm.com // haven't found an entry with a row hit to a new rank 7979974SN/A if (earliest_banks == 0) 79810393Swendy.elsasser@arm.com // Determine entries with earliest bank prep delay 79910393Swendy.elsasser@arm.com // Function will give priority to commands that access the 80010393Swendy.elsasser@arm.com // same rank as previous burst and can prep the bank seamlessly 80110393Swendy.elsasser@arm.com earliest_banks = minBankPrep(queue, switched_cmd_type); 80210211Sandreas.hansson@arm.com 80310393Swendy.elsasser@arm.com // FCFS - Bank is first available bank 80410393Swendy.elsasser@arm.com if (bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) { 8059974SN/A // Remember the packet to be scheduled to one of the earliest 80610211Sandreas.hansson@arm.com // banks available, FCFS amongst the earliest banks 8079974SN/A selected_pkt_it = i; 8089974SN/A found_earliest_pkt = true; 8099974SN/A } 8109974SN/A } 8119974SN/A } 8129974SN/A 8139974SN/A DRAMPacket* selected_pkt = *selected_pkt_it; 8149974SN/A queue.erase(selected_pkt_it); 8159974SN/A queue.push_front(selected_pkt); 8169974SN/A} 8179974SN/A 8189974SN/Avoid 81910146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 8209243SN/A{ 8219243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 8229243SN/A 8239243SN/A bool needsResponse = pkt->needsResponse(); 8249243SN/A // do the actual memory access which also turns the packet into a 8259243SN/A // response 8269243SN/A access(pkt); 8279243SN/A 8289243SN/A // turn packet around to go back to requester if response expected 8299243SN/A if (needsResponse) { 8309243SN/A // access already turned the packet into a response 8319243SN/A assert(pkt->isResponse()); 8329243SN/A 8339549SN/A // @todo someone should pay for this 83410405Sandreas.hansson@arm.com pkt->firstWordDelay = pkt->lastWordDelay = 0; 8359549SN/A 8369726SN/A // queue the packet in the response queue to be sent out after 8379726SN/A // the static latency has passed 8389726SN/A port.schedTimingResp(pkt, curTick() + static_latency); 8399243SN/A } else { 8409587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 8419587SN/A // is still having a pointer to it 8429587SN/A pendingDelete.push_back(pkt); 8439243SN/A } 8449243SN/A 8459243SN/A DPRINTF(DRAM, "Done\n"); 8469243SN/A 8479243SN/A return; 8489243SN/A} 8499243SN/A 8509243SN/Avoid 85110246Sandreas.hansson@arm.comDRAMCtrl::activateBank(Bank& bank, Tick act_tick, uint32_t row) 8529488SN/A{ 85310246Sandreas.hansson@arm.com // get the rank index from the bank 85410246Sandreas.hansson@arm.com uint8_t rank = bank.rank; 85510246Sandreas.hansson@arm.com 8569969SN/A assert(actTicks[rank].size() == activationLimit); 8579488SN/A 8589488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 8599488SN/A 86010207Sandreas.hansson@arm.com // update the open row 86110246Sandreas.hansson@arm.com assert(bank.openRow == Bank::NO_ROW); 86210246Sandreas.hansson@arm.com bank.openRow = row; 86310207Sandreas.hansson@arm.com 86410207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 86510207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 86610207Sandreas.hansson@arm.com // precharge 86710246Sandreas.hansson@arm.com bank.bytesAccessed = 0; 86810246Sandreas.hansson@arm.com bank.rowAccesses = 0; 86910207Sandreas.hansson@arm.com 87010207Sandreas.hansson@arm.com ++numBanksActive; 87110207Sandreas.hansson@arm.com assert(numBanksActive <= banksPerRank * ranksPerChannel); 87210207Sandreas.hansson@arm.com 87310247Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n", 87410247Sandreas.hansson@arm.com bank.bank, bank.rank, act_tick, numBanksActive); 87510247Sandreas.hansson@arm.com 87610432SOmar.Naji@arm.com rankPower[bank.rank].powerlib.doCommand(MemCommand::ACT, bank.bank, 87710432SOmar.Naji@arm.com divCeil(act_tick, tCK) - 87810432SOmar.Naji@arm.com timeStampOffset); 87910432SOmar.Naji@arm.com 88010432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK) - 88110432SOmar.Naji@arm.com timeStampOffset, bank.bank, bank.rank); 8829975SN/A 88310211Sandreas.hansson@arm.com // The next access has to respect tRAS for this bank 88410246Sandreas.hansson@arm.com bank.preAllowedAt = act_tick + tRAS; 88510211Sandreas.hansson@arm.com 88610211Sandreas.hansson@arm.com // Respect the row-to-column command delay 88710394Swendy.elsasser@arm.com bank.colAllowedAt = std::max(act_tick + tRCD, bank.colAllowedAt); 88810211Sandreas.hansson@arm.com 8899971SN/A // start by enforcing tRRD 8909971SN/A for(int i = 0; i < banksPerRank; i++) { 89110210Sandreas.hansson@arm.com // next activate to any bank in this rank must not happen 89210210Sandreas.hansson@arm.com // before tRRD 89310394Swendy.elsasser@arm.com if (bankGroupArch && (bank.bankgr == banks[rank][i].bankgr)) { 89410394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 89510394Swendy.elsasser@arm.com // ACT commands within the same bank group. Use tRRD_L 89610394Swendy.elsasser@arm.com // in this case 89710394Swendy.elsasser@arm.com banks[rank][i].actAllowedAt = std::max(act_tick + tRRD_L, 89810394Swendy.elsasser@arm.com banks[rank][i].actAllowedAt); 89910394Swendy.elsasser@arm.com } else { 90010394Swendy.elsasser@arm.com // use shorter tRRD value when either 90110394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 90210394Swendy.elsasser@arm.com // 2) bank is in a different bank group 90310394Swendy.elsasser@arm.com banks[rank][i].actAllowedAt = std::max(act_tick + tRRD, 90410394Swendy.elsasser@arm.com banks[rank][i].actAllowedAt); 90510394Swendy.elsasser@arm.com } 9069971SN/A } 90710208Sandreas.hansson@arm.com 9089971SN/A // next, we deal with tXAW, if the activation limit is disabled 9099971SN/A // then we are done 9109969SN/A if (actTicks[rank].empty()) 9119824SN/A return; 9129824SN/A 9139488SN/A // sanity check 9149969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 91510210Sandreas.hansson@arm.com panic("Got %d activates in window %d (%llu - %llu) which is smaller " 91610210Sandreas.hansson@arm.com "than %llu\n", activationLimit, act_tick - actTicks[rank].back(), 91710210Sandreas.hansson@arm.com act_tick, actTicks[rank].back(), tXAW); 9189488SN/A } 9199488SN/A 9209488SN/A // shift the times used for the book keeping, the last element 9219488SN/A // (highest index) is the oldest one and hence the lowest value 9229969SN/A actTicks[rank].pop_back(); 9239488SN/A 9249488SN/A // record an new activation (in the future) 9259969SN/A actTicks[rank].push_front(act_tick); 9269488SN/A 9279488SN/A // cannot activate more than X times in time window tXAW, push the 9289488SN/A // next one (the X + 1'st activate) to be tXAW away from the 9299488SN/A // oldest in our window of X 9309969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 9319488SN/A DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate no earlier " 93210210Sandreas.hansson@arm.com "than %llu\n", activationLimit, actTicks[rank].back() + tXAW); 9339488SN/A for(int j = 0; j < banksPerRank; j++) 9349488SN/A // next activate must not happen before end of window 93510210Sandreas.hansson@arm.com banks[rank][j].actAllowedAt = 93610210Sandreas.hansson@arm.com std::max(actTicks[rank].back() + tXAW, 93710210Sandreas.hansson@arm.com banks[rank][j].actAllowedAt); 9389488SN/A } 93910208Sandreas.hansson@arm.com 94010208Sandreas.hansson@arm.com // at the point when this activate takes place, make sure we 94110208Sandreas.hansson@arm.com // transition to the active power state 94210208Sandreas.hansson@arm.com if (!activateEvent.scheduled()) 94310208Sandreas.hansson@arm.com schedule(activateEvent, act_tick); 94410208Sandreas.hansson@arm.com else if (activateEvent.when() > act_tick) 94510208Sandreas.hansson@arm.com // move it sooner in time 94610208Sandreas.hansson@arm.com reschedule(activateEvent, act_tick); 94710208Sandreas.hansson@arm.com} 94810208Sandreas.hansson@arm.com 94910208Sandreas.hansson@arm.comvoid 95010208Sandreas.hansson@arm.comDRAMCtrl::processActivateEvent() 95110208Sandreas.hansson@arm.com{ 95210208Sandreas.hansson@arm.com // we should transition to the active state as soon as any bank is active 95310208Sandreas.hansson@arm.com if (pwrState != PWR_ACT) 95410208Sandreas.hansson@arm.com // note that at this point numBanksActive could be back at 95510208Sandreas.hansson@arm.com // zero again due to a precharge scheduled in the future 95610208Sandreas.hansson@arm.com schedulePowerEvent(PWR_ACT, curTick()); 9579488SN/A} 9589488SN/A 9599488SN/Avoid 96010247Sandreas.hansson@arm.comDRAMCtrl::prechargeBank(Bank& bank, Tick pre_at, bool trace) 96110207Sandreas.hansson@arm.com{ 96210207Sandreas.hansson@arm.com // make sure the bank has an open row 96310207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 96410207Sandreas.hansson@arm.com 96510207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 96610207Sandreas.hansson@arm.com // the page 96710207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 96810207Sandreas.hansson@arm.com 96910207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 97010207Sandreas.hansson@arm.com 97110214Sandreas.hansson@arm.com // no precharge allowed before this one 97210214Sandreas.hansson@arm.com bank.preAllowedAt = pre_at; 97310214Sandreas.hansson@arm.com 97410211Sandreas.hansson@arm.com Tick pre_done_at = pre_at + tRP; 97510211Sandreas.hansson@arm.com 97610211Sandreas.hansson@arm.com bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at); 97710207Sandreas.hansson@arm.com 97810207Sandreas.hansson@arm.com assert(numBanksActive != 0); 97910207Sandreas.hansson@arm.com --numBanksActive; 98010207Sandreas.hansson@arm.com 98110247Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got " 98210247Sandreas.hansson@arm.com "%d active\n", bank.bank, bank.rank, pre_at, numBanksActive); 98310247Sandreas.hansson@arm.com 98410432SOmar.Naji@arm.com if (trace) { 98510207Sandreas.hansson@arm.com 98610432SOmar.Naji@arm.com rankPower[bank.rank].powerlib.doCommand(MemCommand::PRE, bank.bank, 98710432SOmar.Naji@arm.com divCeil(pre_at, tCK) - 98810432SOmar.Naji@arm.com timeStampOffset); 98910432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK) - 99010432SOmar.Naji@arm.com timeStampOffset, bank.bank, bank.rank); 99110432SOmar.Naji@arm.com } 99210208Sandreas.hansson@arm.com // if we look at the current number of active banks we might be 99310208Sandreas.hansson@arm.com // tempted to think the DRAM is now idle, however this can be 99410208Sandreas.hansson@arm.com // undone by an activate that is scheduled to happen before we 99510208Sandreas.hansson@arm.com // would have reached the idle state, so schedule an event and 99610208Sandreas.hansson@arm.com // rather check once we actually make it to the point in time when 99710208Sandreas.hansson@arm.com // the (last) precharge takes place 99810208Sandreas.hansson@arm.com if (!prechargeEvent.scheduled()) 99910211Sandreas.hansson@arm.com schedule(prechargeEvent, pre_done_at); 100010211Sandreas.hansson@arm.com else if (prechargeEvent.when() < pre_done_at) 100110211Sandreas.hansson@arm.com reschedule(prechargeEvent, pre_done_at); 100210208Sandreas.hansson@arm.com} 100310208Sandreas.hansson@arm.com 100410208Sandreas.hansson@arm.comvoid 100510208Sandreas.hansson@arm.comDRAMCtrl::processPrechargeEvent() 100610208Sandreas.hansson@arm.com{ 100710207Sandreas.hansson@arm.com // if we reached zero, then special conditions apply as we track 100810207Sandreas.hansson@arm.com // if all banks are precharged for the power models 100910207Sandreas.hansson@arm.com if (numBanksActive == 0) { 101010208Sandreas.hansson@arm.com // we should transition to the idle state when the last bank 101110208Sandreas.hansson@arm.com // is precharged 101210208Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 101310207Sandreas.hansson@arm.com } 101410207Sandreas.hansson@arm.com} 101510207Sandreas.hansson@arm.com 101610207Sandreas.hansson@arm.comvoid 101710146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 10189243SN/A{ 10199243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 10209243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 10219243SN/A 102210211Sandreas.hansson@arm.com // get the bank 10239967SN/A Bank& bank = dram_pkt->bankRef; 10249243SN/A 102510211Sandreas.hansson@arm.com // for the state we need to track if it is a row hit or not 102610211Sandreas.hansson@arm.com bool row_hit = true; 102710211Sandreas.hansson@arm.com 102810211Sandreas.hansson@arm.com // respect any constraints on the command (e.g. tRCD or tCCD) 102910211Sandreas.hansson@arm.com Tick cmd_at = std::max(bank.colAllowedAt, curTick()); 103010211Sandreas.hansson@arm.com 103110211Sandreas.hansson@arm.com // Determine the access latency and update the bank state 103210211Sandreas.hansson@arm.com if (bank.openRow == dram_pkt->row) { 103310211Sandreas.hansson@arm.com // nothing to do 103410209Sandreas.hansson@arm.com } else { 103510211Sandreas.hansson@arm.com row_hit = false; 103610211Sandreas.hansson@arm.com 103710209Sandreas.hansson@arm.com // If there is a page open, precharge it. 103810209Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 103910211Sandreas.hansson@arm.com prechargeBank(bank, std::max(bank.preAllowedAt, curTick())); 10409488SN/A } 10419973SN/A 104210211Sandreas.hansson@arm.com // next we need to account for the delay in activating the 104310211Sandreas.hansson@arm.com // page 104410211Sandreas.hansson@arm.com Tick act_tick = std::max(bank.actAllowedAt, curTick()); 10459973SN/A 104610210Sandreas.hansson@arm.com // Record the activation and deal with all the global timing 104710210Sandreas.hansson@arm.com // constraints caused be a new activation (tRRD and tXAW) 104810246Sandreas.hansson@arm.com activateBank(bank, act_tick, dram_pkt->row); 104910210Sandreas.hansson@arm.com 105010211Sandreas.hansson@arm.com // issue the command as early as possible 105110211Sandreas.hansson@arm.com cmd_at = bank.colAllowedAt; 105210209Sandreas.hansson@arm.com } 105310209Sandreas.hansson@arm.com 105410211Sandreas.hansson@arm.com // we need to wait until the bus is available before we can issue 105510211Sandreas.hansson@arm.com // the command 105610211Sandreas.hansson@arm.com cmd_at = std::max(cmd_at, busBusyUntil - tCL); 105710211Sandreas.hansson@arm.com 105810211Sandreas.hansson@arm.com // update the packet ready time 105910211Sandreas.hansson@arm.com dram_pkt->readyTime = cmd_at + tCL + tBURST; 106010211Sandreas.hansson@arm.com 106110211Sandreas.hansson@arm.com // only one burst can use the bus at any one point in time 106210211Sandreas.hansson@arm.com assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 106310211Sandreas.hansson@arm.com 106410394Swendy.elsasser@arm.com // update the time for the next read/write burst for each 106510394Swendy.elsasser@arm.com // bank (add a max with tCCD/tCCD_L here) 106610394Swendy.elsasser@arm.com Tick cmd_dly; 106710394Swendy.elsasser@arm.com for(int j = 0; j < ranksPerChannel; j++) { 106810394Swendy.elsasser@arm.com for(int i = 0; i < banksPerRank; i++) { 106910394Swendy.elsasser@arm.com // next burst to same bank group in this rank must not happen 107010394Swendy.elsasser@arm.com // before tCCD_L. Different bank group timing requirement is 107110394Swendy.elsasser@arm.com // tBURST; Add tCS for different ranks 107210394Swendy.elsasser@arm.com if (dram_pkt->rank == j) { 107310394Swendy.elsasser@arm.com if (bankGroupArch && (bank.bankgr == banks[j][i].bankgr)) { 107410394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 107510394Swendy.elsasser@arm.com // RD/WR burst commands to the same bank group. 107610394Swendy.elsasser@arm.com // Use tCCD_L in this case 107710394Swendy.elsasser@arm.com cmd_dly = tCCD_L; 107810394Swendy.elsasser@arm.com } else { 107910394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), the shorter 108010394Swendy.elsasser@arm.com // cas-to-cas delay value, when either: 108110394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 108210394Swendy.elsasser@arm.com // 2) bank is in a different bank group 108310394Swendy.elsasser@arm.com cmd_dly = tBURST; 108410394Swendy.elsasser@arm.com } 108510394Swendy.elsasser@arm.com } else { 108610394Swendy.elsasser@arm.com // different rank is by default in a different bank group 108710394Swendy.elsasser@arm.com // use tBURST (equivalent to tCCD_S), which is the shorter 108810394Swendy.elsasser@arm.com // cas-to-cas delay in this case 108910394Swendy.elsasser@arm.com // Add tCS to account for rank-to-rank bus delay requirements 109010394Swendy.elsasser@arm.com cmd_dly = tBURST + tCS; 109110394Swendy.elsasser@arm.com } 109210394Swendy.elsasser@arm.com banks[j][i].colAllowedAt = std::max(cmd_at + cmd_dly, 109310394Swendy.elsasser@arm.com banks[j][i].colAllowedAt); 109410394Swendy.elsasser@arm.com } 109510394Swendy.elsasser@arm.com } 109610211Sandreas.hansson@arm.com 109710393Swendy.elsasser@arm.com // Save rank of current access 109810393Swendy.elsasser@arm.com activeRank = dram_pkt->rank; 109910393Swendy.elsasser@arm.com 110010212Sandreas.hansson@arm.com // If this is a write, we also need to respect the write recovery 110110212Sandreas.hansson@arm.com // time before a precharge, in the case of a read, respect the 110210212Sandreas.hansson@arm.com // read to precharge constraint 110310212Sandreas.hansson@arm.com bank.preAllowedAt = std::max(bank.preAllowedAt, 110410212Sandreas.hansson@arm.com dram_pkt->isRead ? cmd_at + tRTP : 110510212Sandreas.hansson@arm.com dram_pkt->readyTime + tWR); 110610210Sandreas.hansson@arm.com 110710209Sandreas.hansson@arm.com // increment the bytes accessed and the accesses per row 110810209Sandreas.hansson@arm.com bank.bytesAccessed += burstSize; 110910209Sandreas.hansson@arm.com ++bank.rowAccesses; 111010209Sandreas.hansson@arm.com 111110209Sandreas.hansson@arm.com // if we reached the max, then issue with an auto-precharge 111210209Sandreas.hansson@arm.com bool auto_precharge = pageMgmt == Enums::close || 111310209Sandreas.hansson@arm.com bank.rowAccesses == maxAccessesPerRow; 111410209Sandreas.hansson@arm.com 111510209Sandreas.hansson@arm.com // if we did not hit the limit, we might still want to 111610209Sandreas.hansson@arm.com // auto-precharge 111710209Sandreas.hansson@arm.com if (!auto_precharge && 111810209Sandreas.hansson@arm.com (pageMgmt == Enums::open_adaptive || 111910209Sandreas.hansson@arm.com pageMgmt == Enums::close_adaptive)) { 112010209Sandreas.hansson@arm.com // a twist on the open and close page policies: 112110209Sandreas.hansson@arm.com // 1) open_adaptive page policy does not blindly keep the 112210209Sandreas.hansson@arm.com // page open, but close it if there are no row hits, and there 112310209Sandreas.hansson@arm.com // are bank conflicts in the queue 112410209Sandreas.hansson@arm.com // 2) close_adaptive page policy does not blindly close the 112510209Sandreas.hansson@arm.com // page, but closes it only if there are no row hits in the queue. 112610209Sandreas.hansson@arm.com // In this case, only force an auto precharge when there 112710209Sandreas.hansson@arm.com // are no same page hits in the queue 112810209Sandreas.hansson@arm.com bool got_more_hits = false; 112910209Sandreas.hansson@arm.com bool got_bank_conflict = false; 113010209Sandreas.hansson@arm.com 113110209Sandreas.hansson@arm.com // either look at the read queue or write queue 113210209Sandreas.hansson@arm.com const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 113310209Sandreas.hansson@arm.com writeQueue; 113410209Sandreas.hansson@arm.com auto p = queue.begin(); 113510209Sandreas.hansson@arm.com // make sure we are not considering the packet that we are 113610209Sandreas.hansson@arm.com // currently dealing with (which is the head of the queue) 113710209Sandreas.hansson@arm.com ++p; 113810209Sandreas.hansson@arm.com 113910209Sandreas.hansson@arm.com // keep on looking until we have found required condition or 114010209Sandreas.hansson@arm.com // reached the end 114110209Sandreas.hansson@arm.com while (!(got_more_hits && 114210209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive)) && 114310209Sandreas.hansson@arm.com p != queue.end()) { 114410209Sandreas.hansson@arm.com bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 114510209Sandreas.hansson@arm.com (dram_pkt->bank == (*p)->bank); 114610209Sandreas.hansson@arm.com bool same_row = dram_pkt->row == (*p)->row; 114710209Sandreas.hansson@arm.com got_more_hits |= same_rank_bank && same_row; 114810209Sandreas.hansson@arm.com got_bank_conflict |= same_rank_bank && !same_row; 11499973SN/A ++p; 115010141SN/A } 115110141SN/A 115210209Sandreas.hansson@arm.com // auto pre-charge when either 115310209Sandreas.hansson@arm.com // 1) open_adaptive policy, we have not got any more hits, and 115410209Sandreas.hansson@arm.com // have a bank conflict 115510209Sandreas.hansson@arm.com // 2) close_adaptive policy and we have not got any more hits 115610209Sandreas.hansson@arm.com auto_precharge = !got_more_hits && 115710209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive); 115810209Sandreas.hansson@arm.com } 115910142SN/A 116010247Sandreas.hansson@arm.com // DRAMPower trace command to be written 116110247Sandreas.hansson@arm.com std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR"; 116210247Sandreas.hansson@arm.com 116310432SOmar.Naji@arm.com // MemCommand required for DRAMPower library 116410432SOmar.Naji@arm.com MemCommand::cmds command = (mem_cmd == "RD") ? MemCommand::RD : 116510432SOmar.Naji@arm.com MemCommand::WR; 116610432SOmar.Naji@arm.com 116710209Sandreas.hansson@arm.com // if this access should use auto-precharge, then we are 116810209Sandreas.hansson@arm.com // closing the row 116910209Sandreas.hansson@arm.com if (auto_precharge) { 117010432SOmar.Naji@arm.com // if auto-precharge push a PRE command at the correct tick to the 117110432SOmar.Naji@arm.com // list used by DRAMPower library to calculate power 117210432SOmar.Naji@arm.com prechargeBank(bank, std::max(curTick(), bank.preAllowedAt)); 11739973SN/A 117410209Sandreas.hansson@arm.com DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 117510209Sandreas.hansson@arm.com } 11769963SN/A 11779243SN/A // Update bus state 11789243SN/A busBusyUntil = dram_pkt->readyTime; 11799243SN/A 118010211Sandreas.hansson@arm.com DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n", 118110211Sandreas.hansson@arm.com dram_pkt->addr, dram_pkt->readyTime, busBusyUntil); 11829243SN/A 118310432SOmar.Naji@arm.com rankPower[dram_pkt->rank].powerlib.doCommand(command, dram_pkt->bank, 118410432SOmar.Naji@arm.com divCeil(cmd_at, tCK) - 118510432SOmar.Naji@arm.com timeStampOffset); 118610432SOmar.Naji@arm.com 118710432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK) - 118810432SOmar.Naji@arm.com timeStampOffset, mem_cmd, dram_pkt->bank, dram_pkt->rank); 118910247Sandreas.hansson@arm.com 119010206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 119110206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 119210206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 119310206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 119410206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 11959972SN/A 119610206Sandreas.hansson@arm.com // Update the stats and schedule the next request 11979977SN/A if (dram_pkt->isRead) { 119810147Sandreas.hansson@arm.com ++readsThisTime; 119910211Sandreas.hansson@arm.com if (row_hit) 12009977SN/A readRowHits++; 12019977SN/A bytesReadDRAM += burstSize; 12029977SN/A perBankRdBursts[dram_pkt->bankId]++; 120310206Sandreas.hansson@arm.com 120410206Sandreas.hansson@arm.com // Update latency stats 120510206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 120610206Sandreas.hansson@arm.com totBusLat += tBURST; 120710211Sandreas.hansson@arm.com totQLat += cmd_at - dram_pkt->entryTime; 12089977SN/A } else { 120910147Sandreas.hansson@arm.com ++writesThisTime; 121010211Sandreas.hansson@arm.com if (row_hit) 12119977SN/A writeRowHits++; 12129977SN/A bytesWritten += burstSize; 12139977SN/A perBankWrBursts[dram_pkt->bankId]++; 12149243SN/A } 12159243SN/A} 12169243SN/A 12179243SN/Avoid 121810206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 12199243SN/A{ 122010393Swendy.elsasser@arm.com // pre-emptively set to false. Overwrite if in READ_TO_WRITE 122110393Swendy.elsasser@arm.com // or WRITE_TO_READ state 122210393Swendy.elsasser@arm.com bool switched_cmd_type = false; 122310206Sandreas.hansson@arm.com if (busState == READ_TO_WRITE) { 122410206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 122510206Sandreas.hansson@arm.com "waiting\n", readsThisTime, readQueue.size()); 12269243SN/A 122710206Sandreas.hansson@arm.com // sample and reset the read-related stats as we are now 122810206Sandreas.hansson@arm.com // transitioning to writes, and all reads are done 122910206Sandreas.hansson@arm.com rdPerTurnAround.sample(readsThisTime); 123010206Sandreas.hansson@arm.com readsThisTime = 0; 123110206Sandreas.hansson@arm.com 123210206Sandreas.hansson@arm.com // now proceed to do the actual writes 123310206Sandreas.hansson@arm.com busState = WRITE; 123410393Swendy.elsasser@arm.com switched_cmd_type = true; 123510206Sandreas.hansson@arm.com } else if (busState == WRITE_TO_READ) { 123610206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 123710206Sandreas.hansson@arm.com "waiting\n", writesThisTime, writeQueue.size()); 123810206Sandreas.hansson@arm.com 123910206Sandreas.hansson@arm.com wrPerTurnAround.sample(writesThisTime); 124010206Sandreas.hansson@arm.com writesThisTime = 0; 124110206Sandreas.hansson@arm.com 124210206Sandreas.hansson@arm.com busState = READ; 124310393Swendy.elsasser@arm.com switched_cmd_type = true; 124410206Sandreas.hansson@arm.com } 124510206Sandreas.hansson@arm.com 124610207Sandreas.hansson@arm.com if (refreshState != REF_IDLE) { 124710207Sandreas.hansson@arm.com // if a refresh waiting for this event loop to finish, then hand 124810207Sandreas.hansson@arm.com // over now, and do not schedule a new nextReqEvent 124910207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 125010207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 125110207Sandreas.hansson@arm.com 125210207Sandreas.hansson@arm.com refreshState = REF_PRE; 125310207Sandreas.hansson@arm.com 125410207Sandreas.hansson@arm.com // hand control back to the refresh event loop 125510207Sandreas.hansson@arm.com schedule(refreshEvent, curTick()); 125610207Sandreas.hansson@arm.com } 125710207Sandreas.hansson@arm.com 125810207Sandreas.hansson@arm.com // let the refresh finish before issuing any further requests 125910207Sandreas.hansson@arm.com return; 126010207Sandreas.hansson@arm.com } 126110207Sandreas.hansson@arm.com 126210206Sandreas.hansson@arm.com // when we get here it is either a read or a write 126310206Sandreas.hansson@arm.com if (busState == READ) { 126410206Sandreas.hansson@arm.com 126510206Sandreas.hansson@arm.com // track if we should switch or not 126610206Sandreas.hansson@arm.com bool switch_to_writes = false; 126710206Sandreas.hansson@arm.com 126810206Sandreas.hansson@arm.com if (readQueue.empty()) { 126910206Sandreas.hansson@arm.com // In the case there is no read request to go next, 127010206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 127110206Sandreas.hansson@arm.com // if we are draining) 127210206Sandreas.hansson@arm.com if (!writeQueue.empty() && 127310206Sandreas.hansson@arm.com (drainManager || writeQueue.size() > writeLowThreshold)) { 127410206Sandreas.hansson@arm.com 127510206Sandreas.hansson@arm.com switch_to_writes = true; 127610206Sandreas.hansson@arm.com } else { 127710206Sandreas.hansson@arm.com // check if we are drained 127810206Sandreas.hansson@arm.com if (respQueue.empty () && drainManager) { 127910206Sandreas.hansson@arm.com drainManager->signalDrainDone(); 128010206Sandreas.hansson@arm.com drainManager = NULL; 128110206Sandreas.hansson@arm.com } 128210206Sandreas.hansson@arm.com 128310206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 128410206Sandreas.hansson@arm.com // event for the next request 128510206Sandreas.hansson@arm.com return; 128610206Sandreas.hansson@arm.com } 128710206Sandreas.hansson@arm.com } else { 128810206Sandreas.hansson@arm.com // Figure out which read request goes next, and move it to the 128910206Sandreas.hansson@arm.com // front of the read queue 129010393Swendy.elsasser@arm.com chooseNext(readQueue, switched_cmd_type); 129110206Sandreas.hansson@arm.com 129210215Sandreas.hansson@arm.com DRAMPacket* dram_pkt = readQueue.front(); 129310215Sandreas.hansson@arm.com 129410393Swendy.elsasser@arm.com // here we get a bit creative and shift the bus busy time not 129510393Swendy.elsasser@arm.com // just the tWTR, but also a CAS latency to capture the fact 129610393Swendy.elsasser@arm.com // that we are allowed to prepare a new bank, but not issue a 129710393Swendy.elsasser@arm.com // read command until after tWTR, in essence we capture a 129810393Swendy.elsasser@arm.com // bubble on the data bus that is tWTR + tCL 129910394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 130010394Swendy.elsasser@arm.com busBusyUntil += tWTR + tCL; 130110393Swendy.elsasser@arm.com } 130210393Swendy.elsasser@arm.com 130310215Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 130410206Sandreas.hansson@arm.com 130510206Sandreas.hansson@arm.com // At this point we're done dealing with the request 130610215Sandreas.hansson@arm.com readQueue.pop_front(); 130710215Sandreas.hansson@arm.com 130810215Sandreas.hansson@arm.com // sanity check 130910215Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 131010215Sandreas.hansson@arm.com assert(dram_pkt->readyTime >= curTick()); 131110215Sandreas.hansson@arm.com 131210215Sandreas.hansson@arm.com // Insert into response queue. It will be sent back to the 131310215Sandreas.hansson@arm.com // requestor at its readyTime 131410215Sandreas.hansson@arm.com if (respQueue.empty()) { 131510215Sandreas.hansson@arm.com assert(!respondEvent.scheduled()); 131610215Sandreas.hansson@arm.com schedule(respondEvent, dram_pkt->readyTime); 131710215Sandreas.hansson@arm.com } else { 131810215Sandreas.hansson@arm.com assert(respQueue.back()->readyTime <= dram_pkt->readyTime); 131910215Sandreas.hansson@arm.com assert(respondEvent.scheduled()); 132010215Sandreas.hansson@arm.com } 132110215Sandreas.hansson@arm.com 132210215Sandreas.hansson@arm.com respQueue.push_back(dram_pkt); 132310206Sandreas.hansson@arm.com 132410206Sandreas.hansson@arm.com // we have so many writes that we have to transition 132510206Sandreas.hansson@arm.com if (writeQueue.size() > writeHighThreshold) { 132610206Sandreas.hansson@arm.com switch_to_writes = true; 132710206Sandreas.hansson@arm.com } 132810206Sandreas.hansson@arm.com } 132910206Sandreas.hansson@arm.com 133010206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 133110206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 133210206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 133310206Sandreas.hansson@arm.com if (switch_to_writes) { 133410206Sandreas.hansson@arm.com // transition to writing 133510206Sandreas.hansson@arm.com busState = READ_TO_WRITE; 133610206Sandreas.hansson@arm.com } 13379352SN/A } else { 133810393Swendy.elsasser@arm.com chooseNext(writeQueue, switched_cmd_type); 133910206Sandreas.hansson@arm.com DRAMPacket* dram_pkt = writeQueue.front(); 134010206Sandreas.hansson@arm.com // sanity check 134110206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 134210393Swendy.elsasser@arm.com 134310394Swendy.elsasser@arm.com // add a bubble to the data bus, as defined by the 134410394Swendy.elsasser@arm.com // tRTW when access is to the same rank as previous burst 134510394Swendy.elsasser@arm.com // Different rank timing is handled with tCS, which is 134610394Swendy.elsasser@arm.com // applied to colAllowedAt 134710394Swendy.elsasser@arm.com if (switched_cmd_type && dram_pkt->rank == activeRank) { 134810394Swendy.elsasser@arm.com busBusyUntil += tRTW; 134910393Swendy.elsasser@arm.com } 135010393Swendy.elsasser@arm.com 135110206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 135210206Sandreas.hansson@arm.com 135310206Sandreas.hansson@arm.com writeQueue.pop_front(); 135410206Sandreas.hansson@arm.com delete dram_pkt; 135510206Sandreas.hansson@arm.com 135610206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 135710206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 135810206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 135910206Sandreas.hansson@arm.com // writes, then switch to reads. 136010206Sandreas.hansson@arm.com if (writeQueue.empty() || 136110206Sandreas.hansson@arm.com (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 136210206Sandreas.hansson@arm.com !drainManager) || 136310206Sandreas.hansson@arm.com (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 136410206Sandreas.hansson@arm.com // turn the bus back around for reads again 136510206Sandreas.hansson@arm.com busState = WRITE_TO_READ; 136610206Sandreas.hansson@arm.com 136710206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 136810206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 136910206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 137010206Sandreas.hansson@arm.com // nothing to do 137110206Sandreas.hansson@arm.com } 137210206Sandreas.hansson@arm.com } 137310206Sandreas.hansson@arm.com 137410206Sandreas.hansson@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 137510206Sandreas.hansson@arm.com 137610206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 137710206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 137810206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 137910206Sandreas.hansson@arm.com // the next request processing 138010206Sandreas.hansson@arm.com if (retryWrReq && writeQueue.size() < writeBufferSize) { 138110206Sandreas.hansson@arm.com retryWrReq = false; 138210206Sandreas.hansson@arm.com port.sendRetry(); 13839352SN/A } 13849243SN/A} 13859243SN/A 13869967SN/Auint64_t 138710393Swendy.elsasser@arm.comDRAMCtrl::minBankPrep(const deque<DRAMPacket*>& queue, 138810393Swendy.elsasser@arm.com bool switched_cmd_type) const 13899967SN/A{ 13909967SN/A uint64_t bank_mask = 0; 139110211Sandreas.hansson@arm.com Tick min_act_at = MaxTick; 13929967SN/A 139310393Swendy.elsasser@arm.com uint64_t bank_mask_same_rank = 0; 139410393Swendy.elsasser@arm.com Tick min_act_at_same_rank = MaxTick; 139510393Swendy.elsasser@arm.com 139610393Swendy.elsasser@arm.com // Give precedence to commands that access same rank as previous command 139710393Swendy.elsasser@arm.com bool same_rank_match = false; 139810393Swendy.elsasser@arm.com 139910393Swendy.elsasser@arm.com // determine if we have queued transactions targetting the 14009967SN/A // bank in question 14019967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 14029967SN/A for (auto p = queue.begin(); p != queue.end(); ++p) { 14039967SN/A got_waiting[(*p)->bankId] = true; 14049967SN/A } 14059967SN/A 14069967SN/A for (int i = 0; i < ranksPerChannel; i++) { 14079967SN/A for (int j = 0; j < banksPerRank; j++) { 140810211Sandreas.hansson@arm.com uint8_t bank_id = i * banksPerRank + j; 140910211Sandreas.hansson@arm.com 14109967SN/A // if we have waiting requests for the bank, and it is 14119967SN/A // amongst the first available, update the mask 141210211Sandreas.hansson@arm.com if (got_waiting[bank_id]) { 141310211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue 141410211Sandreas.hansson@arm.com // an activate, ignoring any rank-to-rank switching 141510393Swendy.elsasser@arm.com // cost in this calculation 141610211Sandreas.hansson@arm.com Tick act_at = banks[i][j].openRow == Bank::NO_ROW ? 141710211Sandreas.hansson@arm.com banks[i][j].actAllowedAt : 141810211Sandreas.hansson@arm.com std::max(banks[i][j].preAllowedAt, curTick()) + tRP; 141910211Sandreas.hansson@arm.com 142010393Swendy.elsasser@arm.com // prioritize commands that access the 142110393Swendy.elsasser@arm.com // same rank as previous burst 142210393Swendy.elsasser@arm.com // Calculate bank mask separately for the case and 142310393Swendy.elsasser@arm.com // evaluate after loop iterations complete 142410393Swendy.elsasser@arm.com if (i == activeRank && ranksPerChannel > 1) { 142510393Swendy.elsasser@arm.com if (act_at <= min_act_at_same_rank) { 142610393Swendy.elsasser@arm.com // reset same rank bank mask if new minimum is found 142710393Swendy.elsasser@arm.com // and previous minimum could not immediately send ACT 142810393Swendy.elsasser@arm.com if (act_at < min_act_at_same_rank && 142910393Swendy.elsasser@arm.com min_act_at_same_rank > curTick()) 143010393Swendy.elsasser@arm.com bank_mask_same_rank = 0; 143110393Swendy.elsasser@arm.com 143210393Swendy.elsasser@arm.com // Set flag indicating that a same rank 143310393Swendy.elsasser@arm.com // opportunity was found 143410393Swendy.elsasser@arm.com same_rank_match = true; 143510393Swendy.elsasser@arm.com 143610393Swendy.elsasser@arm.com // set the bit corresponding to the available bank 143710393Swendy.elsasser@arm.com replaceBits(bank_mask_same_rank, bank_id, bank_id, 1); 143810393Swendy.elsasser@arm.com min_act_at_same_rank = act_at; 143910393Swendy.elsasser@arm.com } 144010393Swendy.elsasser@arm.com } else { 144110393Swendy.elsasser@arm.com if (act_at <= min_act_at) { 144210393Swendy.elsasser@arm.com // reset bank mask if new minimum is found 144310393Swendy.elsasser@arm.com // and either previous minimum could not immediately send ACT 144410393Swendy.elsasser@arm.com if (act_at < min_act_at && min_act_at > curTick()) 144510393Swendy.elsasser@arm.com bank_mask = 0; 144610393Swendy.elsasser@arm.com // set the bit corresponding to the available bank 144710393Swendy.elsasser@arm.com replaceBits(bank_mask, bank_id, bank_id, 1); 144810393Swendy.elsasser@arm.com min_act_at = act_at; 144910393Swendy.elsasser@arm.com } 145010211Sandreas.hansson@arm.com } 14519967SN/A } 14529967SN/A } 14539967SN/A } 145410211Sandreas.hansson@arm.com 145510393Swendy.elsasser@arm.com // Determine the earliest time when the next burst can issue based 145610393Swendy.elsasser@arm.com // on the current busBusyUntil delay. 145710393Swendy.elsasser@arm.com // Offset by tRCD to correlate with ACT timing variables 145810393Swendy.elsasser@arm.com Tick min_cmd_at = busBusyUntil - tCL - tRCD; 145910393Swendy.elsasser@arm.com 146010393Swendy.elsasser@arm.com // Prioritize same rank accesses that can issue B2B 146110393Swendy.elsasser@arm.com // Only optimize for same ranks when the command type 146210393Swendy.elsasser@arm.com // does not change; do not want to unnecessarily incur tWTR 146310393Swendy.elsasser@arm.com // 146410393Swendy.elsasser@arm.com // Resulting FCFS prioritization Order is: 146510393Swendy.elsasser@arm.com // 1) Commands that access the same rank as previous burst 146610393Swendy.elsasser@arm.com // and can prep the bank seamlessly. 146710393Swendy.elsasser@arm.com // 2) Commands (any rank) with earliest bank prep 146810393Swendy.elsasser@arm.com if (!switched_cmd_type && same_rank_match && 146910393Swendy.elsasser@arm.com min_act_at_same_rank <= min_cmd_at) { 147010393Swendy.elsasser@arm.com bank_mask = bank_mask_same_rank; 147110393Swendy.elsasser@arm.com } 147210393Swendy.elsasser@arm.com 14739967SN/A return bank_mask; 14749967SN/A} 14759967SN/A 14769243SN/Avoid 147710146Sandreas.hansson@arm.comDRAMCtrl::processRefreshEvent() 14789243SN/A{ 147910207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 148010207Sandreas.hansson@arm.com if (refreshState == REF_IDLE) { 148110207Sandreas.hansson@arm.com // remember when the refresh is due 148210207Sandreas.hansson@arm.com refreshDueAt = curTick(); 14839243SN/A 148410207Sandreas.hansson@arm.com // proceed to drain 148510207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 14869243SN/A 148710207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 148810207Sandreas.hansson@arm.com } 148910207Sandreas.hansson@arm.com 149010207Sandreas.hansson@arm.com // let any scheduled read or write go ahead, after which it will 149110207Sandreas.hansson@arm.com // hand control back to this event loop 149210207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 149310207Sandreas.hansson@arm.com if (nextReqEvent.scheduled()) { 149410207Sandreas.hansson@arm.com // hand control over to the request loop until it is 149510207Sandreas.hansson@arm.com // evaluated next 149610207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 149710207Sandreas.hansson@arm.com 149810207Sandreas.hansson@arm.com return; 149910207Sandreas.hansson@arm.com } else { 150010207Sandreas.hansson@arm.com refreshState = REF_PRE; 150110207Sandreas.hansson@arm.com } 150210207Sandreas.hansson@arm.com } 150310207Sandreas.hansson@arm.com 150410207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 150510207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 150610208Sandreas.hansson@arm.com // precharge any active bank if we are not already in the idle 150710208Sandreas.hansson@arm.com // state 150810208Sandreas.hansson@arm.com if (pwrState != PWR_IDLE) { 150910214Sandreas.hansson@arm.com // at the moment, we use a precharge all even if there is 151010214Sandreas.hansson@arm.com // only a single bank open 151110208Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 151210214Sandreas.hansson@arm.com 151310214Sandreas.hansson@arm.com // first determine when we can precharge 151410214Sandreas.hansson@arm.com Tick pre_at = curTick(); 151510214Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 151610214Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 151710214Sandreas.hansson@arm.com // respect both causality and any existing bank 151810214Sandreas.hansson@arm.com // constraints, some banks could already have a 151910214Sandreas.hansson@arm.com // (auto) precharge scheduled 152010214Sandreas.hansson@arm.com pre_at = std::max(banks[i][j].preAllowedAt, pre_at); 152110214Sandreas.hansson@arm.com } 152210214Sandreas.hansson@arm.com } 152310214Sandreas.hansson@arm.com 152410214Sandreas.hansson@arm.com // make sure all banks are precharged, and for those that 152510214Sandreas.hansson@arm.com // already are, update their availability 152610214Sandreas.hansson@arm.com Tick act_allowed_at = pre_at + tRP; 152710214Sandreas.hansson@arm.com 152810208Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 152910208Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 153010208Sandreas.hansson@arm.com if (banks[i][j].openRow != Bank::NO_ROW) { 153110247Sandreas.hansson@arm.com prechargeBank(banks[i][j], pre_at, false); 153210214Sandreas.hansson@arm.com } else { 153310214Sandreas.hansson@arm.com banks[i][j].actAllowedAt = 153410214Sandreas.hansson@arm.com std::max(banks[i][j].actAllowedAt, act_allowed_at); 153510214Sandreas.hansson@arm.com banks[i][j].preAllowedAt = 153610214Sandreas.hansson@arm.com std::max(banks[i][j].preAllowedAt, pre_at); 153710208Sandreas.hansson@arm.com } 153810207Sandreas.hansson@arm.com } 153910247Sandreas.hansson@arm.com 154010247Sandreas.hansson@arm.com // at the moment this affects all ranks 154110432SOmar.Naji@arm.com rankPower[i].powerlib.doCommand(MemCommand::PREA, 0, 154210432SOmar.Naji@arm.com divCeil(pre_at, tCK) - 154310432SOmar.Naji@arm.com timeStampOffset); 154410432SOmar.Naji@arm.com 154510432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PREA,0,%d\n", divCeil(pre_at, tCK) - 154610432SOmar.Naji@arm.com timeStampOffset, i); 154710207Sandreas.hansson@arm.com } 154810208Sandreas.hansson@arm.com } else { 154910208Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 155010208Sandreas.hansson@arm.com 155110208Sandreas.hansson@arm.com // go ahead and kick the power state machine into gear if 155210208Sandreas.hansson@arm.com // we are already idle 155310208Sandreas.hansson@arm.com schedulePowerEvent(PWR_REF, curTick()); 15549975SN/A } 15559975SN/A 155610208Sandreas.hansson@arm.com refreshState = REF_RUN; 155710208Sandreas.hansson@arm.com assert(numBanksActive == 0); 15589243SN/A 155910208Sandreas.hansson@arm.com // wait for all banks to be precharged, at which point the 156010208Sandreas.hansson@arm.com // power state machine will transition to the idle state, and 156110208Sandreas.hansson@arm.com // automatically move to a refresh, at that point it will also 156210208Sandreas.hansson@arm.com // call this method to get the refresh event loop going again 156310207Sandreas.hansson@arm.com return; 156410207Sandreas.hansson@arm.com } 156510207Sandreas.hansson@arm.com 156610207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 156710207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 156810207Sandreas.hansson@arm.com // should never get here with any banks active 156910207Sandreas.hansson@arm.com assert(numBanksActive == 0); 157010208Sandreas.hansson@arm.com assert(pwrState == PWR_REF); 157110207Sandreas.hansson@arm.com 157210211Sandreas.hansson@arm.com Tick ref_done_at = curTick() + tRFC; 157310207Sandreas.hansson@arm.com 157410207Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 157510207Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 157610211Sandreas.hansson@arm.com banks[i][j].actAllowedAt = ref_done_at; 157710207Sandreas.hansson@arm.com } 157810247Sandreas.hansson@arm.com 157910247Sandreas.hansson@arm.com // at the moment this affects all ranks 158010432SOmar.Naji@arm.com rankPower[i].powerlib.doCommand(MemCommand::REF, 0, 158110432SOmar.Naji@arm.com divCeil(curTick(), tCK) - 158210432SOmar.Naji@arm.com timeStampOffset); 158310432SOmar.Naji@arm.com 158410432SOmar.Naji@arm.com // at the moment sort the list of commands and update the counters 158510432SOmar.Naji@arm.com // for DRAMPower libray when doing a refresh 158610432SOmar.Naji@arm.com sort(rankPower[i].powerlib.cmdList.begin(), 158710432SOmar.Naji@arm.com rankPower[i].powerlib.cmdList.end(), DRAMCtrl::sortTime); 158810432SOmar.Naji@arm.com 158910432SOmar.Naji@arm.com // update the counters for DRAMPower, passing false to 159010432SOmar.Naji@arm.com // indicate that this is not the last command in the 159110432SOmar.Naji@arm.com // list. DRAMPower requires this information for the 159210432SOmar.Naji@arm.com // correct calculation of the background energy at the end 159310432SOmar.Naji@arm.com // of the simulation. Ideally we would want to call this 159410432SOmar.Naji@arm.com // function with true once at the end of the 159510432SOmar.Naji@arm.com // simulation. However, the discarded energy is extremly 159610432SOmar.Naji@arm.com // small and does not effect the final results. 159710432SOmar.Naji@arm.com rankPower[i].powerlib.updateCounters(false); 159810432SOmar.Naji@arm.com 159910432SOmar.Naji@arm.com // call the energy function 160010432SOmar.Naji@arm.com rankPower[i].powerlib.calcEnergy(); 160110432SOmar.Naji@arm.com 160210432SOmar.Naji@arm.com // Update the stats 160310432SOmar.Naji@arm.com updatePowerStats(i); 160410432SOmar.Naji@arm.com 160510432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), tCK) - 160610432SOmar.Naji@arm.com timeStampOffset, i); 160710207Sandreas.hansson@arm.com } 160810207Sandreas.hansson@arm.com 160910207Sandreas.hansson@arm.com // make sure we did not wait so long that we cannot make up 161010207Sandreas.hansson@arm.com // for it 161110211Sandreas.hansson@arm.com if (refreshDueAt + tREFI < ref_done_at) { 161210207Sandreas.hansson@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 161310207Sandreas.hansson@arm.com } 161410207Sandreas.hansson@arm.com 161510207Sandreas.hansson@arm.com // compensate for the delay in actually performing the refresh 161610207Sandreas.hansson@arm.com // when scheduling the next one 161710207Sandreas.hansson@arm.com schedule(refreshEvent, refreshDueAt + tREFI - tRP); 161810207Sandreas.hansson@arm.com 161910208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 162010207Sandreas.hansson@arm.com 162110208Sandreas.hansson@arm.com // move to the idle power state once the refresh is done, this 162210208Sandreas.hansson@arm.com // will also move the refresh state machine to the refresh 162310208Sandreas.hansson@arm.com // idle state 162410211Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, ref_done_at); 162510207Sandreas.hansson@arm.com 162610208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n", 162710211Sandreas.hansson@arm.com ref_done_at, refreshDueAt + tREFI); 162810208Sandreas.hansson@arm.com } 162910208Sandreas.hansson@arm.com} 163010208Sandreas.hansson@arm.com 163110208Sandreas.hansson@arm.comvoid 163210208Sandreas.hansson@arm.comDRAMCtrl::schedulePowerEvent(PowerState pwr_state, Tick tick) 163310208Sandreas.hansson@arm.com{ 163410208Sandreas.hansson@arm.com // respect causality 163510208Sandreas.hansson@arm.com assert(tick >= curTick()); 163610208Sandreas.hansson@arm.com 163710208Sandreas.hansson@arm.com if (!powerEvent.scheduled()) { 163810208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 163910208Sandreas.hansson@arm.com tick, pwr_state); 164010208Sandreas.hansson@arm.com 164110208Sandreas.hansson@arm.com // insert the new transition 164210208Sandreas.hansson@arm.com pwrStateTrans = pwr_state; 164310208Sandreas.hansson@arm.com 164410208Sandreas.hansson@arm.com schedule(powerEvent, tick); 164510208Sandreas.hansson@arm.com } else { 164610208Sandreas.hansson@arm.com panic("Scheduled power event at %llu to state %d, " 164710208Sandreas.hansson@arm.com "with scheduled event at %llu to %d\n", tick, pwr_state, 164810208Sandreas.hansson@arm.com powerEvent.when(), pwrStateTrans); 164910208Sandreas.hansson@arm.com } 165010208Sandreas.hansson@arm.com} 165110208Sandreas.hansson@arm.com 165210208Sandreas.hansson@arm.comvoid 165310208Sandreas.hansson@arm.comDRAMCtrl::processPowerEvent() 165410208Sandreas.hansson@arm.com{ 165510208Sandreas.hansson@arm.com // remember where we were, and for how long 165610208Sandreas.hansson@arm.com Tick duration = curTick() - pwrStateTick; 165710208Sandreas.hansson@arm.com PowerState prev_state = pwrState; 165810208Sandreas.hansson@arm.com 165910208Sandreas.hansson@arm.com // update the accounting 166010208Sandreas.hansson@arm.com pwrStateTime[prev_state] += duration; 166110208Sandreas.hansson@arm.com 166210208Sandreas.hansson@arm.com pwrState = pwrStateTrans; 166310208Sandreas.hansson@arm.com pwrStateTick = curTick(); 166410208Sandreas.hansson@arm.com 166510208Sandreas.hansson@arm.com if (pwrState == PWR_IDLE) { 166610208Sandreas.hansson@arm.com DPRINTF(DRAMState, "All banks precharged\n"); 166710208Sandreas.hansson@arm.com 166810208Sandreas.hansson@arm.com // if we were refreshing, make sure we start scheduling requests again 166910208Sandreas.hansson@arm.com if (prev_state == PWR_REF) { 167010208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 167110208Sandreas.hansson@arm.com assert(pwrState == PWR_IDLE); 167210208Sandreas.hansson@arm.com 167310208Sandreas.hansson@arm.com // kick things into action again 167410208Sandreas.hansson@arm.com refreshState = REF_IDLE; 167510208Sandreas.hansson@arm.com assert(!nextReqEvent.scheduled()); 167610208Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 167710208Sandreas.hansson@arm.com } else { 167810208Sandreas.hansson@arm.com assert(prev_state == PWR_ACT); 167910208Sandreas.hansson@arm.com 168010208Sandreas.hansson@arm.com // if we have a pending refresh, and are now moving to 168110208Sandreas.hansson@arm.com // the idle state, direclty transition to a refresh 168210208Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 168310208Sandreas.hansson@arm.com // there should be nothing waiting at this point 168410208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 168510208Sandreas.hansson@arm.com 168610208Sandreas.hansson@arm.com // update the state in zero time and proceed below 168710208Sandreas.hansson@arm.com pwrState = PWR_REF; 168810208Sandreas.hansson@arm.com } 168910208Sandreas.hansson@arm.com } 169010208Sandreas.hansson@arm.com } 169110208Sandreas.hansson@arm.com 169210208Sandreas.hansson@arm.com // we transition to the refresh state, let the refresh state 169310208Sandreas.hansson@arm.com // machine know of this state update and let it deal with the 169410208Sandreas.hansson@arm.com // scheduling of the next power state transition as well as the 169510208Sandreas.hansson@arm.com // following refresh 169610208Sandreas.hansson@arm.com if (pwrState == PWR_REF) { 169710208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refreshing\n"); 169810208Sandreas.hansson@arm.com // kick the refresh event loop into action again, and that 169910208Sandreas.hansson@arm.com // in turn will schedule a transition to the idle power 170010208Sandreas.hansson@arm.com // state once the refresh is done 170110208Sandreas.hansson@arm.com assert(refreshState == REF_RUN); 170210208Sandreas.hansson@arm.com processRefreshEvent(); 170310207Sandreas.hansson@arm.com } 17049243SN/A} 17059243SN/A 17069243SN/Avoid 170710432SOmar.Naji@arm.comDRAMCtrl::updatePowerStats(uint8_t rank) 170810432SOmar.Naji@arm.com{ 170910432SOmar.Naji@arm.com // Get the energy and power from DRAMPower 171010432SOmar.Naji@arm.com Data::MemoryPowerModel::Energy energy = 171110432SOmar.Naji@arm.com rankPower[rank].powerlib.getEnergy(); 171210432SOmar.Naji@arm.com Data::MemoryPowerModel::Power power = 171310432SOmar.Naji@arm.com rankPower[rank].powerlib.getPower(); 171410432SOmar.Naji@arm.com 171510432SOmar.Naji@arm.com actEnergy[rank] = energy.act_energy * devicesPerRank; 171610432SOmar.Naji@arm.com preEnergy[rank] = energy.pre_energy * devicesPerRank; 171710432SOmar.Naji@arm.com readEnergy[rank] = energy.read_energy * devicesPerRank; 171810432SOmar.Naji@arm.com writeEnergy[rank] = energy.write_energy * devicesPerRank; 171910432SOmar.Naji@arm.com refreshEnergy[rank] = energy.ref_energy * devicesPerRank; 172010432SOmar.Naji@arm.com actBackEnergy[rank] = energy.act_stdby_energy * devicesPerRank; 172110432SOmar.Naji@arm.com preBackEnergy[rank] = energy.pre_stdby_energy * devicesPerRank; 172210432SOmar.Naji@arm.com totalEnergy[rank] = energy.total_energy * devicesPerRank; 172310432SOmar.Naji@arm.com averagePower[rank] = power.average_power * devicesPerRank; 172410432SOmar.Naji@arm.com} 172510432SOmar.Naji@arm.com 172610432SOmar.Naji@arm.comvoid 172710146Sandreas.hansson@arm.comDRAMCtrl::regStats() 17289243SN/A{ 17299243SN/A using namespace Stats; 17309243SN/A 17319243SN/A AbstractMemory::regStats(); 17329243SN/A 17339243SN/A readReqs 17349243SN/A .name(name() + ".readReqs") 17359977SN/A .desc("Number of read requests accepted"); 17369243SN/A 17379243SN/A writeReqs 17389243SN/A .name(name() + ".writeReqs") 17399977SN/A .desc("Number of write requests accepted"); 17409831SN/A 17419831SN/A readBursts 17429831SN/A .name(name() + ".readBursts") 17439977SN/A .desc("Number of DRAM read bursts, " 17449977SN/A "including those serviced by the write queue"); 17459831SN/A 17469831SN/A writeBursts 17479831SN/A .name(name() + ".writeBursts") 17489977SN/A .desc("Number of DRAM write bursts, " 17499977SN/A "including those merged in the write queue"); 17509243SN/A 17519243SN/A servicedByWrQ 17529243SN/A .name(name() + ".servicedByWrQ") 17539977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 17549977SN/A 17559977SN/A mergedWrBursts 17569977SN/A .name(name() + ".mergedWrBursts") 17579977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 17589243SN/A 17599243SN/A neitherReadNorWrite 17609977SN/A .name(name() + ".neitherReadNorWriteReqs") 17619977SN/A .desc("Number of requests that are neither read nor write"); 17629243SN/A 17639977SN/A perBankRdBursts 17649243SN/A .init(banksPerRank * ranksPerChannel) 17659977SN/A .name(name() + ".perBankRdBursts") 17669977SN/A .desc("Per bank write bursts"); 17679243SN/A 17689977SN/A perBankWrBursts 17699243SN/A .init(banksPerRank * ranksPerChannel) 17709977SN/A .name(name() + ".perBankWrBursts") 17719977SN/A .desc("Per bank write bursts"); 17729243SN/A 17739243SN/A avgRdQLen 17749243SN/A .name(name() + ".avgRdQLen") 17759977SN/A .desc("Average read queue length when enqueuing") 17769243SN/A .precision(2); 17779243SN/A 17789243SN/A avgWrQLen 17799243SN/A .name(name() + ".avgWrQLen") 17809977SN/A .desc("Average write queue length when enqueuing") 17819243SN/A .precision(2); 17829243SN/A 17839243SN/A totQLat 17849243SN/A .name(name() + ".totQLat") 17859977SN/A .desc("Total ticks spent queuing"); 17869243SN/A 17879243SN/A totBusLat 17889243SN/A .name(name() + ".totBusLat") 17899977SN/A .desc("Total ticks spent in databus transfers"); 17909243SN/A 17919243SN/A totMemAccLat 17929243SN/A .name(name() + ".totMemAccLat") 17939977SN/A .desc("Total ticks spent from burst creation until serviced " 17949977SN/A "by the DRAM"); 17959243SN/A 17969243SN/A avgQLat 17979243SN/A .name(name() + ".avgQLat") 17989977SN/A .desc("Average queueing delay per DRAM burst") 17999243SN/A .precision(2); 18009243SN/A 18019831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 18029243SN/A 18039243SN/A avgBusLat 18049243SN/A .name(name() + ".avgBusLat") 18059977SN/A .desc("Average bus latency per DRAM burst") 18069243SN/A .precision(2); 18079243SN/A 18089831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 18099243SN/A 18109243SN/A avgMemAccLat 18119243SN/A .name(name() + ".avgMemAccLat") 18129977SN/A .desc("Average memory access latency per DRAM burst") 18139243SN/A .precision(2); 18149243SN/A 18159831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 18169243SN/A 18179243SN/A numRdRetry 18189243SN/A .name(name() + ".numRdRetry") 18199977SN/A .desc("Number of times read queue was full causing retry"); 18209243SN/A 18219243SN/A numWrRetry 18229243SN/A .name(name() + ".numWrRetry") 18239977SN/A .desc("Number of times write queue was full causing retry"); 18249243SN/A 18259243SN/A readRowHits 18269243SN/A .name(name() + ".readRowHits") 18279243SN/A .desc("Number of row buffer hits during reads"); 18289243SN/A 18299243SN/A writeRowHits 18309243SN/A .name(name() + ".writeRowHits") 18319243SN/A .desc("Number of row buffer hits during writes"); 18329243SN/A 18339243SN/A readRowHitRate 18349243SN/A .name(name() + ".readRowHitRate") 18359243SN/A .desc("Row buffer hit rate for reads") 18369243SN/A .precision(2); 18379243SN/A 18389831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 18399243SN/A 18409243SN/A writeRowHitRate 18419243SN/A .name(name() + ".writeRowHitRate") 18429243SN/A .desc("Row buffer hit rate for writes") 18439243SN/A .precision(2); 18449243SN/A 18459977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 18469243SN/A 18479243SN/A readPktSize 18489831SN/A .init(ceilLog2(burstSize) + 1) 18499243SN/A .name(name() + ".readPktSize") 18509977SN/A .desc("Read request sizes (log2)"); 18519243SN/A 18529243SN/A writePktSize 18539831SN/A .init(ceilLog2(burstSize) + 1) 18549243SN/A .name(name() + ".writePktSize") 18559977SN/A .desc("Write request sizes (log2)"); 18569243SN/A 18579243SN/A rdQLenPdf 18589567SN/A .init(readBufferSize) 18599243SN/A .name(name() + ".rdQLenPdf") 18609243SN/A .desc("What read queue length does an incoming req see"); 18619243SN/A 18629243SN/A wrQLenPdf 18639567SN/A .init(writeBufferSize) 18649243SN/A .name(name() + ".wrQLenPdf") 18659243SN/A .desc("What write queue length does an incoming req see"); 18669243SN/A 18679727SN/A bytesPerActivate 186810141SN/A .init(maxAccessesPerRow) 18699727SN/A .name(name() + ".bytesPerActivate") 18709727SN/A .desc("Bytes accessed per row activation") 18719727SN/A .flags(nozero); 18729243SN/A 187310147Sandreas.hansson@arm.com rdPerTurnAround 187410147Sandreas.hansson@arm.com .init(readBufferSize) 187510147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 187610147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 187710147Sandreas.hansson@arm.com .flags(nozero); 187810147Sandreas.hansson@arm.com 187910147Sandreas.hansson@arm.com wrPerTurnAround 188010147Sandreas.hansson@arm.com .init(writeBufferSize) 188110147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 188210147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 188310147Sandreas.hansson@arm.com .flags(nozero); 188410147Sandreas.hansson@arm.com 18859975SN/A bytesReadDRAM 18869975SN/A .name(name() + ".bytesReadDRAM") 18879975SN/A .desc("Total number of bytes read from DRAM"); 18889975SN/A 18899975SN/A bytesReadWrQ 18909975SN/A .name(name() + ".bytesReadWrQ") 18919975SN/A .desc("Total number of bytes read from write queue"); 18929243SN/A 18939243SN/A bytesWritten 18949243SN/A .name(name() + ".bytesWritten") 18959977SN/A .desc("Total number of bytes written to DRAM"); 18969243SN/A 18979977SN/A bytesReadSys 18989977SN/A .name(name() + ".bytesReadSys") 18999977SN/A .desc("Total read bytes from the system interface side"); 19009243SN/A 19019977SN/A bytesWrittenSys 19029977SN/A .name(name() + ".bytesWrittenSys") 19039977SN/A .desc("Total written bytes from the system interface side"); 19049243SN/A 19059243SN/A avgRdBW 19069243SN/A .name(name() + ".avgRdBW") 19079977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 19089243SN/A .precision(2); 19099243SN/A 19109977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 19119243SN/A 19129243SN/A avgWrBW 19139243SN/A .name(name() + ".avgWrBW") 19149977SN/A .desc("Average achieved write bandwidth in MiByte/s") 19159243SN/A .precision(2); 19169243SN/A 19179243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 19189243SN/A 19199977SN/A avgRdBWSys 19209977SN/A .name(name() + ".avgRdBWSys") 19219977SN/A .desc("Average system read bandwidth in MiByte/s") 19229243SN/A .precision(2); 19239243SN/A 19249977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 19259243SN/A 19269977SN/A avgWrBWSys 19279977SN/A .name(name() + ".avgWrBWSys") 19289977SN/A .desc("Average system write bandwidth in MiByte/s") 19299243SN/A .precision(2); 19309243SN/A 19319977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 19329243SN/A 19339243SN/A peakBW 19349243SN/A .name(name() + ".peakBW") 19359977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 19369243SN/A .precision(2); 19379243SN/A 19389831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 19399243SN/A 19409243SN/A busUtil 19419243SN/A .name(name() + ".busUtil") 19429243SN/A .desc("Data bus utilization in percentage") 19439243SN/A .precision(2); 19449243SN/A 19459243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 19469243SN/A 19479243SN/A totGap 19489243SN/A .name(name() + ".totGap") 19499243SN/A .desc("Total gap between requests"); 19509243SN/A 19519243SN/A avgGap 19529243SN/A .name(name() + ".avgGap") 19539243SN/A .desc("Average gap between requests") 19549243SN/A .precision(2); 19559243SN/A 19569243SN/A avgGap = totGap / (readReqs + writeReqs); 19579975SN/A 19589975SN/A // Stats for DRAM Power calculation based on Micron datasheet 19599975SN/A busUtilRead 19609975SN/A .name(name() + ".busUtilRead") 19619975SN/A .desc("Data bus utilization in percentage for reads") 19629975SN/A .precision(2); 19639975SN/A 19649975SN/A busUtilRead = avgRdBW / peakBW * 100; 19659975SN/A 19669975SN/A busUtilWrite 19679975SN/A .name(name() + ".busUtilWrite") 19689975SN/A .desc("Data bus utilization in percentage for writes") 19699975SN/A .precision(2); 19709975SN/A 19719975SN/A busUtilWrite = avgWrBW / peakBW * 100; 19729975SN/A 19739975SN/A pageHitRate 19749975SN/A .name(name() + ".pageHitRate") 19759975SN/A .desc("Row buffer hit rate, read and write combined") 19769975SN/A .precision(2); 19779975SN/A 19789977SN/A pageHitRate = (writeRowHits + readRowHits) / 19799977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 19809975SN/A 198110208Sandreas.hansson@arm.com pwrStateTime 198210208Sandreas.hansson@arm.com .init(5) 198310208Sandreas.hansson@arm.com .name(name() + ".memoryStateTime") 198410208Sandreas.hansson@arm.com .desc("Time in different power states"); 198510208Sandreas.hansson@arm.com pwrStateTime.subname(0, "IDLE"); 198610208Sandreas.hansson@arm.com pwrStateTime.subname(1, "REF"); 198710208Sandreas.hansson@arm.com pwrStateTime.subname(2, "PRE_PDN"); 198810208Sandreas.hansson@arm.com pwrStateTime.subname(3, "ACT"); 198910208Sandreas.hansson@arm.com pwrStateTime.subname(4, "ACT_PDN"); 199010432SOmar.Naji@arm.com 199110432SOmar.Naji@arm.com actEnergy 199210432SOmar.Naji@arm.com .init(ranksPerChannel) 199310432SOmar.Naji@arm.com .name(name() + ".actEnergy") 199410432SOmar.Naji@arm.com .desc("Energy for activate commands per rank (pJ)"); 199510432SOmar.Naji@arm.com 199610432SOmar.Naji@arm.com preEnergy 199710432SOmar.Naji@arm.com .init(ranksPerChannel) 199810432SOmar.Naji@arm.com .name(name() + ".preEnergy") 199910432SOmar.Naji@arm.com .desc("Energy for precharge commands per rank (pJ)"); 200010432SOmar.Naji@arm.com 200110432SOmar.Naji@arm.com readEnergy 200210432SOmar.Naji@arm.com .init(ranksPerChannel) 200310432SOmar.Naji@arm.com .name(name() + ".readEnergy") 200410432SOmar.Naji@arm.com .desc("Energy for read commands per rank (pJ)"); 200510432SOmar.Naji@arm.com 200610432SOmar.Naji@arm.com writeEnergy 200710432SOmar.Naji@arm.com .init(ranksPerChannel) 200810432SOmar.Naji@arm.com .name(name() + ".writeEnergy") 200910432SOmar.Naji@arm.com .desc("Energy for write commands per rank (pJ)"); 201010432SOmar.Naji@arm.com 201110432SOmar.Naji@arm.com refreshEnergy 201210432SOmar.Naji@arm.com .init(ranksPerChannel) 201310432SOmar.Naji@arm.com .name(name() + ".refreshEnergy") 201410432SOmar.Naji@arm.com .desc("Energy for refresh commands per rank (pJ)"); 201510432SOmar.Naji@arm.com 201610432SOmar.Naji@arm.com actBackEnergy 201710432SOmar.Naji@arm.com .init(ranksPerChannel) 201810432SOmar.Naji@arm.com .name(name() + ".actBackEnergy") 201910432SOmar.Naji@arm.com .desc("Energy for active background per rank (pJ)"); 202010432SOmar.Naji@arm.com 202110432SOmar.Naji@arm.com preBackEnergy 202210432SOmar.Naji@arm.com .init(ranksPerChannel) 202310432SOmar.Naji@arm.com .name(name() + ".preBackEnergy") 202410432SOmar.Naji@arm.com .desc("Energy for precharge background per rank (pJ)"); 202510432SOmar.Naji@arm.com 202610432SOmar.Naji@arm.com totalEnergy 202710432SOmar.Naji@arm.com .init(ranksPerChannel) 202810432SOmar.Naji@arm.com .name(name() + ".totalEnergy") 202910432SOmar.Naji@arm.com .desc("Total energy per rank (pJ)"); 203010432SOmar.Naji@arm.com 203110432SOmar.Naji@arm.com averagePower 203210432SOmar.Naji@arm.com .init(ranksPerChannel) 203310432SOmar.Naji@arm.com .name(name() + ".averagePower") 203410432SOmar.Naji@arm.com .desc("Core power per rank (mW)"); 20359243SN/A} 20369243SN/A 20379243SN/Avoid 203810146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 20399243SN/A{ 20409243SN/A // rely on the abstract memory 20419243SN/A functionalAccess(pkt); 20429243SN/A} 20439243SN/A 20449294SN/ABaseSlavePort& 204510146Sandreas.hansson@arm.comDRAMCtrl::getSlavePort(const string &if_name, PortID idx) 20469243SN/A{ 20479243SN/A if (if_name != "port") { 20489243SN/A return MemObject::getSlavePort(if_name, idx); 20499243SN/A } else { 20509243SN/A return port; 20519243SN/A } 20529243SN/A} 20539243SN/A 20549243SN/Aunsigned int 205510146Sandreas.hansson@arm.comDRAMCtrl::drain(DrainManager *dm) 20569243SN/A{ 20579342SN/A unsigned int count = port.drain(dm); 20589243SN/A 20599243SN/A // if there is anything in any of our internal queues, keep track 20609243SN/A // of that as well 20619567SN/A if (!(writeQueue.empty() && readQueue.empty() && 20629567SN/A respQueue.empty())) { 20639352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 20649567SN/A " resp: %d\n", writeQueue.size(), readQueue.size(), 20659567SN/A respQueue.size()); 20669243SN/A ++count; 20679342SN/A drainManager = dm; 206810206Sandreas.hansson@arm.com 20699352SN/A // the only part that is not drained automatically over time 207010206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 207110206Sandreas.hansson@arm.com if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 207210206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 207310206Sandreas.hansson@arm.com } 20749243SN/A } 20759243SN/A 20769243SN/A if (count) 20779342SN/A setDrainState(Drainable::Draining); 20789243SN/A else 20799342SN/A setDrainState(Drainable::Drained); 20809243SN/A return count; 20819243SN/A} 20829243SN/A 208310146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 20849243SN/A : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 20859243SN/A memory(_memory) 20869243SN/A{ } 20879243SN/A 20889243SN/AAddrRangeList 208910146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 20909243SN/A{ 20919243SN/A AddrRangeList ranges; 20929243SN/A ranges.push_back(memory.getAddrRange()); 20939243SN/A return ranges; 20949243SN/A} 20959243SN/A 20969243SN/Avoid 209710146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 20989243SN/A{ 20999243SN/A pkt->pushLabel(memory.name()); 21009243SN/A 21019243SN/A if (!queue.checkFunctional(pkt)) { 21029243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 21039243SN/A // calls recvAtomic() and throws away the latency; we can save a 21049243SN/A // little here by just not calculating the latency. 21059243SN/A memory.recvFunctional(pkt); 21069243SN/A } 21079243SN/A 21089243SN/A pkt->popLabel(); 21099243SN/A} 21109243SN/A 21119243SN/ATick 211210146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 21139243SN/A{ 21149243SN/A return memory.recvAtomic(pkt); 21159243SN/A} 21169243SN/A 21179243SN/Abool 211810146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 21199243SN/A{ 21209243SN/A // pass it to the memory controller 21219243SN/A return memory.recvTimingReq(pkt); 21229243SN/A} 21239243SN/A 212410146Sandreas.hansson@arm.comDRAMCtrl* 212510146Sandreas.hansson@arm.comDRAMCtrlParams::create() 21269243SN/A{ 212710146Sandreas.hansson@arm.com return new DRAMCtrl(this); 21289243SN/A} 2129