dram_ctrl.cc revision 10393
19243SN/A/* 210206Sandreas.hansson@arm.com * Copyright (c) 2010-2014 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 439243SN/A */ 449243SN/A 4510146Sandreas.hansson@arm.com#include "base/bitfield.hh" 469356SN/A#include "base/trace.hh" 4710146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 4810247Sandreas.hansson@arm.com#include "debug/DRAMPower.hh" 4910208Sandreas.hansson@arm.com#include "debug/DRAMState.hh" 509352SN/A#include "debug/Drain.hh" 5110146Sandreas.hansson@arm.com#include "mem/dram_ctrl.hh" 529814SN/A#include "sim/system.hh" 539243SN/A 549243SN/Ausing namespace std; 559243SN/A 5610146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 579243SN/A AbstractMemory(p), 589243SN/A port(name() + ".port", *this), 599243SN/A retryRdReq(false), retryWrReq(false), 6010211Sandreas.hansson@arm.com busState(READ), 6110208Sandreas.hansson@arm.com nextReqEvent(this), respondEvent(this), activateEvent(this), 6210208Sandreas.hansson@arm.com prechargeEvent(this), refreshEvent(this), powerEvent(this), 6310208Sandreas.hansson@arm.com drainManager(NULL), 649831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 659831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 669831SN/A devicesPerRank(p->devices_per_rank), 679831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 689831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 6910140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 7010286Sandreas.hansson@arm.com columnsPerStripe(range.granularity() / burstSize), 719243SN/A ranksPerChannel(p->ranks_per_channel), 729566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 739243SN/A readBufferSize(p->read_buffer_size), 749243SN/A writeBufferSize(p->write_buffer_size), 7510140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 7610140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 7710147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 7810147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 7910393Swendy.elsasser@arm.com tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST), 8010210Sandreas.hansson@arm.com tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), tWR(p->tWR), 8110212Sandreas.hansson@arm.com tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 829488SN/A tXAW(p->tXAW), activationLimit(p->activation_limit), 839243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 849243SN/A pageMgmt(p->page_policy), 8510141SN/A maxAccessesPerRow(p->max_accesses_per_row), 869726SN/A frontendLatency(p->static_frontend_latency), 879726SN/A backendLatency(p->static_backend_latency), 8810208Sandreas.hansson@arm.com busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE), 8910208Sandreas.hansson@arm.com pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), prevArrival(0), 9010393Swendy.elsasser@arm.com nextReqTime(0), pwrStateTick(0), numBanksActive(0), 9110393Swendy.elsasser@arm.com activeRank(0) 929243SN/A{ 939243SN/A // create the bank states based on the dimensions of the ranks and 949243SN/A // banks 959243SN/A banks.resize(ranksPerChannel); 969969SN/A actTicks.resize(ranksPerChannel); 979243SN/A for (size_t c = 0; c < ranksPerChannel; ++c) { 989243SN/A banks[c].resize(banksPerRank); 999969SN/A actTicks[c].resize(activationLimit, 0); 1009243SN/A } 1019243SN/A 10210246Sandreas.hansson@arm.com // set the bank indices 10310246Sandreas.hansson@arm.com for (int r = 0; r < ranksPerChannel; r++) { 10410246Sandreas.hansson@arm.com for (int b = 0; b < banksPerRank; b++) { 10510246Sandreas.hansson@arm.com banks[r][b].rank = r; 10610246Sandreas.hansson@arm.com banks[r][b].bank = b; 10710246Sandreas.hansson@arm.com } 10810246Sandreas.hansson@arm.com } 10910246Sandreas.hansson@arm.com 11010140SN/A // perform a basic check of the write thresholds 11110140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 11210140SN/A fatal("Write buffer low threshold %d must be smaller than the " 11310140SN/A "high threshold %d\n", p->write_low_thresh_perc, 11410140SN/A p->write_high_thresh_perc); 1159243SN/A 1169243SN/A // determine the rows per bank by looking at the total capacity 1179567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1189243SN/A 1199243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1209243SN/A AbstractMemory::size()); 1219831SN/A 1229831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1239831SN/A rowBufferSize, columnsPerRowBuffer); 1249831SN/A 1259831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1269243SN/A 12710286Sandreas.hansson@arm.com // a bit of sanity checks on the interleaving 1289566SN/A if (range.interleaved()) { 1299566SN/A if (channels != range.stripes()) 13010143SN/A fatal("%s has %d interleaved address stripes but %d channel(s)\n", 1319566SN/A name(), range.stripes(), channels); 1329566SN/A 13310136SN/A if (addrMapping == Enums::RoRaBaChCo) { 1349831SN/A if (rowBufferSize != range.granularity()) { 13510286Sandreas.hansson@arm.com fatal("Channel interleaving of %s doesn't match RoRaBaChCo " 13610136SN/A "address map\n", name()); 1379566SN/A } 13810286Sandreas.hansson@arm.com } else if (addrMapping == Enums::RoRaBaCoCh || 13910286Sandreas.hansson@arm.com addrMapping == Enums::RoCoRaBaCh) { 14010286Sandreas.hansson@arm.com // for the interleavings with channel bits in the bottom, 14110286Sandreas.hansson@arm.com // if the system uses a channel striping granularity that 14210286Sandreas.hansson@arm.com // is larger than the DRAM burst size, then map the 14310286Sandreas.hansson@arm.com // sequential accesses within a stripe to a number of 14410286Sandreas.hansson@arm.com // columns in the DRAM, effectively placing some of the 14510286Sandreas.hansson@arm.com // lower-order column bits as the least-significant bits 14610286Sandreas.hansson@arm.com // of the address (above the ones denoting the burst size) 14710286Sandreas.hansson@arm.com assert(columnsPerStripe >= 1); 14810286Sandreas.hansson@arm.com 14910286Sandreas.hansson@arm.com // channel striping has to be done at a granularity that 15010286Sandreas.hansson@arm.com // is equal or larger to a cache line 15110286Sandreas.hansson@arm.com if (system()->cacheLineSize() > range.granularity()) { 15210286Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at least as large " 15310286Sandreas.hansson@arm.com "as the cache line size\n", name()); 1549669SN/A } 15510286Sandreas.hansson@arm.com 15610286Sandreas.hansson@arm.com // ...and equal or smaller than the row-buffer size 15710286Sandreas.hansson@arm.com if (rowBufferSize < range.granularity()) { 15810286Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at most as large " 15910286Sandreas.hansson@arm.com "as the row-buffer size\n", name()); 16010286Sandreas.hansson@arm.com } 16110286Sandreas.hansson@arm.com // this is essentially the check above, so just to be sure 16210286Sandreas.hansson@arm.com assert(columnsPerStripe <= columnsPerRowBuffer); 1639566SN/A } 1649566SN/A } 16510207Sandreas.hansson@arm.com 16610207Sandreas.hansson@arm.com // some basic sanity checks 16710207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 16810207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 16910207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 17010207Sandreas.hansson@arm.com } 1719243SN/A} 1729243SN/A 1739243SN/Avoid 17410146Sandreas.hansson@arm.comDRAMCtrl::init() 17510140SN/A{ 17610140SN/A if (!port.isConnected()) { 17710146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 17810140SN/A } else { 17910140SN/A port.sendRangeChange(); 18010140SN/A } 18110140SN/A} 18210140SN/A 18310140SN/Avoid 18410146Sandreas.hansson@arm.comDRAMCtrl::startup() 1859243SN/A{ 18610143SN/A // update the start tick for the precharge accounting to the 18710143SN/A // current tick 18810208Sandreas.hansson@arm.com pwrStateTick = curTick(); 18910143SN/A 19010206Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 19110206Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 19210206Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 19310206Sandreas.hansson@arm.com // start of simulation 19410206Sandreas.hansson@arm.com busBusyUntil = curTick() + tRP + tRCD + tCL; 19510206Sandreas.hansson@arm.com 19610207Sandreas.hansson@arm.com // kick off the refresh, and give ourselves enough time to 19710207Sandreas.hansson@arm.com // precharge 19810207Sandreas.hansson@arm.com schedule(refreshEvent, curTick() + tREFI - tRP); 1999243SN/A} 2009243SN/A 2019243SN/ATick 20210146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 2039243SN/A{ 2049243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 2059243SN/A 2069243SN/A // do the actual memory access and turn the packet into a response 2079243SN/A access(pkt); 2089243SN/A 2099243SN/A Tick latency = 0; 2109243SN/A if (!pkt->memInhibitAsserted() && pkt->hasData()) { 2119243SN/A // this value is not supposed to be accurate, just enough to 2129243SN/A // keep things going, mimic a closed page 2139243SN/A latency = tRP + tRCD + tCL; 2149243SN/A } 2159243SN/A return latency; 2169243SN/A} 2179243SN/A 2189243SN/Abool 21910146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 2209243SN/A{ 2219831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 2229831SN/A readBufferSize, readQueue.size() + respQueue.size(), 2239831SN/A neededEntries); 2249243SN/A 2259831SN/A return 2269831SN/A (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 2279243SN/A} 2289243SN/A 2299243SN/Abool 23010146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 2319243SN/A{ 2329831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 2339831SN/A writeBufferSize, writeQueue.size(), neededEntries); 2349831SN/A return (writeQueue.size() + neededEntries) > writeBufferSize; 2359243SN/A} 2369243SN/A 23710146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 23810146Sandreas.hansson@arm.comDRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 23910143SN/A bool isRead) 2409243SN/A{ 2419669SN/A // decode the address based on the address mapping scheme, with 24210136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 24310136SN/A // channel, respectively 2449243SN/A uint8_t rank; 2459967SN/A uint8_t bank; 24610245Sandreas.hansson@arm.com // use a 64-bit unsigned during the computations as the row is 24710245Sandreas.hansson@arm.com // always the top bits, and check before creating the DRAMPacket 24810245Sandreas.hansson@arm.com uint64_t row; 2499243SN/A 25010286Sandreas.hansson@arm.com // truncate the address to a DRAM burst, which makes it unique to 25110286Sandreas.hansson@arm.com // a specific column, row, bank, rank and channel 2529831SN/A Addr addr = dramPktAddr / burstSize; 2539243SN/A 2549491SN/A // we have removed the lowest order address bits that denote the 2559831SN/A // position within the column 25610136SN/A if (addrMapping == Enums::RoRaBaChCo) { 2579491SN/A // the lowest order bits denote the column to ensure that 2589491SN/A // sequential cache lines occupy the same row 2599831SN/A addr = addr / columnsPerRowBuffer; 2609243SN/A 2619669SN/A // take out the channel part of the address 2629566SN/A addr = addr / channels; 2639566SN/A 2649669SN/A // after the channel bits, get the bank bits to interleave 2659669SN/A // over the banks 2669669SN/A bank = addr % banksPerRank; 2679669SN/A addr = addr / banksPerRank; 2689669SN/A 2699669SN/A // after the bank, we get the rank bits which thus interleaves 2709669SN/A // over the ranks 2719669SN/A rank = addr % ranksPerChannel; 2729669SN/A addr = addr / ranksPerChannel; 2739669SN/A 2749669SN/A // lastly, get the row bits 2759669SN/A row = addr % rowsPerBank; 2769669SN/A addr = addr / rowsPerBank; 27710136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 27810286Sandreas.hansson@arm.com // take out the lower-order column bits 27910286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 28010286Sandreas.hansson@arm.com 2819669SN/A // take out the channel part of the address 2829669SN/A addr = addr / channels; 2839669SN/A 28410286Sandreas.hansson@arm.com // next, the higher-order column bites 28510286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 2869669SN/A 2879669SN/A // after the column bits, we get the bank bits to interleave 2889491SN/A // over the banks 2899243SN/A bank = addr % banksPerRank; 2909243SN/A addr = addr / banksPerRank; 2919243SN/A 2929491SN/A // after the bank, we get the rank bits which thus interleaves 2939491SN/A // over the ranks 2949243SN/A rank = addr % ranksPerChannel; 2959243SN/A addr = addr / ranksPerChannel; 2969243SN/A 2979491SN/A // lastly, get the row bits 2989243SN/A row = addr % rowsPerBank; 2999243SN/A addr = addr / rowsPerBank; 30010136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 3019491SN/A // optimise for closed page mode and utilise maximum 3029491SN/A // parallelism of the DRAM (at the cost of power) 3039491SN/A 30410286Sandreas.hansson@arm.com // take out the lower-order column bits 30510286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 30610286Sandreas.hansson@arm.com 3079566SN/A // take out the channel part of the address, not that this has 3089566SN/A // to match with how accesses are interleaved between the 3099566SN/A // controllers in the address mapping 3109566SN/A addr = addr / channels; 3119566SN/A 3129491SN/A // start with the bank bits, as this provides the maximum 3139491SN/A // opportunity for parallelism between requests 3149243SN/A bank = addr % banksPerRank; 3159243SN/A addr = addr / banksPerRank; 3169243SN/A 3179491SN/A // next get the rank bits 3189243SN/A rank = addr % ranksPerChannel; 3199243SN/A addr = addr / ranksPerChannel; 3209243SN/A 32110286Sandreas.hansson@arm.com // next, the higher-order column bites 32210286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3239243SN/A 3249491SN/A // lastly, get the row bits 3259243SN/A row = addr % rowsPerBank; 3269243SN/A addr = addr / rowsPerBank; 3279243SN/A } else 3289243SN/A panic("Unknown address mapping policy chosen!"); 3299243SN/A 3309243SN/A assert(rank < ranksPerChannel); 3319243SN/A assert(bank < banksPerRank); 3329243SN/A assert(row < rowsPerBank); 33310245Sandreas.hansson@arm.com assert(row < Bank::NO_ROW); 3349243SN/A 3359243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 3369831SN/A dramPktAddr, rank, bank, row); 3379243SN/A 3389243SN/A // create the corresponding DRAM packet with the entry time and 3399567SN/A // ready time set to the current tick, the latter will be updated 3409567SN/A // later 3419967SN/A uint16_t bank_id = banksPerRank * rank + bank; 3429967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 3439967SN/A size, banks[rank][bank]); 3449243SN/A} 3459243SN/A 3469243SN/Avoid 34710146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 3489243SN/A{ 3499243SN/A // only add to the read queue here. whenever the request is 3509243SN/A // eventually done, set the readyTime, and call schedule() 3519243SN/A assert(!pkt->isWrite()); 3529243SN/A 3539831SN/A assert(pktCount != 0); 3549831SN/A 3559831SN/A // if the request size is larger than burst size, the pkt is split into 3569831SN/A // multiple DRAM packets 3579831SN/A // Note if the pkt starting address is not aligened to burst size, the 3589831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 3599831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 3609831SN/A // check read packets against packets in write queue. 3619243SN/A Addr addr = pkt->getAddr(); 3629831SN/A unsigned pktsServicedByWrQ = 0; 3639831SN/A BurstHelper* burst_helper = NULL; 3649831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 3659831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 3669831SN/A pkt->getAddr() + pkt->getSize()) - addr; 3679831SN/A readPktSize[ceilLog2(size)]++; 3689831SN/A readBursts++; 3699243SN/A 3709831SN/A // First check write buffer to see if the data is already at 3719831SN/A // the controller 3729831SN/A bool foundInWrQ = false; 3739833SN/A for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) { 3749832SN/A // check if the read is subsumed in the write entry we are 3759832SN/A // looking at 3769832SN/A if ((*i)->addr <= addr && 3779832SN/A (addr + size) <= ((*i)->addr + (*i)->size)) { 3789831SN/A foundInWrQ = true; 3799831SN/A servicedByWrQ++; 3809831SN/A pktsServicedByWrQ++; 3819831SN/A DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 3829831SN/A "write queue\n", addr, size); 3839975SN/A bytesReadWrQ += burstSize; 3849831SN/A break; 3859831SN/A } 3869243SN/A } 3879831SN/A 3889831SN/A // If not found in the write q, make a DRAM packet and 3899831SN/A // push it onto the read queue 3909831SN/A if (!foundInWrQ) { 3919831SN/A 3929831SN/A // Make the burst helper for split packets 3939831SN/A if (pktCount > 1 && burst_helper == NULL) { 3949831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 3959831SN/A "dram requests\n", pkt->getAddr(), pktCount); 3969831SN/A burst_helper = new BurstHelper(pktCount); 3979831SN/A } 3989831SN/A 3999966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 4009831SN/A dram_pkt->burstHelper = burst_helper; 4019831SN/A 4029831SN/A assert(!readQueueFull(1)); 4039831SN/A rdQLenPdf[readQueue.size() + respQueue.size()]++; 4049831SN/A 4059831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 4069831SN/A 4079831SN/A readQueue.push_back(dram_pkt); 4089831SN/A 4099831SN/A // Update stats 4109831SN/A avgRdQLen = readQueue.size() + respQueue.size(); 4119831SN/A } 4129831SN/A 4139831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 4149831SN/A addr = (addr | (burstSize - 1)) + 1; 4159243SN/A } 4169243SN/A 4179831SN/A // If all packets are serviced by write queue, we send the repsonse back 4189831SN/A if (pktsServicedByWrQ == pktCount) { 4199831SN/A accessAndRespond(pkt, frontendLatency); 4209831SN/A return; 4219831SN/A } 4229243SN/A 4239831SN/A // Update how many split packets are serviced by write queue 4249831SN/A if (burst_helper != NULL) 4259831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 4269243SN/A 42710206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 42810206Sandreas.hansson@arm.com // queue, do so now 42910206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 4309567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 4319567SN/A schedule(nextReqEvent, curTick()); 4329243SN/A } 4339243SN/A} 4349243SN/A 4359243SN/Avoid 43610146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 4379243SN/A{ 4389243SN/A // only add to the write queue here. whenever the request is 4399243SN/A // eventually done, set the readyTime, and call schedule() 4409243SN/A assert(pkt->isWrite()); 4419243SN/A 4429831SN/A // if the request size is larger than burst size, the pkt is split into 4439831SN/A // multiple DRAM packets 4449831SN/A Addr addr = pkt->getAddr(); 4459831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4469831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4479831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4489831SN/A writePktSize[ceilLog2(size)]++; 4499831SN/A writeBursts++; 4509243SN/A 4519832SN/A // see if we can merge with an existing item in the write 4529838SN/A // queue and keep track of whether we have merged or not so we 4539838SN/A // can stop at that point and also avoid enqueueing a new 4549838SN/A // request 4559832SN/A bool merged = false; 4569832SN/A auto w = writeQueue.begin(); 4579243SN/A 4589832SN/A while(!merged && w != writeQueue.end()) { 4599832SN/A // either of the two could be first, if they are the same 4609832SN/A // it does not matter which way we go 4619832SN/A if ((*w)->addr >= addr) { 4629838SN/A // the existing one starts after the new one, figure 4639838SN/A // out where the new one ends with respect to the 4649838SN/A // existing one 4659832SN/A if ((addr + size) >= ((*w)->addr + (*w)->size)) { 4669832SN/A // check if the existing one is completely 4679832SN/A // subsumed in the new one 4689832SN/A DPRINTF(DRAM, "Merging write covering existing burst\n"); 4699832SN/A merged = true; 4709832SN/A // update both the address and the size 4719832SN/A (*w)->addr = addr; 4729832SN/A (*w)->size = size; 4739832SN/A } else if ((addr + size) >= (*w)->addr && 4749832SN/A ((*w)->addr + (*w)->size - addr) <= burstSize) { 4759832SN/A // the new one is just before or partially 4769832SN/A // overlapping with the existing one, and together 4779832SN/A // they fit within a burst 4789832SN/A DPRINTF(DRAM, "Merging write before existing burst\n"); 4799832SN/A merged = true; 4809832SN/A // the existing queue item needs to be adjusted with 4819832SN/A // respect to both address and size 48210047SN/A (*w)->size = (*w)->addr + (*w)->size - addr; 4839832SN/A (*w)->addr = addr; 4849832SN/A } 4859832SN/A } else { 4869838SN/A // the new one starts after the current one, figure 4879838SN/A // out where the existing one ends with respect to the 4889838SN/A // new one 4899832SN/A if (((*w)->addr + (*w)->size) >= (addr + size)) { 4909832SN/A // check if the new one is completely subsumed in the 4919832SN/A // existing one 4929832SN/A DPRINTF(DRAM, "Merging write into existing burst\n"); 4939832SN/A merged = true; 4949832SN/A // no adjustments necessary 4959832SN/A } else if (((*w)->addr + (*w)->size) >= addr && 4969832SN/A (addr + size - (*w)->addr) <= burstSize) { 4979832SN/A // the existing one is just before or partially 4989832SN/A // overlapping with the new one, and together 4999832SN/A // they fit within a burst 5009832SN/A DPRINTF(DRAM, "Merging write after existing burst\n"); 5019832SN/A merged = true; 5029832SN/A // the address is right, and only the size has 5039832SN/A // to be adjusted 5049832SN/A (*w)->size = addr + size - (*w)->addr; 5059832SN/A } 5069832SN/A } 5079832SN/A ++w; 5089832SN/A } 5099243SN/A 5109832SN/A // if the item was not merged we need to create a new write 5119832SN/A // and enqueue it 5129832SN/A if (!merged) { 5139966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 5149243SN/A 5159832SN/A assert(writeQueue.size() < writeBufferSize); 5169832SN/A wrQLenPdf[writeQueue.size()]++; 5179243SN/A 5189832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 5199831SN/A 5209832SN/A writeQueue.push_back(dram_pkt); 5219831SN/A 5229832SN/A // Update stats 5239832SN/A avgWrQLen = writeQueue.size(); 5249977SN/A } else { 5259977SN/A // keep track of the fact that this burst effectively 5269977SN/A // disappeared as it was merged with an existing one 5279977SN/A mergedWrBursts++; 5289832SN/A } 5299832SN/A 5309831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 5319831SN/A addr = (addr | (burstSize - 1)) + 1; 5329831SN/A } 5339243SN/A 5349243SN/A // we do not wait for the writes to be send to the actual memory, 5359243SN/A // but instead take responsibility for the consistency here and 5369243SN/A // snoop the write queue for any upcoming reads 5379831SN/A // @todo, if a pkt size is larger than burst size, we might need a 5389831SN/A // different front end latency 5399726SN/A accessAndRespond(pkt, frontendLatency); 5409243SN/A 54110206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 54210206Sandreas.hansson@arm.com // queue, do so now 54310206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 54410206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 54510206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 5469243SN/A } 5479243SN/A} 5489243SN/A 5499243SN/Avoid 55010146Sandreas.hansson@arm.comDRAMCtrl::printQs() const { 5519243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 5529833SN/A for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 5539243SN/A DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 5549243SN/A } 5559243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 5569833SN/A for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 5579243SN/A DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 5589243SN/A } 5599243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 5609833SN/A for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 5619243SN/A DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 5629243SN/A } 5639243SN/A} 5649243SN/A 5659243SN/Abool 56610146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 5679243SN/A{ 5689349SN/A /// @todo temporary hack to deal with memory corruption issues until 5699349SN/A /// 4-phase transactions are complete 5709349SN/A for (int x = 0; x < pendingDelete.size(); x++) 5719349SN/A delete pendingDelete[x]; 5729349SN/A pendingDelete.clear(); 5739349SN/A 5749243SN/A // This is where we enter from the outside world 5759567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 5769831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 5779243SN/A 5789567SN/A // simply drop inhibited packets for now 5799567SN/A if (pkt->memInhibitAsserted()) { 58010143SN/A DPRINTF(DRAM, "Inhibited packet -- Dropping it now\n"); 5819567SN/A pendingDelete.push_back(pkt); 5829567SN/A return true; 5839567SN/A } 5849243SN/A 5859243SN/A // Calc avg gap between requests 5869243SN/A if (prevArrival != 0) { 5879243SN/A totGap += curTick() - prevArrival; 5889243SN/A } 5899243SN/A prevArrival = curTick(); 5909243SN/A 5919831SN/A 5929831SN/A // Find out how many dram packets a pkt translates to 5939831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 5949831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 5959831SN/A // multiple dram packets 5969243SN/A unsigned size = pkt->getSize(); 5979831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 5989831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 5999243SN/A 6009243SN/A // check local buffers and do not accept if full 6019243SN/A if (pkt->isRead()) { 6029567SN/A assert(size != 0); 6039831SN/A if (readQueueFull(dram_pkt_count)) { 6049567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 6059243SN/A // remember that we have to retry this port 6069243SN/A retryRdReq = true; 6079243SN/A numRdRetry++; 6089243SN/A return false; 6099243SN/A } else { 6109831SN/A addToReadQueue(pkt, dram_pkt_count); 6119243SN/A readReqs++; 6129977SN/A bytesReadSys += size; 6139243SN/A } 6149243SN/A } else if (pkt->isWrite()) { 6159567SN/A assert(size != 0); 6169831SN/A if (writeQueueFull(dram_pkt_count)) { 6179567SN/A DPRINTF(DRAM, "Write queue full, not accepting\n"); 6189243SN/A // remember that we have to retry this port 6199243SN/A retryWrReq = true; 6209243SN/A numWrRetry++; 6219243SN/A return false; 6229243SN/A } else { 6239831SN/A addToWriteQueue(pkt, dram_pkt_count); 6249243SN/A writeReqs++; 6259977SN/A bytesWrittenSys += size; 6269243SN/A } 6279243SN/A } else { 6289243SN/A DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 6299243SN/A neitherReadNorWrite++; 6309726SN/A accessAndRespond(pkt, 1); 6319243SN/A } 6329243SN/A 6339243SN/A return true; 6349243SN/A} 6359243SN/A 6369243SN/Avoid 63710146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 6389243SN/A{ 6399243SN/A DPRINTF(DRAM, 6409243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 6419243SN/A 6429831SN/A DRAMPacket* dram_pkt = respQueue.front(); 6439243SN/A 6449831SN/A if (dram_pkt->burstHelper) { 6459831SN/A // it is a split packet 6469831SN/A dram_pkt->burstHelper->burstsServiced++; 6479831SN/A if (dram_pkt->burstHelper->burstsServiced == 64810143SN/A dram_pkt->burstHelper->burstCount) { 6499831SN/A // we have now serviced all children packets of a system packet 6509831SN/A // so we can now respond to the requester 6519831SN/A // @todo we probably want to have a different front end and back 6529831SN/A // end latency for split packets 6539831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6549831SN/A delete dram_pkt->burstHelper; 6559831SN/A dram_pkt->burstHelper = NULL; 6569831SN/A } 6579831SN/A } else { 6589831SN/A // it is not a split packet 6599831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6609831SN/A } 6619243SN/A 6629831SN/A delete respQueue.front(); 6639831SN/A respQueue.pop_front(); 6649243SN/A 6659831SN/A if (!respQueue.empty()) { 6669831SN/A assert(respQueue.front()->readyTime >= curTick()); 6679831SN/A assert(!respondEvent.scheduled()); 6689831SN/A schedule(respondEvent, respQueue.front()->readyTime); 6699831SN/A } else { 6709831SN/A // if there is nothing left in any queue, signal a drain 6719831SN/A if (writeQueue.empty() && readQueue.empty() && 6729831SN/A drainManager) { 6739831SN/A drainManager->signalDrainDone(); 6749831SN/A drainManager = NULL; 6759831SN/A } 6769831SN/A } 6779567SN/A 6789831SN/A // We have made a location in the queue available at this point, 6799831SN/A // so if there is a read that was forced to wait, retry now 6809831SN/A if (retryRdReq) { 6819831SN/A retryRdReq = false; 6829831SN/A port.sendRetry(); 6839831SN/A } 6849243SN/A} 6859243SN/A 6869243SN/Avoid 68710393Swendy.elsasser@arm.comDRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue, bool switched_cmd_type) 6889243SN/A{ 68910206Sandreas.hansson@arm.com // This method does the arbitration between requests. The chosen 69010206Sandreas.hansson@arm.com // packet is simply moved to the head of the queue. The other 69110206Sandreas.hansson@arm.com // methods know that this is the place to look. For example, with 69210206Sandreas.hansson@arm.com // FCFS, this method does nothing 69310206Sandreas.hansson@arm.com assert(!queue.empty()); 6949243SN/A 69510206Sandreas.hansson@arm.com if (queue.size() == 1) { 69610206Sandreas.hansson@arm.com DPRINTF(DRAM, "Single request, nothing to do\n"); 6979243SN/A return; 6989243SN/A } 6999243SN/A 7009243SN/A if (memSchedPolicy == Enums::fcfs) { 7019243SN/A // Do nothing, since the correct request is already head 7029243SN/A } else if (memSchedPolicy == Enums::frfcfs) { 70310393Swendy.elsasser@arm.com reorderQueue(queue, switched_cmd_type); 7049243SN/A } else 7059243SN/A panic("No scheduling policy chosen\n"); 7069243SN/A} 7079243SN/A 7089243SN/Avoid 70910393Swendy.elsasser@arm.comDRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue, bool switched_cmd_type) 7109974SN/A{ 7119974SN/A // Only determine this when needed 7129974SN/A uint64_t earliest_banks = 0; 7139974SN/A 7149974SN/A // Search for row hits first, if no row hit is found then schedule the 7159974SN/A // packet to one of the earliest banks available 7169974SN/A bool found_earliest_pkt = false; 71710393Swendy.elsasser@arm.com bool found_prepped_diff_rank_pkt = false; 7189974SN/A auto selected_pkt_it = queue.begin(); 7199974SN/A 7209974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 7219974SN/A DRAMPacket* dram_pkt = *i; 7229974SN/A const Bank& bank = dram_pkt->bankRef; 7239974SN/A // Check if it is a row hit 7249974SN/A if (bank.openRow == dram_pkt->row) { 72510393Swendy.elsasser@arm.com if (dram_pkt->rank == activeRank || switched_cmd_type) { 72610393Swendy.elsasser@arm.com // FCFS within the hits, giving priority to commands 72710393Swendy.elsasser@arm.com // that access the same rank as the previous burst 72810393Swendy.elsasser@arm.com // to minimize bus turnaround delays 72910393Swendy.elsasser@arm.com // Only give rank prioity when command type is not changing 73010393Swendy.elsasser@arm.com DPRINTF(DRAM, "Row buffer hit\n"); 73110393Swendy.elsasser@arm.com selected_pkt_it = i; 73210393Swendy.elsasser@arm.com break; 73310393Swendy.elsasser@arm.com } else if (!found_prepped_diff_rank_pkt) { 73410393Swendy.elsasser@arm.com // found row hit for command on different rank than prev burst 73510393Swendy.elsasser@arm.com selected_pkt_it = i; 73610393Swendy.elsasser@arm.com found_prepped_diff_rank_pkt = true; 73710393Swendy.elsasser@arm.com } 73810393Swendy.elsasser@arm.com } else if (!found_earliest_pkt & !found_prepped_diff_rank_pkt) { 73910393Swendy.elsasser@arm.com // No row hit and 74010393Swendy.elsasser@arm.com // haven't found an entry with a row hit to a new rank 7419974SN/A if (earliest_banks == 0) 74210393Swendy.elsasser@arm.com // Determine entries with earliest bank prep delay 74310393Swendy.elsasser@arm.com // Function will give priority to commands that access the 74410393Swendy.elsasser@arm.com // same rank as previous burst and can prep the bank seamlessly 74510393Swendy.elsasser@arm.com earliest_banks = minBankPrep(queue, switched_cmd_type); 74610211Sandreas.hansson@arm.com 74710393Swendy.elsasser@arm.com // FCFS - Bank is first available bank 74810393Swendy.elsasser@arm.com if (bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) { 7499974SN/A // Remember the packet to be scheduled to one of the earliest 75010211Sandreas.hansson@arm.com // banks available, FCFS amongst the earliest banks 7519974SN/A selected_pkt_it = i; 7529974SN/A found_earliest_pkt = true; 7539974SN/A } 7549974SN/A } 7559974SN/A } 7569974SN/A 7579974SN/A DRAMPacket* selected_pkt = *selected_pkt_it; 7589974SN/A queue.erase(selected_pkt_it); 7599974SN/A queue.push_front(selected_pkt); 7609974SN/A} 7619974SN/A 7629974SN/Avoid 76310146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 7649243SN/A{ 7659243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 7669243SN/A 7679243SN/A bool needsResponse = pkt->needsResponse(); 7689243SN/A // do the actual memory access which also turns the packet into a 7699243SN/A // response 7709243SN/A access(pkt); 7719243SN/A 7729243SN/A // turn packet around to go back to requester if response expected 7739243SN/A if (needsResponse) { 7749243SN/A // access already turned the packet into a response 7759243SN/A assert(pkt->isResponse()); 7769243SN/A 7779549SN/A // @todo someone should pay for this 7789549SN/A pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; 7799549SN/A 7809726SN/A // queue the packet in the response queue to be sent out after 7819726SN/A // the static latency has passed 7829726SN/A port.schedTimingResp(pkt, curTick() + static_latency); 7839243SN/A } else { 7849587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 7859587SN/A // is still having a pointer to it 7869587SN/A pendingDelete.push_back(pkt); 7879243SN/A } 7889243SN/A 7899243SN/A DPRINTF(DRAM, "Done\n"); 7909243SN/A 7919243SN/A return; 7929243SN/A} 7939243SN/A 7949243SN/Avoid 79510246Sandreas.hansson@arm.comDRAMCtrl::activateBank(Bank& bank, Tick act_tick, uint32_t row) 7969488SN/A{ 79710246Sandreas.hansson@arm.com // get the rank index from the bank 79810246Sandreas.hansson@arm.com uint8_t rank = bank.rank; 79910246Sandreas.hansson@arm.com 8009969SN/A assert(actTicks[rank].size() == activationLimit); 8019488SN/A 8029488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 8039488SN/A 80410207Sandreas.hansson@arm.com // update the open row 80510246Sandreas.hansson@arm.com assert(bank.openRow == Bank::NO_ROW); 80610246Sandreas.hansson@arm.com bank.openRow = row; 80710207Sandreas.hansson@arm.com 80810207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 80910207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 81010207Sandreas.hansson@arm.com // precharge 81110246Sandreas.hansson@arm.com bank.bytesAccessed = 0; 81210246Sandreas.hansson@arm.com bank.rowAccesses = 0; 81310207Sandreas.hansson@arm.com 81410207Sandreas.hansson@arm.com ++numBanksActive; 81510207Sandreas.hansson@arm.com assert(numBanksActive <= banksPerRank * ranksPerChannel); 81610207Sandreas.hansson@arm.com 81710247Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n", 81810247Sandreas.hansson@arm.com bank.bank, bank.rank, act_tick, numBanksActive); 81910247Sandreas.hansson@arm.com 82010247Sandreas.hansson@arm.com DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK), bank.bank, 82110247Sandreas.hansson@arm.com bank.rank); 8229975SN/A 82310211Sandreas.hansson@arm.com // The next access has to respect tRAS for this bank 82410246Sandreas.hansson@arm.com bank.preAllowedAt = act_tick + tRAS; 82510211Sandreas.hansson@arm.com 82610211Sandreas.hansson@arm.com // Respect the row-to-column command delay 82710246Sandreas.hansson@arm.com bank.colAllowedAt = act_tick + tRCD; 82810211Sandreas.hansson@arm.com 8299971SN/A // start by enforcing tRRD 8309971SN/A for(int i = 0; i < banksPerRank; i++) { 83110210Sandreas.hansson@arm.com // next activate to any bank in this rank must not happen 83210210Sandreas.hansson@arm.com // before tRRD 83310210Sandreas.hansson@arm.com banks[rank][i].actAllowedAt = std::max(act_tick + tRRD, 83410210Sandreas.hansson@arm.com banks[rank][i].actAllowedAt); 8359971SN/A } 83610208Sandreas.hansson@arm.com 8379971SN/A // next, we deal with tXAW, if the activation limit is disabled 8389971SN/A // then we are done 8399969SN/A if (actTicks[rank].empty()) 8409824SN/A return; 8419824SN/A 8429488SN/A // sanity check 8439969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 84410210Sandreas.hansson@arm.com panic("Got %d activates in window %d (%llu - %llu) which is smaller " 84510210Sandreas.hansson@arm.com "than %llu\n", activationLimit, act_tick - actTicks[rank].back(), 84610210Sandreas.hansson@arm.com act_tick, actTicks[rank].back(), tXAW); 8479488SN/A } 8489488SN/A 8499488SN/A // shift the times used for the book keeping, the last element 8509488SN/A // (highest index) is the oldest one and hence the lowest value 8519969SN/A actTicks[rank].pop_back(); 8529488SN/A 8539488SN/A // record an new activation (in the future) 8549969SN/A actTicks[rank].push_front(act_tick); 8559488SN/A 8569488SN/A // cannot activate more than X times in time window tXAW, push the 8579488SN/A // next one (the X + 1'st activate) to be tXAW away from the 8589488SN/A // oldest in our window of X 8599969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 8609488SN/A DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate no earlier " 86110210Sandreas.hansson@arm.com "than %llu\n", activationLimit, actTicks[rank].back() + tXAW); 8629488SN/A for(int j = 0; j < banksPerRank; j++) 8639488SN/A // next activate must not happen before end of window 86410210Sandreas.hansson@arm.com banks[rank][j].actAllowedAt = 86510210Sandreas.hansson@arm.com std::max(actTicks[rank].back() + tXAW, 86610210Sandreas.hansson@arm.com banks[rank][j].actAllowedAt); 8679488SN/A } 86810208Sandreas.hansson@arm.com 86910208Sandreas.hansson@arm.com // at the point when this activate takes place, make sure we 87010208Sandreas.hansson@arm.com // transition to the active power state 87110208Sandreas.hansson@arm.com if (!activateEvent.scheduled()) 87210208Sandreas.hansson@arm.com schedule(activateEvent, act_tick); 87310208Sandreas.hansson@arm.com else if (activateEvent.when() > act_tick) 87410208Sandreas.hansson@arm.com // move it sooner in time 87510208Sandreas.hansson@arm.com reschedule(activateEvent, act_tick); 87610208Sandreas.hansson@arm.com} 87710208Sandreas.hansson@arm.com 87810208Sandreas.hansson@arm.comvoid 87910208Sandreas.hansson@arm.comDRAMCtrl::processActivateEvent() 88010208Sandreas.hansson@arm.com{ 88110208Sandreas.hansson@arm.com // we should transition to the active state as soon as any bank is active 88210208Sandreas.hansson@arm.com if (pwrState != PWR_ACT) 88310208Sandreas.hansson@arm.com // note that at this point numBanksActive could be back at 88410208Sandreas.hansson@arm.com // zero again due to a precharge scheduled in the future 88510208Sandreas.hansson@arm.com schedulePowerEvent(PWR_ACT, curTick()); 8869488SN/A} 8879488SN/A 8889488SN/Avoid 88910247Sandreas.hansson@arm.comDRAMCtrl::prechargeBank(Bank& bank, Tick pre_at, bool trace) 89010207Sandreas.hansson@arm.com{ 89110207Sandreas.hansson@arm.com // make sure the bank has an open row 89210207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 89310207Sandreas.hansson@arm.com 89410207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 89510207Sandreas.hansson@arm.com // the page 89610207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 89710207Sandreas.hansson@arm.com 89810207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 89910207Sandreas.hansson@arm.com 90010214Sandreas.hansson@arm.com // no precharge allowed before this one 90110214Sandreas.hansson@arm.com bank.preAllowedAt = pre_at; 90210214Sandreas.hansson@arm.com 90310211Sandreas.hansson@arm.com Tick pre_done_at = pre_at + tRP; 90410211Sandreas.hansson@arm.com 90510211Sandreas.hansson@arm.com bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at); 90610207Sandreas.hansson@arm.com 90710207Sandreas.hansson@arm.com assert(numBanksActive != 0); 90810207Sandreas.hansson@arm.com --numBanksActive; 90910207Sandreas.hansson@arm.com 91010247Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got " 91110247Sandreas.hansson@arm.com "%d active\n", bank.bank, bank.rank, pre_at, numBanksActive); 91210247Sandreas.hansson@arm.com 91310247Sandreas.hansson@arm.com if (trace) 91410247Sandreas.hansson@arm.com DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK), 91510247Sandreas.hansson@arm.com bank.bank, bank.rank); 91610207Sandreas.hansson@arm.com 91710208Sandreas.hansson@arm.com // if we look at the current number of active banks we might be 91810208Sandreas.hansson@arm.com // tempted to think the DRAM is now idle, however this can be 91910208Sandreas.hansson@arm.com // undone by an activate that is scheduled to happen before we 92010208Sandreas.hansson@arm.com // would have reached the idle state, so schedule an event and 92110208Sandreas.hansson@arm.com // rather check once we actually make it to the point in time when 92210208Sandreas.hansson@arm.com // the (last) precharge takes place 92310208Sandreas.hansson@arm.com if (!prechargeEvent.scheduled()) 92410211Sandreas.hansson@arm.com schedule(prechargeEvent, pre_done_at); 92510211Sandreas.hansson@arm.com else if (prechargeEvent.when() < pre_done_at) 92610211Sandreas.hansson@arm.com reschedule(prechargeEvent, pre_done_at); 92710208Sandreas.hansson@arm.com} 92810208Sandreas.hansson@arm.com 92910208Sandreas.hansson@arm.comvoid 93010208Sandreas.hansson@arm.comDRAMCtrl::processPrechargeEvent() 93110208Sandreas.hansson@arm.com{ 93210207Sandreas.hansson@arm.com // if we reached zero, then special conditions apply as we track 93310207Sandreas.hansson@arm.com // if all banks are precharged for the power models 93410207Sandreas.hansson@arm.com if (numBanksActive == 0) { 93510208Sandreas.hansson@arm.com // we should transition to the idle state when the last bank 93610208Sandreas.hansson@arm.com // is precharged 93710208Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 93810207Sandreas.hansson@arm.com } 93910207Sandreas.hansson@arm.com} 94010207Sandreas.hansson@arm.com 94110207Sandreas.hansson@arm.comvoid 94210146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 9439243SN/A{ 9449243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 9459243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 9469243SN/A 94710211Sandreas.hansson@arm.com // get the bank 9489967SN/A Bank& bank = dram_pkt->bankRef; 9499243SN/A 95010211Sandreas.hansson@arm.com // for the state we need to track if it is a row hit or not 95110211Sandreas.hansson@arm.com bool row_hit = true; 95210211Sandreas.hansson@arm.com 95310211Sandreas.hansson@arm.com // respect any constraints on the command (e.g. tRCD or tCCD) 95410211Sandreas.hansson@arm.com Tick cmd_at = std::max(bank.colAllowedAt, curTick()); 95510211Sandreas.hansson@arm.com 95610211Sandreas.hansson@arm.com // Determine the access latency and update the bank state 95710211Sandreas.hansson@arm.com if (bank.openRow == dram_pkt->row) { 95810211Sandreas.hansson@arm.com // nothing to do 95910209Sandreas.hansson@arm.com } else { 96010211Sandreas.hansson@arm.com row_hit = false; 96110211Sandreas.hansson@arm.com 96210209Sandreas.hansson@arm.com // If there is a page open, precharge it. 96310209Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 96410211Sandreas.hansson@arm.com prechargeBank(bank, std::max(bank.preAllowedAt, curTick())); 9659488SN/A } 9669973SN/A 96710211Sandreas.hansson@arm.com // next we need to account for the delay in activating the 96810211Sandreas.hansson@arm.com // page 96910211Sandreas.hansson@arm.com Tick act_tick = std::max(bank.actAllowedAt, curTick()); 9709973SN/A 97110210Sandreas.hansson@arm.com // Record the activation and deal with all the global timing 97210210Sandreas.hansson@arm.com // constraints caused be a new activation (tRRD and tXAW) 97310246Sandreas.hansson@arm.com activateBank(bank, act_tick, dram_pkt->row); 97410210Sandreas.hansson@arm.com 97510211Sandreas.hansson@arm.com // issue the command as early as possible 97610211Sandreas.hansson@arm.com cmd_at = bank.colAllowedAt; 97710209Sandreas.hansson@arm.com } 97810209Sandreas.hansson@arm.com 97910211Sandreas.hansson@arm.com // we need to wait until the bus is available before we can issue 98010211Sandreas.hansson@arm.com // the command 98110211Sandreas.hansson@arm.com cmd_at = std::max(cmd_at, busBusyUntil - tCL); 98210211Sandreas.hansson@arm.com 98310211Sandreas.hansson@arm.com // update the packet ready time 98410211Sandreas.hansson@arm.com dram_pkt->readyTime = cmd_at + tCL + tBURST; 98510211Sandreas.hansson@arm.com 98610211Sandreas.hansson@arm.com // only one burst can use the bus at any one point in time 98710211Sandreas.hansson@arm.com assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 98810211Sandreas.hansson@arm.com 98910211Sandreas.hansson@arm.com // not strictly necessary, but update the time for the next 99010211Sandreas.hansson@arm.com // read/write (add a max with tCCD here) 99110211Sandreas.hansson@arm.com bank.colAllowedAt = cmd_at + tBURST; 99210211Sandreas.hansson@arm.com 99310393Swendy.elsasser@arm.com // Save rank of current access 99410393Swendy.elsasser@arm.com activeRank = dram_pkt->rank; 99510393Swendy.elsasser@arm.com 99610212Sandreas.hansson@arm.com // If this is a write, we also need to respect the write recovery 99710212Sandreas.hansson@arm.com // time before a precharge, in the case of a read, respect the 99810212Sandreas.hansson@arm.com // read to precharge constraint 99910212Sandreas.hansson@arm.com bank.preAllowedAt = std::max(bank.preAllowedAt, 100010212Sandreas.hansson@arm.com dram_pkt->isRead ? cmd_at + tRTP : 100110212Sandreas.hansson@arm.com dram_pkt->readyTime + tWR); 100210210Sandreas.hansson@arm.com 100310209Sandreas.hansson@arm.com // increment the bytes accessed and the accesses per row 100410209Sandreas.hansson@arm.com bank.bytesAccessed += burstSize; 100510209Sandreas.hansson@arm.com ++bank.rowAccesses; 100610209Sandreas.hansson@arm.com 100710209Sandreas.hansson@arm.com // if we reached the max, then issue with an auto-precharge 100810209Sandreas.hansson@arm.com bool auto_precharge = pageMgmt == Enums::close || 100910209Sandreas.hansson@arm.com bank.rowAccesses == maxAccessesPerRow; 101010209Sandreas.hansson@arm.com 101110209Sandreas.hansson@arm.com // if we did not hit the limit, we might still want to 101210209Sandreas.hansson@arm.com // auto-precharge 101310209Sandreas.hansson@arm.com if (!auto_precharge && 101410209Sandreas.hansson@arm.com (pageMgmt == Enums::open_adaptive || 101510209Sandreas.hansson@arm.com pageMgmt == Enums::close_adaptive)) { 101610209Sandreas.hansson@arm.com // a twist on the open and close page policies: 101710209Sandreas.hansson@arm.com // 1) open_adaptive page policy does not blindly keep the 101810209Sandreas.hansson@arm.com // page open, but close it if there are no row hits, and there 101910209Sandreas.hansson@arm.com // are bank conflicts in the queue 102010209Sandreas.hansson@arm.com // 2) close_adaptive page policy does not blindly close the 102110209Sandreas.hansson@arm.com // page, but closes it only if there are no row hits in the queue. 102210209Sandreas.hansson@arm.com // In this case, only force an auto precharge when there 102310209Sandreas.hansson@arm.com // are no same page hits in the queue 102410209Sandreas.hansson@arm.com bool got_more_hits = false; 102510209Sandreas.hansson@arm.com bool got_bank_conflict = false; 102610209Sandreas.hansson@arm.com 102710209Sandreas.hansson@arm.com // either look at the read queue or write queue 102810209Sandreas.hansson@arm.com const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 102910209Sandreas.hansson@arm.com writeQueue; 103010209Sandreas.hansson@arm.com auto p = queue.begin(); 103110209Sandreas.hansson@arm.com // make sure we are not considering the packet that we are 103210209Sandreas.hansson@arm.com // currently dealing with (which is the head of the queue) 103310209Sandreas.hansson@arm.com ++p; 103410209Sandreas.hansson@arm.com 103510209Sandreas.hansson@arm.com // keep on looking until we have found required condition or 103610209Sandreas.hansson@arm.com // reached the end 103710209Sandreas.hansson@arm.com while (!(got_more_hits && 103810209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive)) && 103910209Sandreas.hansson@arm.com p != queue.end()) { 104010209Sandreas.hansson@arm.com bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 104110209Sandreas.hansson@arm.com (dram_pkt->bank == (*p)->bank); 104210209Sandreas.hansson@arm.com bool same_row = dram_pkt->row == (*p)->row; 104310209Sandreas.hansson@arm.com got_more_hits |= same_rank_bank && same_row; 104410209Sandreas.hansson@arm.com got_bank_conflict |= same_rank_bank && !same_row; 10459973SN/A ++p; 104610141SN/A } 104710141SN/A 104810209Sandreas.hansson@arm.com // auto pre-charge when either 104910209Sandreas.hansson@arm.com // 1) open_adaptive policy, we have not got any more hits, and 105010209Sandreas.hansson@arm.com // have a bank conflict 105110209Sandreas.hansson@arm.com // 2) close_adaptive policy and we have not got any more hits 105210209Sandreas.hansson@arm.com auto_precharge = !got_more_hits && 105310209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive); 105410209Sandreas.hansson@arm.com } 105510142SN/A 105610247Sandreas.hansson@arm.com // DRAMPower trace command to be written 105710247Sandreas.hansson@arm.com std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR"; 105810247Sandreas.hansson@arm.com 105910209Sandreas.hansson@arm.com // if this access should use auto-precharge, then we are 106010209Sandreas.hansson@arm.com // closing the row 106110209Sandreas.hansson@arm.com if (auto_precharge) { 106210247Sandreas.hansson@arm.com prechargeBank(bank, std::max(curTick(), bank.preAllowedAt), false); 106310247Sandreas.hansson@arm.com 106410247Sandreas.hansson@arm.com mem_cmd.append("A"); 10659973SN/A 106610209Sandreas.hansson@arm.com DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 106710209Sandreas.hansson@arm.com } 10689963SN/A 10699243SN/A // Update bus state 10709243SN/A busBusyUntil = dram_pkt->readyTime; 10719243SN/A 107210211Sandreas.hansson@arm.com DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n", 107310211Sandreas.hansson@arm.com dram_pkt->addr, dram_pkt->readyTime, busBusyUntil); 10749243SN/A 107510247Sandreas.hansson@arm.com DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK), mem_cmd, 107610247Sandreas.hansson@arm.com dram_pkt->bank, dram_pkt->rank); 107710247Sandreas.hansson@arm.com 107810206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 107910206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 108010206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 108110206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 108210206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 10839972SN/A 108410206Sandreas.hansson@arm.com // Update the stats and schedule the next request 10859977SN/A if (dram_pkt->isRead) { 108610147Sandreas.hansson@arm.com ++readsThisTime; 108710211Sandreas.hansson@arm.com if (row_hit) 10889977SN/A readRowHits++; 10899977SN/A bytesReadDRAM += burstSize; 10909977SN/A perBankRdBursts[dram_pkt->bankId]++; 109110206Sandreas.hansson@arm.com 109210206Sandreas.hansson@arm.com // Update latency stats 109310206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 109410206Sandreas.hansson@arm.com totBusLat += tBURST; 109510211Sandreas.hansson@arm.com totQLat += cmd_at - dram_pkt->entryTime; 10969977SN/A } else { 109710147Sandreas.hansson@arm.com ++writesThisTime; 109810211Sandreas.hansson@arm.com if (row_hit) 10999977SN/A writeRowHits++; 11009977SN/A bytesWritten += burstSize; 11019977SN/A perBankWrBursts[dram_pkt->bankId]++; 11029243SN/A } 11039243SN/A} 11049243SN/A 11059243SN/Avoid 110610206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 11079243SN/A{ 110810393Swendy.elsasser@arm.com // pre-emptively set to false. Overwrite if in READ_TO_WRITE 110910393Swendy.elsasser@arm.com // or WRITE_TO_READ state 111010393Swendy.elsasser@arm.com bool switched_cmd_type = false; 111110206Sandreas.hansson@arm.com if (busState == READ_TO_WRITE) { 111210206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 111310206Sandreas.hansson@arm.com "waiting\n", readsThisTime, readQueue.size()); 11149243SN/A 111510206Sandreas.hansson@arm.com // sample and reset the read-related stats as we are now 111610206Sandreas.hansson@arm.com // transitioning to writes, and all reads are done 111710206Sandreas.hansson@arm.com rdPerTurnAround.sample(readsThisTime); 111810206Sandreas.hansson@arm.com readsThisTime = 0; 111910206Sandreas.hansson@arm.com 112010206Sandreas.hansson@arm.com // now proceed to do the actual writes 112110206Sandreas.hansson@arm.com busState = WRITE; 112210393Swendy.elsasser@arm.com switched_cmd_type = true; 112310206Sandreas.hansson@arm.com } else if (busState == WRITE_TO_READ) { 112410206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 112510206Sandreas.hansson@arm.com "waiting\n", writesThisTime, writeQueue.size()); 112610206Sandreas.hansson@arm.com 112710206Sandreas.hansson@arm.com wrPerTurnAround.sample(writesThisTime); 112810206Sandreas.hansson@arm.com writesThisTime = 0; 112910206Sandreas.hansson@arm.com 113010206Sandreas.hansson@arm.com busState = READ; 113110393Swendy.elsasser@arm.com switched_cmd_type = true; 113210206Sandreas.hansson@arm.com } 113310206Sandreas.hansson@arm.com 113410207Sandreas.hansson@arm.com if (refreshState != REF_IDLE) { 113510207Sandreas.hansson@arm.com // if a refresh waiting for this event loop to finish, then hand 113610207Sandreas.hansson@arm.com // over now, and do not schedule a new nextReqEvent 113710207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 113810207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 113910207Sandreas.hansson@arm.com 114010207Sandreas.hansson@arm.com refreshState = REF_PRE; 114110207Sandreas.hansson@arm.com 114210207Sandreas.hansson@arm.com // hand control back to the refresh event loop 114310207Sandreas.hansson@arm.com schedule(refreshEvent, curTick()); 114410207Sandreas.hansson@arm.com } 114510207Sandreas.hansson@arm.com 114610207Sandreas.hansson@arm.com // let the refresh finish before issuing any further requests 114710207Sandreas.hansson@arm.com return; 114810207Sandreas.hansson@arm.com } 114910207Sandreas.hansson@arm.com 115010206Sandreas.hansson@arm.com // when we get here it is either a read or a write 115110206Sandreas.hansson@arm.com if (busState == READ) { 115210206Sandreas.hansson@arm.com 115310206Sandreas.hansson@arm.com // track if we should switch or not 115410206Sandreas.hansson@arm.com bool switch_to_writes = false; 115510206Sandreas.hansson@arm.com 115610206Sandreas.hansson@arm.com if (readQueue.empty()) { 115710206Sandreas.hansson@arm.com // In the case there is no read request to go next, 115810206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 115910206Sandreas.hansson@arm.com // if we are draining) 116010206Sandreas.hansson@arm.com if (!writeQueue.empty() && 116110206Sandreas.hansson@arm.com (drainManager || writeQueue.size() > writeLowThreshold)) { 116210206Sandreas.hansson@arm.com 116310206Sandreas.hansson@arm.com switch_to_writes = true; 116410206Sandreas.hansson@arm.com } else { 116510206Sandreas.hansson@arm.com // check if we are drained 116610206Sandreas.hansson@arm.com if (respQueue.empty () && drainManager) { 116710206Sandreas.hansson@arm.com drainManager->signalDrainDone(); 116810206Sandreas.hansson@arm.com drainManager = NULL; 116910206Sandreas.hansson@arm.com } 117010206Sandreas.hansson@arm.com 117110206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 117210206Sandreas.hansson@arm.com // event for the next request 117310206Sandreas.hansson@arm.com return; 117410206Sandreas.hansson@arm.com } 117510206Sandreas.hansson@arm.com } else { 117610206Sandreas.hansson@arm.com // Figure out which read request goes next, and move it to the 117710206Sandreas.hansson@arm.com // front of the read queue 117810393Swendy.elsasser@arm.com chooseNext(readQueue, switched_cmd_type); 117910206Sandreas.hansson@arm.com 118010215Sandreas.hansson@arm.com DRAMPacket* dram_pkt = readQueue.front(); 118110215Sandreas.hansson@arm.com 118210393Swendy.elsasser@arm.com // here we get a bit creative and shift the bus busy time not 118310393Swendy.elsasser@arm.com // just the tWTR, but also a CAS latency to capture the fact 118410393Swendy.elsasser@arm.com // that we are allowed to prepare a new bank, but not issue a 118510393Swendy.elsasser@arm.com // read command until after tWTR, in essence we capture a 118610393Swendy.elsasser@arm.com // bubble on the data bus that is tWTR + tCL 118710393Swendy.elsasser@arm.com if (switched_cmd_type) { 118810393Swendy.elsasser@arm.com // add a bubble to the data bus for write-to-read turn around 118910393Swendy.elsasser@arm.com // or tCS (different rank bus delay). 119010393Swendy.elsasser@arm.com busBusyUntil += (dram_pkt->rank == activeRank) ? tWTR + tCL : 119110393Swendy.elsasser@arm.com tCS; 119210393Swendy.elsasser@arm.com } else if (dram_pkt->rank != activeRank) { 119310393Swendy.elsasser@arm.com // add a bubble to the data bus, as defined by the 119410393Swendy.elsasser@arm.com // tCS parameter for rank-to-rank delay 119510393Swendy.elsasser@arm.com busBusyUntil += tCS; 119610393Swendy.elsasser@arm.com } 119710393Swendy.elsasser@arm.com 119810215Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 119910206Sandreas.hansson@arm.com 120010206Sandreas.hansson@arm.com // At this point we're done dealing with the request 120110215Sandreas.hansson@arm.com readQueue.pop_front(); 120210215Sandreas.hansson@arm.com 120310215Sandreas.hansson@arm.com // sanity check 120410215Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 120510215Sandreas.hansson@arm.com assert(dram_pkt->readyTime >= curTick()); 120610215Sandreas.hansson@arm.com 120710215Sandreas.hansson@arm.com // Insert into response queue. It will be sent back to the 120810215Sandreas.hansson@arm.com // requestor at its readyTime 120910215Sandreas.hansson@arm.com if (respQueue.empty()) { 121010215Sandreas.hansson@arm.com assert(!respondEvent.scheduled()); 121110215Sandreas.hansson@arm.com schedule(respondEvent, dram_pkt->readyTime); 121210215Sandreas.hansson@arm.com } else { 121310215Sandreas.hansson@arm.com assert(respQueue.back()->readyTime <= dram_pkt->readyTime); 121410215Sandreas.hansson@arm.com assert(respondEvent.scheduled()); 121510215Sandreas.hansson@arm.com } 121610215Sandreas.hansson@arm.com 121710215Sandreas.hansson@arm.com respQueue.push_back(dram_pkt); 121810206Sandreas.hansson@arm.com 121910206Sandreas.hansson@arm.com // we have so many writes that we have to transition 122010206Sandreas.hansson@arm.com if (writeQueue.size() > writeHighThreshold) { 122110206Sandreas.hansson@arm.com switch_to_writes = true; 122210206Sandreas.hansson@arm.com } 122310206Sandreas.hansson@arm.com } 122410206Sandreas.hansson@arm.com 122510206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 122610206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 122710206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 122810206Sandreas.hansson@arm.com if (switch_to_writes) { 122910206Sandreas.hansson@arm.com // transition to writing 123010206Sandreas.hansson@arm.com busState = READ_TO_WRITE; 123110206Sandreas.hansson@arm.com } 12329352SN/A } else { 123310393Swendy.elsasser@arm.com chooseNext(writeQueue, switched_cmd_type); 123410206Sandreas.hansson@arm.com DRAMPacket* dram_pkt = writeQueue.front(); 123510206Sandreas.hansson@arm.com // sanity check 123610206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 123710393Swendy.elsasser@arm.com 123810393Swendy.elsasser@arm.com if (switched_cmd_type) { 123910393Swendy.elsasser@arm.com // add a bubble to the data bus, as defined by the 124010393Swendy.elsasser@arm.com // tRTW or tCS parameter, depending on whether changing ranks 124110393Swendy.elsasser@arm.com busBusyUntil += (dram_pkt->rank == activeRank) ? tRTW : tCS; 124210393Swendy.elsasser@arm.com } else if (dram_pkt->rank != activeRank) { 124310393Swendy.elsasser@arm.com // add a bubble to the data bus, as defined by the 124410393Swendy.elsasser@arm.com // tCS parameter for rank-to-rank delay 124510393Swendy.elsasser@arm.com busBusyUntil += tCS; 124610393Swendy.elsasser@arm.com } 124710393Swendy.elsasser@arm.com 124810206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 124910206Sandreas.hansson@arm.com 125010206Sandreas.hansson@arm.com writeQueue.pop_front(); 125110206Sandreas.hansson@arm.com delete dram_pkt; 125210206Sandreas.hansson@arm.com 125310206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 125410206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 125510206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 125610206Sandreas.hansson@arm.com // writes, then switch to reads. 125710206Sandreas.hansson@arm.com if (writeQueue.empty() || 125810206Sandreas.hansson@arm.com (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 125910206Sandreas.hansson@arm.com !drainManager) || 126010206Sandreas.hansson@arm.com (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 126110206Sandreas.hansson@arm.com // turn the bus back around for reads again 126210206Sandreas.hansson@arm.com busState = WRITE_TO_READ; 126310206Sandreas.hansson@arm.com 126410206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 126510206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 126610206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 126710206Sandreas.hansson@arm.com // nothing to do 126810206Sandreas.hansson@arm.com } 126910206Sandreas.hansson@arm.com } 127010206Sandreas.hansson@arm.com 127110206Sandreas.hansson@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 127210206Sandreas.hansson@arm.com 127310206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 127410206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 127510206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 127610206Sandreas.hansson@arm.com // the next request processing 127710206Sandreas.hansson@arm.com if (retryWrReq && writeQueue.size() < writeBufferSize) { 127810206Sandreas.hansson@arm.com retryWrReq = false; 127910206Sandreas.hansson@arm.com port.sendRetry(); 12809352SN/A } 12819243SN/A} 12829243SN/A 12839967SN/Auint64_t 128410393Swendy.elsasser@arm.comDRAMCtrl::minBankPrep(const deque<DRAMPacket*>& queue, 128510393Swendy.elsasser@arm.com bool switched_cmd_type) const 12869967SN/A{ 12879967SN/A uint64_t bank_mask = 0; 128810211Sandreas.hansson@arm.com Tick min_act_at = MaxTick; 12899967SN/A 129010393Swendy.elsasser@arm.com uint64_t bank_mask_same_rank = 0; 129110393Swendy.elsasser@arm.com Tick min_act_at_same_rank = MaxTick; 129210393Swendy.elsasser@arm.com 129310393Swendy.elsasser@arm.com // Give precedence to commands that access same rank as previous command 129410393Swendy.elsasser@arm.com bool same_rank_match = false; 129510393Swendy.elsasser@arm.com 129610393Swendy.elsasser@arm.com // determine if we have queued transactions targetting the 12979967SN/A // bank in question 12989967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 12999967SN/A for (auto p = queue.begin(); p != queue.end(); ++p) { 13009967SN/A got_waiting[(*p)->bankId] = true; 13019967SN/A } 13029967SN/A 13039967SN/A for (int i = 0; i < ranksPerChannel; i++) { 13049967SN/A for (int j = 0; j < banksPerRank; j++) { 130510211Sandreas.hansson@arm.com uint8_t bank_id = i * banksPerRank + j; 130610211Sandreas.hansson@arm.com 13079967SN/A // if we have waiting requests for the bank, and it is 13089967SN/A // amongst the first available, update the mask 130910211Sandreas.hansson@arm.com if (got_waiting[bank_id]) { 131010211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue 131110211Sandreas.hansson@arm.com // an activate, ignoring any rank-to-rank switching 131210393Swendy.elsasser@arm.com // cost in this calculation 131310211Sandreas.hansson@arm.com Tick act_at = banks[i][j].openRow == Bank::NO_ROW ? 131410211Sandreas.hansson@arm.com banks[i][j].actAllowedAt : 131510211Sandreas.hansson@arm.com std::max(banks[i][j].preAllowedAt, curTick()) + tRP; 131610211Sandreas.hansson@arm.com 131710393Swendy.elsasser@arm.com // prioritize commands that access the 131810393Swendy.elsasser@arm.com // same rank as previous burst 131910393Swendy.elsasser@arm.com // Calculate bank mask separately for the case and 132010393Swendy.elsasser@arm.com // evaluate after loop iterations complete 132110393Swendy.elsasser@arm.com if (i == activeRank && ranksPerChannel > 1) { 132210393Swendy.elsasser@arm.com if (act_at <= min_act_at_same_rank) { 132310393Swendy.elsasser@arm.com // reset same rank bank mask if new minimum is found 132410393Swendy.elsasser@arm.com // and previous minimum could not immediately send ACT 132510393Swendy.elsasser@arm.com if (act_at < min_act_at_same_rank && 132610393Swendy.elsasser@arm.com min_act_at_same_rank > curTick()) 132710393Swendy.elsasser@arm.com bank_mask_same_rank = 0; 132810393Swendy.elsasser@arm.com 132910393Swendy.elsasser@arm.com // Set flag indicating that a same rank 133010393Swendy.elsasser@arm.com // opportunity was found 133110393Swendy.elsasser@arm.com same_rank_match = true; 133210393Swendy.elsasser@arm.com 133310393Swendy.elsasser@arm.com // set the bit corresponding to the available bank 133410393Swendy.elsasser@arm.com replaceBits(bank_mask_same_rank, bank_id, bank_id, 1); 133510393Swendy.elsasser@arm.com min_act_at_same_rank = act_at; 133610393Swendy.elsasser@arm.com } 133710393Swendy.elsasser@arm.com } else { 133810393Swendy.elsasser@arm.com if (act_at <= min_act_at) { 133910393Swendy.elsasser@arm.com // reset bank mask if new minimum is found 134010393Swendy.elsasser@arm.com // and either previous minimum could not immediately send ACT 134110393Swendy.elsasser@arm.com if (act_at < min_act_at && min_act_at > curTick()) 134210393Swendy.elsasser@arm.com bank_mask = 0; 134310393Swendy.elsasser@arm.com // set the bit corresponding to the available bank 134410393Swendy.elsasser@arm.com replaceBits(bank_mask, bank_id, bank_id, 1); 134510393Swendy.elsasser@arm.com min_act_at = act_at; 134610393Swendy.elsasser@arm.com } 134710211Sandreas.hansson@arm.com } 13489967SN/A } 13499967SN/A } 13509967SN/A } 135110211Sandreas.hansson@arm.com 135210393Swendy.elsasser@arm.com // Determine the earliest time when the next burst can issue based 135310393Swendy.elsasser@arm.com // on the current busBusyUntil delay. 135410393Swendy.elsasser@arm.com // Offset by tRCD to correlate with ACT timing variables 135510393Swendy.elsasser@arm.com Tick min_cmd_at = busBusyUntil - tCL - tRCD; 135610393Swendy.elsasser@arm.com 135710393Swendy.elsasser@arm.com // Prioritize same rank accesses that can issue B2B 135810393Swendy.elsasser@arm.com // Only optimize for same ranks when the command type 135910393Swendy.elsasser@arm.com // does not change; do not want to unnecessarily incur tWTR 136010393Swendy.elsasser@arm.com // 136110393Swendy.elsasser@arm.com // Resulting FCFS prioritization Order is: 136210393Swendy.elsasser@arm.com // 1) Commands that access the same rank as previous burst 136310393Swendy.elsasser@arm.com // and can prep the bank seamlessly. 136410393Swendy.elsasser@arm.com // 2) Commands (any rank) with earliest bank prep 136510393Swendy.elsasser@arm.com if (!switched_cmd_type && same_rank_match && 136610393Swendy.elsasser@arm.com min_act_at_same_rank <= min_cmd_at) { 136710393Swendy.elsasser@arm.com bank_mask = bank_mask_same_rank; 136810393Swendy.elsasser@arm.com } 136910393Swendy.elsasser@arm.com 13709967SN/A return bank_mask; 13719967SN/A} 13729967SN/A 13739243SN/Avoid 137410146Sandreas.hansson@arm.comDRAMCtrl::processRefreshEvent() 13759243SN/A{ 137610207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 137710207Sandreas.hansson@arm.com if (refreshState == REF_IDLE) { 137810207Sandreas.hansson@arm.com // remember when the refresh is due 137910207Sandreas.hansson@arm.com refreshDueAt = curTick(); 13809243SN/A 138110207Sandreas.hansson@arm.com // proceed to drain 138210207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 13839243SN/A 138410207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 138510207Sandreas.hansson@arm.com } 138610207Sandreas.hansson@arm.com 138710207Sandreas.hansson@arm.com // let any scheduled read or write go ahead, after which it will 138810207Sandreas.hansson@arm.com // hand control back to this event loop 138910207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 139010207Sandreas.hansson@arm.com if (nextReqEvent.scheduled()) { 139110207Sandreas.hansson@arm.com // hand control over to the request loop until it is 139210207Sandreas.hansson@arm.com // evaluated next 139310207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 139410207Sandreas.hansson@arm.com 139510207Sandreas.hansson@arm.com return; 139610207Sandreas.hansson@arm.com } else { 139710207Sandreas.hansson@arm.com refreshState = REF_PRE; 139810207Sandreas.hansson@arm.com } 139910207Sandreas.hansson@arm.com } 140010207Sandreas.hansson@arm.com 140110207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 140210207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 140310208Sandreas.hansson@arm.com // precharge any active bank if we are not already in the idle 140410208Sandreas.hansson@arm.com // state 140510208Sandreas.hansson@arm.com if (pwrState != PWR_IDLE) { 140610214Sandreas.hansson@arm.com // at the moment, we use a precharge all even if there is 140710214Sandreas.hansson@arm.com // only a single bank open 140810208Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 140910214Sandreas.hansson@arm.com 141010214Sandreas.hansson@arm.com // first determine when we can precharge 141110214Sandreas.hansson@arm.com Tick pre_at = curTick(); 141210214Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 141310214Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 141410214Sandreas.hansson@arm.com // respect both causality and any existing bank 141510214Sandreas.hansson@arm.com // constraints, some banks could already have a 141610214Sandreas.hansson@arm.com // (auto) precharge scheduled 141710214Sandreas.hansson@arm.com pre_at = std::max(banks[i][j].preAllowedAt, pre_at); 141810214Sandreas.hansson@arm.com } 141910214Sandreas.hansson@arm.com } 142010214Sandreas.hansson@arm.com 142110214Sandreas.hansson@arm.com // make sure all banks are precharged, and for those that 142210214Sandreas.hansson@arm.com // already are, update their availability 142310214Sandreas.hansson@arm.com Tick act_allowed_at = pre_at + tRP; 142410214Sandreas.hansson@arm.com 142510208Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 142610208Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 142710208Sandreas.hansson@arm.com if (banks[i][j].openRow != Bank::NO_ROW) { 142810247Sandreas.hansson@arm.com prechargeBank(banks[i][j], pre_at, false); 142910214Sandreas.hansson@arm.com } else { 143010214Sandreas.hansson@arm.com banks[i][j].actAllowedAt = 143110214Sandreas.hansson@arm.com std::max(banks[i][j].actAllowedAt, act_allowed_at); 143210214Sandreas.hansson@arm.com banks[i][j].preAllowedAt = 143310214Sandreas.hansson@arm.com std::max(banks[i][j].preAllowedAt, pre_at); 143410208Sandreas.hansson@arm.com } 143510207Sandreas.hansson@arm.com } 143610247Sandreas.hansson@arm.com 143710247Sandreas.hansson@arm.com // at the moment this affects all ranks 143810247Sandreas.hansson@arm.com DPRINTF(DRAMPower, "%llu,PREA,0,%d\n", divCeil(pre_at, tCK), 143910247Sandreas.hansson@arm.com i); 144010207Sandreas.hansson@arm.com } 144110208Sandreas.hansson@arm.com } else { 144210208Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 144310208Sandreas.hansson@arm.com 144410208Sandreas.hansson@arm.com // go ahead and kick the power state machine into gear if 144510208Sandreas.hansson@arm.com // we are already idle 144610208Sandreas.hansson@arm.com schedulePowerEvent(PWR_REF, curTick()); 14479975SN/A } 14489975SN/A 144910208Sandreas.hansson@arm.com refreshState = REF_RUN; 145010208Sandreas.hansson@arm.com assert(numBanksActive == 0); 14519243SN/A 145210208Sandreas.hansson@arm.com // wait for all banks to be precharged, at which point the 145310208Sandreas.hansson@arm.com // power state machine will transition to the idle state, and 145410208Sandreas.hansson@arm.com // automatically move to a refresh, at that point it will also 145510208Sandreas.hansson@arm.com // call this method to get the refresh event loop going again 145610207Sandreas.hansson@arm.com return; 145710207Sandreas.hansson@arm.com } 145810207Sandreas.hansson@arm.com 145910207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 146010207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 146110207Sandreas.hansson@arm.com // should never get here with any banks active 146210207Sandreas.hansson@arm.com assert(numBanksActive == 0); 146310208Sandreas.hansson@arm.com assert(pwrState == PWR_REF); 146410207Sandreas.hansson@arm.com 146510211Sandreas.hansson@arm.com Tick ref_done_at = curTick() + tRFC; 146610207Sandreas.hansson@arm.com 146710207Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 146810207Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 146910211Sandreas.hansson@arm.com banks[i][j].actAllowedAt = ref_done_at; 147010207Sandreas.hansson@arm.com } 147110247Sandreas.hansson@arm.com 147210247Sandreas.hansson@arm.com // at the moment this affects all ranks 147310247Sandreas.hansson@arm.com DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), tCK), i); 147410207Sandreas.hansson@arm.com } 147510207Sandreas.hansson@arm.com 147610207Sandreas.hansson@arm.com // make sure we did not wait so long that we cannot make up 147710207Sandreas.hansson@arm.com // for it 147810211Sandreas.hansson@arm.com if (refreshDueAt + tREFI < ref_done_at) { 147910207Sandreas.hansson@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 148010207Sandreas.hansson@arm.com } 148110207Sandreas.hansson@arm.com 148210207Sandreas.hansson@arm.com // compensate for the delay in actually performing the refresh 148310207Sandreas.hansson@arm.com // when scheduling the next one 148410207Sandreas.hansson@arm.com schedule(refreshEvent, refreshDueAt + tREFI - tRP); 148510207Sandreas.hansson@arm.com 148610208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 148710207Sandreas.hansson@arm.com 148810208Sandreas.hansson@arm.com // move to the idle power state once the refresh is done, this 148910208Sandreas.hansson@arm.com // will also move the refresh state machine to the refresh 149010208Sandreas.hansson@arm.com // idle state 149110211Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, ref_done_at); 149210207Sandreas.hansson@arm.com 149310208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n", 149410211Sandreas.hansson@arm.com ref_done_at, refreshDueAt + tREFI); 149510208Sandreas.hansson@arm.com } 149610208Sandreas.hansson@arm.com} 149710208Sandreas.hansson@arm.com 149810208Sandreas.hansson@arm.comvoid 149910208Sandreas.hansson@arm.comDRAMCtrl::schedulePowerEvent(PowerState pwr_state, Tick tick) 150010208Sandreas.hansson@arm.com{ 150110208Sandreas.hansson@arm.com // respect causality 150210208Sandreas.hansson@arm.com assert(tick >= curTick()); 150310208Sandreas.hansson@arm.com 150410208Sandreas.hansson@arm.com if (!powerEvent.scheduled()) { 150510208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 150610208Sandreas.hansson@arm.com tick, pwr_state); 150710208Sandreas.hansson@arm.com 150810208Sandreas.hansson@arm.com // insert the new transition 150910208Sandreas.hansson@arm.com pwrStateTrans = pwr_state; 151010208Sandreas.hansson@arm.com 151110208Sandreas.hansson@arm.com schedule(powerEvent, tick); 151210208Sandreas.hansson@arm.com } else { 151310208Sandreas.hansson@arm.com panic("Scheduled power event at %llu to state %d, " 151410208Sandreas.hansson@arm.com "with scheduled event at %llu to %d\n", tick, pwr_state, 151510208Sandreas.hansson@arm.com powerEvent.when(), pwrStateTrans); 151610208Sandreas.hansson@arm.com } 151710208Sandreas.hansson@arm.com} 151810208Sandreas.hansson@arm.com 151910208Sandreas.hansson@arm.comvoid 152010208Sandreas.hansson@arm.comDRAMCtrl::processPowerEvent() 152110208Sandreas.hansson@arm.com{ 152210208Sandreas.hansson@arm.com // remember where we were, and for how long 152310208Sandreas.hansson@arm.com Tick duration = curTick() - pwrStateTick; 152410208Sandreas.hansson@arm.com PowerState prev_state = pwrState; 152510208Sandreas.hansson@arm.com 152610208Sandreas.hansson@arm.com // update the accounting 152710208Sandreas.hansson@arm.com pwrStateTime[prev_state] += duration; 152810208Sandreas.hansson@arm.com 152910208Sandreas.hansson@arm.com pwrState = pwrStateTrans; 153010208Sandreas.hansson@arm.com pwrStateTick = curTick(); 153110208Sandreas.hansson@arm.com 153210208Sandreas.hansson@arm.com if (pwrState == PWR_IDLE) { 153310208Sandreas.hansson@arm.com DPRINTF(DRAMState, "All banks precharged\n"); 153410208Sandreas.hansson@arm.com 153510208Sandreas.hansson@arm.com // if we were refreshing, make sure we start scheduling requests again 153610208Sandreas.hansson@arm.com if (prev_state == PWR_REF) { 153710208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 153810208Sandreas.hansson@arm.com assert(pwrState == PWR_IDLE); 153910208Sandreas.hansson@arm.com 154010208Sandreas.hansson@arm.com // kick things into action again 154110208Sandreas.hansson@arm.com refreshState = REF_IDLE; 154210208Sandreas.hansson@arm.com assert(!nextReqEvent.scheduled()); 154310208Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 154410208Sandreas.hansson@arm.com } else { 154510208Sandreas.hansson@arm.com assert(prev_state == PWR_ACT); 154610208Sandreas.hansson@arm.com 154710208Sandreas.hansson@arm.com // if we have a pending refresh, and are now moving to 154810208Sandreas.hansson@arm.com // the idle state, direclty transition to a refresh 154910208Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 155010208Sandreas.hansson@arm.com // there should be nothing waiting at this point 155110208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 155210208Sandreas.hansson@arm.com 155310208Sandreas.hansson@arm.com // update the state in zero time and proceed below 155410208Sandreas.hansson@arm.com pwrState = PWR_REF; 155510208Sandreas.hansson@arm.com } 155610208Sandreas.hansson@arm.com } 155710208Sandreas.hansson@arm.com } 155810208Sandreas.hansson@arm.com 155910208Sandreas.hansson@arm.com // we transition to the refresh state, let the refresh state 156010208Sandreas.hansson@arm.com // machine know of this state update and let it deal with the 156110208Sandreas.hansson@arm.com // scheduling of the next power state transition as well as the 156210208Sandreas.hansson@arm.com // following refresh 156310208Sandreas.hansson@arm.com if (pwrState == PWR_REF) { 156410208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refreshing\n"); 156510208Sandreas.hansson@arm.com // kick the refresh event loop into action again, and that 156610208Sandreas.hansson@arm.com // in turn will schedule a transition to the idle power 156710208Sandreas.hansson@arm.com // state once the refresh is done 156810208Sandreas.hansson@arm.com assert(refreshState == REF_RUN); 156910208Sandreas.hansson@arm.com processRefreshEvent(); 157010207Sandreas.hansson@arm.com } 15719243SN/A} 15729243SN/A 15739243SN/Avoid 157410146Sandreas.hansson@arm.comDRAMCtrl::regStats() 15759243SN/A{ 15769243SN/A using namespace Stats; 15779243SN/A 15789243SN/A AbstractMemory::regStats(); 15799243SN/A 15809243SN/A readReqs 15819243SN/A .name(name() + ".readReqs") 15829977SN/A .desc("Number of read requests accepted"); 15839243SN/A 15849243SN/A writeReqs 15859243SN/A .name(name() + ".writeReqs") 15869977SN/A .desc("Number of write requests accepted"); 15879831SN/A 15889831SN/A readBursts 15899831SN/A .name(name() + ".readBursts") 15909977SN/A .desc("Number of DRAM read bursts, " 15919977SN/A "including those serviced by the write queue"); 15929831SN/A 15939831SN/A writeBursts 15949831SN/A .name(name() + ".writeBursts") 15959977SN/A .desc("Number of DRAM write bursts, " 15969977SN/A "including those merged in the write queue"); 15979243SN/A 15989243SN/A servicedByWrQ 15999243SN/A .name(name() + ".servicedByWrQ") 16009977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 16019977SN/A 16029977SN/A mergedWrBursts 16039977SN/A .name(name() + ".mergedWrBursts") 16049977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 16059243SN/A 16069243SN/A neitherReadNorWrite 16079977SN/A .name(name() + ".neitherReadNorWriteReqs") 16089977SN/A .desc("Number of requests that are neither read nor write"); 16099243SN/A 16109977SN/A perBankRdBursts 16119243SN/A .init(banksPerRank * ranksPerChannel) 16129977SN/A .name(name() + ".perBankRdBursts") 16139977SN/A .desc("Per bank write bursts"); 16149243SN/A 16159977SN/A perBankWrBursts 16169243SN/A .init(banksPerRank * ranksPerChannel) 16179977SN/A .name(name() + ".perBankWrBursts") 16189977SN/A .desc("Per bank write bursts"); 16199243SN/A 16209243SN/A avgRdQLen 16219243SN/A .name(name() + ".avgRdQLen") 16229977SN/A .desc("Average read queue length when enqueuing") 16239243SN/A .precision(2); 16249243SN/A 16259243SN/A avgWrQLen 16269243SN/A .name(name() + ".avgWrQLen") 16279977SN/A .desc("Average write queue length when enqueuing") 16289243SN/A .precision(2); 16299243SN/A 16309243SN/A totQLat 16319243SN/A .name(name() + ".totQLat") 16329977SN/A .desc("Total ticks spent queuing"); 16339243SN/A 16349243SN/A totBusLat 16359243SN/A .name(name() + ".totBusLat") 16369977SN/A .desc("Total ticks spent in databus transfers"); 16379243SN/A 16389243SN/A totMemAccLat 16399243SN/A .name(name() + ".totMemAccLat") 16409977SN/A .desc("Total ticks spent from burst creation until serviced " 16419977SN/A "by the DRAM"); 16429243SN/A 16439243SN/A avgQLat 16449243SN/A .name(name() + ".avgQLat") 16459977SN/A .desc("Average queueing delay per DRAM burst") 16469243SN/A .precision(2); 16479243SN/A 16489831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 16499243SN/A 16509243SN/A avgBusLat 16519243SN/A .name(name() + ".avgBusLat") 16529977SN/A .desc("Average bus latency per DRAM burst") 16539243SN/A .precision(2); 16549243SN/A 16559831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 16569243SN/A 16579243SN/A avgMemAccLat 16589243SN/A .name(name() + ".avgMemAccLat") 16599977SN/A .desc("Average memory access latency per DRAM burst") 16609243SN/A .precision(2); 16619243SN/A 16629831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 16639243SN/A 16649243SN/A numRdRetry 16659243SN/A .name(name() + ".numRdRetry") 16669977SN/A .desc("Number of times read queue was full causing retry"); 16679243SN/A 16689243SN/A numWrRetry 16699243SN/A .name(name() + ".numWrRetry") 16709977SN/A .desc("Number of times write queue was full causing retry"); 16719243SN/A 16729243SN/A readRowHits 16739243SN/A .name(name() + ".readRowHits") 16749243SN/A .desc("Number of row buffer hits during reads"); 16759243SN/A 16769243SN/A writeRowHits 16779243SN/A .name(name() + ".writeRowHits") 16789243SN/A .desc("Number of row buffer hits during writes"); 16799243SN/A 16809243SN/A readRowHitRate 16819243SN/A .name(name() + ".readRowHitRate") 16829243SN/A .desc("Row buffer hit rate for reads") 16839243SN/A .precision(2); 16849243SN/A 16859831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 16869243SN/A 16879243SN/A writeRowHitRate 16889243SN/A .name(name() + ".writeRowHitRate") 16899243SN/A .desc("Row buffer hit rate for writes") 16909243SN/A .precision(2); 16919243SN/A 16929977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 16939243SN/A 16949243SN/A readPktSize 16959831SN/A .init(ceilLog2(burstSize) + 1) 16969243SN/A .name(name() + ".readPktSize") 16979977SN/A .desc("Read request sizes (log2)"); 16989243SN/A 16999243SN/A writePktSize 17009831SN/A .init(ceilLog2(burstSize) + 1) 17019243SN/A .name(name() + ".writePktSize") 17029977SN/A .desc("Write request sizes (log2)"); 17039243SN/A 17049243SN/A rdQLenPdf 17059567SN/A .init(readBufferSize) 17069243SN/A .name(name() + ".rdQLenPdf") 17079243SN/A .desc("What read queue length does an incoming req see"); 17089243SN/A 17099243SN/A wrQLenPdf 17109567SN/A .init(writeBufferSize) 17119243SN/A .name(name() + ".wrQLenPdf") 17129243SN/A .desc("What write queue length does an incoming req see"); 17139243SN/A 17149727SN/A bytesPerActivate 171510141SN/A .init(maxAccessesPerRow) 17169727SN/A .name(name() + ".bytesPerActivate") 17179727SN/A .desc("Bytes accessed per row activation") 17189727SN/A .flags(nozero); 17199243SN/A 172010147Sandreas.hansson@arm.com rdPerTurnAround 172110147Sandreas.hansson@arm.com .init(readBufferSize) 172210147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 172310147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 172410147Sandreas.hansson@arm.com .flags(nozero); 172510147Sandreas.hansson@arm.com 172610147Sandreas.hansson@arm.com wrPerTurnAround 172710147Sandreas.hansson@arm.com .init(writeBufferSize) 172810147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 172910147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 173010147Sandreas.hansson@arm.com .flags(nozero); 173110147Sandreas.hansson@arm.com 17329975SN/A bytesReadDRAM 17339975SN/A .name(name() + ".bytesReadDRAM") 17349975SN/A .desc("Total number of bytes read from DRAM"); 17359975SN/A 17369975SN/A bytesReadWrQ 17379975SN/A .name(name() + ".bytesReadWrQ") 17389975SN/A .desc("Total number of bytes read from write queue"); 17399243SN/A 17409243SN/A bytesWritten 17419243SN/A .name(name() + ".bytesWritten") 17429977SN/A .desc("Total number of bytes written to DRAM"); 17439243SN/A 17449977SN/A bytesReadSys 17459977SN/A .name(name() + ".bytesReadSys") 17469977SN/A .desc("Total read bytes from the system interface side"); 17479243SN/A 17489977SN/A bytesWrittenSys 17499977SN/A .name(name() + ".bytesWrittenSys") 17509977SN/A .desc("Total written bytes from the system interface side"); 17519243SN/A 17529243SN/A avgRdBW 17539243SN/A .name(name() + ".avgRdBW") 17549977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 17559243SN/A .precision(2); 17569243SN/A 17579977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 17589243SN/A 17599243SN/A avgWrBW 17609243SN/A .name(name() + ".avgWrBW") 17619977SN/A .desc("Average achieved write bandwidth in MiByte/s") 17629243SN/A .precision(2); 17639243SN/A 17649243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 17659243SN/A 17669977SN/A avgRdBWSys 17679977SN/A .name(name() + ".avgRdBWSys") 17689977SN/A .desc("Average system read bandwidth in MiByte/s") 17699243SN/A .precision(2); 17709243SN/A 17719977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 17729243SN/A 17739977SN/A avgWrBWSys 17749977SN/A .name(name() + ".avgWrBWSys") 17759977SN/A .desc("Average system write bandwidth in MiByte/s") 17769243SN/A .precision(2); 17779243SN/A 17789977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 17799243SN/A 17809243SN/A peakBW 17819243SN/A .name(name() + ".peakBW") 17829977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 17839243SN/A .precision(2); 17849243SN/A 17859831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 17869243SN/A 17879243SN/A busUtil 17889243SN/A .name(name() + ".busUtil") 17899243SN/A .desc("Data bus utilization in percentage") 17909243SN/A .precision(2); 17919243SN/A 17929243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 17939243SN/A 17949243SN/A totGap 17959243SN/A .name(name() + ".totGap") 17969243SN/A .desc("Total gap between requests"); 17979243SN/A 17989243SN/A avgGap 17999243SN/A .name(name() + ".avgGap") 18009243SN/A .desc("Average gap between requests") 18019243SN/A .precision(2); 18029243SN/A 18039243SN/A avgGap = totGap / (readReqs + writeReqs); 18049975SN/A 18059975SN/A // Stats for DRAM Power calculation based on Micron datasheet 18069975SN/A busUtilRead 18079975SN/A .name(name() + ".busUtilRead") 18089975SN/A .desc("Data bus utilization in percentage for reads") 18099975SN/A .precision(2); 18109975SN/A 18119975SN/A busUtilRead = avgRdBW / peakBW * 100; 18129975SN/A 18139975SN/A busUtilWrite 18149975SN/A .name(name() + ".busUtilWrite") 18159975SN/A .desc("Data bus utilization in percentage for writes") 18169975SN/A .precision(2); 18179975SN/A 18189975SN/A busUtilWrite = avgWrBW / peakBW * 100; 18199975SN/A 18209975SN/A pageHitRate 18219975SN/A .name(name() + ".pageHitRate") 18229975SN/A .desc("Row buffer hit rate, read and write combined") 18239975SN/A .precision(2); 18249975SN/A 18259977SN/A pageHitRate = (writeRowHits + readRowHits) / 18269977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 18279975SN/A 182810208Sandreas.hansson@arm.com pwrStateTime 182910208Sandreas.hansson@arm.com .init(5) 183010208Sandreas.hansson@arm.com .name(name() + ".memoryStateTime") 183110208Sandreas.hansson@arm.com .desc("Time in different power states"); 183210208Sandreas.hansson@arm.com pwrStateTime.subname(0, "IDLE"); 183310208Sandreas.hansson@arm.com pwrStateTime.subname(1, "REF"); 183410208Sandreas.hansson@arm.com pwrStateTime.subname(2, "PRE_PDN"); 183510208Sandreas.hansson@arm.com pwrStateTime.subname(3, "ACT"); 183610208Sandreas.hansson@arm.com pwrStateTime.subname(4, "ACT_PDN"); 18379243SN/A} 18389243SN/A 18399243SN/Avoid 184010146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 18419243SN/A{ 18429243SN/A // rely on the abstract memory 18439243SN/A functionalAccess(pkt); 18449243SN/A} 18459243SN/A 18469294SN/ABaseSlavePort& 184710146Sandreas.hansson@arm.comDRAMCtrl::getSlavePort(const string &if_name, PortID idx) 18489243SN/A{ 18499243SN/A if (if_name != "port") { 18509243SN/A return MemObject::getSlavePort(if_name, idx); 18519243SN/A } else { 18529243SN/A return port; 18539243SN/A } 18549243SN/A} 18559243SN/A 18569243SN/Aunsigned int 185710146Sandreas.hansson@arm.comDRAMCtrl::drain(DrainManager *dm) 18589243SN/A{ 18599342SN/A unsigned int count = port.drain(dm); 18609243SN/A 18619243SN/A // if there is anything in any of our internal queues, keep track 18629243SN/A // of that as well 18639567SN/A if (!(writeQueue.empty() && readQueue.empty() && 18649567SN/A respQueue.empty())) { 18659352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 18669567SN/A " resp: %d\n", writeQueue.size(), readQueue.size(), 18679567SN/A respQueue.size()); 18689243SN/A ++count; 18699342SN/A drainManager = dm; 187010206Sandreas.hansson@arm.com 18719352SN/A // the only part that is not drained automatically over time 187210206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 187310206Sandreas.hansson@arm.com if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 187410206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 187510206Sandreas.hansson@arm.com } 18769243SN/A } 18779243SN/A 18789243SN/A if (count) 18799342SN/A setDrainState(Drainable::Draining); 18809243SN/A else 18819342SN/A setDrainState(Drainable::Drained); 18829243SN/A return count; 18839243SN/A} 18849243SN/A 188510146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 18869243SN/A : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 18879243SN/A memory(_memory) 18889243SN/A{ } 18899243SN/A 18909243SN/AAddrRangeList 189110146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 18929243SN/A{ 18939243SN/A AddrRangeList ranges; 18949243SN/A ranges.push_back(memory.getAddrRange()); 18959243SN/A return ranges; 18969243SN/A} 18979243SN/A 18989243SN/Avoid 189910146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 19009243SN/A{ 19019243SN/A pkt->pushLabel(memory.name()); 19029243SN/A 19039243SN/A if (!queue.checkFunctional(pkt)) { 19049243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 19059243SN/A // calls recvAtomic() and throws away the latency; we can save a 19069243SN/A // little here by just not calculating the latency. 19079243SN/A memory.recvFunctional(pkt); 19089243SN/A } 19099243SN/A 19109243SN/A pkt->popLabel(); 19119243SN/A} 19129243SN/A 19139243SN/ATick 191410146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 19159243SN/A{ 19169243SN/A return memory.recvAtomic(pkt); 19179243SN/A} 19189243SN/A 19199243SN/Abool 192010146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 19219243SN/A{ 19229243SN/A // pass it to the memory controller 19239243SN/A return memory.recvTimingReq(pkt); 19249243SN/A} 19259243SN/A 192610146Sandreas.hansson@arm.comDRAMCtrl* 192710146Sandreas.hansson@arm.comDRAMCtrlParams::create() 19289243SN/A{ 192910146Sandreas.hansson@arm.com return new DRAMCtrl(this); 19309243SN/A} 1931