dram_ctrl.cc revision 10286
19243SN/A/* 210206Sandreas.hansson@arm.com * Copyright (c) 2010-2014 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 439243SN/A */ 449243SN/A 4510146Sandreas.hansson@arm.com#include "base/bitfield.hh" 469356SN/A#include "base/trace.hh" 4710146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 4810247Sandreas.hansson@arm.com#include "debug/DRAMPower.hh" 4910208Sandreas.hansson@arm.com#include "debug/DRAMState.hh" 509352SN/A#include "debug/Drain.hh" 5110146Sandreas.hansson@arm.com#include "mem/dram_ctrl.hh" 529814SN/A#include "sim/system.hh" 539243SN/A 549243SN/Ausing namespace std; 559243SN/A 5610146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 579243SN/A AbstractMemory(p), 589243SN/A port(name() + ".port", *this), 599243SN/A retryRdReq(false), retryWrReq(false), 6010211Sandreas.hansson@arm.com busState(READ), 6110208Sandreas.hansson@arm.com nextReqEvent(this), respondEvent(this), activateEvent(this), 6210208Sandreas.hansson@arm.com prechargeEvent(this), refreshEvent(this), powerEvent(this), 6310208Sandreas.hansson@arm.com drainManager(NULL), 649831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 659831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 669831SN/A devicesPerRank(p->devices_per_rank), 679831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 689831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 6910140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 7010286Sandreas.hansson@arm.com columnsPerStripe(range.granularity() / burstSize), 719243SN/A ranksPerChannel(p->ranks_per_channel), 729566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 739243SN/A readBufferSize(p->read_buffer_size), 749243SN/A writeBufferSize(p->write_buffer_size), 7510140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 7610140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 7710147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 7810147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 7910216Sandreas.hansson@arm.com tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tBURST(p->tBURST), 8010210Sandreas.hansson@arm.com tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), tWR(p->tWR), 8110212Sandreas.hansson@arm.com tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 829488SN/A tXAW(p->tXAW), activationLimit(p->activation_limit), 839243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 849243SN/A pageMgmt(p->page_policy), 8510141SN/A maxAccessesPerRow(p->max_accesses_per_row), 869726SN/A frontendLatency(p->static_frontend_latency), 879726SN/A backendLatency(p->static_backend_latency), 8810208Sandreas.hansson@arm.com busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE), 8910208Sandreas.hansson@arm.com pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), prevArrival(0), 9010208Sandreas.hansson@arm.com nextReqTime(0), pwrStateTick(0), numBanksActive(0) 919243SN/A{ 929243SN/A // create the bank states based on the dimensions of the ranks and 939243SN/A // banks 949243SN/A banks.resize(ranksPerChannel); 959969SN/A actTicks.resize(ranksPerChannel); 969243SN/A for (size_t c = 0; c < ranksPerChannel; ++c) { 979243SN/A banks[c].resize(banksPerRank); 989969SN/A actTicks[c].resize(activationLimit, 0); 999243SN/A } 1009243SN/A 10110246Sandreas.hansson@arm.com // set the bank indices 10210246Sandreas.hansson@arm.com for (int r = 0; r < ranksPerChannel; r++) { 10310246Sandreas.hansson@arm.com for (int b = 0; b < banksPerRank; b++) { 10410246Sandreas.hansson@arm.com banks[r][b].rank = r; 10510246Sandreas.hansson@arm.com banks[r][b].bank = b; 10610246Sandreas.hansson@arm.com } 10710246Sandreas.hansson@arm.com } 10810246Sandreas.hansson@arm.com 10910140SN/A // perform a basic check of the write thresholds 11010140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 11110140SN/A fatal("Write buffer low threshold %d must be smaller than the " 11210140SN/A "high threshold %d\n", p->write_low_thresh_perc, 11310140SN/A p->write_high_thresh_perc); 1149243SN/A 1159243SN/A // determine the rows per bank by looking at the total capacity 1169567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1179243SN/A 1189243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1199243SN/A AbstractMemory::size()); 1209831SN/A 1219831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1229831SN/A rowBufferSize, columnsPerRowBuffer); 1239831SN/A 1249831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1259243SN/A 12610286Sandreas.hansson@arm.com // a bit of sanity checks on the interleaving 1279566SN/A if (range.interleaved()) { 1289566SN/A if (channels != range.stripes()) 12910143SN/A fatal("%s has %d interleaved address stripes but %d channel(s)\n", 1309566SN/A name(), range.stripes(), channels); 1319566SN/A 13210136SN/A if (addrMapping == Enums::RoRaBaChCo) { 1339831SN/A if (rowBufferSize != range.granularity()) { 13410286Sandreas.hansson@arm.com fatal("Channel interleaving of %s doesn't match RoRaBaChCo " 13510136SN/A "address map\n", name()); 1369566SN/A } 13710286Sandreas.hansson@arm.com } else if (addrMapping == Enums::RoRaBaCoCh || 13810286Sandreas.hansson@arm.com addrMapping == Enums::RoCoRaBaCh) { 13910286Sandreas.hansson@arm.com // for the interleavings with channel bits in the bottom, 14010286Sandreas.hansson@arm.com // if the system uses a channel striping granularity that 14110286Sandreas.hansson@arm.com // is larger than the DRAM burst size, then map the 14210286Sandreas.hansson@arm.com // sequential accesses within a stripe to a number of 14310286Sandreas.hansson@arm.com // columns in the DRAM, effectively placing some of the 14410286Sandreas.hansson@arm.com // lower-order column bits as the least-significant bits 14510286Sandreas.hansson@arm.com // of the address (above the ones denoting the burst size) 14610286Sandreas.hansson@arm.com assert(columnsPerStripe >= 1); 14710286Sandreas.hansson@arm.com 14810286Sandreas.hansson@arm.com // channel striping has to be done at a granularity that 14910286Sandreas.hansson@arm.com // is equal or larger to a cache line 15010286Sandreas.hansson@arm.com if (system()->cacheLineSize() > range.granularity()) { 15110286Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at least as large " 15210286Sandreas.hansson@arm.com "as the cache line size\n", name()); 1539669SN/A } 15410286Sandreas.hansson@arm.com 15510286Sandreas.hansson@arm.com // ...and equal or smaller than the row-buffer size 15610286Sandreas.hansson@arm.com if (rowBufferSize < range.granularity()) { 15710286Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at most as large " 15810286Sandreas.hansson@arm.com "as the row-buffer size\n", name()); 15910286Sandreas.hansson@arm.com } 16010286Sandreas.hansson@arm.com // this is essentially the check above, so just to be sure 16110286Sandreas.hansson@arm.com assert(columnsPerStripe <= columnsPerRowBuffer); 1629566SN/A } 1639566SN/A } 16410207Sandreas.hansson@arm.com 16510207Sandreas.hansson@arm.com // some basic sanity checks 16610207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 16710207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 16810207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 16910207Sandreas.hansson@arm.com } 1709243SN/A} 1719243SN/A 1729243SN/Avoid 17310146Sandreas.hansson@arm.comDRAMCtrl::init() 17410140SN/A{ 17510140SN/A if (!port.isConnected()) { 17610146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 17710140SN/A } else { 17810140SN/A port.sendRangeChange(); 17910140SN/A } 18010140SN/A} 18110140SN/A 18210140SN/Avoid 18310146Sandreas.hansson@arm.comDRAMCtrl::startup() 1849243SN/A{ 18510143SN/A // update the start tick for the precharge accounting to the 18610143SN/A // current tick 18710208Sandreas.hansson@arm.com pwrStateTick = curTick(); 18810143SN/A 18910206Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 19010206Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 19110206Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 19210206Sandreas.hansson@arm.com // start of simulation 19310206Sandreas.hansson@arm.com busBusyUntil = curTick() + tRP + tRCD + tCL; 19410206Sandreas.hansson@arm.com 19510207Sandreas.hansson@arm.com // kick off the refresh, and give ourselves enough time to 19610207Sandreas.hansson@arm.com // precharge 19710207Sandreas.hansson@arm.com schedule(refreshEvent, curTick() + tREFI - tRP); 1989243SN/A} 1999243SN/A 2009243SN/ATick 20110146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 2029243SN/A{ 2039243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 2049243SN/A 2059243SN/A // do the actual memory access and turn the packet into a response 2069243SN/A access(pkt); 2079243SN/A 2089243SN/A Tick latency = 0; 2099243SN/A if (!pkt->memInhibitAsserted() && pkt->hasData()) { 2109243SN/A // this value is not supposed to be accurate, just enough to 2119243SN/A // keep things going, mimic a closed page 2129243SN/A latency = tRP + tRCD + tCL; 2139243SN/A } 2149243SN/A return latency; 2159243SN/A} 2169243SN/A 2179243SN/Abool 21810146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 2199243SN/A{ 2209831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 2219831SN/A readBufferSize, readQueue.size() + respQueue.size(), 2229831SN/A neededEntries); 2239243SN/A 2249831SN/A return 2259831SN/A (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 2269243SN/A} 2279243SN/A 2289243SN/Abool 22910146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 2309243SN/A{ 2319831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 2329831SN/A writeBufferSize, writeQueue.size(), neededEntries); 2339831SN/A return (writeQueue.size() + neededEntries) > writeBufferSize; 2349243SN/A} 2359243SN/A 23610146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 23710146Sandreas.hansson@arm.comDRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 23810143SN/A bool isRead) 2399243SN/A{ 2409669SN/A // decode the address based on the address mapping scheme, with 24110136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 24210136SN/A // channel, respectively 2439243SN/A uint8_t rank; 2449967SN/A uint8_t bank; 24510245Sandreas.hansson@arm.com // use a 64-bit unsigned during the computations as the row is 24610245Sandreas.hansson@arm.com // always the top bits, and check before creating the DRAMPacket 24710245Sandreas.hansson@arm.com uint64_t row; 2489243SN/A 24910286Sandreas.hansson@arm.com // truncate the address to a DRAM burst, which makes it unique to 25010286Sandreas.hansson@arm.com // a specific column, row, bank, rank and channel 2519831SN/A Addr addr = dramPktAddr / burstSize; 2529243SN/A 2539491SN/A // we have removed the lowest order address bits that denote the 2549831SN/A // position within the column 25510136SN/A if (addrMapping == Enums::RoRaBaChCo) { 2569491SN/A // the lowest order bits denote the column to ensure that 2579491SN/A // sequential cache lines occupy the same row 2589831SN/A addr = addr / columnsPerRowBuffer; 2599243SN/A 2609669SN/A // take out the channel part of the address 2619566SN/A addr = addr / channels; 2629566SN/A 2639669SN/A // after the channel bits, get the bank bits to interleave 2649669SN/A // over the banks 2659669SN/A bank = addr % banksPerRank; 2669669SN/A addr = addr / banksPerRank; 2679669SN/A 2689669SN/A // after the bank, we get the rank bits which thus interleaves 2699669SN/A // over the ranks 2709669SN/A rank = addr % ranksPerChannel; 2719669SN/A addr = addr / ranksPerChannel; 2729669SN/A 2739669SN/A // lastly, get the row bits 2749669SN/A row = addr % rowsPerBank; 2759669SN/A addr = addr / rowsPerBank; 27610136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 27710286Sandreas.hansson@arm.com // take out the lower-order column bits 27810286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 27910286Sandreas.hansson@arm.com 2809669SN/A // take out the channel part of the address 2819669SN/A addr = addr / channels; 2829669SN/A 28310286Sandreas.hansson@arm.com // next, the higher-order column bites 28410286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 2859669SN/A 2869669SN/A // after the column bits, we get the bank bits to interleave 2879491SN/A // over the banks 2889243SN/A bank = addr % banksPerRank; 2899243SN/A addr = addr / banksPerRank; 2909243SN/A 2919491SN/A // after the bank, we get the rank bits which thus interleaves 2929491SN/A // over the ranks 2939243SN/A rank = addr % ranksPerChannel; 2949243SN/A addr = addr / ranksPerChannel; 2959243SN/A 2969491SN/A // lastly, get the row bits 2979243SN/A row = addr % rowsPerBank; 2989243SN/A addr = addr / rowsPerBank; 29910136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 3009491SN/A // optimise for closed page mode and utilise maximum 3019491SN/A // parallelism of the DRAM (at the cost of power) 3029491SN/A 30310286Sandreas.hansson@arm.com // take out the lower-order column bits 30410286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 30510286Sandreas.hansson@arm.com 3069566SN/A // take out the channel part of the address, not that this has 3079566SN/A // to match with how accesses are interleaved between the 3089566SN/A // controllers in the address mapping 3099566SN/A addr = addr / channels; 3109566SN/A 3119491SN/A // start with the bank bits, as this provides the maximum 3129491SN/A // opportunity for parallelism between requests 3139243SN/A bank = addr % banksPerRank; 3149243SN/A addr = addr / banksPerRank; 3159243SN/A 3169491SN/A // next get the rank bits 3179243SN/A rank = addr % ranksPerChannel; 3189243SN/A addr = addr / ranksPerChannel; 3199243SN/A 32010286Sandreas.hansson@arm.com // next, the higher-order column bites 32110286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3229243SN/A 3239491SN/A // lastly, get the row bits 3249243SN/A row = addr % rowsPerBank; 3259243SN/A addr = addr / rowsPerBank; 3269243SN/A } else 3279243SN/A panic("Unknown address mapping policy chosen!"); 3289243SN/A 3299243SN/A assert(rank < ranksPerChannel); 3309243SN/A assert(bank < banksPerRank); 3319243SN/A assert(row < rowsPerBank); 33210245Sandreas.hansson@arm.com assert(row < Bank::NO_ROW); 3339243SN/A 3349243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 3359831SN/A dramPktAddr, rank, bank, row); 3369243SN/A 3379243SN/A // create the corresponding DRAM packet with the entry time and 3389567SN/A // ready time set to the current tick, the latter will be updated 3399567SN/A // later 3409967SN/A uint16_t bank_id = banksPerRank * rank + bank; 3419967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 3429967SN/A size, banks[rank][bank]); 3439243SN/A} 3449243SN/A 3459243SN/Avoid 34610146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 3479243SN/A{ 3489243SN/A // only add to the read queue here. whenever the request is 3499243SN/A // eventually done, set the readyTime, and call schedule() 3509243SN/A assert(!pkt->isWrite()); 3519243SN/A 3529831SN/A assert(pktCount != 0); 3539831SN/A 3549831SN/A // if the request size is larger than burst size, the pkt is split into 3559831SN/A // multiple DRAM packets 3569831SN/A // Note if the pkt starting address is not aligened to burst size, the 3579831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 3589831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 3599831SN/A // check read packets against packets in write queue. 3609243SN/A Addr addr = pkt->getAddr(); 3619831SN/A unsigned pktsServicedByWrQ = 0; 3629831SN/A BurstHelper* burst_helper = NULL; 3639831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 3649831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 3659831SN/A pkt->getAddr() + pkt->getSize()) - addr; 3669831SN/A readPktSize[ceilLog2(size)]++; 3679831SN/A readBursts++; 3689243SN/A 3699831SN/A // First check write buffer to see if the data is already at 3709831SN/A // the controller 3719831SN/A bool foundInWrQ = false; 3729833SN/A for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) { 3739832SN/A // check if the read is subsumed in the write entry we are 3749832SN/A // looking at 3759832SN/A if ((*i)->addr <= addr && 3769832SN/A (addr + size) <= ((*i)->addr + (*i)->size)) { 3779831SN/A foundInWrQ = true; 3789831SN/A servicedByWrQ++; 3799831SN/A pktsServicedByWrQ++; 3809831SN/A DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 3819831SN/A "write queue\n", addr, size); 3829975SN/A bytesReadWrQ += burstSize; 3839831SN/A break; 3849831SN/A } 3859243SN/A } 3869831SN/A 3879831SN/A // If not found in the write q, make a DRAM packet and 3889831SN/A // push it onto the read queue 3899831SN/A if (!foundInWrQ) { 3909831SN/A 3919831SN/A // Make the burst helper for split packets 3929831SN/A if (pktCount > 1 && burst_helper == NULL) { 3939831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 3949831SN/A "dram requests\n", pkt->getAddr(), pktCount); 3959831SN/A burst_helper = new BurstHelper(pktCount); 3969831SN/A } 3979831SN/A 3989966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 3999831SN/A dram_pkt->burstHelper = burst_helper; 4009831SN/A 4019831SN/A assert(!readQueueFull(1)); 4029831SN/A rdQLenPdf[readQueue.size() + respQueue.size()]++; 4039831SN/A 4049831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 4059831SN/A 4069831SN/A readQueue.push_back(dram_pkt); 4079831SN/A 4089831SN/A // Update stats 4099831SN/A avgRdQLen = readQueue.size() + respQueue.size(); 4109831SN/A } 4119831SN/A 4129831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 4139831SN/A addr = (addr | (burstSize - 1)) + 1; 4149243SN/A } 4159243SN/A 4169831SN/A // If all packets are serviced by write queue, we send the repsonse back 4179831SN/A if (pktsServicedByWrQ == pktCount) { 4189831SN/A accessAndRespond(pkt, frontendLatency); 4199831SN/A return; 4209831SN/A } 4219243SN/A 4229831SN/A // Update how many split packets are serviced by write queue 4239831SN/A if (burst_helper != NULL) 4249831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 4259243SN/A 42610206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 42710206Sandreas.hansson@arm.com // queue, do so now 42810206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 4299567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 4309567SN/A schedule(nextReqEvent, curTick()); 4319243SN/A } 4329243SN/A} 4339243SN/A 4349243SN/Avoid 43510146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 4369243SN/A{ 4379243SN/A // only add to the write queue here. whenever the request is 4389243SN/A // eventually done, set the readyTime, and call schedule() 4399243SN/A assert(pkt->isWrite()); 4409243SN/A 4419831SN/A // if the request size is larger than burst size, the pkt is split into 4429831SN/A // multiple DRAM packets 4439831SN/A Addr addr = pkt->getAddr(); 4449831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4459831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4469831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4479831SN/A writePktSize[ceilLog2(size)]++; 4489831SN/A writeBursts++; 4499243SN/A 4509832SN/A // see if we can merge with an existing item in the write 4519838SN/A // queue and keep track of whether we have merged or not so we 4529838SN/A // can stop at that point and also avoid enqueueing a new 4539838SN/A // request 4549832SN/A bool merged = false; 4559832SN/A auto w = writeQueue.begin(); 4569243SN/A 4579832SN/A while(!merged && w != writeQueue.end()) { 4589832SN/A // either of the two could be first, if they are the same 4599832SN/A // it does not matter which way we go 4609832SN/A if ((*w)->addr >= addr) { 4619838SN/A // the existing one starts after the new one, figure 4629838SN/A // out where the new one ends with respect to the 4639838SN/A // existing one 4649832SN/A if ((addr + size) >= ((*w)->addr + (*w)->size)) { 4659832SN/A // check if the existing one is completely 4669832SN/A // subsumed in the new one 4679832SN/A DPRINTF(DRAM, "Merging write covering existing burst\n"); 4689832SN/A merged = true; 4699832SN/A // update both the address and the size 4709832SN/A (*w)->addr = addr; 4719832SN/A (*w)->size = size; 4729832SN/A } else if ((addr + size) >= (*w)->addr && 4739832SN/A ((*w)->addr + (*w)->size - addr) <= burstSize) { 4749832SN/A // the new one is just before or partially 4759832SN/A // overlapping with the existing one, and together 4769832SN/A // they fit within a burst 4779832SN/A DPRINTF(DRAM, "Merging write before existing burst\n"); 4789832SN/A merged = true; 4799832SN/A // the existing queue item needs to be adjusted with 4809832SN/A // respect to both address and size 48110047SN/A (*w)->size = (*w)->addr + (*w)->size - addr; 4829832SN/A (*w)->addr = addr; 4839832SN/A } 4849832SN/A } else { 4859838SN/A // the new one starts after the current one, figure 4869838SN/A // out where the existing one ends with respect to the 4879838SN/A // new one 4889832SN/A if (((*w)->addr + (*w)->size) >= (addr + size)) { 4899832SN/A // check if the new one is completely subsumed in the 4909832SN/A // existing one 4919832SN/A DPRINTF(DRAM, "Merging write into existing burst\n"); 4929832SN/A merged = true; 4939832SN/A // no adjustments necessary 4949832SN/A } else if (((*w)->addr + (*w)->size) >= addr && 4959832SN/A (addr + size - (*w)->addr) <= burstSize) { 4969832SN/A // the existing one is just before or partially 4979832SN/A // overlapping with the new one, and together 4989832SN/A // they fit within a burst 4999832SN/A DPRINTF(DRAM, "Merging write after existing burst\n"); 5009832SN/A merged = true; 5019832SN/A // the address is right, and only the size has 5029832SN/A // to be adjusted 5039832SN/A (*w)->size = addr + size - (*w)->addr; 5049832SN/A } 5059832SN/A } 5069832SN/A ++w; 5079832SN/A } 5089243SN/A 5099832SN/A // if the item was not merged we need to create a new write 5109832SN/A // and enqueue it 5119832SN/A if (!merged) { 5129966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 5139243SN/A 5149832SN/A assert(writeQueue.size() < writeBufferSize); 5159832SN/A wrQLenPdf[writeQueue.size()]++; 5169243SN/A 5179832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 5189831SN/A 5199832SN/A writeQueue.push_back(dram_pkt); 5209831SN/A 5219832SN/A // Update stats 5229832SN/A avgWrQLen = writeQueue.size(); 5239977SN/A } else { 5249977SN/A // keep track of the fact that this burst effectively 5259977SN/A // disappeared as it was merged with an existing one 5269977SN/A mergedWrBursts++; 5279832SN/A } 5289832SN/A 5299831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 5309831SN/A addr = (addr | (burstSize - 1)) + 1; 5319831SN/A } 5329243SN/A 5339243SN/A // we do not wait for the writes to be send to the actual memory, 5349243SN/A // but instead take responsibility for the consistency here and 5359243SN/A // snoop the write queue for any upcoming reads 5369831SN/A // @todo, if a pkt size is larger than burst size, we might need a 5379831SN/A // different front end latency 5389726SN/A accessAndRespond(pkt, frontendLatency); 5399243SN/A 54010206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 54110206Sandreas.hansson@arm.com // queue, do so now 54210206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 54310206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 54410206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 5459243SN/A } 5469243SN/A} 5479243SN/A 5489243SN/Avoid 54910146Sandreas.hansson@arm.comDRAMCtrl::printQs() const { 5509243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 5519833SN/A for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 5529243SN/A DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 5539243SN/A } 5549243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 5559833SN/A for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 5569243SN/A DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 5579243SN/A } 5589243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 5599833SN/A for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 5609243SN/A DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 5619243SN/A } 5629243SN/A} 5639243SN/A 5649243SN/Abool 56510146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 5669243SN/A{ 5679349SN/A /// @todo temporary hack to deal with memory corruption issues until 5689349SN/A /// 4-phase transactions are complete 5699349SN/A for (int x = 0; x < pendingDelete.size(); x++) 5709349SN/A delete pendingDelete[x]; 5719349SN/A pendingDelete.clear(); 5729349SN/A 5739243SN/A // This is where we enter from the outside world 5749567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 5759831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 5769243SN/A 5779567SN/A // simply drop inhibited packets for now 5789567SN/A if (pkt->memInhibitAsserted()) { 57910143SN/A DPRINTF(DRAM, "Inhibited packet -- Dropping it now\n"); 5809567SN/A pendingDelete.push_back(pkt); 5819567SN/A return true; 5829567SN/A } 5839243SN/A 5849243SN/A // Calc avg gap between requests 5859243SN/A if (prevArrival != 0) { 5869243SN/A totGap += curTick() - prevArrival; 5879243SN/A } 5889243SN/A prevArrival = curTick(); 5899243SN/A 5909831SN/A 5919831SN/A // Find out how many dram packets a pkt translates to 5929831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 5939831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 5949831SN/A // multiple dram packets 5959243SN/A unsigned size = pkt->getSize(); 5969831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 5979831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 5989243SN/A 5999243SN/A // check local buffers and do not accept if full 6009243SN/A if (pkt->isRead()) { 6019567SN/A assert(size != 0); 6029831SN/A if (readQueueFull(dram_pkt_count)) { 6039567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 6049243SN/A // remember that we have to retry this port 6059243SN/A retryRdReq = true; 6069243SN/A numRdRetry++; 6079243SN/A return false; 6089243SN/A } else { 6099831SN/A addToReadQueue(pkt, dram_pkt_count); 6109243SN/A readReqs++; 6119977SN/A bytesReadSys += size; 6129243SN/A } 6139243SN/A } else if (pkt->isWrite()) { 6149567SN/A assert(size != 0); 6159831SN/A if (writeQueueFull(dram_pkt_count)) { 6169567SN/A DPRINTF(DRAM, "Write queue full, not accepting\n"); 6179243SN/A // remember that we have to retry this port 6189243SN/A retryWrReq = true; 6199243SN/A numWrRetry++; 6209243SN/A return false; 6219243SN/A } else { 6229831SN/A addToWriteQueue(pkt, dram_pkt_count); 6239243SN/A writeReqs++; 6249977SN/A bytesWrittenSys += size; 6259243SN/A } 6269243SN/A } else { 6279243SN/A DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 6289243SN/A neitherReadNorWrite++; 6299726SN/A accessAndRespond(pkt, 1); 6309243SN/A } 6319243SN/A 6329243SN/A return true; 6339243SN/A} 6349243SN/A 6359243SN/Avoid 63610146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 6379243SN/A{ 6389243SN/A DPRINTF(DRAM, 6399243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 6409243SN/A 6419831SN/A DRAMPacket* dram_pkt = respQueue.front(); 6429243SN/A 6439831SN/A if (dram_pkt->burstHelper) { 6449831SN/A // it is a split packet 6459831SN/A dram_pkt->burstHelper->burstsServiced++; 6469831SN/A if (dram_pkt->burstHelper->burstsServiced == 64710143SN/A dram_pkt->burstHelper->burstCount) { 6489831SN/A // we have now serviced all children packets of a system packet 6499831SN/A // so we can now respond to the requester 6509831SN/A // @todo we probably want to have a different front end and back 6519831SN/A // end latency for split packets 6529831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6539831SN/A delete dram_pkt->burstHelper; 6549831SN/A dram_pkt->burstHelper = NULL; 6559831SN/A } 6569831SN/A } else { 6579831SN/A // it is not a split packet 6589831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6599831SN/A } 6609243SN/A 6619831SN/A delete respQueue.front(); 6629831SN/A respQueue.pop_front(); 6639243SN/A 6649831SN/A if (!respQueue.empty()) { 6659831SN/A assert(respQueue.front()->readyTime >= curTick()); 6669831SN/A assert(!respondEvent.scheduled()); 6679831SN/A schedule(respondEvent, respQueue.front()->readyTime); 6689831SN/A } else { 6699831SN/A // if there is nothing left in any queue, signal a drain 6709831SN/A if (writeQueue.empty() && readQueue.empty() && 6719831SN/A drainManager) { 6729831SN/A drainManager->signalDrainDone(); 6739831SN/A drainManager = NULL; 6749831SN/A } 6759831SN/A } 6769567SN/A 6779831SN/A // We have made a location in the queue available at this point, 6789831SN/A // so if there is a read that was forced to wait, retry now 6799831SN/A if (retryRdReq) { 6809831SN/A retryRdReq = false; 6819831SN/A port.sendRetry(); 6829831SN/A } 6839243SN/A} 6849243SN/A 6859243SN/Avoid 68610206Sandreas.hansson@arm.comDRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue) 6879243SN/A{ 68810206Sandreas.hansson@arm.com // This method does the arbitration between requests. The chosen 68910206Sandreas.hansson@arm.com // packet is simply moved to the head of the queue. The other 69010206Sandreas.hansson@arm.com // methods know that this is the place to look. For example, with 69110206Sandreas.hansson@arm.com // FCFS, this method does nothing 69210206Sandreas.hansson@arm.com assert(!queue.empty()); 6939243SN/A 69410206Sandreas.hansson@arm.com if (queue.size() == 1) { 69510206Sandreas.hansson@arm.com DPRINTF(DRAM, "Single request, nothing to do\n"); 6969243SN/A return; 6979243SN/A } 6989243SN/A 6999243SN/A if (memSchedPolicy == Enums::fcfs) { 7009243SN/A // Do nothing, since the correct request is already head 7019243SN/A } else if (memSchedPolicy == Enums::frfcfs) { 70210206Sandreas.hansson@arm.com reorderQueue(queue); 7039243SN/A } else 7049243SN/A panic("No scheduling policy chosen\n"); 7059243SN/A} 7069243SN/A 7079243SN/Avoid 70810146Sandreas.hansson@arm.comDRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue) 7099974SN/A{ 7109974SN/A // Only determine this when needed 7119974SN/A uint64_t earliest_banks = 0; 7129974SN/A 7139974SN/A // Search for row hits first, if no row hit is found then schedule the 7149974SN/A // packet to one of the earliest banks available 7159974SN/A bool found_earliest_pkt = false; 7169974SN/A auto selected_pkt_it = queue.begin(); 7179974SN/A 7189974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 7199974SN/A DRAMPacket* dram_pkt = *i; 7209974SN/A const Bank& bank = dram_pkt->bankRef; 7219974SN/A // Check if it is a row hit 7229974SN/A if (bank.openRow == dram_pkt->row) { 72310211Sandreas.hansson@arm.com // FCFS within the hits 7249974SN/A DPRINTF(DRAM, "Row buffer hit\n"); 7259974SN/A selected_pkt_it = i; 7269974SN/A break; 7279974SN/A } else if (!found_earliest_pkt) { 7289974SN/A // No row hit, go for first ready 7299974SN/A if (earliest_banks == 0) 73010211Sandreas.hansson@arm.com earliest_banks = minBankActAt(queue); 73110211Sandreas.hansson@arm.com 73210211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue an 73310211Sandreas.hansson@arm.com // activate, this is calculated in minBankActAt and could 73410211Sandreas.hansson@arm.com // be cached 73510211Sandreas.hansson@arm.com Tick act_at = bank.openRow == Bank::NO_ROW ? 73610211Sandreas.hansson@arm.com bank.actAllowedAt : 73710211Sandreas.hansson@arm.com std::max(bank.preAllowedAt, curTick()) + tRP; 7389974SN/A 7399974SN/A // Bank is ready or is the first available bank 74010211Sandreas.hansson@arm.com if (act_at <= curTick() || 7419974SN/A bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) { 7429974SN/A // Remember the packet to be scheduled to one of the earliest 74310211Sandreas.hansson@arm.com // banks available, FCFS amongst the earliest banks 7449974SN/A selected_pkt_it = i; 7459974SN/A found_earliest_pkt = true; 7469974SN/A } 7479974SN/A } 7489974SN/A } 7499974SN/A 7509974SN/A DRAMPacket* selected_pkt = *selected_pkt_it; 7519974SN/A queue.erase(selected_pkt_it); 7529974SN/A queue.push_front(selected_pkt); 7539974SN/A} 7549974SN/A 7559974SN/Avoid 75610146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 7579243SN/A{ 7589243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 7599243SN/A 7609243SN/A bool needsResponse = pkt->needsResponse(); 7619243SN/A // do the actual memory access which also turns the packet into a 7629243SN/A // response 7639243SN/A access(pkt); 7649243SN/A 7659243SN/A // turn packet around to go back to requester if response expected 7669243SN/A if (needsResponse) { 7679243SN/A // access already turned the packet into a response 7689243SN/A assert(pkt->isResponse()); 7699243SN/A 7709549SN/A // @todo someone should pay for this 7719549SN/A pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; 7729549SN/A 7739726SN/A // queue the packet in the response queue to be sent out after 7749726SN/A // the static latency has passed 7759726SN/A port.schedTimingResp(pkt, curTick() + static_latency); 7769243SN/A } else { 7779587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 7789587SN/A // is still having a pointer to it 7799587SN/A pendingDelete.push_back(pkt); 7809243SN/A } 7819243SN/A 7829243SN/A DPRINTF(DRAM, "Done\n"); 7839243SN/A 7849243SN/A return; 7859243SN/A} 7869243SN/A 7879243SN/Avoid 78810246Sandreas.hansson@arm.comDRAMCtrl::activateBank(Bank& bank, Tick act_tick, uint32_t row) 7899488SN/A{ 79010246Sandreas.hansson@arm.com // get the rank index from the bank 79110246Sandreas.hansson@arm.com uint8_t rank = bank.rank; 79210246Sandreas.hansson@arm.com 7939969SN/A assert(actTicks[rank].size() == activationLimit); 7949488SN/A 7959488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 7969488SN/A 79710207Sandreas.hansson@arm.com // update the open row 79810246Sandreas.hansson@arm.com assert(bank.openRow == Bank::NO_ROW); 79910246Sandreas.hansson@arm.com bank.openRow = row; 80010207Sandreas.hansson@arm.com 80110207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 80210207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 80310207Sandreas.hansson@arm.com // precharge 80410246Sandreas.hansson@arm.com bank.bytesAccessed = 0; 80510246Sandreas.hansson@arm.com bank.rowAccesses = 0; 80610207Sandreas.hansson@arm.com 80710207Sandreas.hansson@arm.com ++numBanksActive; 80810207Sandreas.hansson@arm.com assert(numBanksActive <= banksPerRank * ranksPerChannel); 80910207Sandreas.hansson@arm.com 81010247Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n", 81110247Sandreas.hansson@arm.com bank.bank, bank.rank, act_tick, numBanksActive); 81210247Sandreas.hansson@arm.com 81310247Sandreas.hansson@arm.com DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK), bank.bank, 81410247Sandreas.hansson@arm.com bank.rank); 8159975SN/A 81610211Sandreas.hansson@arm.com // The next access has to respect tRAS for this bank 81710246Sandreas.hansson@arm.com bank.preAllowedAt = act_tick + tRAS; 81810211Sandreas.hansson@arm.com 81910211Sandreas.hansson@arm.com // Respect the row-to-column command delay 82010246Sandreas.hansson@arm.com bank.colAllowedAt = act_tick + tRCD; 82110211Sandreas.hansson@arm.com 8229971SN/A // start by enforcing tRRD 8239971SN/A for(int i = 0; i < banksPerRank; i++) { 82410210Sandreas.hansson@arm.com // next activate to any bank in this rank must not happen 82510210Sandreas.hansson@arm.com // before tRRD 82610210Sandreas.hansson@arm.com banks[rank][i].actAllowedAt = std::max(act_tick + tRRD, 82710210Sandreas.hansson@arm.com banks[rank][i].actAllowedAt); 8289971SN/A } 82910208Sandreas.hansson@arm.com 8309971SN/A // next, we deal with tXAW, if the activation limit is disabled 8319971SN/A // then we are done 8329969SN/A if (actTicks[rank].empty()) 8339824SN/A return; 8349824SN/A 8359488SN/A // sanity check 8369969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 83710210Sandreas.hansson@arm.com panic("Got %d activates in window %d (%llu - %llu) which is smaller " 83810210Sandreas.hansson@arm.com "than %llu\n", activationLimit, act_tick - actTicks[rank].back(), 83910210Sandreas.hansson@arm.com act_tick, actTicks[rank].back(), tXAW); 8409488SN/A } 8419488SN/A 8429488SN/A // shift the times used for the book keeping, the last element 8439488SN/A // (highest index) is the oldest one and hence the lowest value 8449969SN/A actTicks[rank].pop_back(); 8459488SN/A 8469488SN/A // record an new activation (in the future) 8479969SN/A actTicks[rank].push_front(act_tick); 8489488SN/A 8499488SN/A // cannot activate more than X times in time window tXAW, push the 8509488SN/A // next one (the X + 1'st activate) to be tXAW away from the 8519488SN/A // oldest in our window of X 8529969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 8539488SN/A DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate no earlier " 85410210Sandreas.hansson@arm.com "than %llu\n", activationLimit, actTicks[rank].back() + tXAW); 8559488SN/A for(int j = 0; j < banksPerRank; j++) 8569488SN/A // next activate must not happen before end of window 85710210Sandreas.hansson@arm.com banks[rank][j].actAllowedAt = 85810210Sandreas.hansson@arm.com std::max(actTicks[rank].back() + tXAW, 85910210Sandreas.hansson@arm.com banks[rank][j].actAllowedAt); 8609488SN/A } 86110208Sandreas.hansson@arm.com 86210208Sandreas.hansson@arm.com // at the point when this activate takes place, make sure we 86310208Sandreas.hansson@arm.com // transition to the active power state 86410208Sandreas.hansson@arm.com if (!activateEvent.scheduled()) 86510208Sandreas.hansson@arm.com schedule(activateEvent, act_tick); 86610208Sandreas.hansson@arm.com else if (activateEvent.when() > act_tick) 86710208Sandreas.hansson@arm.com // move it sooner in time 86810208Sandreas.hansson@arm.com reschedule(activateEvent, act_tick); 86910208Sandreas.hansson@arm.com} 87010208Sandreas.hansson@arm.com 87110208Sandreas.hansson@arm.comvoid 87210208Sandreas.hansson@arm.comDRAMCtrl::processActivateEvent() 87310208Sandreas.hansson@arm.com{ 87410208Sandreas.hansson@arm.com // we should transition to the active state as soon as any bank is active 87510208Sandreas.hansson@arm.com if (pwrState != PWR_ACT) 87610208Sandreas.hansson@arm.com // note that at this point numBanksActive could be back at 87710208Sandreas.hansson@arm.com // zero again due to a precharge scheduled in the future 87810208Sandreas.hansson@arm.com schedulePowerEvent(PWR_ACT, curTick()); 8799488SN/A} 8809488SN/A 8819488SN/Avoid 88210247Sandreas.hansson@arm.comDRAMCtrl::prechargeBank(Bank& bank, Tick pre_at, bool trace) 88310207Sandreas.hansson@arm.com{ 88410207Sandreas.hansson@arm.com // make sure the bank has an open row 88510207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 88610207Sandreas.hansson@arm.com 88710207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 88810207Sandreas.hansson@arm.com // the page 88910207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 89010207Sandreas.hansson@arm.com 89110207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 89210207Sandreas.hansson@arm.com 89310214Sandreas.hansson@arm.com // no precharge allowed before this one 89410214Sandreas.hansson@arm.com bank.preAllowedAt = pre_at; 89510214Sandreas.hansson@arm.com 89610211Sandreas.hansson@arm.com Tick pre_done_at = pre_at + tRP; 89710211Sandreas.hansson@arm.com 89810211Sandreas.hansson@arm.com bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at); 89910207Sandreas.hansson@arm.com 90010207Sandreas.hansson@arm.com assert(numBanksActive != 0); 90110207Sandreas.hansson@arm.com --numBanksActive; 90210207Sandreas.hansson@arm.com 90310247Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got " 90410247Sandreas.hansson@arm.com "%d active\n", bank.bank, bank.rank, pre_at, numBanksActive); 90510247Sandreas.hansson@arm.com 90610247Sandreas.hansson@arm.com if (trace) 90710247Sandreas.hansson@arm.com DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK), 90810247Sandreas.hansson@arm.com bank.bank, bank.rank); 90910207Sandreas.hansson@arm.com 91010208Sandreas.hansson@arm.com // if we look at the current number of active banks we might be 91110208Sandreas.hansson@arm.com // tempted to think the DRAM is now idle, however this can be 91210208Sandreas.hansson@arm.com // undone by an activate that is scheduled to happen before we 91310208Sandreas.hansson@arm.com // would have reached the idle state, so schedule an event and 91410208Sandreas.hansson@arm.com // rather check once we actually make it to the point in time when 91510208Sandreas.hansson@arm.com // the (last) precharge takes place 91610208Sandreas.hansson@arm.com if (!prechargeEvent.scheduled()) 91710211Sandreas.hansson@arm.com schedule(prechargeEvent, pre_done_at); 91810211Sandreas.hansson@arm.com else if (prechargeEvent.when() < pre_done_at) 91910211Sandreas.hansson@arm.com reschedule(prechargeEvent, pre_done_at); 92010208Sandreas.hansson@arm.com} 92110208Sandreas.hansson@arm.com 92210208Sandreas.hansson@arm.comvoid 92310208Sandreas.hansson@arm.comDRAMCtrl::processPrechargeEvent() 92410208Sandreas.hansson@arm.com{ 92510207Sandreas.hansson@arm.com // if we reached zero, then special conditions apply as we track 92610207Sandreas.hansson@arm.com // if all banks are precharged for the power models 92710207Sandreas.hansson@arm.com if (numBanksActive == 0) { 92810208Sandreas.hansson@arm.com // we should transition to the idle state when the last bank 92910208Sandreas.hansson@arm.com // is precharged 93010208Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 93110207Sandreas.hansson@arm.com } 93210207Sandreas.hansson@arm.com} 93310207Sandreas.hansson@arm.com 93410207Sandreas.hansson@arm.comvoid 93510146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 9369243SN/A{ 9379243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 9389243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 9399243SN/A 94010211Sandreas.hansson@arm.com // get the bank 9419967SN/A Bank& bank = dram_pkt->bankRef; 9429243SN/A 94310211Sandreas.hansson@arm.com // for the state we need to track if it is a row hit or not 94410211Sandreas.hansson@arm.com bool row_hit = true; 94510211Sandreas.hansson@arm.com 94610211Sandreas.hansson@arm.com // respect any constraints on the command (e.g. tRCD or tCCD) 94710211Sandreas.hansson@arm.com Tick cmd_at = std::max(bank.colAllowedAt, curTick()); 94810211Sandreas.hansson@arm.com 94910211Sandreas.hansson@arm.com // Determine the access latency and update the bank state 95010211Sandreas.hansson@arm.com if (bank.openRow == dram_pkt->row) { 95110211Sandreas.hansson@arm.com // nothing to do 95210209Sandreas.hansson@arm.com } else { 95310211Sandreas.hansson@arm.com row_hit = false; 95410211Sandreas.hansson@arm.com 95510209Sandreas.hansson@arm.com // If there is a page open, precharge it. 95610209Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 95710211Sandreas.hansson@arm.com prechargeBank(bank, std::max(bank.preAllowedAt, curTick())); 9589488SN/A } 9599973SN/A 96010211Sandreas.hansson@arm.com // next we need to account for the delay in activating the 96110211Sandreas.hansson@arm.com // page 96210211Sandreas.hansson@arm.com Tick act_tick = std::max(bank.actAllowedAt, curTick()); 9639973SN/A 96410210Sandreas.hansson@arm.com // Record the activation and deal with all the global timing 96510210Sandreas.hansson@arm.com // constraints caused be a new activation (tRRD and tXAW) 96610246Sandreas.hansson@arm.com activateBank(bank, act_tick, dram_pkt->row); 96710210Sandreas.hansson@arm.com 96810211Sandreas.hansson@arm.com // issue the command as early as possible 96910211Sandreas.hansson@arm.com cmd_at = bank.colAllowedAt; 97010209Sandreas.hansson@arm.com } 97110209Sandreas.hansson@arm.com 97210211Sandreas.hansson@arm.com // we need to wait until the bus is available before we can issue 97310211Sandreas.hansson@arm.com // the command 97410211Sandreas.hansson@arm.com cmd_at = std::max(cmd_at, busBusyUntil - tCL); 97510211Sandreas.hansson@arm.com 97610211Sandreas.hansson@arm.com // update the packet ready time 97710211Sandreas.hansson@arm.com dram_pkt->readyTime = cmd_at + tCL + tBURST; 97810211Sandreas.hansson@arm.com 97910211Sandreas.hansson@arm.com // only one burst can use the bus at any one point in time 98010211Sandreas.hansson@arm.com assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 98110211Sandreas.hansson@arm.com 98210211Sandreas.hansson@arm.com // not strictly necessary, but update the time for the next 98310211Sandreas.hansson@arm.com // read/write (add a max with tCCD here) 98410211Sandreas.hansson@arm.com bank.colAllowedAt = cmd_at + tBURST; 98510211Sandreas.hansson@arm.com 98610212Sandreas.hansson@arm.com // If this is a write, we also need to respect the write recovery 98710212Sandreas.hansson@arm.com // time before a precharge, in the case of a read, respect the 98810212Sandreas.hansson@arm.com // read to precharge constraint 98910212Sandreas.hansson@arm.com bank.preAllowedAt = std::max(bank.preAllowedAt, 99010212Sandreas.hansson@arm.com dram_pkt->isRead ? cmd_at + tRTP : 99110212Sandreas.hansson@arm.com dram_pkt->readyTime + tWR); 99210210Sandreas.hansson@arm.com 99310209Sandreas.hansson@arm.com // increment the bytes accessed and the accesses per row 99410209Sandreas.hansson@arm.com bank.bytesAccessed += burstSize; 99510209Sandreas.hansson@arm.com ++bank.rowAccesses; 99610209Sandreas.hansson@arm.com 99710209Sandreas.hansson@arm.com // if we reached the max, then issue with an auto-precharge 99810209Sandreas.hansson@arm.com bool auto_precharge = pageMgmt == Enums::close || 99910209Sandreas.hansson@arm.com bank.rowAccesses == maxAccessesPerRow; 100010209Sandreas.hansson@arm.com 100110209Sandreas.hansson@arm.com // if we did not hit the limit, we might still want to 100210209Sandreas.hansson@arm.com // auto-precharge 100310209Sandreas.hansson@arm.com if (!auto_precharge && 100410209Sandreas.hansson@arm.com (pageMgmt == Enums::open_adaptive || 100510209Sandreas.hansson@arm.com pageMgmt == Enums::close_adaptive)) { 100610209Sandreas.hansson@arm.com // a twist on the open and close page policies: 100710209Sandreas.hansson@arm.com // 1) open_adaptive page policy does not blindly keep the 100810209Sandreas.hansson@arm.com // page open, but close it if there are no row hits, and there 100910209Sandreas.hansson@arm.com // are bank conflicts in the queue 101010209Sandreas.hansson@arm.com // 2) close_adaptive page policy does not blindly close the 101110209Sandreas.hansson@arm.com // page, but closes it only if there are no row hits in the queue. 101210209Sandreas.hansson@arm.com // In this case, only force an auto precharge when there 101310209Sandreas.hansson@arm.com // are no same page hits in the queue 101410209Sandreas.hansson@arm.com bool got_more_hits = false; 101510209Sandreas.hansson@arm.com bool got_bank_conflict = false; 101610209Sandreas.hansson@arm.com 101710209Sandreas.hansson@arm.com // either look at the read queue or write queue 101810209Sandreas.hansson@arm.com const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 101910209Sandreas.hansson@arm.com writeQueue; 102010209Sandreas.hansson@arm.com auto p = queue.begin(); 102110209Sandreas.hansson@arm.com // make sure we are not considering the packet that we are 102210209Sandreas.hansson@arm.com // currently dealing with (which is the head of the queue) 102310209Sandreas.hansson@arm.com ++p; 102410209Sandreas.hansson@arm.com 102510209Sandreas.hansson@arm.com // keep on looking until we have found required condition or 102610209Sandreas.hansson@arm.com // reached the end 102710209Sandreas.hansson@arm.com while (!(got_more_hits && 102810209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive)) && 102910209Sandreas.hansson@arm.com p != queue.end()) { 103010209Sandreas.hansson@arm.com bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 103110209Sandreas.hansson@arm.com (dram_pkt->bank == (*p)->bank); 103210209Sandreas.hansson@arm.com bool same_row = dram_pkt->row == (*p)->row; 103310209Sandreas.hansson@arm.com got_more_hits |= same_rank_bank && same_row; 103410209Sandreas.hansson@arm.com got_bank_conflict |= same_rank_bank && !same_row; 10359973SN/A ++p; 103610141SN/A } 103710141SN/A 103810209Sandreas.hansson@arm.com // auto pre-charge when either 103910209Sandreas.hansson@arm.com // 1) open_adaptive policy, we have not got any more hits, and 104010209Sandreas.hansson@arm.com // have a bank conflict 104110209Sandreas.hansson@arm.com // 2) close_adaptive policy and we have not got any more hits 104210209Sandreas.hansson@arm.com auto_precharge = !got_more_hits && 104310209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive); 104410209Sandreas.hansson@arm.com } 104510142SN/A 104610247Sandreas.hansson@arm.com // DRAMPower trace command to be written 104710247Sandreas.hansson@arm.com std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR"; 104810247Sandreas.hansson@arm.com 104910209Sandreas.hansson@arm.com // if this access should use auto-precharge, then we are 105010209Sandreas.hansson@arm.com // closing the row 105110209Sandreas.hansson@arm.com if (auto_precharge) { 105210247Sandreas.hansson@arm.com prechargeBank(bank, std::max(curTick(), bank.preAllowedAt), false); 105310247Sandreas.hansson@arm.com 105410247Sandreas.hansson@arm.com mem_cmd.append("A"); 10559973SN/A 105610209Sandreas.hansson@arm.com DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 105710209Sandreas.hansson@arm.com } 10589963SN/A 10599243SN/A // Update bus state 10609243SN/A busBusyUntil = dram_pkt->readyTime; 10619243SN/A 106210211Sandreas.hansson@arm.com DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n", 106310211Sandreas.hansson@arm.com dram_pkt->addr, dram_pkt->readyTime, busBusyUntil); 10649243SN/A 106510247Sandreas.hansson@arm.com DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK), mem_cmd, 106610247Sandreas.hansson@arm.com dram_pkt->bank, dram_pkt->rank); 106710247Sandreas.hansson@arm.com 106810206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 106910206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 107010206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 107110206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 107210206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 10739972SN/A 107410206Sandreas.hansson@arm.com // Update the stats and schedule the next request 10759977SN/A if (dram_pkt->isRead) { 107610147Sandreas.hansson@arm.com ++readsThisTime; 107710211Sandreas.hansson@arm.com if (row_hit) 10789977SN/A readRowHits++; 10799977SN/A bytesReadDRAM += burstSize; 10809977SN/A perBankRdBursts[dram_pkt->bankId]++; 108110206Sandreas.hansson@arm.com 108210206Sandreas.hansson@arm.com // Update latency stats 108310206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 108410206Sandreas.hansson@arm.com totBusLat += tBURST; 108510211Sandreas.hansson@arm.com totQLat += cmd_at - dram_pkt->entryTime; 10869977SN/A } else { 108710147Sandreas.hansson@arm.com ++writesThisTime; 108810211Sandreas.hansson@arm.com if (row_hit) 10899977SN/A writeRowHits++; 10909977SN/A bytesWritten += burstSize; 10919977SN/A perBankWrBursts[dram_pkt->bankId]++; 10929243SN/A } 10939243SN/A} 10949243SN/A 10959243SN/Avoid 109610206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 10979243SN/A{ 109810206Sandreas.hansson@arm.com if (busState == READ_TO_WRITE) { 109910206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 110010206Sandreas.hansson@arm.com "waiting\n", readsThisTime, readQueue.size()); 11019243SN/A 110210206Sandreas.hansson@arm.com // sample and reset the read-related stats as we are now 110310206Sandreas.hansson@arm.com // transitioning to writes, and all reads are done 110410206Sandreas.hansson@arm.com rdPerTurnAround.sample(readsThisTime); 110510206Sandreas.hansson@arm.com readsThisTime = 0; 110610206Sandreas.hansson@arm.com 110710206Sandreas.hansson@arm.com // now proceed to do the actual writes 110810206Sandreas.hansson@arm.com busState = WRITE; 110910206Sandreas.hansson@arm.com } else if (busState == WRITE_TO_READ) { 111010206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 111110206Sandreas.hansson@arm.com "waiting\n", writesThisTime, writeQueue.size()); 111210206Sandreas.hansson@arm.com 111310206Sandreas.hansson@arm.com wrPerTurnAround.sample(writesThisTime); 111410206Sandreas.hansson@arm.com writesThisTime = 0; 111510206Sandreas.hansson@arm.com 111610206Sandreas.hansson@arm.com busState = READ; 111710206Sandreas.hansson@arm.com } 111810206Sandreas.hansson@arm.com 111910207Sandreas.hansson@arm.com if (refreshState != REF_IDLE) { 112010207Sandreas.hansson@arm.com // if a refresh waiting for this event loop to finish, then hand 112110207Sandreas.hansson@arm.com // over now, and do not schedule a new nextReqEvent 112210207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 112310207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 112410207Sandreas.hansson@arm.com 112510207Sandreas.hansson@arm.com refreshState = REF_PRE; 112610207Sandreas.hansson@arm.com 112710207Sandreas.hansson@arm.com // hand control back to the refresh event loop 112810207Sandreas.hansson@arm.com schedule(refreshEvent, curTick()); 112910207Sandreas.hansson@arm.com } 113010207Sandreas.hansson@arm.com 113110207Sandreas.hansson@arm.com // let the refresh finish before issuing any further requests 113210207Sandreas.hansson@arm.com return; 113310207Sandreas.hansson@arm.com } 113410207Sandreas.hansson@arm.com 113510206Sandreas.hansson@arm.com // when we get here it is either a read or a write 113610206Sandreas.hansson@arm.com if (busState == READ) { 113710206Sandreas.hansson@arm.com 113810206Sandreas.hansson@arm.com // track if we should switch or not 113910206Sandreas.hansson@arm.com bool switch_to_writes = false; 114010206Sandreas.hansson@arm.com 114110206Sandreas.hansson@arm.com if (readQueue.empty()) { 114210206Sandreas.hansson@arm.com // In the case there is no read request to go next, 114310206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 114410206Sandreas.hansson@arm.com // if we are draining) 114510206Sandreas.hansson@arm.com if (!writeQueue.empty() && 114610206Sandreas.hansson@arm.com (drainManager || writeQueue.size() > writeLowThreshold)) { 114710206Sandreas.hansson@arm.com 114810206Sandreas.hansson@arm.com switch_to_writes = true; 114910206Sandreas.hansson@arm.com } else { 115010206Sandreas.hansson@arm.com // check if we are drained 115110206Sandreas.hansson@arm.com if (respQueue.empty () && drainManager) { 115210206Sandreas.hansson@arm.com drainManager->signalDrainDone(); 115310206Sandreas.hansson@arm.com drainManager = NULL; 115410206Sandreas.hansson@arm.com } 115510206Sandreas.hansson@arm.com 115610206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 115710206Sandreas.hansson@arm.com // event for the next request 115810206Sandreas.hansson@arm.com return; 115910206Sandreas.hansson@arm.com } 116010206Sandreas.hansson@arm.com } else { 116110206Sandreas.hansson@arm.com // Figure out which read request goes next, and move it to the 116210206Sandreas.hansson@arm.com // front of the read queue 116310206Sandreas.hansson@arm.com chooseNext(readQueue); 116410206Sandreas.hansson@arm.com 116510215Sandreas.hansson@arm.com DRAMPacket* dram_pkt = readQueue.front(); 116610215Sandreas.hansson@arm.com 116710215Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 116810206Sandreas.hansson@arm.com 116910206Sandreas.hansson@arm.com // At this point we're done dealing with the request 117010215Sandreas.hansson@arm.com readQueue.pop_front(); 117110215Sandreas.hansson@arm.com 117210215Sandreas.hansson@arm.com // sanity check 117310215Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 117410215Sandreas.hansson@arm.com assert(dram_pkt->readyTime >= curTick()); 117510215Sandreas.hansson@arm.com 117610215Sandreas.hansson@arm.com // Insert into response queue. It will be sent back to the 117710215Sandreas.hansson@arm.com // requestor at its readyTime 117810215Sandreas.hansson@arm.com if (respQueue.empty()) { 117910215Sandreas.hansson@arm.com assert(!respondEvent.scheduled()); 118010215Sandreas.hansson@arm.com schedule(respondEvent, dram_pkt->readyTime); 118110215Sandreas.hansson@arm.com } else { 118210215Sandreas.hansson@arm.com assert(respQueue.back()->readyTime <= dram_pkt->readyTime); 118310215Sandreas.hansson@arm.com assert(respondEvent.scheduled()); 118410215Sandreas.hansson@arm.com } 118510215Sandreas.hansson@arm.com 118610215Sandreas.hansson@arm.com respQueue.push_back(dram_pkt); 118710206Sandreas.hansson@arm.com 118810206Sandreas.hansson@arm.com // we have so many writes that we have to transition 118910206Sandreas.hansson@arm.com if (writeQueue.size() > writeHighThreshold) { 119010206Sandreas.hansson@arm.com switch_to_writes = true; 119110206Sandreas.hansson@arm.com } 119210206Sandreas.hansson@arm.com } 119310206Sandreas.hansson@arm.com 119410206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 119510206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 119610206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 119710206Sandreas.hansson@arm.com if (switch_to_writes) { 119810206Sandreas.hansson@arm.com // transition to writing 119910206Sandreas.hansson@arm.com busState = READ_TO_WRITE; 120010206Sandreas.hansson@arm.com 120110206Sandreas.hansson@arm.com // add a bubble to the data bus, as defined by the 120210206Sandreas.hansson@arm.com // tRTW parameter 120310206Sandreas.hansson@arm.com busBusyUntil += tRTW; 120410206Sandreas.hansson@arm.com 120510206Sandreas.hansson@arm.com // update the minimum timing between the requests, 120610206Sandreas.hansson@arm.com // this shifts us back in time far enough to do any 120710206Sandreas.hansson@arm.com // bank preparation 120810206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 120910206Sandreas.hansson@arm.com } 12109352SN/A } else { 121110206Sandreas.hansson@arm.com chooseNext(writeQueue); 121210206Sandreas.hansson@arm.com DRAMPacket* dram_pkt = writeQueue.front(); 121310206Sandreas.hansson@arm.com // sanity check 121410206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 121510206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 121610206Sandreas.hansson@arm.com 121710206Sandreas.hansson@arm.com writeQueue.pop_front(); 121810206Sandreas.hansson@arm.com delete dram_pkt; 121910206Sandreas.hansson@arm.com 122010206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 122110206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 122210206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 122310206Sandreas.hansson@arm.com // writes, then switch to reads. 122410206Sandreas.hansson@arm.com if (writeQueue.empty() || 122510206Sandreas.hansson@arm.com (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 122610206Sandreas.hansson@arm.com !drainManager) || 122710206Sandreas.hansson@arm.com (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 122810206Sandreas.hansson@arm.com // turn the bus back around for reads again 122910206Sandreas.hansson@arm.com busState = WRITE_TO_READ; 123010206Sandreas.hansson@arm.com 123110206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 123210206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 123310206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 123410206Sandreas.hansson@arm.com // nothing to do 123510206Sandreas.hansson@arm.com 123610206Sandreas.hansson@arm.com // here we get a bit creative and shift the bus busy time not 123710206Sandreas.hansson@arm.com // just the tWTR, but also a CAS latency to capture the fact 123810206Sandreas.hansson@arm.com // that we are allowed to prepare a new bank, but not issue a 123910206Sandreas.hansson@arm.com // read command until after tWTR, in essence we capture a 124010206Sandreas.hansson@arm.com // bubble on the data bus that is tWTR + tCL 124110206Sandreas.hansson@arm.com busBusyUntil += tWTR + tCL; 124210206Sandreas.hansson@arm.com 124310206Sandreas.hansson@arm.com // update the minimum timing between the requests, this shifts 124410206Sandreas.hansson@arm.com // us back in time far enough to do any bank preparation 124510206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 124610206Sandreas.hansson@arm.com } 124710206Sandreas.hansson@arm.com } 124810206Sandreas.hansson@arm.com 124910206Sandreas.hansson@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 125010206Sandreas.hansson@arm.com 125110206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 125210206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 125310206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 125410206Sandreas.hansson@arm.com // the next request processing 125510206Sandreas.hansson@arm.com if (retryWrReq && writeQueue.size() < writeBufferSize) { 125610206Sandreas.hansson@arm.com retryWrReq = false; 125710206Sandreas.hansson@arm.com port.sendRetry(); 12589352SN/A } 12599243SN/A} 12609243SN/A 12619967SN/Auint64_t 126210211Sandreas.hansson@arm.comDRAMCtrl::minBankActAt(const deque<DRAMPacket*>& queue) const 12639967SN/A{ 12649967SN/A uint64_t bank_mask = 0; 126510211Sandreas.hansson@arm.com Tick min_act_at = MaxTick; 12669967SN/A 126710211Sandreas.hansson@arm.com // deterimne if we have queued transactions targetting a 12689967SN/A // bank in question 12699967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 12709967SN/A for (auto p = queue.begin(); p != queue.end(); ++p) { 12719967SN/A got_waiting[(*p)->bankId] = true; 12729967SN/A } 12739967SN/A 12749967SN/A for (int i = 0; i < ranksPerChannel; i++) { 12759967SN/A for (int j = 0; j < banksPerRank; j++) { 127610211Sandreas.hansson@arm.com uint8_t bank_id = i * banksPerRank + j; 127710211Sandreas.hansson@arm.com 12789967SN/A // if we have waiting requests for the bank, and it is 12799967SN/A // amongst the first available, update the mask 128010211Sandreas.hansson@arm.com if (got_waiting[bank_id]) { 128110211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue 128210211Sandreas.hansson@arm.com // an activate, ignoring any rank-to-rank switching 128310211Sandreas.hansson@arm.com // cost 128410211Sandreas.hansson@arm.com Tick act_at = banks[i][j].openRow == Bank::NO_ROW ? 128510211Sandreas.hansson@arm.com banks[i][j].actAllowedAt : 128610211Sandreas.hansson@arm.com std::max(banks[i][j].preAllowedAt, curTick()) + tRP; 128710211Sandreas.hansson@arm.com 128810211Sandreas.hansson@arm.com if (act_at <= min_act_at) { 128910211Sandreas.hansson@arm.com // reset bank mask if new minimum is found 129010211Sandreas.hansson@arm.com if (act_at < min_act_at) 129110211Sandreas.hansson@arm.com bank_mask = 0; 129210211Sandreas.hansson@arm.com // set the bit corresponding to the available bank 129310211Sandreas.hansson@arm.com replaceBits(bank_mask, bank_id, bank_id, 1); 129410211Sandreas.hansson@arm.com min_act_at = act_at; 129510211Sandreas.hansson@arm.com } 12969967SN/A } 12979967SN/A } 12989967SN/A } 129910211Sandreas.hansson@arm.com 13009967SN/A return bank_mask; 13019967SN/A} 13029967SN/A 13039243SN/Avoid 130410146Sandreas.hansson@arm.comDRAMCtrl::processRefreshEvent() 13059243SN/A{ 130610207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 130710207Sandreas.hansson@arm.com if (refreshState == REF_IDLE) { 130810207Sandreas.hansson@arm.com // remember when the refresh is due 130910207Sandreas.hansson@arm.com refreshDueAt = curTick(); 13109243SN/A 131110207Sandreas.hansson@arm.com // proceed to drain 131210207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 13139243SN/A 131410207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 131510207Sandreas.hansson@arm.com } 131610207Sandreas.hansson@arm.com 131710207Sandreas.hansson@arm.com // let any scheduled read or write go ahead, after which it will 131810207Sandreas.hansson@arm.com // hand control back to this event loop 131910207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 132010207Sandreas.hansson@arm.com if (nextReqEvent.scheduled()) { 132110207Sandreas.hansson@arm.com // hand control over to the request loop until it is 132210207Sandreas.hansson@arm.com // evaluated next 132310207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 132410207Sandreas.hansson@arm.com 132510207Sandreas.hansson@arm.com return; 132610207Sandreas.hansson@arm.com } else { 132710207Sandreas.hansson@arm.com refreshState = REF_PRE; 132810207Sandreas.hansson@arm.com } 132910207Sandreas.hansson@arm.com } 133010207Sandreas.hansson@arm.com 133110207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 133210207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 133310208Sandreas.hansson@arm.com // precharge any active bank if we are not already in the idle 133410208Sandreas.hansson@arm.com // state 133510208Sandreas.hansson@arm.com if (pwrState != PWR_IDLE) { 133610214Sandreas.hansson@arm.com // at the moment, we use a precharge all even if there is 133710214Sandreas.hansson@arm.com // only a single bank open 133810208Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 133910214Sandreas.hansson@arm.com 134010214Sandreas.hansson@arm.com // first determine when we can precharge 134110214Sandreas.hansson@arm.com Tick pre_at = curTick(); 134210214Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 134310214Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 134410214Sandreas.hansson@arm.com // respect both causality and any existing bank 134510214Sandreas.hansson@arm.com // constraints, some banks could already have a 134610214Sandreas.hansson@arm.com // (auto) precharge scheduled 134710214Sandreas.hansson@arm.com pre_at = std::max(banks[i][j].preAllowedAt, pre_at); 134810214Sandreas.hansson@arm.com } 134910214Sandreas.hansson@arm.com } 135010214Sandreas.hansson@arm.com 135110214Sandreas.hansson@arm.com // make sure all banks are precharged, and for those that 135210214Sandreas.hansson@arm.com // already are, update their availability 135310214Sandreas.hansson@arm.com Tick act_allowed_at = pre_at + tRP; 135410214Sandreas.hansson@arm.com 135510208Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 135610208Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 135710208Sandreas.hansson@arm.com if (banks[i][j].openRow != Bank::NO_ROW) { 135810247Sandreas.hansson@arm.com prechargeBank(banks[i][j], pre_at, false); 135910214Sandreas.hansson@arm.com } else { 136010214Sandreas.hansson@arm.com banks[i][j].actAllowedAt = 136110214Sandreas.hansson@arm.com std::max(banks[i][j].actAllowedAt, act_allowed_at); 136210214Sandreas.hansson@arm.com banks[i][j].preAllowedAt = 136310214Sandreas.hansson@arm.com std::max(banks[i][j].preAllowedAt, pre_at); 136410208Sandreas.hansson@arm.com } 136510207Sandreas.hansson@arm.com } 136610247Sandreas.hansson@arm.com 136710247Sandreas.hansson@arm.com // at the moment this affects all ranks 136810247Sandreas.hansson@arm.com DPRINTF(DRAMPower, "%llu,PREA,0,%d\n", divCeil(pre_at, tCK), 136910247Sandreas.hansson@arm.com i); 137010207Sandreas.hansson@arm.com } 137110208Sandreas.hansson@arm.com } else { 137210208Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 137310208Sandreas.hansson@arm.com 137410208Sandreas.hansson@arm.com // go ahead and kick the power state machine into gear if 137510208Sandreas.hansson@arm.com // we are already idle 137610208Sandreas.hansson@arm.com schedulePowerEvent(PWR_REF, curTick()); 13779975SN/A } 13789975SN/A 137910208Sandreas.hansson@arm.com refreshState = REF_RUN; 138010208Sandreas.hansson@arm.com assert(numBanksActive == 0); 13819243SN/A 138210208Sandreas.hansson@arm.com // wait for all banks to be precharged, at which point the 138310208Sandreas.hansson@arm.com // power state machine will transition to the idle state, and 138410208Sandreas.hansson@arm.com // automatically move to a refresh, at that point it will also 138510208Sandreas.hansson@arm.com // call this method to get the refresh event loop going again 138610207Sandreas.hansson@arm.com return; 138710207Sandreas.hansson@arm.com } 138810207Sandreas.hansson@arm.com 138910207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 139010207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 139110207Sandreas.hansson@arm.com // should never get here with any banks active 139210207Sandreas.hansson@arm.com assert(numBanksActive == 0); 139310208Sandreas.hansson@arm.com assert(pwrState == PWR_REF); 139410207Sandreas.hansson@arm.com 139510211Sandreas.hansson@arm.com Tick ref_done_at = curTick() + tRFC; 139610207Sandreas.hansson@arm.com 139710207Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 139810207Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 139910211Sandreas.hansson@arm.com banks[i][j].actAllowedAt = ref_done_at; 140010207Sandreas.hansson@arm.com } 140110247Sandreas.hansson@arm.com 140210247Sandreas.hansson@arm.com // at the moment this affects all ranks 140310247Sandreas.hansson@arm.com DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), tCK), i); 140410207Sandreas.hansson@arm.com } 140510207Sandreas.hansson@arm.com 140610207Sandreas.hansson@arm.com // make sure we did not wait so long that we cannot make up 140710207Sandreas.hansson@arm.com // for it 140810211Sandreas.hansson@arm.com if (refreshDueAt + tREFI < ref_done_at) { 140910207Sandreas.hansson@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 141010207Sandreas.hansson@arm.com } 141110207Sandreas.hansson@arm.com 141210207Sandreas.hansson@arm.com // compensate for the delay in actually performing the refresh 141310207Sandreas.hansson@arm.com // when scheduling the next one 141410207Sandreas.hansson@arm.com schedule(refreshEvent, refreshDueAt + tREFI - tRP); 141510207Sandreas.hansson@arm.com 141610208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 141710207Sandreas.hansson@arm.com 141810208Sandreas.hansson@arm.com // move to the idle power state once the refresh is done, this 141910208Sandreas.hansson@arm.com // will also move the refresh state machine to the refresh 142010208Sandreas.hansson@arm.com // idle state 142110211Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, ref_done_at); 142210207Sandreas.hansson@arm.com 142310208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n", 142410211Sandreas.hansson@arm.com ref_done_at, refreshDueAt + tREFI); 142510208Sandreas.hansson@arm.com } 142610208Sandreas.hansson@arm.com} 142710208Sandreas.hansson@arm.com 142810208Sandreas.hansson@arm.comvoid 142910208Sandreas.hansson@arm.comDRAMCtrl::schedulePowerEvent(PowerState pwr_state, Tick tick) 143010208Sandreas.hansson@arm.com{ 143110208Sandreas.hansson@arm.com // respect causality 143210208Sandreas.hansson@arm.com assert(tick >= curTick()); 143310208Sandreas.hansson@arm.com 143410208Sandreas.hansson@arm.com if (!powerEvent.scheduled()) { 143510208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 143610208Sandreas.hansson@arm.com tick, pwr_state); 143710208Sandreas.hansson@arm.com 143810208Sandreas.hansson@arm.com // insert the new transition 143910208Sandreas.hansson@arm.com pwrStateTrans = pwr_state; 144010208Sandreas.hansson@arm.com 144110208Sandreas.hansson@arm.com schedule(powerEvent, tick); 144210208Sandreas.hansson@arm.com } else { 144310208Sandreas.hansson@arm.com panic("Scheduled power event at %llu to state %d, " 144410208Sandreas.hansson@arm.com "with scheduled event at %llu to %d\n", tick, pwr_state, 144510208Sandreas.hansson@arm.com powerEvent.when(), pwrStateTrans); 144610208Sandreas.hansson@arm.com } 144710208Sandreas.hansson@arm.com} 144810208Sandreas.hansson@arm.com 144910208Sandreas.hansson@arm.comvoid 145010208Sandreas.hansson@arm.comDRAMCtrl::processPowerEvent() 145110208Sandreas.hansson@arm.com{ 145210208Sandreas.hansson@arm.com // remember where we were, and for how long 145310208Sandreas.hansson@arm.com Tick duration = curTick() - pwrStateTick; 145410208Sandreas.hansson@arm.com PowerState prev_state = pwrState; 145510208Sandreas.hansson@arm.com 145610208Sandreas.hansson@arm.com // update the accounting 145710208Sandreas.hansson@arm.com pwrStateTime[prev_state] += duration; 145810208Sandreas.hansson@arm.com 145910208Sandreas.hansson@arm.com pwrState = pwrStateTrans; 146010208Sandreas.hansson@arm.com pwrStateTick = curTick(); 146110208Sandreas.hansson@arm.com 146210208Sandreas.hansson@arm.com if (pwrState == PWR_IDLE) { 146310208Sandreas.hansson@arm.com DPRINTF(DRAMState, "All banks precharged\n"); 146410208Sandreas.hansson@arm.com 146510208Sandreas.hansson@arm.com // if we were refreshing, make sure we start scheduling requests again 146610208Sandreas.hansson@arm.com if (prev_state == PWR_REF) { 146710208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 146810208Sandreas.hansson@arm.com assert(pwrState == PWR_IDLE); 146910208Sandreas.hansson@arm.com 147010208Sandreas.hansson@arm.com // kick things into action again 147110208Sandreas.hansson@arm.com refreshState = REF_IDLE; 147210208Sandreas.hansson@arm.com assert(!nextReqEvent.scheduled()); 147310208Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 147410208Sandreas.hansson@arm.com } else { 147510208Sandreas.hansson@arm.com assert(prev_state == PWR_ACT); 147610208Sandreas.hansson@arm.com 147710208Sandreas.hansson@arm.com // if we have a pending refresh, and are now moving to 147810208Sandreas.hansson@arm.com // the idle state, direclty transition to a refresh 147910208Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 148010208Sandreas.hansson@arm.com // there should be nothing waiting at this point 148110208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 148210208Sandreas.hansson@arm.com 148310208Sandreas.hansson@arm.com // update the state in zero time and proceed below 148410208Sandreas.hansson@arm.com pwrState = PWR_REF; 148510208Sandreas.hansson@arm.com } 148610208Sandreas.hansson@arm.com } 148710208Sandreas.hansson@arm.com } 148810208Sandreas.hansson@arm.com 148910208Sandreas.hansson@arm.com // we transition to the refresh state, let the refresh state 149010208Sandreas.hansson@arm.com // machine know of this state update and let it deal with the 149110208Sandreas.hansson@arm.com // scheduling of the next power state transition as well as the 149210208Sandreas.hansson@arm.com // following refresh 149310208Sandreas.hansson@arm.com if (pwrState == PWR_REF) { 149410208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refreshing\n"); 149510208Sandreas.hansson@arm.com // kick the refresh event loop into action again, and that 149610208Sandreas.hansson@arm.com // in turn will schedule a transition to the idle power 149710208Sandreas.hansson@arm.com // state once the refresh is done 149810208Sandreas.hansson@arm.com assert(refreshState == REF_RUN); 149910208Sandreas.hansson@arm.com processRefreshEvent(); 150010207Sandreas.hansson@arm.com } 15019243SN/A} 15029243SN/A 15039243SN/Avoid 150410146Sandreas.hansson@arm.comDRAMCtrl::regStats() 15059243SN/A{ 15069243SN/A using namespace Stats; 15079243SN/A 15089243SN/A AbstractMemory::regStats(); 15099243SN/A 15109243SN/A readReqs 15119243SN/A .name(name() + ".readReqs") 15129977SN/A .desc("Number of read requests accepted"); 15139243SN/A 15149243SN/A writeReqs 15159243SN/A .name(name() + ".writeReqs") 15169977SN/A .desc("Number of write requests accepted"); 15179831SN/A 15189831SN/A readBursts 15199831SN/A .name(name() + ".readBursts") 15209977SN/A .desc("Number of DRAM read bursts, " 15219977SN/A "including those serviced by the write queue"); 15229831SN/A 15239831SN/A writeBursts 15249831SN/A .name(name() + ".writeBursts") 15259977SN/A .desc("Number of DRAM write bursts, " 15269977SN/A "including those merged in the write queue"); 15279243SN/A 15289243SN/A servicedByWrQ 15299243SN/A .name(name() + ".servicedByWrQ") 15309977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 15319977SN/A 15329977SN/A mergedWrBursts 15339977SN/A .name(name() + ".mergedWrBursts") 15349977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 15359243SN/A 15369243SN/A neitherReadNorWrite 15379977SN/A .name(name() + ".neitherReadNorWriteReqs") 15389977SN/A .desc("Number of requests that are neither read nor write"); 15399243SN/A 15409977SN/A perBankRdBursts 15419243SN/A .init(banksPerRank * ranksPerChannel) 15429977SN/A .name(name() + ".perBankRdBursts") 15439977SN/A .desc("Per bank write bursts"); 15449243SN/A 15459977SN/A perBankWrBursts 15469243SN/A .init(banksPerRank * ranksPerChannel) 15479977SN/A .name(name() + ".perBankWrBursts") 15489977SN/A .desc("Per bank write bursts"); 15499243SN/A 15509243SN/A avgRdQLen 15519243SN/A .name(name() + ".avgRdQLen") 15529977SN/A .desc("Average read queue length when enqueuing") 15539243SN/A .precision(2); 15549243SN/A 15559243SN/A avgWrQLen 15569243SN/A .name(name() + ".avgWrQLen") 15579977SN/A .desc("Average write queue length when enqueuing") 15589243SN/A .precision(2); 15599243SN/A 15609243SN/A totQLat 15619243SN/A .name(name() + ".totQLat") 15629977SN/A .desc("Total ticks spent queuing"); 15639243SN/A 15649243SN/A totBusLat 15659243SN/A .name(name() + ".totBusLat") 15669977SN/A .desc("Total ticks spent in databus transfers"); 15679243SN/A 15689243SN/A totMemAccLat 15699243SN/A .name(name() + ".totMemAccLat") 15709977SN/A .desc("Total ticks spent from burst creation until serviced " 15719977SN/A "by the DRAM"); 15729243SN/A 15739243SN/A avgQLat 15749243SN/A .name(name() + ".avgQLat") 15759977SN/A .desc("Average queueing delay per DRAM burst") 15769243SN/A .precision(2); 15779243SN/A 15789831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 15799243SN/A 15809243SN/A avgBusLat 15819243SN/A .name(name() + ".avgBusLat") 15829977SN/A .desc("Average bus latency per DRAM burst") 15839243SN/A .precision(2); 15849243SN/A 15859831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 15869243SN/A 15879243SN/A avgMemAccLat 15889243SN/A .name(name() + ".avgMemAccLat") 15899977SN/A .desc("Average memory access latency per DRAM burst") 15909243SN/A .precision(2); 15919243SN/A 15929831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 15939243SN/A 15949243SN/A numRdRetry 15959243SN/A .name(name() + ".numRdRetry") 15969977SN/A .desc("Number of times read queue was full causing retry"); 15979243SN/A 15989243SN/A numWrRetry 15999243SN/A .name(name() + ".numWrRetry") 16009977SN/A .desc("Number of times write queue was full causing retry"); 16019243SN/A 16029243SN/A readRowHits 16039243SN/A .name(name() + ".readRowHits") 16049243SN/A .desc("Number of row buffer hits during reads"); 16059243SN/A 16069243SN/A writeRowHits 16079243SN/A .name(name() + ".writeRowHits") 16089243SN/A .desc("Number of row buffer hits during writes"); 16099243SN/A 16109243SN/A readRowHitRate 16119243SN/A .name(name() + ".readRowHitRate") 16129243SN/A .desc("Row buffer hit rate for reads") 16139243SN/A .precision(2); 16149243SN/A 16159831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 16169243SN/A 16179243SN/A writeRowHitRate 16189243SN/A .name(name() + ".writeRowHitRate") 16199243SN/A .desc("Row buffer hit rate for writes") 16209243SN/A .precision(2); 16219243SN/A 16229977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 16239243SN/A 16249243SN/A readPktSize 16259831SN/A .init(ceilLog2(burstSize) + 1) 16269243SN/A .name(name() + ".readPktSize") 16279977SN/A .desc("Read request sizes (log2)"); 16289243SN/A 16299243SN/A writePktSize 16309831SN/A .init(ceilLog2(burstSize) + 1) 16319243SN/A .name(name() + ".writePktSize") 16329977SN/A .desc("Write request sizes (log2)"); 16339243SN/A 16349243SN/A rdQLenPdf 16359567SN/A .init(readBufferSize) 16369243SN/A .name(name() + ".rdQLenPdf") 16379243SN/A .desc("What read queue length does an incoming req see"); 16389243SN/A 16399243SN/A wrQLenPdf 16409567SN/A .init(writeBufferSize) 16419243SN/A .name(name() + ".wrQLenPdf") 16429243SN/A .desc("What write queue length does an incoming req see"); 16439243SN/A 16449727SN/A bytesPerActivate 164510141SN/A .init(maxAccessesPerRow) 16469727SN/A .name(name() + ".bytesPerActivate") 16479727SN/A .desc("Bytes accessed per row activation") 16489727SN/A .flags(nozero); 16499243SN/A 165010147Sandreas.hansson@arm.com rdPerTurnAround 165110147Sandreas.hansson@arm.com .init(readBufferSize) 165210147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 165310147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 165410147Sandreas.hansson@arm.com .flags(nozero); 165510147Sandreas.hansson@arm.com 165610147Sandreas.hansson@arm.com wrPerTurnAround 165710147Sandreas.hansson@arm.com .init(writeBufferSize) 165810147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 165910147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 166010147Sandreas.hansson@arm.com .flags(nozero); 166110147Sandreas.hansson@arm.com 16629975SN/A bytesReadDRAM 16639975SN/A .name(name() + ".bytesReadDRAM") 16649975SN/A .desc("Total number of bytes read from DRAM"); 16659975SN/A 16669975SN/A bytesReadWrQ 16679975SN/A .name(name() + ".bytesReadWrQ") 16689975SN/A .desc("Total number of bytes read from write queue"); 16699243SN/A 16709243SN/A bytesWritten 16719243SN/A .name(name() + ".bytesWritten") 16729977SN/A .desc("Total number of bytes written to DRAM"); 16739243SN/A 16749977SN/A bytesReadSys 16759977SN/A .name(name() + ".bytesReadSys") 16769977SN/A .desc("Total read bytes from the system interface side"); 16779243SN/A 16789977SN/A bytesWrittenSys 16799977SN/A .name(name() + ".bytesWrittenSys") 16809977SN/A .desc("Total written bytes from the system interface side"); 16819243SN/A 16829243SN/A avgRdBW 16839243SN/A .name(name() + ".avgRdBW") 16849977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 16859243SN/A .precision(2); 16869243SN/A 16879977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 16889243SN/A 16899243SN/A avgWrBW 16909243SN/A .name(name() + ".avgWrBW") 16919977SN/A .desc("Average achieved write bandwidth in MiByte/s") 16929243SN/A .precision(2); 16939243SN/A 16949243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 16959243SN/A 16969977SN/A avgRdBWSys 16979977SN/A .name(name() + ".avgRdBWSys") 16989977SN/A .desc("Average system read bandwidth in MiByte/s") 16999243SN/A .precision(2); 17009243SN/A 17019977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 17029243SN/A 17039977SN/A avgWrBWSys 17049977SN/A .name(name() + ".avgWrBWSys") 17059977SN/A .desc("Average system write bandwidth in MiByte/s") 17069243SN/A .precision(2); 17079243SN/A 17089977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 17099243SN/A 17109243SN/A peakBW 17119243SN/A .name(name() + ".peakBW") 17129977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 17139243SN/A .precision(2); 17149243SN/A 17159831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 17169243SN/A 17179243SN/A busUtil 17189243SN/A .name(name() + ".busUtil") 17199243SN/A .desc("Data bus utilization in percentage") 17209243SN/A .precision(2); 17219243SN/A 17229243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 17239243SN/A 17249243SN/A totGap 17259243SN/A .name(name() + ".totGap") 17269243SN/A .desc("Total gap between requests"); 17279243SN/A 17289243SN/A avgGap 17299243SN/A .name(name() + ".avgGap") 17309243SN/A .desc("Average gap between requests") 17319243SN/A .precision(2); 17329243SN/A 17339243SN/A avgGap = totGap / (readReqs + writeReqs); 17349975SN/A 17359975SN/A // Stats for DRAM Power calculation based on Micron datasheet 17369975SN/A busUtilRead 17379975SN/A .name(name() + ".busUtilRead") 17389975SN/A .desc("Data bus utilization in percentage for reads") 17399975SN/A .precision(2); 17409975SN/A 17419975SN/A busUtilRead = avgRdBW / peakBW * 100; 17429975SN/A 17439975SN/A busUtilWrite 17449975SN/A .name(name() + ".busUtilWrite") 17459975SN/A .desc("Data bus utilization in percentage for writes") 17469975SN/A .precision(2); 17479975SN/A 17489975SN/A busUtilWrite = avgWrBW / peakBW * 100; 17499975SN/A 17509975SN/A pageHitRate 17519975SN/A .name(name() + ".pageHitRate") 17529975SN/A .desc("Row buffer hit rate, read and write combined") 17539975SN/A .precision(2); 17549975SN/A 17559977SN/A pageHitRate = (writeRowHits + readRowHits) / 17569977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 17579975SN/A 175810208Sandreas.hansson@arm.com pwrStateTime 175910208Sandreas.hansson@arm.com .init(5) 176010208Sandreas.hansson@arm.com .name(name() + ".memoryStateTime") 176110208Sandreas.hansson@arm.com .desc("Time in different power states"); 176210208Sandreas.hansson@arm.com pwrStateTime.subname(0, "IDLE"); 176310208Sandreas.hansson@arm.com pwrStateTime.subname(1, "REF"); 176410208Sandreas.hansson@arm.com pwrStateTime.subname(2, "PRE_PDN"); 176510208Sandreas.hansson@arm.com pwrStateTime.subname(3, "ACT"); 176610208Sandreas.hansson@arm.com pwrStateTime.subname(4, "ACT_PDN"); 17679243SN/A} 17689243SN/A 17699243SN/Avoid 177010146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 17719243SN/A{ 17729243SN/A // rely on the abstract memory 17739243SN/A functionalAccess(pkt); 17749243SN/A} 17759243SN/A 17769294SN/ABaseSlavePort& 177710146Sandreas.hansson@arm.comDRAMCtrl::getSlavePort(const string &if_name, PortID idx) 17789243SN/A{ 17799243SN/A if (if_name != "port") { 17809243SN/A return MemObject::getSlavePort(if_name, idx); 17819243SN/A } else { 17829243SN/A return port; 17839243SN/A } 17849243SN/A} 17859243SN/A 17869243SN/Aunsigned int 178710146Sandreas.hansson@arm.comDRAMCtrl::drain(DrainManager *dm) 17889243SN/A{ 17899342SN/A unsigned int count = port.drain(dm); 17909243SN/A 17919243SN/A // if there is anything in any of our internal queues, keep track 17929243SN/A // of that as well 17939567SN/A if (!(writeQueue.empty() && readQueue.empty() && 17949567SN/A respQueue.empty())) { 17959352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 17969567SN/A " resp: %d\n", writeQueue.size(), readQueue.size(), 17979567SN/A respQueue.size()); 17989243SN/A ++count; 17999342SN/A drainManager = dm; 180010206Sandreas.hansson@arm.com 18019352SN/A // the only part that is not drained automatically over time 180210206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 180310206Sandreas.hansson@arm.com if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 180410206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 180510206Sandreas.hansson@arm.com } 18069243SN/A } 18079243SN/A 18089243SN/A if (count) 18099342SN/A setDrainState(Drainable::Draining); 18109243SN/A else 18119342SN/A setDrainState(Drainable::Drained); 18129243SN/A return count; 18139243SN/A} 18149243SN/A 181510146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 18169243SN/A : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 18179243SN/A memory(_memory) 18189243SN/A{ } 18199243SN/A 18209243SN/AAddrRangeList 182110146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 18229243SN/A{ 18239243SN/A AddrRangeList ranges; 18249243SN/A ranges.push_back(memory.getAddrRange()); 18259243SN/A return ranges; 18269243SN/A} 18279243SN/A 18289243SN/Avoid 182910146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 18309243SN/A{ 18319243SN/A pkt->pushLabel(memory.name()); 18329243SN/A 18339243SN/A if (!queue.checkFunctional(pkt)) { 18349243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 18359243SN/A // calls recvAtomic() and throws away the latency; we can save a 18369243SN/A // little here by just not calculating the latency. 18379243SN/A memory.recvFunctional(pkt); 18389243SN/A } 18399243SN/A 18409243SN/A pkt->popLabel(); 18419243SN/A} 18429243SN/A 18439243SN/ATick 184410146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 18459243SN/A{ 18469243SN/A return memory.recvAtomic(pkt); 18479243SN/A} 18489243SN/A 18499243SN/Abool 185010146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 18519243SN/A{ 18529243SN/A // pass it to the memory controller 18539243SN/A return memory.recvTimingReq(pkt); 18549243SN/A} 18559243SN/A 185610146Sandreas.hansson@arm.comDRAMCtrl* 185710146Sandreas.hansson@arm.comDRAMCtrlParams::create() 18589243SN/A{ 185910146Sandreas.hansson@arm.com return new DRAMCtrl(this); 18609243SN/A} 1861