dram_ctrl.cc revision 10246
19243SN/A/* 210206Sandreas.hansson@arm.com * Copyright (c) 2010-2014 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 439243SN/A */ 449243SN/A 4510146Sandreas.hansson@arm.com#include "base/bitfield.hh" 469356SN/A#include "base/trace.hh" 4710146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 4810208Sandreas.hansson@arm.com#include "debug/DRAMState.hh" 499352SN/A#include "debug/Drain.hh" 5010146Sandreas.hansson@arm.com#include "mem/dram_ctrl.hh" 519814SN/A#include "sim/system.hh" 529243SN/A 539243SN/Ausing namespace std; 549243SN/A 5510146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 569243SN/A AbstractMemory(p), 579243SN/A port(name() + ".port", *this), 589243SN/A retryRdReq(false), retryWrReq(false), 5910211Sandreas.hansson@arm.com busState(READ), 6010208Sandreas.hansson@arm.com nextReqEvent(this), respondEvent(this), activateEvent(this), 6110208Sandreas.hansson@arm.com prechargeEvent(this), refreshEvent(this), powerEvent(this), 6210208Sandreas.hansson@arm.com drainManager(NULL), 639831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 649831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 659831SN/A devicesPerRank(p->devices_per_rank), 669831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 679831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 6810140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 699243SN/A ranksPerChannel(p->ranks_per_channel), 709566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 719243SN/A readBufferSize(p->read_buffer_size), 729243SN/A writeBufferSize(p->write_buffer_size), 7310140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 7410140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 7510147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 7610147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 7710216Sandreas.hansson@arm.com tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tBURST(p->tBURST), 7810210Sandreas.hansson@arm.com tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), tWR(p->tWR), 7910212Sandreas.hansson@arm.com tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 809488SN/A tXAW(p->tXAW), activationLimit(p->activation_limit), 819243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 829243SN/A pageMgmt(p->page_policy), 8310141SN/A maxAccessesPerRow(p->max_accesses_per_row), 849726SN/A frontendLatency(p->static_frontend_latency), 859726SN/A backendLatency(p->static_backend_latency), 8610208Sandreas.hansson@arm.com busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE), 8710208Sandreas.hansson@arm.com pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), prevArrival(0), 8810208Sandreas.hansson@arm.com nextReqTime(0), pwrStateTick(0), numBanksActive(0) 899243SN/A{ 909243SN/A // create the bank states based on the dimensions of the ranks and 919243SN/A // banks 929243SN/A banks.resize(ranksPerChannel); 939969SN/A actTicks.resize(ranksPerChannel); 949243SN/A for (size_t c = 0; c < ranksPerChannel; ++c) { 959243SN/A banks[c].resize(banksPerRank); 969969SN/A actTicks[c].resize(activationLimit, 0); 979243SN/A } 989243SN/A 9910246Sandreas.hansson@arm.com // set the bank indices 10010246Sandreas.hansson@arm.com for (int r = 0; r < ranksPerChannel; r++) { 10110246Sandreas.hansson@arm.com for (int b = 0; b < banksPerRank; b++) { 10210246Sandreas.hansson@arm.com banks[r][b].rank = r; 10310246Sandreas.hansson@arm.com banks[r][b].bank = b; 10410246Sandreas.hansson@arm.com } 10510246Sandreas.hansson@arm.com } 10610246Sandreas.hansson@arm.com 10710140SN/A // perform a basic check of the write thresholds 10810140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 10910140SN/A fatal("Write buffer low threshold %d must be smaller than the " 11010140SN/A "high threshold %d\n", p->write_low_thresh_perc, 11110140SN/A p->write_high_thresh_perc); 1129243SN/A 1139243SN/A // determine the rows per bank by looking at the total capacity 1149567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1159243SN/A 1169243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1179243SN/A AbstractMemory::size()); 1189831SN/A 1199831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1209831SN/A rowBufferSize, columnsPerRowBuffer); 1219831SN/A 1229831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1239243SN/A 1249566SN/A if (range.interleaved()) { 1259566SN/A if (channels != range.stripes()) 12610143SN/A fatal("%s has %d interleaved address stripes but %d channel(s)\n", 1279566SN/A name(), range.stripes(), channels); 1289566SN/A 12910136SN/A if (addrMapping == Enums::RoRaBaChCo) { 1309831SN/A if (rowBufferSize != range.granularity()) { 13110143SN/A fatal("Interleaving of %s doesn't match RoRaBaChCo " 13210136SN/A "address map\n", name()); 1339566SN/A } 13410136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 13510136SN/A if (system()->cacheLineSize() != range.granularity()) { 13610143SN/A fatal("Interleaving of %s doesn't match RoRaBaCoCh " 13710136SN/A "address map\n", name()); 1389669SN/A } 13910136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 14010136SN/A if (system()->cacheLineSize() != range.granularity()) 14110143SN/A fatal("Interleaving of %s doesn't match RoCoRaBaCh " 14210136SN/A "address map\n", name()); 1439566SN/A } 1449566SN/A } 14510207Sandreas.hansson@arm.com 14610207Sandreas.hansson@arm.com // some basic sanity checks 14710207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 14810207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 14910207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 15010207Sandreas.hansson@arm.com } 1519243SN/A} 1529243SN/A 1539243SN/Avoid 15410146Sandreas.hansson@arm.comDRAMCtrl::init() 15510140SN/A{ 15610140SN/A if (!port.isConnected()) { 15710146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 15810140SN/A } else { 15910140SN/A port.sendRangeChange(); 16010140SN/A } 16110140SN/A} 16210140SN/A 16310140SN/Avoid 16410146Sandreas.hansson@arm.comDRAMCtrl::startup() 1659243SN/A{ 16610143SN/A // update the start tick for the precharge accounting to the 16710143SN/A // current tick 16810208Sandreas.hansson@arm.com pwrStateTick = curTick(); 16910143SN/A 17010206Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 17110206Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 17210206Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 17310206Sandreas.hansson@arm.com // start of simulation 17410206Sandreas.hansson@arm.com busBusyUntil = curTick() + tRP + tRCD + tCL; 17510206Sandreas.hansson@arm.com 17610207Sandreas.hansson@arm.com // kick off the refresh, and give ourselves enough time to 17710207Sandreas.hansson@arm.com // precharge 17810207Sandreas.hansson@arm.com schedule(refreshEvent, curTick() + tREFI - tRP); 1799243SN/A} 1809243SN/A 1819243SN/ATick 18210146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 1839243SN/A{ 1849243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 1859243SN/A 1869243SN/A // do the actual memory access and turn the packet into a response 1879243SN/A access(pkt); 1889243SN/A 1899243SN/A Tick latency = 0; 1909243SN/A if (!pkt->memInhibitAsserted() && pkt->hasData()) { 1919243SN/A // this value is not supposed to be accurate, just enough to 1929243SN/A // keep things going, mimic a closed page 1939243SN/A latency = tRP + tRCD + tCL; 1949243SN/A } 1959243SN/A return latency; 1969243SN/A} 1979243SN/A 1989243SN/Abool 19910146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 2009243SN/A{ 2019831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 2029831SN/A readBufferSize, readQueue.size() + respQueue.size(), 2039831SN/A neededEntries); 2049243SN/A 2059831SN/A return 2069831SN/A (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 2079243SN/A} 2089243SN/A 2099243SN/Abool 21010146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 2119243SN/A{ 2129831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 2139831SN/A writeBufferSize, writeQueue.size(), neededEntries); 2149831SN/A return (writeQueue.size() + neededEntries) > writeBufferSize; 2159243SN/A} 2169243SN/A 21710146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 21810146Sandreas.hansson@arm.comDRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 21910143SN/A bool isRead) 2209243SN/A{ 2219669SN/A // decode the address based on the address mapping scheme, with 22210136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 22310136SN/A // channel, respectively 2249243SN/A uint8_t rank; 2259967SN/A uint8_t bank; 22610245Sandreas.hansson@arm.com // use a 64-bit unsigned during the computations as the row is 22710245Sandreas.hansson@arm.com // always the top bits, and check before creating the DRAMPacket 22810245Sandreas.hansson@arm.com uint64_t row; 2299243SN/A 2309243SN/A // truncate the address to the access granularity 2319831SN/A Addr addr = dramPktAddr / burstSize; 2329243SN/A 2339491SN/A // we have removed the lowest order address bits that denote the 2349831SN/A // position within the column 23510136SN/A if (addrMapping == Enums::RoRaBaChCo) { 2369491SN/A // the lowest order bits denote the column to ensure that 2379491SN/A // sequential cache lines occupy the same row 2389831SN/A addr = addr / columnsPerRowBuffer; 2399243SN/A 2409669SN/A // take out the channel part of the address 2419566SN/A addr = addr / channels; 2429566SN/A 2439669SN/A // after the channel bits, get the bank bits to interleave 2449669SN/A // over the banks 2459669SN/A bank = addr % banksPerRank; 2469669SN/A addr = addr / banksPerRank; 2479669SN/A 2489669SN/A // after the bank, we get the rank bits which thus interleaves 2499669SN/A // over the ranks 2509669SN/A rank = addr % ranksPerChannel; 2519669SN/A addr = addr / ranksPerChannel; 2529669SN/A 2539669SN/A // lastly, get the row bits 2549669SN/A row = addr % rowsPerBank; 2559669SN/A addr = addr / rowsPerBank; 25610136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 2579669SN/A // take out the channel part of the address 2589669SN/A addr = addr / channels; 2599669SN/A 2609669SN/A // next, the column 2619831SN/A addr = addr / columnsPerRowBuffer; 2629669SN/A 2639669SN/A // after the column bits, we get the bank bits to interleave 2649491SN/A // over the banks 2659243SN/A bank = addr % banksPerRank; 2669243SN/A addr = addr / banksPerRank; 2679243SN/A 2689491SN/A // after the bank, we get the rank bits which thus interleaves 2699491SN/A // over the ranks 2709243SN/A rank = addr % ranksPerChannel; 2719243SN/A addr = addr / ranksPerChannel; 2729243SN/A 2739491SN/A // lastly, get the row bits 2749243SN/A row = addr % rowsPerBank; 2759243SN/A addr = addr / rowsPerBank; 27610136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 2779491SN/A // optimise for closed page mode and utilise maximum 2789491SN/A // parallelism of the DRAM (at the cost of power) 2799491SN/A 2809566SN/A // take out the channel part of the address, not that this has 2819566SN/A // to match with how accesses are interleaved between the 2829566SN/A // controllers in the address mapping 2839566SN/A addr = addr / channels; 2849566SN/A 2859491SN/A // start with the bank bits, as this provides the maximum 2869491SN/A // opportunity for parallelism between requests 2879243SN/A bank = addr % banksPerRank; 2889243SN/A addr = addr / banksPerRank; 2899243SN/A 2909491SN/A // next get the rank bits 2919243SN/A rank = addr % ranksPerChannel; 2929243SN/A addr = addr / ranksPerChannel; 2939243SN/A 2949491SN/A // next the column bits which we do not need to keep track of 2959491SN/A // and simply skip past 2969831SN/A addr = addr / columnsPerRowBuffer; 2979243SN/A 2989491SN/A // lastly, get the row bits 2999243SN/A row = addr % rowsPerBank; 3009243SN/A addr = addr / rowsPerBank; 3019243SN/A } else 3029243SN/A panic("Unknown address mapping policy chosen!"); 3039243SN/A 3049243SN/A assert(rank < ranksPerChannel); 3059243SN/A assert(bank < banksPerRank); 3069243SN/A assert(row < rowsPerBank); 30710245Sandreas.hansson@arm.com assert(row < Bank::NO_ROW); 3089243SN/A 3099243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 3109831SN/A dramPktAddr, rank, bank, row); 3119243SN/A 3129243SN/A // create the corresponding DRAM packet with the entry time and 3139567SN/A // ready time set to the current tick, the latter will be updated 3149567SN/A // later 3159967SN/A uint16_t bank_id = banksPerRank * rank + bank; 3169967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 3179967SN/A size, banks[rank][bank]); 3189243SN/A} 3199243SN/A 3209243SN/Avoid 32110146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 3229243SN/A{ 3239243SN/A // only add to the read queue here. whenever the request is 3249243SN/A // eventually done, set the readyTime, and call schedule() 3259243SN/A assert(!pkt->isWrite()); 3269243SN/A 3279831SN/A assert(pktCount != 0); 3289831SN/A 3299831SN/A // if the request size is larger than burst size, the pkt is split into 3309831SN/A // multiple DRAM packets 3319831SN/A // Note if the pkt starting address is not aligened to burst size, the 3329831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 3339831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 3349831SN/A // check read packets against packets in write queue. 3359243SN/A Addr addr = pkt->getAddr(); 3369831SN/A unsigned pktsServicedByWrQ = 0; 3379831SN/A BurstHelper* burst_helper = NULL; 3389831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 3399831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 3409831SN/A pkt->getAddr() + pkt->getSize()) - addr; 3419831SN/A readPktSize[ceilLog2(size)]++; 3429831SN/A readBursts++; 3439243SN/A 3449831SN/A // First check write buffer to see if the data is already at 3459831SN/A // the controller 3469831SN/A bool foundInWrQ = false; 3479833SN/A for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) { 3489832SN/A // check if the read is subsumed in the write entry we are 3499832SN/A // looking at 3509832SN/A if ((*i)->addr <= addr && 3519832SN/A (addr + size) <= ((*i)->addr + (*i)->size)) { 3529831SN/A foundInWrQ = true; 3539831SN/A servicedByWrQ++; 3549831SN/A pktsServicedByWrQ++; 3559831SN/A DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 3569831SN/A "write queue\n", addr, size); 3579975SN/A bytesReadWrQ += burstSize; 3589831SN/A break; 3599831SN/A } 3609243SN/A } 3619831SN/A 3629831SN/A // If not found in the write q, make a DRAM packet and 3639831SN/A // push it onto the read queue 3649831SN/A if (!foundInWrQ) { 3659831SN/A 3669831SN/A // Make the burst helper for split packets 3679831SN/A if (pktCount > 1 && burst_helper == NULL) { 3689831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 3699831SN/A "dram requests\n", pkt->getAddr(), pktCount); 3709831SN/A burst_helper = new BurstHelper(pktCount); 3719831SN/A } 3729831SN/A 3739966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 3749831SN/A dram_pkt->burstHelper = burst_helper; 3759831SN/A 3769831SN/A assert(!readQueueFull(1)); 3779831SN/A rdQLenPdf[readQueue.size() + respQueue.size()]++; 3789831SN/A 3799831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 3809831SN/A 3819831SN/A readQueue.push_back(dram_pkt); 3829831SN/A 3839831SN/A // Update stats 3849831SN/A avgRdQLen = readQueue.size() + respQueue.size(); 3859831SN/A } 3869831SN/A 3879831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 3889831SN/A addr = (addr | (burstSize - 1)) + 1; 3899243SN/A } 3909243SN/A 3919831SN/A // If all packets are serviced by write queue, we send the repsonse back 3929831SN/A if (pktsServicedByWrQ == pktCount) { 3939831SN/A accessAndRespond(pkt, frontendLatency); 3949831SN/A return; 3959831SN/A } 3969243SN/A 3979831SN/A // Update how many split packets are serviced by write queue 3989831SN/A if (burst_helper != NULL) 3999831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 4009243SN/A 40110206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 40210206Sandreas.hansson@arm.com // queue, do so now 40310206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 4049567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 4059567SN/A schedule(nextReqEvent, curTick()); 4069243SN/A } 4079243SN/A} 4089243SN/A 4099243SN/Avoid 41010146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 4119243SN/A{ 4129243SN/A // only add to the write queue here. whenever the request is 4139243SN/A // eventually done, set the readyTime, and call schedule() 4149243SN/A assert(pkt->isWrite()); 4159243SN/A 4169831SN/A // if the request size is larger than burst size, the pkt is split into 4179831SN/A // multiple DRAM packets 4189831SN/A Addr addr = pkt->getAddr(); 4199831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4209831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4219831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4229831SN/A writePktSize[ceilLog2(size)]++; 4239831SN/A writeBursts++; 4249243SN/A 4259832SN/A // see if we can merge with an existing item in the write 4269838SN/A // queue and keep track of whether we have merged or not so we 4279838SN/A // can stop at that point and also avoid enqueueing a new 4289838SN/A // request 4299832SN/A bool merged = false; 4309832SN/A auto w = writeQueue.begin(); 4319243SN/A 4329832SN/A while(!merged && w != writeQueue.end()) { 4339832SN/A // either of the two could be first, if they are the same 4349832SN/A // it does not matter which way we go 4359832SN/A if ((*w)->addr >= addr) { 4369838SN/A // the existing one starts after the new one, figure 4379838SN/A // out where the new one ends with respect to the 4389838SN/A // existing one 4399832SN/A if ((addr + size) >= ((*w)->addr + (*w)->size)) { 4409832SN/A // check if the existing one is completely 4419832SN/A // subsumed in the new one 4429832SN/A DPRINTF(DRAM, "Merging write covering existing burst\n"); 4439832SN/A merged = true; 4449832SN/A // update both the address and the size 4459832SN/A (*w)->addr = addr; 4469832SN/A (*w)->size = size; 4479832SN/A } else if ((addr + size) >= (*w)->addr && 4489832SN/A ((*w)->addr + (*w)->size - addr) <= burstSize) { 4499832SN/A // the new one is just before or partially 4509832SN/A // overlapping with the existing one, and together 4519832SN/A // they fit within a burst 4529832SN/A DPRINTF(DRAM, "Merging write before existing burst\n"); 4539832SN/A merged = true; 4549832SN/A // the existing queue item needs to be adjusted with 4559832SN/A // respect to both address and size 45610047SN/A (*w)->size = (*w)->addr + (*w)->size - addr; 4579832SN/A (*w)->addr = addr; 4589832SN/A } 4599832SN/A } else { 4609838SN/A // the new one starts after the current one, figure 4619838SN/A // out where the existing one ends with respect to the 4629838SN/A // new one 4639832SN/A if (((*w)->addr + (*w)->size) >= (addr + size)) { 4649832SN/A // check if the new one is completely subsumed in the 4659832SN/A // existing one 4669832SN/A DPRINTF(DRAM, "Merging write into existing burst\n"); 4679832SN/A merged = true; 4689832SN/A // no adjustments necessary 4699832SN/A } else if (((*w)->addr + (*w)->size) >= addr && 4709832SN/A (addr + size - (*w)->addr) <= burstSize) { 4719832SN/A // the existing one is just before or partially 4729832SN/A // overlapping with the new one, and together 4739832SN/A // they fit within a burst 4749832SN/A DPRINTF(DRAM, "Merging write after existing burst\n"); 4759832SN/A merged = true; 4769832SN/A // the address is right, and only the size has 4779832SN/A // to be adjusted 4789832SN/A (*w)->size = addr + size - (*w)->addr; 4799832SN/A } 4809832SN/A } 4819832SN/A ++w; 4829832SN/A } 4839243SN/A 4849832SN/A // if the item was not merged we need to create a new write 4859832SN/A // and enqueue it 4869832SN/A if (!merged) { 4879966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 4889243SN/A 4899832SN/A assert(writeQueue.size() < writeBufferSize); 4909832SN/A wrQLenPdf[writeQueue.size()]++; 4919243SN/A 4929832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 4939831SN/A 4949832SN/A writeQueue.push_back(dram_pkt); 4959831SN/A 4969832SN/A // Update stats 4979832SN/A avgWrQLen = writeQueue.size(); 4989977SN/A } else { 4999977SN/A // keep track of the fact that this burst effectively 5009977SN/A // disappeared as it was merged with an existing one 5019977SN/A mergedWrBursts++; 5029832SN/A } 5039832SN/A 5049831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 5059831SN/A addr = (addr | (burstSize - 1)) + 1; 5069831SN/A } 5079243SN/A 5089243SN/A // we do not wait for the writes to be send to the actual memory, 5099243SN/A // but instead take responsibility for the consistency here and 5109243SN/A // snoop the write queue for any upcoming reads 5119831SN/A // @todo, if a pkt size is larger than burst size, we might need a 5129831SN/A // different front end latency 5139726SN/A accessAndRespond(pkt, frontendLatency); 5149243SN/A 51510206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 51610206Sandreas.hansson@arm.com // queue, do so now 51710206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 51810206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 51910206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 5209243SN/A } 5219243SN/A} 5229243SN/A 5239243SN/Avoid 52410146Sandreas.hansson@arm.comDRAMCtrl::printQs() const { 5259243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 5269833SN/A for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 5279243SN/A DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 5289243SN/A } 5299243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 5309833SN/A for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 5319243SN/A DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 5329243SN/A } 5339243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 5349833SN/A for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 5359243SN/A DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 5369243SN/A } 5379243SN/A} 5389243SN/A 5399243SN/Abool 54010146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 5419243SN/A{ 5429349SN/A /// @todo temporary hack to deal with memory corruption issues until 5439349SN/A /// 4-phase transactions are complete 5449349SN/A for (int x = 0; x < pendingDelete.size(); x++) 5459349SN/A delete pendingDelete[x]; 5469349SN/A pendingDelete.clear(); 5479349SN/A 5489243SN/A // This is where we enter from the outside world 5499567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 5509831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 5519243SN/A 5529567SN/A // simply drop inhibited packets for now 5539567SN/A if (pkt->memInhibitAsserted()) { 55410143SN/A DPRINTF(DRAM, "Inhibited packet -- Dropping it now\n"); 5559567SN/A pendingDelete.push_back(pkt); 5569567SN/A return true; 5579567SN/A } 5589243SN/A 5599243SN/A // Calc avg gap between requests 5609243SN/A if (prevArrival != 0) { 5619243SN/A totGap += curTick() - prevArrival; 5629243SN/A } 5639243SN/A prevArrival = curTick(); 5649243SN/A 5659831SN/A 5669831SN/A // Find out how many dram packets a pkt translates to 5679831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 5689831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 5699831SN/A // multiple dram packets 5709243SN/A unsigned size = pkt->getSize(); 5719831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 5729831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 5739243SN/A 5749243SN/A // check local buffers and do not accept if full 5759243SN/A if (pkt->isRead()) { 5769567SN/A assert(size != 0); 5779831SN/A if (readQueueFull(dram_pkt_count)) { 5789567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 5799243SN/A // remember that we have to retry this port 5809243SN/A retryRdReq = true; 5819243SN/A numRdRetry++; 5829243SN/A return false; 5839243SN/A } else { 5849831SN/A addToReadQueue(pkt, dram_pkt_count); 5859243SN/A readReqs++; 5869977SN/A bytesReadSys += size; 5879243SN/A } 5889243SN/A } else if (pkt->isWrite()) { 5899567SN/A assert(size != 0); 5909831SN/A if (writeQueueFull(dram_pkt_count)) { 5919567SN/A DPRINTF(DRAM, "Write queue full, not accepting\n"); 5929243SN/A // remember that we have to retry this port 5939243SN/A retryWrReq = true; 5949243SN/A numWrRetry++; 5959243SN/A return false; 5969243SN/A } else { 5979831SN/A addToWriteQueue(pkt, dram_pkt_count); 5989243SN/A writeReqs++; 5999977SN/A bytesWrittenSys += size; 6009243SN/A } 6019243SN/A } else { 6029243SN/A DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 6039243SN/A neitherReadNorWrite++; 6049726SN/A accessAndRespond(pkt, 1); 6059243SN/A } 6069243SN/A 6079243SN/A return true; 6089243SN/A} 6099243SN/A 6109243SN/Avoid 61110146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 6129243SN/A{ 6139243SN/A DPRINTF(DRAM, 6149243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 6159243SN/A 6169831SN/A DRAMPacket* dram_pkt = respQueue.front(); 6179243SN/A 6189831SN/A if (dram_pkt->burstHelper) { 6199831SN/A // it is a split packet 6209831SN/A dram_pkt->burstHelper->burstsServiced++; 6219831SN/A if (dram_pkt->burstHelper->burstsServiced == 62210143SN/A dram_pkt->burstHelper->burstCount) { 6239831SN/A // we have now serviced all children packets of a system packet 6249831SN/A // so we can now respond to the requester 6259831SN/A // @todo we probably want to have a different front end and back 6269831SN/A // end latency for split packets 6279831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6289831SN/A delete dram_pkt->burstHelper; 6299831SN/A dram_pkt->burstHelper = NULL; 6309831SN/A } 6319831SN/A } else { 6329831SN/A // it is not a split packet 6339831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6349831SN/A } 6359243SN/A 6369831SN/A delete respQueue.front(); 6379831SN/A respQueue.pop_front(); 6389243SN/A 6399831SN/A if (!respQueue.empty()) { 6409831SN/A assert(respQueue.front()->readyTime >= curTick()); 6419831SN/A assert(!respondEvent.scheduled()); 6429831SN/A schedule(respondEvent, respQueue.front()->readyTime); 6439831SN/A } else { 6449831SN/A // if there is nothing left in any queue, signal a drain 6459831SN/A if (writeQueue.empty() && readQueue.empty() && 6469831SN/A drainManager) { 6479831SN/A drainManager->signalDrainDone(); 6489831SN/A drainManager = NULL; 6499831SN/A } 6509831SN/A } 6519567SN/A 6529831SN/A // We have made a location in the queue available at this point, 6539831SN/A // so if there is a read that was forced to wait, retry now 6549831SN/A if (retryRdReq) { 6559831SN/A retryRdReq = false; 6569831SN/A port.sendRetry(); 6579831SN/A } 6589243SN/A} 6599243SN/A 6609243SN/Avoid 66110206Sandreas.hansson@arm.comDRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue) 6629243SN/A{ 66310206Sandreas.hansson@arm.com // This method does the arbitration between requests. The chosen 66410206Sandreas.hansson@arm.com // packet is simply moved to the head of the queue. The other 66510206Sandreas.hansson@arm.com // methods know that this is the place to look. For example, with 66610206Sandreas.hansson@arm.com // FCFS, this method does nothing 66710206Sandreas.hansson@arm.com assert(!queue.empty()); 6689243SN/A 66910206Sandreas.hansson@arm.com if (queue.size() == 1) { 67010206Sandreas.hansson@arm.com DPRINTF(DRAM, "Single request, nothing to do\n"); 6719243SN/A return; 6729243SN/A } 6739243SN/A 6749243SN/A if (memSchedPolicy == Enums::fcfs) { 6759243SN/A // Do nothing, since the correct request is already head 6769243SN/A } else if (memSchedPolicy == Enums::frfcfs) { 67710206Sandreas.hansson@arm.com reorderQueue(queue); 6789243SN/A } else 6799243SN/A panic("No scheduling policy chosen\n"); 6809243SN/A} 6819243SN/A 6829243SN/Avoid 68310146Sandreas.hansson@arm.comDRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue) 6849974SN/A{ 6859974SN/A // Only determine this when needed 6869974SN/A uint64_t earliest_banks = 0; 6879974SN/A 6889974SN/A // Search for row hits first, if no row hit is found then schedule the 6899974SN/A // packet to one of the earliest banks available 6909974SN/A bool found_earliest_pkt = false; 6919974SN/A auto selected_pkt_it = queue.begin(); 6929974SN/A 6939974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 6949974SN/A DRAMPacket* dram_pkt = *i; 6959974SN/A const Bank& bank = dram_pkt->bankRef; 6969974SN/A // Check if it is a row hit 6979974SN/A if (bank.openRow == dram_pkt->row) { 69810211Sandreas.hansson@arm.com // FCFS within the hits 6999974SN/A DPRINTF(DRAM, "Row buffer hit\n"); 7009974SN/A selected_pkt_it = i; 7019974SN/A break; 7029974SN/A } else if (!found_earliest_pkt) { 7039974SN/A // No row hit, go for first ready 7049974SN/A if (earliest_banks == 0) 70510211Sandreas.hansson@arm.com earliest_banks = minBankActAt(queue); 70610211Sandreas.hansson@arm.com 70710211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue an 70810211Sandreas.hansson@arm.com // activate, this is calculated in minBankActAt and could 70910211Sandreas.hansson@arm.com // be cached 71010211Sandreas.hansson@arm.com Tick act_at = bank.openRow == Bank::NO_ROW ? 71110211Sandreas.hansson@arm.com bank.actAllowedAt : 71210211Sandreas.hansson@arm.com std::max(bank.preAllowedAt, curTick()) + tRP; 7139974SN/A 7149974SN/A // Bank is ready or is the first available bank 71510211Sandreas.hansson@arm.com if (act_at <= curTick() || 7169974SN/A bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) { 7179974SN/A // Remember the packet to be scheduled to one of the earliest 71810211Sandreas.hansson@arm.com // banks available, FCFS amongst the earliest banks 7199974SN/A selected_pkt_it = i; 7209974SN/A found_earliest_pkt = true; 7219974SN/A } 7229974SN/A } 7239974SN/A } 7249974SN/A 7259974SN/A DRAMPacket* selected_pkt = *selected_pkt_it; 7269974SN/A queue.erase(selected_pkt_it); 7279974SN/A queue.push_front(selected_pkt); 7289974SN/A} 7299974SN/A 7309974SN/Avoid 73110146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 7329243SN/A{ 7339243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 7349243SN/A 7359243SN/A bool needsResponse = pkt->needsResponse(); 7369243SN/A // do the actual memory access which also turns the packet into a 7379243SN/A // response 7389243SN/A access(pkt); 7399243SN/A 7409243SN/A // turn packet around to go back to requester if response expected 7419243SN/A if (needsResponse) { 7429243SN/A // access already turned the packet into a response 7439243SN/A assert(pkt->isResponse()); 7449243SN/A 7459549SN/A // @todo someone should pay for this 7469549SN/A pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; 7479549SN/A 7489726SN/A // queue the packet in the response queue to be sent out after 7499726SN/A // the static latency has passed 7509726SN/A port.schedTimingResp(pkt, curTick() + static_latency); 7519243SN/A } else { 7529587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 7539587SN/A // is still having a pointer to it 7549587SN/A pendingDelete.push_back(pkt); 7559243SN/A } 7569243SN/A 7579243SN/A DPRINTF(DRAM, "Done\n"); 7589243SN/A 7599243SN/A return; 7609243SN/A} 7619243SN/A 7629243SN/Avoid 76310246Sandreas.hansson@arm.comDRAMCtrl::activateBank(Bank& bank, Tick act_tick, uint32_t row) 7649488SN/A{ 76510246Sandreas.hansson@arm.com // get the rank index from the bank 76610246Sandreas.hansson@arm.com uint8_t rank = bank.rank; 76710246Sandreas.hansson@arm.com 7689969SN/A assert(actTicks[rank].size() == activationLimit); 7699488SN/A 7709488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 7719488SN/A 77210207Sandreas.hansson@arm.com // update the open row 77310246Sandreas.hansson@arm.com assert(bank.openRow == Bank::NO_ROW); 77410246Sandreas.hansson@arm.com bank.openRow = row; 77510207Sandreas.hansson@arm.com 77610207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 77710207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 77810207Sandreas.hansson@arm.com // precharge 77910246Sandreas.hansson@arm.com bank.bytesAccessed = 0; 78010246Sandreas.hansson@arm.com bank.rowAccesses = 0; 78110207Sandreas.hansson@arm.com 78210207Sandreas.hansson@arm.com ++numBanksActive; 78310207Sandreas.hansson@arm.com assert(numBanksActive <= banksPerRank * ranksPerChannel); 78410207Sandreas.hansson@arm.com 78510207Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank at tick %lld, now got %d active\n", 78610207Sandreas.hansson@arm.com act_tick, numBanksActive); 7879975SN/A 78810211Sandreas.hansson@arm.com // The next access has to respect tRAS for this bank 78910246Sandreas.hansson@arm.com bank.preAllowedAt = act_tick + tRAS; 79010211Sandreas.hansson@arm.com 79110211Sandreas.hansson@arm.com // Respect the row-to-column command delay 79210246Sandreas.hansson@arm.com bank.colAllowedAt = act_tick + tRCD; 79310211Sandreas.hansson@arm.com 7949971SN/A // start by enforcing tRRD 7959971SN/A for(int i = 0; i < banksPerRank; i++) { 79610210Sandreas.hansson@arm.com // next activate to any bank in this rank must not happen 79710210Sandreas.hansson@arm.com // before tRRD 79810210Sandreas.hansson@arm.com banks[rank][i].actAllowedAt = std::max(act_tick + tRRD, 79910210Sandreas.hansson@arm.com banks[rank][i].actAllowedAt); 8009971SN/A } 80110208Sandreas.hansson@arm.com 8029971SN/A // next, we deal with tXAW, if the activation limit is disabled 8039971SN/A // then we are done 8049969SN/A if (actTicks[rank].empty()) 8059824SN/A return; 8069824SN/A 8079488SN/A // sanity check 8089969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 80910210Sandreas.hansson@arm.com panic("Got %d activates in window %d (%llu - %llu) which is smaller " 81010210Sandreas.hansson@arm.com "than %llu\n", activationLimit, act_tick - actTicks[rank].back(), 81110210Sandreas.hansson@arm.com act_tick, actTicks[rank].back(), tXAW); 8129488SN/A } 8139488SN/A 8149488SN/A // shift the times used for the book keeping, the last element 8159488SN/A // (highest index) is the oldest one and hence the lowest value 8169969SN/A actTicks[rank].pop_back(); 8179488SN/A 8189488SN/A // record an new activation (in the future) 8199969SN/A actTicks[rank].push_front(act_tick); 8209488SN/A 8219488SN/A // cannot activate more than X times in time window tXAW, push the 8229488SN/A // next one (the X + 1'st activate) to be tXAW away from the 8239488SN/A // oldest in our window of X 8249969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 8259488SN/A DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate no earlier " 82610210Sandreas.hansson@arm.com "than %llu\n", activationLimit, actTicks[rank].back() + tXAW); 8279488SN/A for(int j = 0; j < banksPerRank; j++) 8289488SN/A // next activate must not happen before end of window 82910210Sandreas.hansson@arm.com banks[rank][j].actAllowedAt = 83010210Sandreas.hansson@arm.com std::max(actTicks[rank].back() + tXAW, 83110210Sandreas.hansson@arm.com banks[rank][j].actAllowedAt); 8329488SN/A } 83310208Sandreas.hansson@arm.com 83410208Sandreas.hansson@arm.com // at the point when this activate takes place, make sure we 83510208Sandreas.hansson@arm.com // transition to the active power state 83610208Sandreas.hansson@arm.com if (!activateEvent.scheduled()) 83710208Sandreas.hansson@arm.com schedule(activateEvent, act_tick); 83810208Sandreas.hansson@arm.com else if (activateEvent.when() > act_tick) 83910208Sandreas.hansson@arm.com // move it sooner in time 84010208Sandreas.hansson@arm.com reschedule(activateEvent, act_tick); 84110208Sandreas.hansson@arm.com} 84210208Sandreas.hansson@arm.com 84310208Sandreas.hansson@arm.comvoid 84410208Sandreas.hansson@arm.comDRAMCtrl::processActivateEvent() 84510208Sandreas.hansson@arm.com{ 84610208Sandreas.hansson@arm.com // we should transition to the active state as soon as any bank is active 84710208Sandreas.hansson@arm.com if (pwrState != PWR_ACT) 84810208Sandreas.hansson@arm.com // note that at this point numBanksActive could be back at 84910208Sandreas.hansson@arm.com // zero again due to a precharge scheduled in the future 85010208Sandreas.hansson@arm.com schedulePowerEvent(PWR_ACT, curTick()); 8519488SN/A} 8529488SN/A 8539488SN/Avoid 85410211Sandreas.hansson@arm.comDRAMCtrl::prechargeBank(Bank& bank, Tick pre_at) 85510207Sandreas.hansson@arm.com{ 85610207Sandreas.hansson@arm.com // make sure the bank has an open row 85710207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 85810207Sandreas.hansson@arm.com 85910207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 86010207Sandreas.hansson@arm.com // the page 86110207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 86210207Sandreas.hansson@arm.com 86310207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 86410207Sandreas.hansson@arm.com 86510214Sandreas.hansson@arm.com // no precharge allowed before this one 86610214Sandreas.hansson@arm.com bank.preAllowedAt = pre_at; 86710214Sandreas.hansson@arm.com 86810211Sandreas.hansson@arm.com Tick pre_done_at = pre_at + tRP; 86910211Sandreas.hansson@arm.com 87010211Sandreas.hansson@arm.com bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at); 87110207Sandreas.hansson@arm.com 87210207Sandreas.hansson@arm.com assert(numBanksActive != 0); 87310207Sandreas.hansson@arm.com --numBanksActive; 87410207Sandreas.hansson@arm.com 87510211Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging bank at tick %lld, now got %d active\n", 87610211Sandreas.hansson@arm.com pre_at, numBanksActive); 87710207Sandreas.hansson@arm.com 87810208Sandreas.hansson@arm.com // if we look at the current number of active banks we might be 87910208Sandreas.hansson@arm.com // tempted to think the DRAM is now idle, however this can be 88010208Sandreas.hansson@arm.com // undone by an activate that is scheduled to happen before we 88110208Sandreas.hansson@arm.com // would have reached the idle state, so schedule an event and 88210208Sandreas.hansson@arm.com // rather check once we actually make it to the point in time when 88310208Sandreas.hansson@arm.com // the (last) precharge takes place 88410208Sandreas.hansson@arm.com if (!prechargeEvent.scheduled()) 88510211Sandreas.hansson@arm.com schedule(prechargeEvent, pre_done_at); 88610211Sandreas.hansson@arm.com else if (prechargeEvent.when() < pre_done_at) 88710211Sandreas.hansson@arm.com reschedule(prechargeEvent, pre_done_at); 88810208Sandreas.hansson@arm.com} 88910208Sandreas.hansson@arm.com 89010208Sandreas.hansson@arm.comvoid 89110208Sandreas.hansson@arm.comDRAMCtrl::processPrechargeEvent() 89210208Sandreas.hansson@arm.com{ 89310207Sandreas.hansson@arm.com // if we reached zero, then special conditions apply as we track 89410207Sandreas.hansson@arm.com // if all banks are precharged for the power models 89510207Sandreas.hansson@arm.com if (numBanksActive == 0) { 89610208Sandreas.hansson@arm.com // we should transition to the idle state when the last bank 89710208Sandreas.hansson@arm.com // is precharged 89810208Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 89910207Sandreas.hansson@arm.com } 90010207Sandreas.hansson@arm.com} 90110207Sandreas.hansson@arm.com 90210207Sandreas.hansson@arm.comvoid 90310146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 9049243SN/A{ 9059243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 9069243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 9079243SN/A 90810211Sandreas.hansson@arm.com // get the bank 9099967SN/A Bank& bank = dram_pkt->bankRef; 9109243SN/A 91110211Sandreas.hansson@arm.com // for the state we need to track if it is a row hit or not 91210211Sandreas.hansson@arm.com bool row_hit = true; 91310211Sandreas.hansson@arm.com 91410211Sandreas.hansson@arm.com // respect any constraints on the command (e.g. tRCD or tCCD) 91510211Sandreas.hansson@arm.com Tick cmd_at = std::max(bank.colAllowedAt, curTick()); 91610211Sandreas.hansson@arm.com 91710211Sandreas.hansson@arm.com // Determine the access latency and update the bank state 91810211Sandreas.hansson@arm.com if (bank.openRow == dram_pkt->row) { 91910211Sandreas.hansson@arm.com // nothing to do 92010209Sandreas.hansson@arm.com } else { 92110211Sandreas.hansson@arm.com row_hit = false; 92210211Sandreas.hansson@arm.com 92310209Sandreas.hansson@arm.com // If there is a page open, precharge it. 92410209Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 92510211Sandreas.hansson@arm.com prechargeBank(bank, std::max(bank.preAllowedAt, curTick())); 9269488SN/A } 9279973SN/A 92810211Sandreas.hansson@arm.com // next we need to account for the delay in activating the 92910211Sandreas.hansson@arm.com // page 93010211Sandreas.hansson@arm.com Tick act_tick = std::max(bank.actAllowedAt, curTick()); 9319973SN/A 93210210Sandreas.hansson@arm.com // Record the activation and deal with all the global timing 93310210Sandreas.hansson@arm.com // constraints caused be a new activation (tRRD and tXAW) 93410246Sandreas.hansson@arm.com activateBank(bank, act_tick, dram_pkt->row); 93510210Sandreas.hansson@arm.com 93610211Sandreas.hansson@arm.com // issue the command as early as possible 93710211Sandreas.hansson@arm.com cmd_at = bank.colAllowedAt; 93810209Sandreas.hansson@arm.com } 93910209Sandreas.hansson@arm.com 94010211Sandreas.hansson@arm.com // we need to wait until the bus is available before we can issue 94110211Sandreas.hansson@arm.com // the command 94210211Sandreas.hansson@arm.com cmd_at = std::max(cmd_at, busBusyUntil - tCL); 94310211Sandreas.hansson@arm.com 94410211Sandreas.hansson@arm.com // update the packet ready time 94510211Sandreas.hansson@arm.com dram_pkt->readyTime = cmd_at + tCL + tBURST; 94610211Sandreas.hansson@arm.com 94710211Sandreas.hansson@arm.com // only one burst can use the bus at any one point in time 94810211Sandreas.hansson@arm.com assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 94910211Sandreas.hansson@arm.com 95010211Sandreas.hansson@arm.com // not strictly necessary, but update the time for the next 95110211Sandreas.hansson@arm.com // read/write (add a max with tCCD here) 95210211Sandreas.hansson@arm.com bank.colAllowedAt = cmd_at + tBURST; 95310211Sandreas.hansson@arm.com 95410212Sandreas.hansson@arm.com // If this is a write, we also need to respect the write recovery 95510212Sandreas.hansson@arm.com // time before a precharge, in the case of a read, respect the 95610212Sandreas.hansson@arm.com // read to precharge constraint 95710212Sandreas.hansson@arm.com bank.preAllowedAt = std::max(bank.preAllowedAt, 95810212Sandreas.hansson@arm.com dram_pkt->isRead ? cmd_at + tRTP : 95910212Sandreas.hansson@arm.com dram_pkt->readyTime + tWR); 96010210Sandreas.hansson@arm.com 96110209Sandreas.hansson@arm.com // increment the bytes accessed and the accesses per row 96210209Sandreas.hansson@arm.com bank.bytesAccessed += burstSize; 96310209Sandreas.hansson@arm.com ++bank.rowAccesses; 96410209Sandreas.hansson@arm.com 96510209Sandreas.hansson@arm.com // if we reached the max, then issue with an auto-precharge 96610209Sandreas.hansson@arm.com bool auto_precharge = pageMgmt == Enums::close || 96710209Sandreas.hansson@arm.com bank.rowAccesses == maxAccessesPerRow; 96810209Sandreas.hansson@arm.com 96910209Sandreas.hansson@arm.com // if we did not hit the limit, we might still want to 97010209Sandreas.hansson@arm.com // auto-precharge 97110209Sandreas.hansson@arm.com if (!auto_precharge && 97210209Sandreas.hansson@arm.com (pageMgmt == Enums::open_adaptive || 97310209Sandreas.hansson@arm.com pageMgmt == Enums::close_adaptive)) { 97410209Sandreas.hansson@arm.com // a twist on the open and close page policies: 97510209Sandreas.hansson@arm.com // 1) open_adaptive page policy does not blindly keep the 97610209Sandreas.hansson@arm.com // page open, but close it if there are no row hits, and there 97710209Sandreas.hansson@arm.com // are bank conflicts in the queue 97810209Sandreas.hansson@arm.com // 2) close_adaptive page policy does not blindly close the 97910209Sandreas.hansson@arm.com // page, but closes it only if there are no row hits in the queue. 98010209Sandreas.hansson@arm.com // In this case, only force an auto precharge when there 98110209Sandreas.hansson@arm.com // are no same page hits in the queue 98210209Sandreas.hansson@arm.com bool got_more_hits = false; 98310209Sandreas.hansson@arm.com bool got_bank_conflict = false; 98410209Sandreas.hansson@arm.com 98510209Sandreas.hansson@arm.com // either look at the read queue or write queue 98610209Sandreas.hansson@arm.com const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 98710209Sandreas.hansson@arm.com writeQueue; 98810209Sandreas.hansson@arm.com auto p = queue.begin(); 98910209Sandreas.hansson@arm.com // make sure we are not considering the packet that we are 99010209Sandreas.hansson@arm.com // currently dealing with (which is the head of the queue) 99110209Sandreas.hansson@arm.com ++p; 99210209Sandreas.hansson@arm.com 99310209Sandreas.hansson@arm.com // keep on looking until we have found required condition or 99410209Sandreas.hansson@arm.com // reached the end 99510209Sandreas.hansson@arm.com while (!(got_more_hits && 99610209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive)) && 99710209Sandreas.hansson@arm.com p != queue.end()) { 99810209Sandreas.hansson@arm.com bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 99910209Sandreas.hansson@arm.com (dram_pkt->bank == (*p)->bank); 100010209Sandreas.hansson@arm.com bool same_row = dram_pkt->row == (*p)->row; 100110209Sandreas.hansson@arm.com got_more_hits |= same_rank_bank && same_row; 100210209Sandreas.hansson@arm.com got_bank_conflict |= same_rank_bank && !same_row; 10039973SN/A ++p; 100410141SN/A } 100510141SN/A 100610209Sandreas.hansson@arm.com // auto pre-charge when either 100710209Sandreas.hansson@arm.com // 1) open_adaptive policy, we have not got any more hits, and 100810209Sandreas.hansson@arm.com // have a bank conflict 100910209Sandreas.hansson@arm.com // 2) close_adaptive policy and we have not got any more hits 101010209Sandreas.hansson@arm.com auto_precharge = !got_more_hits && 101110209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive); 101210209Sandreas.hansson@arm.com } 101310142SN/A 101410209Sandreas.hansson@arm.com // if this access should use auto-precharge, then we are 101510209Sandreas.hansson@arm.com // closing the row 101610209Sandreas.hansson@arm.com if (auto_precharge) { 101710211Sandreas.hansson@arm.com prechargeBank(bank, std::max(curTick(), bank.preAllowedAt)); 10189973SN/A 101910209Sandreas.hansson@arm.com DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 102010209Sandreas.hansson@arm.com } 10219963SN/A 10229243SN/A // Update bus state 10239243SN/A busBusyUntil = dram_pkt->readyTime; 10249243SN/A 102510211Sandreas.hansson@arm.com DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n", 102610211Sandreas.hansson@arm.com dram_pkt->addr, dram_pkt->readyTime, busBusyUntil); 10279243SN/A 102810206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 102910206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 103010206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 103110206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 103210206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 10339972SN/A 103410206Sandreas.hansson@arm.com // Update the stats and schedule the next request 10359977SN/A if (dram_pkt->isRead) { 103610147Sandreas.hansson@arm.com ++readsThisTime; 103710211Sandreas.hansson@arm.com if (row_hit) 10389977SN/A readRowHits++; 10399977SN/A bytesReadDRAM += burstSize; 10409977SN/A perBankRdBursts[dram_pkt->bankId]++; 104110206Sandreas.hansson@arm.com 104210206Sandreas.hansson@arm.com // Update latency stats 104310206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 104410206Sandreas.hansson@arm.com totBusLat += tBURST; 104510211Sandreas.hansson@arm.com totQLat += cmd_at - dram_pkt->entryTime; 10469977SN/A } else { 104710147Sandreas.hansson@arm.com ++writesThisTime; 104810211Sandreas.hansson@arm.com if (row_hit) 10499977SN/A writeRowHits++; 10509977SN/A bytesWritten += burstSize; 10519977SN/A perBankWrBursts[dram_pkt->bankId]++; 10529243SN/A } 10539243SN/A} 10549243SN/A 10559243SN/Avoid 105610206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 10579243SN/A{ 105810206Sandreas.hansson@arm.com if (busState == READ_TO_WRITE) { 105910206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 106010206Sandreas.hansson@arm.com "waiting\n", readsThisTime, readQueue.size()); 10619243SN/A 106210206Sandreas.hansson@arm.com // sample and reset the read-related stats as we are now 106310206Sandreas.hansson@arm.com // transitioning to writes, and all reads are done 106410206Sandreas.hansson@arm.com rdPerTurnAround.sample(readsThisTime); 106510206Sandreas.hansson@arm.com readsThisTime = 0; 106610206Sandreas.hansson@arm.com 106710206Sandreas.hansson@arm.com // now proceed to do the actual writes 106810206Sandreas.hansson@arm.com busState = WRITE; 106910206Sandreas.hansson@arm.com } else if (busState == WRITE_TO_READ) { 107010206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 107110206Sandreas.hansson@arm.com "waiting\n", writesThisTime, writeQueue.size()); 107210206Sandreas.hansson@arm.com 107310206Sandreas.hansson@arm.com wrPerTurnAround.sample(writesThisTime); 107410206Sandreas.hansson@arm.com writesThisTime = 0; 107510206Sandreas.hansson@arm.com 107610206Sandreas.hansson@arm.com busState = READ; 107710206Sandreas.hansson@arm.com } 107810206Sandreas.hansson@arm.com 107910207Sandreas.hansson@arm.com if (refreshState != REF_IDLE) { 108010207Sandreas.hansson@arm.com // if a refresh waiting for this event loop to finish, then hand 108110207Sandreas.hansson@arm.com // over now, and do not schedule a new nextReqEvent 108210207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 108310207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 108410207Sandreas.hansson@arm.com 108510207Sandreas.hansson@arm.com refreshState = REF_PRE; 108610207Sandreas.hansson@arm.com 108710207Sandreas.hansson@arm.com // hand control back to the refresh event loop 108810207Sandreas.hansson@arm.com schedule(refreshEvent, curTick()); 108910207Sandreas.hansson@arm.com } 109010207Sandreas.hansson@arm.com 109110207Sandreas.hansson@arm.com // let the refresh finish before issuing any further requests 109210207Sandreas.hansson@arm.com return; 109310207Sandreas.hansson@arm.com } 109410207Sandreas.hansson@arm.com 109510206Sandreas.hansson@arm.com // when we get here it is either a read or a write 109610206Sandreas.hansson@arm.com if (busState == READ) { 109710206Sandreas.hansson@arm.com 109810206Sandreas.hansson@arm.com // track if we should switch or not 109910206Sandreas.hansson@arm.com bool switch_to_writes = false; 110010206Sandreas.hansson@arm.com 110110206Sandreas.hansson@arm.com if (readQueue.empty()) { 110210206Sandreas.hansson@arm.com // In the case there is no read request to go next, 110310206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 110410206Sandreas.hansson@arm.com // if we are draining) 110510206Sandreas.hansson@arm.com if (!writeQueue.empty() && 110610206Sandreas.hansson@arm.com (drainManager || writeQueue.size() > writeLowThreshold)) { 110710206Sandreas.hansson@arm.com 110810206Sandreas.hansson@arm.com switch_to_writes = true; 110910206Sandreas.hansson@arm.com } else { 111010206Sandreas.hansson@arm.com // check if we are drained 111110206Sandreas.hansson@arm.com if (respQueue.empty () && drainManager) { 111210206Sandreas.hansson@arm.com drainManager->signalDrainDone(); 111310206Sandreas.hansson@arm.com drainManager = NULL; 111410206Sandreas.hansson@arm.com } 111510206Sandreas.hansson@arm.com 111610206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 111710206Sandreas.hansson@arm.com // event for the next request 111810206Sandreas.hansson@arm.com return; 111910206Sandreas.hansson@arm.com } 112010206Sandreas.hansson@arm.com } else { 112110206Sandreas.hansson@arm.com // Figure out which read request goes next, and move it to the 112210206Sandreas.hansson@arm.com // front of the read queue 112310206Sandreas.hansson@arm.com chooseNext(readQueue); 112410206Sandreas.hansson@arm.com 112510215Sandreas.hansson@arm.com DRAMPacket* dram_pkt = readQueue.front(); 112610215Sandreas.hansson@arm.com 112710215Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 112810206Sandreas.hansson@arm.com 112910206Sandreas.hansson@arm.com // At this point we're done dealing with the request 113010215Sandreas.hansson@arm.com readQueue.pop_front(); 113110215Sandreas.hansson@arm.com 113210215Sandreas.hansson@arm.com // sanity check 113310215Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 113410215Sandreas.hansson@arm.com assert(dram_pkt->readyTime >= curTick()); 113510215Sandreas.hansson@arm.com 113610215Sandreas.hansson@arm.com // Insert into response queue. It will be sent back to the 113710215Sandreas.hansson@arm.com // requestor at its readyTime 113810215Sandreas.hansson@arm.com if (respQueue.empty()) { 113910215Sandreas.hansson@arm.com assert(!respondEvent.scheduled()); 114010215Sandreas.hansson@arm.com schedule(respondEvent, dram_pkt->readyTime); 114110215Sandreas.hansson@arm.com } else { 114210215Sandreas.hansson@arm.com assert(respQueue.back()->readyTime <= dram_pkt->readyTime); 114310215Sandreas.hansson@arm.com assert(respondEvent.scheduled()); 114410215Sandreas.hansson@arm.com } 114510215Sandreas.hansson@arm.com 114610215Sandreas.hansson@arm.com respQueue.push_back(dram_pkt); 114710206Sandreas.hansson@arm.com 114810206Sandreas.hansson@arm.com // we have so many writes that we have to transition 114910206Sandreas.hansson@arm.com if (writeQueue.size() > writeHighThreshold) { 115010206Sandreas.hansson@arm.com switch_to_writes = true; 115110206Sandreas.hansson@arm.com } 115210206Sandreas.hansson@arm.com } 115310206Sandreas.hansson@arm.com 115410206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 115510206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 115610206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 115710206Sandreas.hansson@arm.com if (switch_to_writes) { 115810206Sandreas.hansson@arm.com // transition to writing 115910206Sandreas.hansson@arm.com busState = READ_TO_WRITE; 116010206Sandreas.hansson@arm.com 116110206Sandreas.hansson@arm.com // add a bubble to the data bus, as defined by the 116210206Sandreas.hansson@arm.com // tRTW parameter 116310206Sandreas.hansson@arm.com busBusyUntil += tRTW; 116410206Sandreas.hansson@arm.com 116510206Sandreas.hansson@arm.com // update the minimum timing between the requests, 116610206Sandreas.hansson@arm.com // this shifts us back in time far enough to do any 116710206Sandreas.hansson@arm.com // bank preparation 116810206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 116910206Sandreas.hansson@arm.com } 11709352SN/A } else { 117110206Sandreas.hansson@arm.com chooseNext(writeQueue); 117210206Sandreas.hansson@arm.com DRAMPacket* dram_pkt = writeQueue.front(); 117310206Sandreas.hansson@arm.com // sanity check 117410206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 117510206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 117610206Sandreas.hansson@arm.com 117710206Sandreas.hansson@arm.com writeQueue.pop_front(); 117810206Sandreas.hansson@arm.com delete dram_pkt; 117910206Sandreas.hansson@arm.com 118010206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 118110206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 118210206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 118310206Sandreas.hansson@arm.com // writes, then switch to reads. 118410206Sandreas.hansson@arm.com if (writeQueue.empty() || 118510206Sandreas.hansson@arm.com (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 118610206Sandreas.hansson@arm.com !drainManager) || 118710206Sandreas.hansson@arm.com (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 118810206Sandreas.hansson@arm.com // turn the bus back around for reads again 118910206Sandreas.hansson@arm.com busState = WRITE_TO_READ; 119010206Sandreas.hansson@arm.com 119110206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 119210206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 119310206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 119410206Sandreas.hansson@arm.com // nothing to do 119510206Sandreas.hansson@arm.com 119610206Sandreas.hansson@arm.com // here we get a bit creative and shift the bus busy time not 119710206Sandreas.hansson@arm.com // just the tWTR, but also a CAS latency to capture the fact 119810206Sandreas.hansson@arm.com // that we are allowed to prepare a new bank, but not issue a 119910206Sandreas.hansson@arm.com // read command until after tWTR, in essence we capture a 120010206Sandreas.hansson@arm.com // bubble on the data bus that is tWTR + tCL 120110206Sandreas.hansson@arm.com busBusyUntil += tWTR + tCL; 120210206Sandreas.hansson@arm.com 120310206Sandreas.hansson@arm.com // update the minimum timing between the requests, this shifts 120410206Sandreas.hansson@arm.com // us back in time far enough to do any bank preparation 120510206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 120610206Sandreas.hansson@arm.com } 120710206Sandreas.hansson@arm.com } 120810206Sandreas.hansson@arm.com 120910206Sandreas.hansson@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 121010206Sandreas.hansson@arm.com 121110206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 121210206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 121310206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 121410206Sandreas.hansson@arm.com // the next request processing 121510206Sandreas.hansson@arm.com if (retryWrReq && writeQueue.size() < writeBufferSize) { 121610206Sandreas.hansson@arm.com retryWrReq = false; 121710206Sandreas.hansson@arm.com port.sendRetry(); 12189352SN/A } 12199243SN/A} 12209243SN/A 12219967SN/Auint64_t 122210211Sandreas.hansson@arm.comDRAMCtrl::minBankActAt(const deque<DRAMPacket*>& queue) const 12239967SN/A{ 12249967SN/A uint64_t bank_mask = 0; 122510211Sandreas.hansson@arm.com Tick min_act_at = MaxTick; 12269967SN/A 122710211Sandreas.hansson@arm.com // deterimne if we have queued transactions targetting a 12289967SN/A // bank in question 12299967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 12309967SN/A for (auto p = queue.begin(); p != queue.end(); ++p) { 12319967SN/A got_waiting[(*p)->bankId] = true; 12329967SN/A } 12339967SN/A 12349967SN/A for (int i = 0; i < ranksPerChannel; i++) { 12359967SN/A for (int j = 0; j < banksPerRank; j++) { 123610211Sandreas.hansson@arm.com uint8_t bank_id = i * banksPerRank + j; 123710211Sandreas.hansson@arm.com 12389967SN/A // if we have waiting requests for the bank, and it is 12399967SN/A // amongst the first available, update the mask 124010211Sandreas.hansson@arm.com if (got_waiting[bank_id]) { 124110211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue 124210211Sandreas.hansson@arm.com // an activate, ignoring any rank-to-rank switching 124310211Sandreas.hansson@arm.com // cost 124410211Sandreas.hansson@arm.com Tick act_at = banks[i][j].openRow == Bank::NO_ROW ? 124510211Sandreas.hansson@arm.com banks[i][j].actAllowedAt : 124610211Sandreas.hansson@arm.com std::max(banks[i][j].preAllowedAt, curTick()) + tRP; 124710211Sandreas.hansson@arm.com 124810211Sandreas.hansson@arm.com if (act_at <= min_act_at) { 124910211Sandreas.hansson@arm.com // reset bank mask if new minimum is found 125010211Sandreas.hansson@arm.com if (act_at < min_act_at) 125110211Sandreas.hansson@arm.com bank_mask = 0; 125210211Sandreas.hansson@arm.com // set the bit corresponding to the available bank 125310211Sandreas.hansson@arm.com replaceBits(bank_mask, bank_id, bank_id, 1); 125410211Sandreas.hansson@arm.com min_act_at = act_at; 125510211Sandreas.hansson@arm.com } 12569967SN/A } 12579967SN/A } 12589967SN/A } 125910211Sandreas.hansson@arm.com 12609967SN/A return bank_mask; 12619967SN/A} 12629967SN/A 12639243SN/Avoid 126410146Sandreas.hansson@arm.comDRAMCtrl::processRefreshEvent() 12659243SN/A{ 126610207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 126710207Sandreas.hansson@arm.com if (refreshState == REF_IDLE) { 126810207Sandreas.hansson@arm.com // remember when the refresh is due 126910207Sandreas.hansson@arm.com refreshDueAt = curTick(); 12709243SN/A 127110207Sandreas.hansson@arm.com // proceed to drain 127210207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 12739243SN/A 127410207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 127510207Sandreas.hansson@arm.com } 127610207Sandreas.hansson@arm.com 127710207Sandreas.hansson@arm.com // let any scheduled read or write go ahead, after which it will 127810207Sandreas.hansson@arm.com // hand control back to this event loop 127910207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 128010207Sandreas.hansson@arm.com if (nextReqEvent.scheduled()) { 128110207Sandreas.hansson@arm.com // hand control over to the request loop until it is 128210207Sandreas.hansson@arm.com // evaluated next 128310207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 128410207Sandreas.hansson@arm.com 128510207Sandreas.hansson@arm.com return; 128610207Sandreas.hansson@arm.com } else { 128710207Sandreas.hansson@arm.com refreshState = REF_PRE; 128810207Sandreas.hansson@arm.com } 128910207Sandreas.hansson@arm.com } 129010207Sandreas.hansson@arm.com 129110207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 129210207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 129310208Sandreas.hansson@arm.com // precharge any active bank if we are not already in the idle 129410208Sandreas.hansson@arm.com // state 129510208Sandreas.hansson@arm.com if (pwrState != PWR_IDLE) { 129610214Sandreas.hansson@arm.com // at the moment, we use a precharge all even if there is 129710214Sandreas.hansson@arm.com // only a single bank open 129810208Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 129910214Sandreas.hansson@arm.com 130010214Sandreas.hansson@arm.com // first determine when we can precharge 130110214Sandreas.hansson@arm.com Tick pre_at = curTick(); 130210214Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 130310214Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 130410214Sandreas.hansson@arm.com // respect both causality and any existing bank 130510214Sandreas.hansson@arm.com // constraints, some banks could already have a 130610214Sandreas.hansson@arm.com // (auto) precharge scheduled 130710214Sandreas.hansson@arm.com pre_at = std::max(banks[i][j].preAllowedAt, pre_at); 130810214Sandreas.hansson@arm.com } 130910214Sandreas.hansson@arm.com } 131010214Sandreas.hansson@arm.com 131110214Sandreas.hansson@arm.com // make sure all banks are precharged, and for those that 131210214Sandreas.hansson@arm.com // already are, update their availability 131310214Sandreas.hansson@arm.com Tick act_allowed_at = pre_at + tRP; 131410214Sandreas.hansson@arm.com 131510208Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 131610208Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 131710208Sandreas.hansson@arm.com if (banks[i][j].openRow != Bank::NO_ROW) { 131810211Sandreas.hansson@arm.com prechargeBank(banks[i][j], pre_at); 131910214Sandreas.hansson@arm.com } else { 132010214Sandreas.hansson@arm.com banks[i][j].actAllowedAt = 132110214Sandreas.hansson@arm.com std::max(banks[i][j].actAllowedAt, act_allowed_at); 132210214Sandreas.hansson@arm.com banks[i][j].preAllowedAt = 132310214Sandreas.hansson@arm.com std::max(banks[i][j].preAllowedAt, pre_at); 132410208Sandreas.hansson@arm.com } 132510207Sandreas.hansson@arm.com } 132610207Sandreas.hansson@arm.com } 132710208Sandreas.hansson@arm.com } else { 132810208Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 132910208Sandreas.hansson@arm.com 133010208Sandreas.hansson@arm.com // go ahead and kick the power state machine into gear if 133110208Sandreas.hansson@arm.com // we are already idle 133210208Sandreas.hansson@arm.com schedulePowerEvent(PWR_REF, curTick()); 13339975SN/A } 13349975SN/A 133510208Sandreas.hansson@arm.com refreshState = REF_RUN; 133610208Sandreas.hansson@arm.com assert(numBanksActive == 0); 13379243SN/A 133810208Sandreas.hansson@arm.com // wait for all banks to be precharged, at which point the 133910208Sandreas.hansson@arm.com // power state machine will transition to the idle state, and 134010208Sandreas.hansson@arm.com // automatically move to a refresh, at that point it will also 134110208Sandreas.hansson@arm.com // call this method to get the refresh event loop going again 134210207Sandreas.hansson@arm.com return; 134310207Sandreas.hansson@arm.com } 134410207Sandreas.hansson@arm.com 134510207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 134610207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 134710207Sandreas.hansson@arm.com // should never get here with any banks active 134810207Sandreas.hansson@arm.com assert(numBanksActive == 0); 134910208Sandreas.hansson@arm.com assert(pwrState == PWR_REF); 135010207Sandreas.hansson@arm.com 135110211Sandreas.hansson@arm.com Tick ref_done_at = curTick() + tRFC; 135210207Sandreas.hansson@arm.com 135310207Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 135410207Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 135510211Sandreas.hansson@arm.com banks[i][j].actAllowedAt = ref_done_at; 135610207Sandreas.hansson@arm.com } 135710207Sandreas.hansson@arm.com } 135810207Sandreas.hansson@arm.com 135910207Sandreas.hansson@arm.com // make sure we did not wait so long that we cannot make up 136010207Sandreas.hansson@arm.com // for it 136110211Sandreas.hansson@arm.com if (refreshDueAt + tREFI < ref_done_at) { 136210207Sandreas.hansson@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 136310207Sandreas.hansson@arm.com } 136410207Sandreas.hansson@arm.com 136510207Sandreas.hansson@arm.com // compensate for the delay in actually performing the refresh 136610207Sandreas.hansson@arm.com // when scheduling the next one 136710207Sandreas.hansson@arm.com schedule(refreshEvent, refreshDueAt + tREFI - tRP); 136810207Sandreas.hansson@arm.com 136910208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 137010207Sandreas.hansson@arm.com 137110208Sandreas.hansson@arm.com // move to the idle power state once the refresh is done, this 137210208Sandreas.hansson@arm.com // will also move the refresh state machine to the refresh 137310208Sandreas.hansson@arm.com // idle state 137410211Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, ref_done_at); 137510207Sandreas.hansson@arm.com 137610208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n", 137710211Sandreas.hansson@arm.com ref_done_at, refreshDueAt + tREFI); 137810208Sandreas.hansson@arm.com } 137910208Sandreas.hansson@arm.com} 138010208Sandreas.hansson@arm.com 138110208Sandreas.hansson@arm.comvoid 138210208Sandreas.hansson@arm.comDRAMCtrl::schedulePowerEvent(PowerState pwr_state, Tick tick) 138310208Sandreas.hansson@arm.com{ 138410208Sandreas.hansson@arm.com // respect causality 138510208Sandreas.hansson@arm.com assert(tick >= curTick()); 138610208Sandreas.hansson@arm.com 138710208Sandreas.hansson@arm.com if (!powerEvent.scheduled()) { 138810208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 138910208Sandreas.hansson@arm.com tick, pwr_state); 139010208Sandreas.hansson@arm.com 139110208Sandreas.hansson@arm.com // insert the new transition 139210208Sandreas.hansson@arm.com pwrStateTrans = pwr_state; 139310208Sandreas.hansson@arm.com 139410208Sandreas.hansson@arm.com schedule(powerEvent, tick); 139510208Sandreas.hansson@arm.com } else { 139610208Sandreas.hansson@arm.com panic("Scheduled power event at %llu to state %d, " 139710208Sandreas.hansson@arm.com "with scheduled event at %llu to %d\n", tick, pwr_state, 139810208Sandreas.hansson@arm.com powerEvent.when(), pwrStateTrans); 139910208Sandreas.hansson@arm.com } 140010208Sandreas.hansson@arm.com} 140110208Sandreas.hansson@arm.com 140210208Sandreas.hansson@arm.comvoid 140310208Sandreas.hansson@arm.comDRAMCtrl::processPowerEvent() 140410208Sandreas.hansson@arm.com{ 140510208Sandreas.hansson@arm.com // remember where we were, and for how long 140610208Sandreas.hansson@arm.com Tick duration = curTick() - pwrStateTick; 140710208Sandreas.hansson@arm.com PowerState prev_state = pwrState; 140810208Sandreas.hansson@arm.com 140910208Sandreas.hansson@arm.com // update the accounting 141010208Sandreas.hansson@arm.com pwrStateTime[prev_state] += duration; 141110208Sandreas.hansson@arm.com 141210208Sandreas.hansson@arm.com pwrState = pwrStateTrans; 141310208Sandreas.hansson@arm.com pwrStateTick = curTick(); 141410208Sandreas.hansson@arm.com 141510208Sandreas.hansson@arm.com if (pwrState == PWR_IDLE) { 141610208Sandreas.hansson@arm.com DPRINTF(DRAMState, "All banks precharged\n"); 141710208Sandreas.hansson@arm.com 141810208Sandreas.hansson@arm.com // if we were refreshing, make sure we start scheduling requests again 141910208Sandreas.hansson@arm.com if (prev_state == PWR_REF) { 142010208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 142110208Sandreas.hansson@arm.com assert(pwrState == PWR_IDLE); 142210208Sandreas.hansson@arm.com 142310208Sandreas.hansson@arm.com // kick things into action again 142410208Sandreas.hansson@arm.com refreshState = REF_IDLE; 142510208Sandreas.hansson@arm.com assert(!nextReqEvent.scheduled()); 142610208Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 142710208Sandreas.hansson@arm.com } else { 142810208Sandreas.hansson@arm.com assert(prev_state == PWR_ACT); 142910208Sandreas.hansson@arm.com 143010208Sandreas.hansson@arm.com // if we have a pending refresh, and are now moving to 143110208Sandreas.hansson@arm.com // the idle state, direclty transition to a refresh 143210208Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 143310208Sandreas.hansson@arm.com // there should be nothing waiting at this point 143410208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 143510208Sandreas.hansson@arm.com 143610208Sandreas.hansson@arm.com // update the state in zero time and proceed below 143710208Sandreas.hansson@arm.com pwrState = PWR_REF; 143810208Sandreas.hansson@arm.com } 143910208Sandreas.hansson@arm.com } 144010208Sandreas.hansson@arm.com } 144110208Sandreas.hansson@arm.com 144210208Sandreas.hansson@arm.com // we transition to the refresh state, let the refresh state 144310208Sandreas.hansson@arm.com // machine know of this state update and let it deal with the 144410208Sandreas.hansson@arm.com // scheduling of the next power state transition as well as the 144510208Sandreas.hansson@arm.com // following refresh 144610208Sandreas.hansson@arm.com if (pwrState == PWR_REF) { 144710208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refreshing\n"); 144810208Sandreas.hansson@arm.com // kick the refresh event loop into action again, and that 144910208Sandreas.hansson@arm.com // in turn will schedule a transition to the idle power 145010208Sandreas.hansson@arm.com // state once the refresh is done 145110208Sandreas.hansson@arm.com assert(refreshState == REF_RUN); 145210208Sandreas.hansson@arm.com processRefreshEvent(); 145310207Sandreas.hansson@arm.com } 14549243SN/A} 14559243SN/A 14569243SN/Avoid 145710146Sandreas.hansson@arm.comDRAMCtrl::regStats() 14589243SN/A{ 14599243SN/A using namespace Stats; 14609243SN/A 14619243SN/A AbstractMemory::regStats(); 14629243SN/A 14639243SN/A readReqs 14649243SN/A .name(name() + ".readReqs") 14659977SN/A .desc("Number of read requests accepted"); 14669243SN/A 14679243SN/A writeReqs 14689243SN/A .name(name() + ".writeReqs") 14699977SN/A .desc("Number of write requests accepted"); 14709831SN/A 14719831SN/A readBursts 14729831SN/A .name(name() + ".readBursts") 14739977SN/A .desc("Number of DRAM read bursts, " 14749977SN/A "including those serviced by the write queue"); 14759831SN/A 14769831SN/A writeBursts 14779831SN/A .name(name() + ".writeBursts") 14789977SN/A .desc("Number of DRAM write bursts, " 14799977SN/A "including those merged in the write queue"); 14809243SN/A 14819243SN/A servicedByWrQ 14829243SN/A .name(name() + ".servicedByWrQ") 14839977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 14849977SN/A 14859977SN/A mergedWrBursts 14869977SN/A .name(name() + ".mergedWrBursts") 14879977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 14889243SN/A 14899243SN/A neitherReadNorWrite 14909977SN/A .name(name() + ".neitherReadNorWriteReqs") 14919977SN/A .desc("Number of requests that are neither read nor write"); 14929243SN/A 14939977SN/A perBankRdBursts 14949243SN/A .init(banksPerRank * ranksPerChannel) 14959977SN/A .name(name() + ".perBankRdBursts") 14969977SN/A .desc("Per bank write bursts"); 14979243SN/A 14989977SN/A perBankWrBursts 14999243SN/A .init(banksPerRank * ranksPerChannel) 15009977SN/A .name(name() + ".perBankWrBursts") 15019977SN/A .desc("Per bank write bursts"); 15029243SN/A 15039243SN/A avgRdQLen 15049243SN/A .name(name() + ".avgRdQLen") 15059977SN/A .desc("Average read queue length when enqueuing") 15069243SN/A .precision(2); 15079243SN/A 15089243SN/A avgWrQLen 15099243SN/A .name(name() + ".avgWrQLen") 15109977SN/A .desc("Average write queue length when enqueuing") 15119243SN/A .precision(2); 15129243SN/A 15139243SN/A totQLat 15149243SN/A .name(name() + ".totQLat") 15159977SN/A .desc("Total ticks spent queuing"); 15169243SN/A 15179243SN/A totBusLat 15189243SN/A .name(name() + ".totBusLat") 15199977SN/A .desc("Total ticks spent in databus transfers"); 15209243SN/A 15219243SN/A totMemAccLat 15229243SN/A .name(name() + ".totMemAccLat") 15239977SN/A .desc("Total ticks spent from burst creation until serviced " 15249977SN/A "by the DRAM"); 15259243SN/A 15269243SN/A avgQLat 15279243SN/A .name(name() + ".avgQLat") 15289977SN/A .desc("Average queueing delay per DRAM burst") 15299243SN/A .precision(2); 15309243SN/A 15319831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 15329243SN/A 15339243SN/A avgBusLat 15349243SN/A .name(name() + ".avgBusLat") 15359977SN/A .desc("Average bus latency per DRAM burst") 15369243SN/A .precision(2); 15379243SN/A 15389831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 15399243SN/A 15409243SN/A avgMemAccLat 15419243SN/A .name(name() + ".avgMemAccLat") 15429977SN/A .desc("Average memory access latency per DRAM burst") 15439243SN/A .precision(2); 15449243SN/A 15459831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 15469243SN/A 15479243SN/A numRdRetry 15489243SN/A .name(name() + ".numRdRetry") 15499977SN/A .desc("Number of times read queue was full causing retry"); 15509243SN/A 15519243SN/A numWrRetry 15529243SN/A .name(name() + ".numWrRetry") 15539977SN/A .desc("Number of times write queue was full causing retry"); 15549243SN/A 15559243SN/A readRowHits 15569243SN/A .name(name() + ".readRowHits") 15579243SN/A .desc("Number of row buffer hits during reads"); 15589243SN/A 15599243SN/A writeRowHits 15609243SN/A .name(name() + ".writeRowHits") 15619243SN/A .desc("Number of row buffer hits during writes"); 15629243SN/A 15639243SN/A readRowHitRate 15649243SN/A .name(name() + ".readRowHitRate") 15659243SN/A .desc("Row buffer hit rate for reads") 15669243SN/A .precision(2); 15679243SN/A 15689831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 15699243SN/A 15709243SN/A writeRowHitRate 15719243SN/A .name(name() + ".writeRowHitRate") 15729243SN/A .desc("Row buffer hit rate for writes") 15739243SN/A .precision(2); 15749243SN/A 15759977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 15769243SN/A 15779243SN/A readPktSize 15789831SN/A .init(ceilLog2(burstSize) + 1) 15799243SN/A .name(name() + ".readPktSize") 15809977SN/A .desc("Read request sizes (log2)"); 15819243SN/A 15829243SN/A writePktSize 15839831SN/A .init(ceilLog2(burstSize) + 1) 15849243SN/A .name(name() + ".writePktSize") 15859977SN/A .desc("Write request sizes (log2)"); 15869243SN/A 15879243SN/A rdQLenPdf 15889567SN/A .init(readBufferSize) 15899243SN/A .name(name() + ".rdQLenPdf") 15909243SN/A .desc("What read queue length does an incoming req see"); 15919243SN/A 15929243SN/A wrQLenPdf 15939567SN/A .init(writeBufferSize) 15949243SN/A .name(name() + ".wrQLenPdf") 15959243SN/A .desc("What write queue length does an incoming req see"); 15969243SN/A 15979727SN/A bytesPerActivate 159810141SN/A .init(maxAccessesPerRow) 15999727SN/A .name(name() + ".bytesPerActivate") 16009727SN/A .desc("Bytes accessed per row activation") 16019727SN/A .flags(nozero); 16029243SN/A 160310147Sandreas.hansson@arm.com rdPerTurnAround 160410147Sandreas.hansson@arm.com .init(readBufferSize) 160510147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 160610147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 160710147Sandreas.hansson@arm.com .flags(nozero); 160810147Sandreas.hansson@arm.com 160910147Sandreas.hansson@arm.com wrPerTurnAround 161010147Sandreas.hansson@arm.com .init(writeBufferSize) 161110147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 161210147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 161310147Sandreas.hansson@arm.com .flags(nozero); 161410147Sandreas.hansson@arm.com 16159975SN/A bytesReadDRAM 16169975SN/A .name(name() + ".bytesReadDRAM") 16179975SN/A .desc("Total number of bytes read from DRAM"); 16189975SN/A 16199975SN/A bytesReadWrQ 16209975SN/A .name(name() + ".bytesReadWrQ") 16219975SN/A .desc("Total number of bytes read from write queue"); 16229243SN/A 16239243SN/A bytesWritten 16249243SN/A .name(name() + ".bytesWritten") 16259977SN/A .desc("Total number of bytes written to DRAM"); 16269243SN/A 16279977SN/A bytesReadSys 16289977SN/A .name(name() + ".bytesReadSys") 16299977SN/A .desc("Total read bytes from the system interface side"); 16309243SN/A 16319977SN/A bytesWrittenSys 16329977SN/A .name(name() + ".bytesWrittenSys") 16339977SN/A .desc("Total written bytes from the system interface side"); 16349243SN/A 16359243SN/A avgRdBW 16369243SN/A .name(name() + ".avgRdBW") 16379977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 16389243SN/A .precision(2); 16399243SN/A 16409977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 16419243SN/A 16429243SN/A avgWrBW 16439243SN/A .name(name() + ".avgWrBW") 16449977SN/A .desc("Average achieved write bandwidth in MiByte/s") 16459243SN/A .precision(2); 16469243SN/A 16479243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 16489243SN/A 16499977SN/A avgRdBWSys 16509977SN/A .name(name() + ".avgRdBWSys") 16519977SN/A .desc("Average system read bandwidth in MiByte/s") 16529243SN/A .precision(2); 16539243SN/A 16549977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 16559243SN/A 16569977SN/A avgWrBWSys 16579977SN/A .name(name() + ".avgWrBWSys") 16589977SN/A .desc("Average system write bandwidth in MiByte/s") 16599243SN/A .precision(2); 16609243SN/A 16619977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 16629243SN/A 16639243SN/A peakBW 16649243SN/A .name(name() + ".peakBW") 16659977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 16669243SN/A .precision(2); 16679243SN/A 16689831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 16699243SN/A 16709243SN/A busUtil 16719243SN/A .name(name() + ".busUtil") 16729243SN/A .desc("Data bus utilization in percentage") 16739243SN/A .precision(2); 16749243SN/A 16759243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 16769243SN/A 16779243SN/A totGap 16789243SN/A .name(name() + ".totGap") 16799243SN/A .desc("Total gap between requests"); 16809243SN/A 16819243SN/A avgGap 16829243SN/A .name(name() + ".avgGap") 16839243SN/A .desc("Average gap between requests") 16849243SN/A .precision(2); 16859243SN/A 16869243SN/A avgGap = totGap / (readReqs + writeReqs); 16879975SN/A 16889975SN/A // Stats for DRAM Power calculation based on Micron datasheet 16899975SN/A busUtilRead 16909975SN/A .name(name() + ".busUtilRead") 16919975SN/A .desc("Data bus utilization in percentage for reads") 16929975SN/A .precision(2); 16939975SN/A 16949975SN/A busUtilRead = avgRdBW / peakBW * 100; 16959975SN/A 16969975SN/A busUtilWrite 16979975SN/A .name(name() + ".busUtilWrite") 16989975SN/A .desc("Data bus utilization in percentage for writes") 16999975SN/A .precision(2); 17009975SN/A 17019975SN/A busUtilWrite = avgWrBW / peakBW * 100; 17029975SN/A 17039975SN/A pageHitRate 17049975SN/A .name(name() + ".pageHitRate") 17059975SN/A .desc("Row buffer hit rate, read and write combined") 17069975SN/A .precision(2); 17079975SN/A 17089977SN/A pageHitRate = (writeRowHits + readRowHits) / 17099977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 17109975SN/A 171110208Sandreas.hansson@arm.com pwrStateTime 171210208Sandreas.hansson@arm.com .init(5) 171310208Sandreas.hansson@arm.com .name(name() + ".memoryStateTime") 171410208Sandreas.hansson@arm.com .desc("Time in different power states"); 171510208Sandreas.hansson@arm.com pwrStateTime.subname(0, "IDLE"); 171610208Sandreas.hansson@arm.com pwrStateTime.subname(1, "REF"); 171710208Sandreas.hansson@arm.com pwrStateTime.subname(2, "PRE_PDN"); 171810208Sandreas.hansson@arm.com pwrStateTime.subname(3, "ACT"); 171910208Sandreas.hansson@arm.com pwrStateTime.subname(4, "ACT_PDN"); 17209243SN/A} 17219243SN/A 17229243SN/Avoid 172310146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 17249243SN/A{ 17259243SN/A // rely on the abstract memory 17269243SN/A functionalAccess(pkt); 17279243SN/A} 17289243SN/A 17299294SN/ABaseSlavePort& 173010146Sandreas.hansson@arm.comDRAMCtrl::getSlavePort(const string &if_name, PortID idx) 17319243SN/A{ 17329243SN/A if (if_name != "port") { 17339243SN/A return MemObject::getSlavePort(if_name, idx); 17349243SN/A } else { 17359243SN/A return port; 17369243SN/A } 17379243SN/A} 17389243SN/A 17399243SN/Aunsigned int 174010146Sandreas.hansson@arm.comDRAMCtrl::drain(DrainManager *dm) 17419243SN/A{ 17429342SN/A unsigned int count = port.drain(dm); 17439243SN/A 17449243SN/A // if there is anything in any of our internal queues, keep track 17459243SN/A // of that as well 17469567SN/A if (!(writeQueue.empty() && readQueue.empty() && 17479567SN/A respQueue.empty())) { 17489352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 17499567SN/A " resp: %d\n", writeQueue.size(), readQueue.size(), 17509567SN/A respQueue.size()); 17519243SN/A ++count; 17529342SN/A drainManager = dm; 175310206Sandreas.hansson@arm.com 17549352SN/A // the only part that is not drained automatically over time 175510206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 175610206Sandreas.hansson@arm.com if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 175710206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 175810206Sandreas.hansson@arm.com } 17599243SN/A } 17609243SN/A 17619243SN/A if (count) 17629342SN/A setDrainState(Drainable::Draining); 17639243SN/A else 17649342SN/A setDrainState(Drainable::Drained); 17659243SN/A return count; 17669243SN/A} 17679243SN/A 176810146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 17699243SN/A : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 17709243SN/A memory(_memory) 17719243SN/A{ } 17729243SN/A 17739243SN/AAddrRangeList 177410146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 17759243SN/A{ 17769243SN/A AddrRangeList ranges; 17779243SN/A ranges.push_back(memory.getAddrRange()); 17789243SN/A return ranges; 17799243SN/A} 17809243SN/A 17819243SN/Avoid 178210146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 17839243SN/A{ 17849243SN/A pkt->pushLabel(memory.name()); 17859243SN/A 17869243SN/A if (!queue.checkFunctional(pkt)) { 17879243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 17889243SN/A // calls recvAtomic() and throws away the latency; we can save a 17899243SN/A // little here by just not calculating the latency. 17909243SN/A memory.recvFunctional(pkt); 17919243SN/A } 17929243SN/A 17939243SN/A pkt->popLabel(); 17949243SN/A} 17959243SN/A 17969243SN/ATick 179710146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 17989243SN/A{ 17999243SN/A return memory.recvAtomic(pkt); 18009243SN/A} 18019243SN/A 18029243SN/Abool 180310146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 18049243SN/A{ 18059243SN/A // pass it to the memory controller 18069243SN/A return memory.recvTimingReq(pkt); 18079243SN/A} 18089243SN/A 180910146Sandreas.hansson@arm.comDRAMCtrl* 181010146Sandreas.hansson@arm.comDRAMCtrlParams::create() 18119243SN/A{ 181210146Sandreas.hansson@arm.com return new DRAMCtrl(this); 18139243SN/A} 1814