dram_ctrl.cc revision 10216
19243SN/A/* 210206Sandreas.hansson@arm.com * Copyright (c) 2010-2014 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 439243SN/A */ 449243SN/A 4510146Sandreas.hansson@arm.com#include "base/bitfield.hh" 469356SN/A#include "base/trace.hh" 4710146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 4810208Sandreas.hansson@arm.com#include "debug/DRAMState.hh" 499352SN/A#include "debug/Drain.hh" 5010146Sandreas.hansson@arm.com#include "mem/dram_ctrl.hh" 519814SN/A#include "sim/system.hh" 529243SN/A 539243SN/Ausing namespace std; 549243SN/A 5510146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 569243SN/A AbstractMemory(p), 579243SN/A port(name() + ".port", *this), 589243SN/A retryRdReq(false), retryWrReq(false), 5910211Sandreas.hansson@arm.com busState(READ), 6010208Sandreas.hansson@arm.com nextReqEvent(this), respondEvent(this), activateEvent(this), 6110208Sandreas.hansson@arm.com prechargeEvent(this), refreshEvent(this), powerEvent(this), 6210208Sandreas.hansson@arm.com drainManager(NULL), 639831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 649831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 659831SN/A devicesPerRank(p->devices_per_rank), 669831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 679831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 6810140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 699243SN/A ranksPerChannel(p->ranks_per_channel), 709566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 719243SN/A readBufferSize(p->read_buffer_size), 729243SN/A writeBufferSize(p->write_buffer_size), 7310140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 7410140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 7510147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 7610147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 7710216Sandreas.hansson@arm.com tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tBURST(p->tBURST), 7810210Sandreas.hansson@arm.com tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), tWR(p->tWR), 7910212Sandreas.hansson@arm.com tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 809488SN/A tXAW(p->tXAW), activationLimit(p->activation_limit), 819243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 829243SN/A pageMgmt(p->page_policy), 8310141SN/A maxAccessesPerRow(p->max_accesses_per_row), 849726SN/A frontendLatency(p->static_frontend_latency), 859726SN/A backendLatency(p->static_backend_latency), 8610208Sandreas.hansson@arm.com busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE), 8710208Sandreas.hansson@arm.com pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), prevArrival(0), 8810208Sandreas.hansson@arm.com nextReqTime(0), pwrStateTick(0), numBanksActive(0) 899243SN/A{ 909243SN/A // create the bank states based on the dimensions of the ranks and 919243SN/A // banks 929243SN/A banks.resize(ranksPerChannel); 939969SN/A actTicks.resize(ranksPerChannel); 949243SN/A for (size_t c = 0; c < ranksPerChannel; ++c) { 959243SN/A banks[c].resize(banksPerRank); 969969SN/A actTicks[c].resize(activationLimit, 0); 979243SN/A } 989243SN/A 9910140SN/A // perform a basic check of the write thresholds 10010140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 10110140SN/A fatal("Write buffer low threshold %d must be smaller than the " 10210140SN/A "high threshold %d\n", p->write_low_thresh_perc, 10310140SN/A p->write_high_thresh_perc); 1049243SN/A 1059243SN/A // determine the rows per bank by looking at the total capacity 1069567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1079243SN/A 1089243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1099243SN/A AbstractMemory::size()); 1109831SN/A 1119831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1129831SN/A rowBufferSize, columnsPerRowBuffer); 1139831SN/A 1149831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1159243SN/A 1169566SN/A if (range.interleaved()) { 1179566SN/A if (channels != range.stripes()) 11810143SN/A fatal("%s has %d interleaved address stripes but %d channel(s)\n", 1199566SN/A name(), range.stripes(), channels); 1209566SN/A 12110136SN/A if (addrMapping == Enums::RoRaBaChCo) { 1229831SN/A if (rowBufferSize != range.granularity()) { 12310143SN/A fatal("Interleaving of %s doesn't match RoRaBaChCo " 12410136SN/A "address map\n", name()); 1259566SN/A } 12610136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 12710136SN/A if (system()->cacheLineSize() != range.granularity()) { 12810143SN/A fatal("Interleaving of %s doesn't match RoRaBaCoCh " 12910136SN/A "address map\n", name()); 1309669SN/A } 13110136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 13210136SN/A if (system()->cacheLineSize() != range.granularity()) 13310143SN/A fatal("Interleaving of %s doesn't match RoCoRaBaCh " 13410136SN/A "address map\n", name()); 1359566SN/A } 1369566SN/A } 13710207Sandreas.hansson@arm.com 13810207Sandreas.hansson@arm.com // some basic sanity checks 13910207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 14010207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 14110207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 14210207Sandreas.hansson@arm.com } 1439243SN/A} 1449243SN/A 1459243SN/Avoid 14610146Sandreas.hansson@arm.comDRAMCtrl::init() 14710140SN/A{ 14810140SN/A if (!port.isConnected()) { 14910146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 15010140SN/A } else { 15110140SN/A port.sendRangeChange(); 15210140SN/A } 15310140SN/A} 15410140SN/A 15510140SN/Avoid 15610146Sandreas.hansson@arm.comDRAMCtrl::startup() 1579243SN/A{ 15810143SN/A // update the start tick for the precharge accounting to the 15910143SN/A // current tick 16010208Sandreas.hansson@arm.com pwrStateTick = curTick(); 16110143SN/A 16210206Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 16310206Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 16410206Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 16510206Sandreas.hansson@arm.com // start of simulation 16610206Sandreas.hansson@arm.com busBusyUntil = curTick() + tRP + tRCD + tCL; 16710206Sandreas.hansson@arm.com 16810207Sandreas.hansson@arm.com // kick off the refresh, and give ourselves enough time to 16910207Sandreas.hansson@arm.com // precharge 17010207Sandreas.hansson@arm.com schedule(refreshEvent, curTick() + tREFI - tRP); 1719243SN/A} 1729243SN/A 1739243SN/ATick 17410146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 1759243SN/A{ 1769243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 1779243SN/A 1789243SN/A // do the actual memory access and turn the packet into a response 1799243SN/A access(pkt); 1809243SN/A 1819243SN/A Tick latency = 0; 1829243SN/A if (!pkt->memInhibitAsserted() && pkt->hasData()) { 1839243SN/A // this value is not supposed to be accurate, just enough to 1849243SN/A // keep things going, mimic a closed page 1859243SN/A latency = tRP + tRCD + tCL; 1869243SN/A } 1879243SN/A return latency; 1889243SN/A} 1899243SN/A 1909243SN/Abool 19110146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 1929243SN/A{ 1939831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 1949831SN/A readBufferSize, readQueue.size() + respQueue.size(), 1959831SN/A neededEntries); 1969243SN/A 1979831SN/A return 1989831SN/A (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 1999243SN/A} 2009243SN/A 2019243SN/Abool 20210146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 2039243SN/A{ 2049831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 2059831SN/A writeBufferSize, writeQueue.size(), neededEntries); 2069831SN/A return (writeQueue.size() + neededEntries) > writeBufferSize; 2079243SN/A} 2089243SN/A 20910146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 21010146Sandreas.hansson@arm.comDRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 21110143SN/A bool isRead) 2129243SN/A{ 2139669SN/A // decode the address based on the address mapping scheme, with 21410136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 21510136SN/A // channel, respectively 2169243SN/A uint8_t rank; 2179967SN/A uint8_t bank; 2189243SN/A uint16_t row; 2199243SN/A 2209243SN/A // truncate the address to the access granularity 2219831SN/A Addr addr = dramPktAddr / burstSize; 2229243SN/A 2239491SN/A // we have removed the lowest order address bits that denote the 2249831SN/A // position within the column 22510136SN/A if (addrMapping == Enums::RoRaBaChCo) { 2269491SN/A // the lowest order bits denote the column to ensure that 2279491SN/A // sequential cache lines occupy the same row 2289831SN/A addr = addr / columnsPerRowBuffer; 2299243SN/A 2309669SN/A // take out the channel part of the address 2319566SN/A addr = addr / channels; 2329566SN/A 2339669SN/A // after the channel bits, get the bank bits to interleave 2349669SN/A // over the banks 2359669SN/A bank = addr % banksPerRank; 2369669SN/A addr = addr / banksPerRank; 2379669SN/A 2389669SN/A // after the bank, we get the rank bits which thus interleaves 2399669SN/A // over the ranks 2409669SN/A rank = addr % ranksPerChannel; 2419669SN/A addr = addr / ranksPerChannel; 2429669SN/A 2439669SN/A // lastly, get the row bits 2449669SN/A row = addr % rowsPerBank; 2459669SN/A addr = addr / rowsPerBank; 24610136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 2479669SN/A // take out the channel part of the address 2489669SN/A addr = addr / channels; 2499669SN/A 2509669SN/A // next, the column 2519831SN/A addr = addr / columnsPerRowBuffer; 2529669SN/A 2539669SN/A // after the column bits, we get the bank bits to interleave 2549491SN/A // over the banks 2559243SN/A bank = addr % banksPerRank; 2569243SN/A addr = addr / banksPerRank; 2579243SN/A 2589491SN/A // after the bank, we get the rank bits which thus interleaves 2599491SN/A // over the ranks 2609243SN/A rank = addr % ranksPerChannel; 2619243SN/A addr = addr / ranksPerChannel; 2629243SN/A 2639491SN/A // lastly, get the row bits 2649243SN/A row = addr % rowsPerBank; 2659243SN/A addr = addr / rowsPerBank; 26610136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 2679491SN/A // optimise for closed page mode and utilise maximum 2689491SN/A // parallelism of the DRAM (at the cost of power) 2699491SN/A 2709566SN/A // take out the channel part of the address, not that this has 2719566SN/A // to match with how accesses are interleaved between the 2729566SN/A // controllers in the address mapping 2739566SN/A addr = addr / channels; 2749566SN/A 2759491SN/A // start with the bank bits, as this provides the maximum 2769491SN/A // opportunity for parallelism between requests 2779243SN/A bank = addr % banksPerRank; 2789243SN/A addr = addr / banksPerRank; 2799243SN/A 2809491SN/A // next get the rank bits 2819243SN/A rank = addr % ranksPerChannel; 2829243SN/A addr = addr / ranksPerChannel; 2839243SN/A 2849491SN/A // next the column bits which we do not need to keep track of 2859491SN/A // and simply skip past 2869831SN/A addr = addr / columnsPerRowBuffer; 2879243SN/A 2889491SN/A // lastly, get the row bits 2899243SN/A row = addr % rowsPerBank; 2909243SN/A addr = addr / rowsPerBank; 2919243SN/A } else 2929243SN/A panic("Unknown address mapping policy chosen!"); 2939243SN/A 2949243SN/A assert(rank < ranksPerChannel); 2959243SN/A assert(bank < banksPerRank); 2969243SN/A assert(row < rowsPerBank); 2979243SN/A 2989243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 2999831SN/A dramPktAddr, rank, bank, row); 3009243SN/A 3019243SN/A // create the corresponding DRAM packet with the entry time and 3029567SN/A // ready time set to the current tick, the latter will be updated 3039567SN/A // later 3049967SN/A uint16_t bank_id = banksPerRank * rank + bank; 3059967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 3069967SN/A size, banks[rank][bank]); 3079243SN/A} 3089243SN/A 3099243SN/Avoid 31010146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 3119243SN/A{ 3129243SN/A // only add to the read queue here. whenever the request is 3139243SN/A // eventually done, set the readyTime, and call schedule() 3149243SN/A assert(!pkt->isWrite()); 3159243SN/A 3169831SN/A assert(pktCount != 0); 3179831SN/A 3189831SN/A // if the request size is larger than burst size, the pkt is split into 3199831SN/A // multiple DRAM packets 3209831SN/A // Note if the pkt starting address is not aligened to burst size, the 3219831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 3229831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 3239831SN/A // check read packets against packets in write queue. 3249243SN/A Addr addr = pkt->getAddr(); 3259831SN/A unsigned pktsServicedByWrQ = 0; 3269831SN/A BurstHelper* burst_helper = NULL; 3279831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 3289831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 3299831SN/A pkt->getAddr() + pkt->getSize()) - addr; 3309831SN/A readPktSize[ceilLog2(size)]++; 3319831SN/A readBursts++; 3329243SN/A 3339831SN/A // First check write buffer to see if the data is already at 3349831SN/A // the controller 3359831SN/A bool foundInWrQ = false; 3369833SN/A for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) { 3379832SN/A // check if the read is subsumed in the write entry we are 3389832SN/A // looking at 3399832SN/A if ((*i)->addr <= addr && 3409832SN/A (addr + size) <= ((*i)->addr + (*i)->size)) { 3419831SN/A foundInWrQ = true; 3429831SN/A servicedByWrQ++; 3439831SN/A pktsServicedByWrQ++; 3449831SN/A DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 3459831SN/A "write queue\n", addr, size); 3469975SN/A bytesReadWrQ += burstSize; 3479831SN/A break; 3489831SN/A } 3499243SN/A } 3509831SN/A 3519831SN/A // If not found in the write q, make a DRAM packet and 3529831SN/A // push it onto the read queue 3539831SN/A if (!foundInWrQ) { 3549831SN/A 3559831SN/A // Make the burst helper for split packets 3569831SN/A if (pktCount > 1 && burst_helper == NULL) { 3579831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 3589831SN/A "dram requests\n", pkt->getAddr(), pktCount); 3599831SN/A burst_helper = new BurstHelper(pktCount); 3609831SN/A } 3619831SN/A 3629966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 3639831SN/A dram_pkt->burstHelper = burst_helper; 3649831SN/A 3659831SN/A assert(!readQueueFull(1)); 3669831SN/A rdQLenPdf[readQueue.size() + respQueue.size()]++; 3679831SN/A 3689831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 3699831SN/A 3709831SN/A readQueue.push_back(dram_pkt); 3719831SN/A 3729831SN/A // Update stats 3739831SN/A avgRdQLen = readQueue.size() + respQueue.size(); 3749831SN/A } 3759831SN/A 3769831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 3779831SN/A addr = (addr | (burstSize - 1)) + 1; 3789243SN/A } 3799243SN/A 3809831SN/A // If all packets are serviced by write queue, we send the repsonse back 3819831SN/A if (pktsServicedByWrQ == pktCount) { 3829831SN/A accessAndRespond(pkt, frontendLatency); 3839831SN/A return; 3849831SN/A } 3859243SN/A 3869831SN/A // Update how many split packets are serviced by write queue 3879831SN/A if (burst_helper != NULL) 3889831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 3899243SN/A 39010206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 39110206Sandreas.hansson@arm.com // queue, do so now 39210206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 3939567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 3949567SN/A schedule(nextReqEvent, curTick()); 3959243SN/A } 3969243SN/A} 3979243SN/A 3989243SN/Avoid 39910146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 4009243SN/A{ 4019243SN/A // only add to the write queue here. whenever the request is 4029243SN/A // eventually done, set the readyTime, and call schedule() 4039243SN/A assert(pkt->isWrite()); 4049243SN/A 4059831SN/A // if the request size is larger than burst size, the pkt is split into 4069831SN/A // multiple DRAM packets 4079831SN/A Addr addr = pkt->getAddr(); 4089831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4099831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4109831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4119831SN/A writePktSize[ceilLog2(size)]++; 4129831SN/A writeBursts++; 4139243SN/A 4149832SN/A // see if we can merge with an existing item in the write 4159838SN/A // queue and keep track of whether we have merged or not so we 4169838SN/A // can stop at that point and also avoid enqueueing a new 4179838SN/A // request 4189832SN/A bool merged = false; 4199832SN/A auto w = writeQueue.begin(); 4209243SN/A 4219832SN/A while(!merged && w != writeQueue.end()) { 4229832SN/A // either of the two could be first, if they are the same 4239832SN/A // it does not matter which way we go 4249832SN/A if ((*w)->addr >= addr) { 4259838SN/A // the existing one starts after the new one, figure 4269838SN/A // out where the new one ends with respect to the 4279838SN/A // existing one 4289832SN/A if ((addr + size) >= ((*w)->addr + (*w)->size)) { 4299832SN/A // check if the existing one is completely 4309832SN/A // subsumed in the new one 4319832SN/A DPRINTF(DRAM, "Merging write covering existing burst\n"); 4329832SN/A merged = true; 4339832SN/A // update both the address and the size 4349832SN/A (*w)->addr = addr; 4359832SN/A (*w)->size = size; 4369832SN/A } else if ((addr + size) >= (*w)->addr && 4379832SN/A ((*w)->addr + (*w)->size - addr) <= burstSize) { 4389832SN/A // the new one is just before or partially 4399832SN/A // overlapping with the existing one, and together 4409832SN/A // they fit within a burst 4419832SN/A DPRINTF(DRAM, "Merging write before existing burst\n"); 4429832SN/A merged = true; 4439832SN/A // the existing queue item needs to be adjusted with 4449832SN/A // respect to both address and size 44510047SN/A (*w)->size = (*w)->addr + (*w)->size - addr; 4469832SN/A (*w)->addr = addr; 4479832SN/A } 4489832SN/A } else { 4499838SN/A // the new one starts after the current one, figure 4509838SN/A // out where the existing one ends with respect to the 4519838SN/A // new one 4529832SN/A if (((*w)->addr + (*w)->size) >= (addr + size)) { 4539832SN/A // check if the new one is completely subsumed in the 4549832SN/A // existing one 4559832SN/A DPRINTF(DRAM, "Merging write into existing burst\n"); 4569832SN/A merged = true; 4579832SN/A // no adjustments necessary 4589832SN/A } else if (((*w)->addr + (*w)->size) >= addr && 4599832SN/A (addr + size - (*w)->addr) <= burstSize) { 4609832SN/A // the existing one is just before or partially 4619832SN/A // overlapping with the new one, and together 4629832SN/A // they fit within a burst 4639832SN/A DPRINTF(DRAM, "Merging write after existing burst\n"); 4649832SN/A merged = true; 4659832SN/A // the address is right, and only the size has 4669832SN/A // to be adjusted 4679832SN/A (*w)->size = addr + size - (*w)->addr; 4689832SN/A } 4699832SN/A } 4709832SN/A ++w; 4719832SN/A } 4729243SN/A 4739832SN/A // if the item was not merged we need to create a new write 4749832SN/A // and enqueue it 4759832SN/A if (!merged) { 4769966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 4779243SN/A 4789832SN/A assert(writeQueue.size() < writeBufferSize); 4799832SN/A wrQLenPdf[writeQueue.size()]++; 4809243SN/A 4819832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 4829831SN/A 4839832SN/A writeQueue.push_back(dram_pkt); 4849831SN/A 4859832SN/A // Update stats 4869832SN/A avgWrQLen = writeQueue.size(); 4879977SN/A } else { 4889977SN/A // keep track of the fact that this burst effectively 4899977SN/A // disappeared as it was merged with an existing one 4909977SN/A mergedWrBursts++; 4919832SN/A } 4929832SN/A 4939831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 4949831SN/A addr = (addr | (burstSize - 1)) + 1; 4959831SN/A } 4969243SN/A 4979243SN/A // we do not wait for the writes to be send to the actual memory, 4989243SN/A // but instead take responsibility for the consistency here and 4999243SN/A // snoop the write queue for any upcoming reads 5009831SN/A // @todo, if a pkt size is larger than burst size, we might need a 5019831SN/A // different front end latency 5029726SN/A accessAndRespond(pkt, frontendLatency); 5039243SN/A 50410206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 50510206Sandreas.hansson@arm.com // queue, do so now 50610206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 50710206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 50810206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 5099243SN/A } 5109243SN/A} 5119243SN/A 5129243SN/Avoid 51310146Sandreas.hansson@arm.comDRAMCtrl::printQs() const { 5149243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 5159833SN/A for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 5169243SN/A DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 5179243SN/A } 5189243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 5199833SN/A for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 5209243SN/A DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 5219243SN/A } 5229243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 5239833SN/A for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 5249243SN/A DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 5259243SN/A } 5269243SN/A} 5279243SN/A 5289243SN/Abool 52910146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 5309243SN/A{ 5319349SN/A /// @todo temporary hack to deal with memory corruption issues until 5329349SN/A /// 4-phase transactions are complete 5339349SN/A for (int x = 0; x < pendingDelete.size(); x++) 5349349SN/A delete pendingDelete[x]; 5359349SN/A pendingDelete.clear(); 5369349SN/A 5379243SN/A // This is where we enter from the outside world 5389567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 5399831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 5409243SN/A 5419567SN/A // simply drop inhibited packets for now 5429567SN/A if (pkt->memInhibitAsserted()) { 54310143SN/A DPRINTF(DRAM, "Inhibited packet -- Dropping it now\n"); 5449567SN/A pendingDelete.push_back(pkt); 5459567SN/A return true; 5469567SN/A } 5479243SN/A 5489243SN/A // Calc avg gap between requests 5499243SN/A if (prevArrival != 0) { 5509243SN/A totGap += curTick() - prevArrival; 5519243SN/A } 5529243SN/A prevArrival = curTick(); 5539243SN/A 5549831SN/A 5559831SN/A // Find out how many dram packets a pkt translates to 5569831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 5579831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 5589831SN/A // multiple dram packets 5599243SN/A unsigned size = pkt->getSize(); 5609831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 5619831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 5629243SN/A 5639243SN/A // check local buffers and do not accept if full 5649243SN/A if (pkt->isRead()) { 5659567SN/A assert(size != 0); 5669831SN/A if (readQueueFull(dram_pkt_count)) { 5679567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 5689243SN/A // remember that we have to retry this port 5699243SN/A retryRdReq = true; 5709243SN/A numRdRetry++; 5719243SN/A return false; 5729243SN/A } else { 5739831SN/A addToReadQueue(pkt, dram_pkt_count); 5749243SN/A readReqs++; 5759977SN/A bytesReadSys += size; 5769243SN/A } 5779243SN/A } else if (pkt->isWrite()) { 5789567SN/A assert(size != 0); 5799831SN/A if (writeQueueFull(dram_pkt_count)) { 5809567SN/A DPRINTF(DRAM, "Write queue full, not accepting\n"); 5819243SN/A // remember that we have to retry this port 5829243SN/A retryWrReq = true; 5839243SN/A numWrRetry++; 5849243SN/A return false; 5859243SN/A } else { 5869831SN/A addToWriteQueue(pkt, dram_pkt_count); 5879243SN/A writeReqs++; 5889977SN/A bytesWrittenSys += size; 5899243SN/A } 5909243SN/A } else { 5919243SN/A DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 5929243SN/A neitherReadNorWrite++; 5939726SN/A accessAndRespond(pkt, 1); 5949243SN/A } 5959243SN/A 5969243SN/A return true; 5979243SN/A} 5989243SN/A 5999243SN/Avoid 60010146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 6019243SN/A{ 6029243SN/A DPRINTF(DRAM, 6039243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 6049243SN/A 6059831SN/A DRAMPacket* dram_pkt = respQueue.front(); 6069243SN/A 6079831SN/A if (dram_pkt->burstHelper) { 6089831SN/A // it is a split packet 6099831SN/A dram_pkt->burstHelper->burstsServiced++; 6109831SN/A if (dram_pkt->burstHelper->burstsServiced == 61110143SN/A dram_pkt->burstHelper->burstCount) { 6129831SN/A // we have now serviced all children packets of a system packet 6139831SN/A // so we can now respond to the requester 6149831SN/A // @todo we probably want to have a different front end and back 6159831SN/A // end latency for split packets 6169831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6179831SN/A delete dram_pkt->burstHelper; 6189831SN/A dram_pkt->burstHelper = NULL; 6199831SN/A } 6209831SN/A } else { 6219831SN/A // it is not a split packet 6229831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6239831SN/A } 6249243SN/A 6259831SN/A delete respQueue.front(); 6269831SN/A respQueue.pop_front(); 6279243SN/A 6289831SN/A if (!respQueue.empty()) { 6299831SN/A assert(respQueue.front()->readyTime >= curTick()); 6309831SN/A assert(!respondEvent.scheduled()); 6319831SN/A schedule(respondEvent, respQueue.front()->readyTime); 6329831SN/A } else { 6339831SN/A // if there is nothing left in any queue, signal a drain 6349831SN/A if (writeQueue.empty() && readQueue.empty() && 6359831SN/A drainManager) { 6369831SN/A drainManager->signalDrainDone(); 6379831SN/A drainManager = NULL; 6389831SN/A } 6399831SN/A } 6409567SN/A 6419831SN/A // We have made a location in the queue available at this point, 6429831SN/A // so if there is a read that was forced to wait, retry now 6439831SN/A if (retryRdReq) { 6449831SN/A retryRdReq = false; 6459831SN/A port.sendRetry(); 6469831SN/A } 6479243SN/A} 6489243SN/A 6499243SN/Avoid 65010206Sandreas.hansson@arm.comDRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue) 6519243SN/A{ 65210206Sandreas.hansson@arm.com // This method does the arbitration between requests. The chosen 65310206Sandreas.hansson@arm.com // packet is simply moved to the head of the queue. The other 65410206Sandreas.hansson@arm.com // methods know that this is the place to look. For example, with 65510206Sandreas.hansson@arm.com // FCFS, this method does nothing 65610206Sandreas.hansson@arm.com assert(!queue.empty()); 6579243SN/A 65810206Sandreas.hansson@arm.com if (queue.size() == 1) { 65910206Sandreas.hansson@arm.com DPRINTF(DRAM, "Single request, nothing to do\n"); 6609243SN/A return; 6619243SN/A } 6629243SN/A 6639243SN/A if (memSchedPolicy == Enums::fcfs) { 6649243SN/A // Do nothing, since the correct request is already head 6659243SN/A } else if (memSchedPolicy == Enums::frfcfs) { 66610206Sandreas.hansson@arm.com reorderQueue(queue); 6679243SN/A } else 6689243SN/A panic("No scheduling policy chosen\n"); 6699243SN/A} 6709243SN/A 6719243SN/Avoid 67210146Sandreas.hansson@arm.comDRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue) 6739974SN/A{ 6749974SN/A // Only determine this when needed 6759974SN/A uint64_t earliest_banks = 0; 6769974SN/A 6779974SN/A // Search for row hits first, if no row hit is found then schedule the 6789974SN/A // packet to one of the earliest banks available 6799974SN/A bool found_earliest_pkt = false; 6809974SN/A auto selected_pkt_it = queue.begin(); 6819974SN/A 6829974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 6839974SN/A DRAMPacket* dram_pkt = *i; 6849974SN/A const Bank& bank = dram_pkt->bankRef; 6859974SN/A // Check if it is a row hit 6869974SN/A if (bank.openRow == dram_pkt->row) { 68710211Sandreas.hansson@arm.com // FCFS within the hits 6889974SN/A DPRINTF(DRAM, "Row buffer hit\n"); 6899974SN/A selected_pkt_it = i; 6909974SN/A break; 6919974SN/A } else if (!found_earliest_pkt) { 6929974SN/A // No row hit, go for first ready 6939974SN/A if (earliest_banks == 0) 69410211Sandreas.hansson@arm.com earliest_banks = minBankActAt(queue); 69510211Sandreas.hansson@arm.com 69610211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue an 69710211Sandreas.hansson@arm.com // activate, this is calculated in minBankActAt and could 69810211Sandreas.hansson@arm.com // be cached 69910211Sandreas.hansson@arm.com Tick act_at = bank.openRow == Bank::NO_ROW ? 70010211Sandreas.hansson@arm.com bank.actAllowedAt : 70110211Sandreas.hansson@arm.com std::max(bank.preAllowedAt, curTick()) + tRP; 7029974SN/A 7039974SN/A // Bank is ready or is the first available bank 70410211Sandreas.hansson@arm.com if (act_at <= curTick() || 7059974SN/A bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) { 7069974SN/A // Remember the packet to be scheduled to one of the earliest 70710211Sandreas.hansson@arm.com // banks available, FCFS amongst the earliest banks 7089974SN/A selected_pkt_it = i; 7099974SN/A found_earliest_pkt = true; 7109974SN/A } 7119974SN/A } 7129974SN/A } 7139974SN/A 7149974SN/A DRAMPacket* selected_pkt = *selected_pkt_it; 7159974SN/A queue.erase(selected_pkt_it); 7169974SN/A queue.push_front(selected_pkt); 7179974SN/A} 7189974SN/A 7199974SN/Avoid 72010146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 7219243SN/A{ 7229243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 7239243SN/A 7249243SN/A bool needsResponse = pkt->needsResponse(); 7259243SN/A // do the actual memory access which also turns the packet into a 7269243SN/A // response 7279243SN/A access(pkt); 7289243SN/A 7299243SN/A // turn packet around to go back to requester if response expected 7309243SN/A if (needsResponse) { 7319243SN/A // access already turned the packet into a response 7329243SN/A assert(pkt->isResponse()); 7339243SN/A 7349549SN/A // @todo someone should pay for this 7359549SN/A pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; 7369549SN/A 7379726SN/A // queue the packet in the response queue to be sent out after 7389726SN/A // the static latency has passed 7399726SN/A port.schedTimingResp(pkt, curTick() + static_latency); 7409243SN/A } else { 7419587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 7429587SN/A // is still having a pointer to it 7439587SN/A pendingDelete.push_back(pkt); 7449243SN/A } 7459243SN/A 7469243SN/A DPRINTF(DRAM, "Done\n"); 7479243SN/A 7489243SN/A return; 7499243SN/A} 7509243SN/A 7519243SN/Avoid 75210210Sandreas.hansson@arm.comDRAMCtrl::activateBank(Tick act_tick, uint8_t rank, uint8_t bank, 75310210Sandreas.hansson@arm.com uint16_t row, Bank& bank_ref) 7549488SN/A{ 7559969SN/A assert(0 <= rank && rank < ranksPerChannel); 7569969SN/A assert(actTicks[rank].size() == activationLimit); 7579488SN/A 7589488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 7599488SN/A 76010207Sandreas.hansson@arm.com // update the open row 76110210Sandreas.hansson@arm.com assert(bank_ref.openRow == Bank::NO_ROW); 76210210Sandreas.hansson@arm.com bank_ref.openRow = row; 76310207Sandreas.hansson@arm.com 76410207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 76510207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 76610207Sandreas.hansson@arm.com // precharge 76710210Sandreas.hansson@arm.com bank_ref.bytesAccessed = 0; 76810210Sandreas.hansson@arm.com bank_ref.rowAccesses = 0; 76910207Sandreas.hansson@arm.com 77010207Sandreas.hansson@arm.com ++numBanksActive; 77110207Sandreas.hansson@arm.com assert(numBanksActive <= banksPerRank * ranksPerChannel); 77210207Sandreas.hansson@arm.com 77310207Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank at tick %lld, now got %d active\n", 77410207Sandreas.hansson@arm.com act_tick, numBanksActive); 7759975SN/A 77610211Sandreas.hansson@arm.com // The next access has to respect tRAS for this bank 77710211Sandreas.hansson@arm.com bank_ref.preAllowedAt = act_tick + tRAS; 77810211Sandreas.hansson@arm.com 77910211Sandreas.hansson@arm.com // Respect the row-to-column command delay 78010211Sandreas.hansson@arm.com bank_ref.colAllowedAt = act_tick + tRCD; 78110211Sandreas.hansson@arm.com 7829971SN/A // start by enforcing tRRD 7839971SN/A for(int i = 0; i < banksPerRank; i++) { 78410210Sandreas.hansson@arm.com // next activate to any bank in this rank must not happen 78510210Sandreas.hansson@arm.com // before tRRD 78610210Sandreas.hansson@arm.com banks[rank][i].actAllowedAt = std::max(act_tick + tRRD, 78710210Sandreas.hansson@arm.com banks[rank][i].actAllowedAt); 7889971SN/A } 78910208Sandreas.hansson@arm.com 7909971SN/A // next, we deal with tXAW, if the activation limit is disabled 7919971SN/A // then we are done 7929969SN/A if (actTicks[rank].empty()) 7939824SN/A return; 7949824SN/A 7959488SN/A // sanity check 7969969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 79710210Sandreas.hansson@arm.com panic("Got %d activates in window %d (%llu - %llu) which is smaller " 79810210Sandreas.hansson@arm.com "than %llu\n", activationLimit, act_tick - actTicks[rank].back(), 79910210Sandreas.hansson@arm.com act_tick, actTicks[rank].back(), tXAW); 8009488SN/A } 8019488SN/A 8029488SN/A // shift the times used for the book keeping, the last element 8039488SN/A // (highest index) is the oldest one and hence the lowest value 8049969SN/A actTicks[rank].pop_back(); 8059488SN/A 8069488SN/A // record an new activation (in the future) 8079969SN/A actTicks[rank].push_front(act_tick); 8089488SN/A 8099488SN/A // cannot activate more than X times in time window tXAW, push the 8109488SN/A // next one (the X + 1'st activate) to be tXAW away from the 8119488SN/A // oldest in our window of X 8129969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 8139488SN/A DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate no earlier " 81410210Sandreas.hansson@arm.com "than %llu\n", activationLimit, actTicks[rank].back() + tXAW); 8159488SN/A for(int j = 0; j < banksPerRank; j++) 8169488SN/A // next activate must not happen before end of window 81710210Sandreas.hansson@arm.com banks[rank][j].actAllowedAt = 81810210Sandreas.hansson@arm.com std::max(actTicks[rank].back() + tXAW, 81910210Sandreas.hansson@arm.com banks[rank][j].actAllowedAt); 8209488SN/A } 82110208Sandreas.hansson@arm.com 82210208Sandreas.hansson@arm.com // at the point when this activate takes place, make sure we 82310208Sandreas.hansson@arm.com // transition to the active power state 82410208Sandreas.hansson@arm.com if (!activateEvent.scheduled()) 82510208Sandreas.hansson@arm.com schedule(activateEvent, act_tick); 82610208Sandreas.hansson@arm.com else if (activateEvent.when() > act_tick) 82710208Sandreas.hansson@arm.com // move it sooner in time 82810208Sandreas.hansson@arm.com reschedule(activateEvent, act_tick); 82910208Sandreas.hansson@arm.com} 83010208Sandreas.hansson@arm.com 83110208Sandreas.hansson@arm.comvoid 83210208Sandreas.hansson@arm.comDRAMCtrl::processActivateEvent() 83310208Sandreas.hansson@arm.com{ 83410208Sandreas.hansson@arm.com // we should transition to the active state as soon as any bank is active 83510208Sandreas.hansson@arm.com if (pwrState != PWR_ACT) 83610208Sandreas.hansson@arm.com // note that at this point numBanksActive could be back at 83710208Sandreas.hansson@arm.com // zero again due to a precharge scheduled in the future 83810208Sandreas.hansson@arm.com schedulePowerEvent(PWR_ACT, curTick()); 8399488SN/A} 8409488SN/A 8419488SN/Avoid 84210211Sandreas.hansson@arm.comDRAMCtrl::prechargeBank(Bank& bank, Tick pre_at) 84310207Sandreas.hansson@arm.com{ 84410207Sandreas.hansson@arm.com // make sure the bank has an open row 84510207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 84610207Sandreas.hansson@arm.com 84710207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 84810207Sandreas.hansson@arm.com // the page 84910207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 85010207Sandreas.hansson@arm.com 85110207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 85210207Sandreas.hansson@arm.com 85310214Sandreas.hansson@arm.com // no precharge allowed before this one 85410214Sandreas.hansson@arm.com bank.preAllowedAt = pre_at; 85510214Sandreas.hansson@arm.com 85610211Sandreas.hansson@arm.com Tick pre_done_at = pre_at + tRP; 85710211Sandreas.hansson@arm.com 85810211Sandreas.hansson@arm.com bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at); 85910207Sandreas.hansson@arm.com 86010207Sandreas.hansson@arm.com assert(numBanksActive != 0); 86110207Sandreas.hansson@arm.com --numBanksActive; 86210207Sandreas.hansson@arm.com 86310211Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging bank at tick %lld, now got %d active\n", 86410211Sandreas.hansson@arm.com pre_at, numBanksActive); 86510207Sandreas.hansson@arm.com 86610208Sandreas.hansson@arm.com // if we look at the current number of active banks we might be 86710208Sandreas.hansson@arm.com // tempted to think the DRAM is now idle, however this can be 86810208Sandreas.hansson@arm.com // undone by an activate that is scheduled to happen before we 86910208Sandreas.hansson@arm.com // would have reached the idle state, so schedule an event and 87010208Sandreas.hansson@arm.com // rather check once we actually make it to the point in time when 87110208Sandreas.hansson@arm.com // the (last) precharge takes place 87210208Sandreas.hansson@arm.com if (!prechargeEvent.scheduled()) 87310211Sandreas.hansson@arm.com schedule(prechargeEvent, pre_done_at); 87410211Sandreas.hansson@arm.com else if (prechargeEvent.when() < pre_done_at) 87510211Sandreas.hansson@arm.com reschedule(prechargeEvent, pre_done_at); 87610208Sandreas.hansson@arm.com} 87710208Sandreas.hansson@arm.com 87810208Sandreas.hansson@arm.comvoid 87910208Sandreas.hansson@arm.comDRAMCtrl::processPrechargeEvent() 88010208Sandreas.hansson@arm.com{ 88110207Sandreas.hansson@arm.com // if we reached zero, then special conditions apply as we track 88210207Sandreas.hansson@arm.com // if all banks are precharged for the power models 88310207Sandreas.hansson@arm.com if (numBanksActive == 0) { 88410208Sandreas.hansson@arm.com // we should transition to the idle state when the last bank 88510208Sandreas.hansson@arm.com // is precharged 88610208Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 88710207Sandreas.hansson@arm.com } 88810207Sandreas.hansson@arm.com} 88910207Sandreas.hansson@arm.com 89010207Sandreas.hansson@arm.comvoid 89110146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 8929243SN/A{ 8939243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 8949243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 8959243SN/A 89610211Sandreas.hansson@arm.com // get the bank 8979967SN/A Bank& bank = dram_pkt->bankRef; 8989243SN/A 89910211Sandreas.hansson@arm.com // for the state we need to track if it is a row hit or not 90010211Sandreas.hansson@arm.com bool row_hit = true; 90110211Sandreas.hansson@arm.com 90210211Sandreas.hansson@arm.com // respect any constraints on the command (e.g. tRCD or tCCD) 90310211Sandreas.hansson@arm.com Tick cmd_at = std::max(bank.colAllowedAt, curTick()); 90410211Sandreas.hansson@arm.com 90510211Sandreas.hansson@arm.com // Determine the access latency and update the bank state 90610211Sandreas.hansson@arm.com if (bank.openRow == dram_pkt->row) { 90710211Sandreas.hansson@arm.com // nothing to do 90810209Sandreas.hansson@arm.com } else { 90910211Sandreas.hansson@arm.com row_hit = false; 91010211Sandreas.hansson@arm.com 91110209Sandreas.hansson@arm.com // If there is a page open, precharge it. 91210209Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 91310211Sandreas.hansson@arm.com prechargeBank(bank, std::max(bank.preAllowedAt, curTick())); 9149488SN/A } 9159973SN/A 91610211Sandreas.hansson@arm.com // next we need to account for the delay in activating the 91710211Sandreas.hansson@arm.com // page 91810211Sandreas.hansson@arm.com Tick act_tick = std::max(bank.actAllowedAt, curTick()); 9199973SN/A 92010210Sandreas.hansson@arm.com // Record the activation and deal with all the global timing 92110210Sandreas.hansson@arm.com // constraints caused be a new activation (tRRD and tXAW) 92210211Sandreas.hansson@arm.com activateBank(act_tick, dram_pkt->rank, dram_pkt->bank, 92310210Sandreas.hansson@arm.com dram_pkt->row, bank); 92410210Sandreas.hansson@arm.com 92510211Sandreas.hansson@arm.com // issue the command as early as possible 92610211Sandreas.hansson@arm.com cmd_at = bank.colAllowedAt; 92710209Sandreas.hansson@arm.com } 92810209Sandreas.hansson@arm.com 92910211Sandreas.hansson@arm.com // we need to wait until the bus is available before we can issue 93010211Sandreas.hansson@arm.com // the command 93110211Sandreas.hansson@arm.com cmd_at = std::max(cmd_at, busBusyUntil - tCL); 93210211Sandreas.hansson@arm.com 93310211Sandreas.hansson@arm.com // update the packet ready time 93410211Sandreas.hansson@arm.com dram_pkt->readyTime = cmd_at + tCL + tBURST; 93510211Sandreas.hansson@arm.com 93610211Sandreas.hansson@arm.com // only one burst can use the bus at any one point in time 93710211Sandreas.hansson@arm.com assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 93810211Sandreas.hansson@arm.com 93910211Sandreas.hansson@arm.com // not strictly necessary, but update the time for the next 94010211Sandreas.hansson@arm.com // read/write (add a max with tCCD here) 94110211Sandreas.hansson@arm.com bank.colAllowedAt = cmd_at + tBURST; 94210211Sandreas.hansson@arm.com 94310212Sandreas.hansson@arm.com // If this is a write, we also need to respect the write recovery 94410212Sandreas.hansson@arm.com // time before a precharge, in the case of a read, respect the 94510212Sandreas.hansson@arm.com // read to precharge constraint 94610212Sandreas.hansson@arm.com bank.preAllowedAt = std::max(bank.preAllowedAt, 94710212Sandreas.hansson@arm.com dram_pkt->isRead ? cmd_at + tRTP : 94810212Sandreas.hansson@arm.com dram_pkt->readyTime + tWR); 94910210Sandreas.hansson@arm.com 95010209Sandreas.hansson@arm.com // increment the bytes accessed and the accesses per row 95110209Sandreas.hansson@arm.com bank.bytesAccessed += burstSize; 95210209Sandreas.hansson@arm.com ++bank.rowAccesses; 95310209Sandreas.hansson@arm.com 95410209Sandreas.hansson@arm.com // if we reached the max, then issue with an auto-precharge 95510209Sandreas.hansson@arm.com bool auto_precharge = pageMgmt == Enums::close || 95610209Sandreas.hansson@arm.com bank.rowAccesses == maxAccessesPerRow; 95710209Sandreas.hansson@arm.com 95810209Sandreas.hansson@arm.com // if we did not hit the limit, we might still want to 95910209Sandreas.hansson@arm.com // auto-precharge 96010209Sandreas.hansson@arm.com if (!auto_precharge && 96110209Sandreas.hansson@arm.com (pageMgmt == Enums::open_adaptive || 96210209Sandreas.hansson@arm.com pageMgmt == Enums::close_adaptive)) { 96310209Sandreas.hansson@arm.com // a twist on the open and close page policies: 96410209Sandreas.hansson@arm.com // 1) open_adaptive page policy does not blindly keep the 96510209Sandreas.hansson@arm.com // page open, but close it if there are no row hits, and there 96610209Sandreas.hansson@arm.com // are bank conflicts in the queue 96710209Sandreas.hansson@arm.com // 2) close_adaptive page policy does not blindly close the 96810209Sandreas.hansson@arm.com // page, but closes it only if there are no row hits in the queue. 96910209Sandreas.hansson@arm.com // In this case, only force an auto precharge when there 97010209Sandreas.hansson@arm.com // are no same page hits in the queue 97110209Sandreas.hansson@arm.com bool got_more_hits = false; 97210209Sandreas.hansson@arm.com bool got_bank_conflict = false; 97310209Sandreas.hansson@arm.com 97410209Sandreas.hansson@arm.com // either look at the read queue or write queue 97510209Sandreas.hansson@arm.com const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 97610209Sandreas.hansson@arm.com writeQueue; 97710209Sandreas.hansson@arm.com auto p = queue.begin(); 97810209Sandreas.hansson@arm.com // make sure we are not considering the packet that we are 97910209Sandreas.hansson@arm.com // currently dealing with (which is the head of the queue) 98010209Sandreas.hansson@arm.com ++p; 98110209Sandreas.hansson@arm.com 98210209Sandreas.hansson@arm.com // keep on looking until we have found required condition or 98310209Sandreas.hansson@arm.com // reached the end 98410209Sandreas.hansson@arm.com while (!(got_more_hits && 98510209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive)) && 98610209Sandreas.hansson@arm.com p != queue.end()) { 98710209Sandreas.hansson@arm.com bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 98810209Sandreas.hansson@arm.com (dram_pkt->bank == (*p)->bank); 98910209Sandreas.hansson@arm.com bool same_row = dram_pkt->row == (*p)->row; 99010209Sandreas.hansson@arm.com got_more_hits |= same_rank_bank && same_row; 99110209Sandreas.hansson@arm.com got_bank_conflict |= same_rank_bank && !same_row; 9929973SN/A ++p; 99310141SN/A } 99410141SN/A 99510209Sandreas.hansson@arm.com // auto pre-charge when either 99610209Sandreas.hansson@arm.com // 1) open_adaptive policy, we have not got any more hits, and 99710209Sandreas.hansson@arm.com // have a bank conflict 99810209Sandreas.hansson@arm.com // 2) close_adaptive policy and we have not got any more hits 99910209Sandreas.hansson@arm.com auto_precharge = !got_more_hits && 100010209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive); 100110209Sandreas.hansson@arm.com } 100210142SN/A 100310209Sandreas.hansson@arm.com // if this access should use auto-precharge, then we are 100410209Sandreas.hansson@arm.com // closing the row 100510209Sandreas.hansson@arm.com if (auto_precharge) { 100610211Sandreas.hansson@arm.com prechargeBank(bank, std::max(curTick(), bank.preAllowedAt)); 10079973SN/A 100810209Sandreas.hansson@arm.com DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 100910209Sandreas.hansson@arm.com } 10109963SN/A 10119243SN/A // Update bus state 10129243SN/A busBusyUntil = dram_pkt->readyTime; 10139243SN/A 101410211Sandreas.hansson@arm.com DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n", 101510211Sandreas.hansson@arm.com dram_pkt->addr, dram_pkt->readyTime, busBusyUntil); 10169243SN/A 101710206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 101810206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 101910206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 102010206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 102110206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 10229972SN/A 102310206Sandreas.hansson@arm.com // Update the stats and schedule the next request 10249977SN/A if (dram_pkt->isRead) { 102510147Sandreas.hansson@arm.com ++readsThisTime; 102610211Sandreas.hansson@arm.com if (row_hit) 10279977SN/A readRowHits++; 10289977SN/A bytesReadDRAM += burstSize; 10299977SN/A perBankRdBursts[dram_pkt->bankId]++; 103010206Sandreas.hansson@arm.com 103110206Sandreas.hansson@arm.com // Update latency stats 103210206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 103310206Sandreas.hansson@arm.com totBusLat += tBURST; 103410211Sandreas.hansson@arm.com totQLat += cmd_at - dram_pkt->entryTime; 10359977SN/A } else { 103610147Sandreas.hansson@arm.com ++writesThisTime; 103710211Sandreas.hansson@arm.com if (row_hit) 10389977SN/A writeRowHits++; 10399977SN/A bytesWritten += burstSize; 10409977SN/A perBankWrBursts[dram_pkt->bankId]++; 10419243SN/A } 10429243SN/A} 10439243SN/A 10449243SN/Avoid 104510206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 10469243SN/A{ 104710206Sandreas.hansson@arm.com if (busState == READ_TO_WRITE) { 104810206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 104910206Sandreas.hansson@arm.com "waiting\n", readsThisTime, readQueue.size()); 10509243SN/A 105110206Sandreas.hansson@arm.com // sample and reset the read-related stats as we are now 105210206Sandreas.hansson@arm.com // transitioning to writes, and all reads are done 105310206Sandreas.hansson@arm.com rdPerTurnAround.sample(readsThisTime); 105410206Sandreas.hansson@arm.com readsThisTime = 0; 105510206Sandreas.hansson@arm.com 105610206Sandreas.hansson@arm.com // now proceed to do the actual writes 105710206Sandreas.hansson@arm.com busState = WRITE; 105810206Sandreas.hansson@arm.com } else if (busState == WRITE_TO_READ) { 105910206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 106010206Sandreas.hansson@arm.com "waiting\n", writesThisTime, writeQueue.size()); 106110206Sandreas.hansson@arm.com 106210206Sandreas.hansson@arm.com wrPerTurnAround.sample(writesThisTime); 106310206Sandreas.hansson@arm.com writesThisTime = 0; 106410206Sandreas.hansson@arm.com 106510206Sandreas.hansson@arm.com busState = READ; 106610206Sandreas.hansson@arm.com } 106710206Sandreas.hansson@arm.com 106810207Sandreas.hansson@arm.com if (refreshState != REF_IDLE) { 106910207Sandreas.hansson@arm.com // if a refresh waiting for this event loop to finish, then hand 107010207Sandreas.hansson@arm.com // over now, and do not schedule a new nextReqEvent 107110207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 107210207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 107310207Sandreas.hansson@arm.com 107410207Sandreas.hansson@arm.com refreshState = REF_PRE; 107510207Sandreas.hansson@arm.com 107610207Sandreas.hansson@arm.com // hand control back to the refresh event loop 107710207Sandreas.hansson@arm.com schedule(refreshEvent, curTick()); 107810207Sandreas.hansson@arm.com } 107910207Sandreas.hansson@arm.com 108010207Sandreas.hansson@arm.com // let the refresh finish before issuing any further requests 108110207Sandreas.hansson@arm.com return; 108210207Sandreas.hansson@arm.com } 108310207Sandreas.hansson@arm.com 108410206Sandreas.hansson@arm.com // when we get here it is either a read or a write 108510206Sandreas.hansson@arm.com if (busState == READ) { 108610206Sandreas.hansson@arm.com 108710206Sandreas.hansson@arm.com // track if we should switch or not 108810206Sandreas.hansson@arm.com bool switch_to_writes = false; 108910206Sandreas.hansson@arm.com 109010206Sandreas.hansson@arm.com if (readQueue.empty()) { 109110206Sandreas.hansson@arm.com // In the case there is no read request to go next, 109210206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 109310206Sandreas.hansson@arm.com // if we are draining) 109410206Sandreas.hansson@arm.com if (!writeQueue.empty() && 109510206Sandreas.hansson@arm.com (drainManager || writeQueue.size() > writeLowThreshold)) { 109610206Sandreas.hansson@arm.com 109710206Sandreas.hansson@arm.com switch_to_writes = true; 109810206Sandreas.hansson@arm.com } else { 109910206Sandreas.hansson@arm.com // check if we are drained 110010206Sandreas.hansson@arm.com if (respQueue.empty () && drainManager) { 110110206Sandreas.hansson@arm.com drainManager->signalDrainDone(); 110210206Sandreas.hansson@arm.com drainManager = NULL; 110310206Sandreas.hansson@arm.com } 110410206Sandreas.hansson@arm.com 110510206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 110610206Sandreas.hansson@arm.com // event for the next request 110710206Sandreas.hansson@arm.com return; 110810206Sandreas.hansson@arm.com } 110910206Sandreas.hansson@arm.com } else { 111010206Sandreas.hansson@arm.com // Figure out which read request goes next, and move it to the 111110206Sandreas.hansson@arm.com // front of the read queue 111210206Sandreas.hansson@arm.com chooseNext(readQueue); 111310206Sandreas.hansson@arm.com 111410215Sandreas.hansson@arm.com DRAMPacket* dram_pkt = readQueue.front(); 111510215Sandreas.hansson@arm.com 111610215Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 111710206Sandreas.hansson@arm.com 111810206Sandreas.hansson@arm.com // At this point we're done dealing with the request 111910215Sandreas.hansson@arm.com readQueue.pop_front(); 112010215Sandreas.hansson@arm.com 112110215Sandreas.hansson@arm.com // sanity check 112210215Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 112310215Sandreas.hansson@arm.com assert(dram_pkt->readyTime >= curTick()); 112410215Sandreas.hansson@arm.com 112510215Sandreas.hansson@arm.com // Insert into response queue. It will be sent back to the 112610215Sandreas.hansson@arm.com // requestor at its readyTime 112710215Sandreas.hansson@arm.com if (respQueue.empty()) { 112810215Sandreas.hansson@arm.com assert(!respondEvent.scheduled()); 112910215Sandreas.hansson@arm.com schedule(respondEvent, dram_pkt->readyTime); 113010215Sandreas.hansson@arm.com } else { 113110215Sandreas.hansson@arm.com assert(respQueue.back()->readyTime <= dram_pkt->readyTime); 113210215Sandreas.hansson@arm.com assert(respondEvent.scheduled()); 113310215Sandreas.hansson@arm.com } 113410215Sandreas.hansson@arm.com 113510215Sandreas.hansson@arm.com respQueue.push_back(dram_pkt); 113610206Sandreas.hansson@arm.com 113710206Sandreas.hansson@arm.com // we have so many writes that we have to transition 113810206Sandreas.hansson@arm.com if (writeQueue.size() > writeHighThreshold) { 113910206Sandreas.hansson@arm.com switch_to_writes = true; 114010206Sandreas.hansson@arm.com } 114110206Sandreas.hansson@arm.com } 114210206Sandreas.hansson@arm.com 114310206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 114410206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 114510206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 114610206Sandreas.hansson@arm.com if (switch_to_writes) { 114710206Sandreas.hansson@arm.com // transition to writing 114810206Sandreas.hansson@arm.com busState = READ_TO_WRITE; 114910206Sandreas.hansson@arm.com 115010206Sandreas.hansson@arm.com // add a bubble to the data bus, as defined by the 115110206Sandreas.hansson@arm.com // tRTW parameter 115210206Sandreas.hansson@arm.com busBusyUntil += tRTW; 115310206Sandreas.hansson@arm.com 115410206Sandreas.hansson@arm.com // update the minimum timing between the requests, 115510206Sandreas.hansson@arm.com // this shifts us back in time far enough to do any 115610206Sandreas.hansson@arm.com // bank preparation 115710206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 115810206Sandreas.hansson@arm.com } 11599352SN/A } else { 116010206Sandreas.hansson@arm.com chooseNext(writeQueue); 116110206Sandreas.hansson@arm.com DRAMPacket* dram_pkt = writeQueue.front(); 116210206Sandreas.hansson@arm.com // sanity check 116310206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 116410206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 116510206Sandreas.hansson@arm.com 116610206Sandreas.hansson@arm.com writeQueue.pop_front(); 116710206Sandreas.hansson@arm.com delete dram_pkt; 116810206Sandreas.hansson@arm.com 116910206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 117010206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 117110206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 117210206Sandreas.hansson@arm.com // writes, then switch to reads. 117310206Sandreas.hansson@arm.com if (writeQueue.empty() || 117410206Sandreas.hansson@arm.com (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 117510206Sandreas.hansson@arm.com !drainManager) || 117610206Sandreas.hansson@arm.com (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 117710206Sandreas.hansson@arm.com // turn the bus back around for reads again 117810206Sandreas.hansson@arm.com busState = WRITE_TO_READ; 117910206Sandreas.hansson@arm.com 118010206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 118110206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 118210206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 118310206Sandreas.hansson@arm.com // nothing to do 118410206Sandreas.hansson@arm.com 118510206Sandreas.hansson@arm.com // here we get a bit creative and shift the bus busy time not 118610206Sandreas.hansson@arm.com // just the tWTR, but also a CAS latency to capture the fact 118710206Sandreas.hansson@arm.com // that we are allowed to prepare a new bank, but not issue a 118810206Sandreas.hansson@arm.com // read command until after tWTR, in essence we capture a 118910206Sandreas.hansson@arm.com // bubble on the data bus that is tWTR + tCL 119010206Sandreas.hansson@arm.com busBusyUntil += tWTR + tCL; 119110206Sandreas.hansson@arm.com 119210206Sandreas.hansson@arm.com // update the minimum timing between the requests, this shifts 119310206Sandreas.hansson@arm.com // us back in time far enough to do any bank preparation 119410206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 119510206Sandreas.hansson@arm.com } 119610206Sandreas.hansson@arm.com } 119710206Sandreas.hansson@arm.com 119810206Sandreas.hansson@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 119910206Sandreas.hansson@arm.com 120010206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 120110206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 120210206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 120310206Sandreas.hansson@arm.com // the next request processing 120410206Sandreas.hansson@arm.com if (retryWrReq && writeQueue.size() < writeBufferSize) { 120510206Sandreas.hansson@arm.com retryWrReq = false; 120610206Sandreas.hansson@arm.com port.sendRetry(); 12079352SN/A } 12089243SN/A} 12099243SN/A 12109967SN/Auint64_t 121110211Sandreas.hansson@arm.comDRAMCtrl::minBankActAt(const deque<DRAMPacket*>& queue) const 12129967SN/A{ 12139967SN/A uint64_t bank_mask = 0; 121410211Sandreas.hansson@arm.com Tick min_act_at = MaxTick; 12159967SN/A 121610211Sandreas.hansson@arm.com // deterimne if we have queued transactions targetting a 12179967SN/A // bank in question 12189967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 12199967SN/A for (auto p = queue.begin(); p != queue.end(); ++p) { 12209967SN/A got_waiting[(*p)->bankId] = true; 12219967SN/A } 12229967SN/A 12239967SN/A for (int i = 0; i < ranksPerChannel; i++) { 12249967SN/A for (int j = 0; j < banksPerRank; j++) { 122510211Sandreas.hansson@arm.com uint8_t bank_id = i * banksPerRank + j; 122610211Sandreas.hansson@arm.com 12279967SN/A // if we have waiting requests for the bank, and it is 12289967SN/A // amongst the first available, update the mask 122910211Sandreas.hansson@arm.com if (got_waiting[bank_id]) { 123010211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue 123110211Sandreas.hansson@arm.com // an activate, ignoring any rank-to-rank switching 123210211Sandreas.hansson@arm.com // cost 123310211Sandreas.hansson@arm.com Tick act_at = banks[i][j].openRow == Bank::NO_ROW ? 123410211Sandreas.hansson@arm.com banks[i][j].actAllowedAt : 123510211Sandreas.hansson@arm.com std::max(banks[i][j].preAllowedAt, curTick()) + tRP; 123610211Sandreas.hansson@arm.com 123710211Sandreas.hansson@arm.com if (act_at <= min_act_at) { 123810211Sandreas.hansson@arm.com // reset bank mask if new minimum is found 123910211Sandreas.hansson@arm.com if (act_at < min_act_at) 124010211Sandreas.hansson@arm.com bank_mask = 0; 124110211Sandreas.hansson@arm.com // set the bit corresponding to the available bank 124210211Sandreas.hansson@arm.com replaceBits(bank_mask, bank_id, bank_id, 1); 124310211Sandreas.hansson@arm.com min_act_at = act_at; 124410211Sandreas.hansson@arm.com } 12459967SN/A } 12469967SN/A } 12479967SN/A } 124810211Sandreas.hansson@arm.com 12499967SN/A return bank_mask; 12509967SN/A} 12519967SN/A 12529243SN/Avoid 125310146Sandreas.hansson@arm.comDRAMCtrl::processRefreshEvent() 12549243SN/A{ 125510207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 125610207Sandreas.hansson@arm.com if (refreshState == REF_IDLE) { 125710207Sandreas.hansson@arm.com // remember when the refresh is due 125810207Sandreas.hansson@arm.com refreshDueAt = curTick(); 12599243SN/A 126010207Sandreas.hansson@arm.com // proceed to drain 126110207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 12629243SN/A 126310207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 126410207Sandreas.hansson@arm.com } 126510207Sandreas.hansson@arm.com 126610207Sandreas.hansson@arm.com // let any scheduled read or write go ahead, after which it will 126710207Sandreas.hansson@arm.com // hand control back to this event loop 126810207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 126910207Sandreas.hansson@arm.com if (nextReqEvent.scheduled()) { 127010207Sandreas.hansson@arm.com // hand control over to the request loop until it is 127110207Sandreas.hansson@arm.com // evaluated next 127210207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 127310207Sandreas.hansson@arm.com 127410207Sandreas.hansson@arm.com return; 127510207Sandreas.hansson@arm.com } else { 127610207Sandreas.hansson@arm.com refreshState = REF_PRE; 127710207Sandreas.hansson@arm.com } 127810207Sandreas.hansson@arm.com } 127910207Sandreas.hansson@arm.com 128010207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 128110207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 128210208Sandreas.hansson@arm.com // precharge any active bank if we are not already in the idle 128310208Sandreas.hansson@arm.com // state 128410208Sandreas.hansson@arm.com if (pwrState != PWR_IDLE) { 128510214Sandreas.hansson@arm.com // at the moment, we use a precharge all even if there is 128610214Sandreas.hansson@arm.com // only a single bank open 128710208Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 128810214Sandreas.hansson@arm.com 128910214Sandreas.hansson@arm.com // first determine when we can precharge 129010214Sandreas.hansson@arm.com Tick pre_at = curTick(); 129110214Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 129210214Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 129310214Sandreas.hansson@arm.com // respect both causality and any existing bank 129410214Sandreas.hansson@arm.com // constraints, some banks could already have a 129510214Sandreas.hansson@arm.com // (auto) precharge scheduled 129610214Sandreas.hansson@arm.com pre_at = std::max(banks[i][j].preAllowedAt, pre_at); 129710214Sandreas.hansson@arm.com } 129810214Sandreas.hansson@arm.com } 129910214Sandreas.hansson@arm.com 130010214Sandreas.hansson@arm.com // make sure all banks are precharged, and for those that 130110214Sandreas.hansson@arm.com // already are, update their availability 130210214Sandreas.hansson@arm.com Tick act_allowed_at = pre_at + tRP; 130310214Sandreas.hansson@arm.com 130410208Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 130510208Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 130610208Sandreas.hansson@arm.com if (banks[i][j].openRow != Bank::NO_ROW) { 130710211Sandreas.hansson@arm.com prechargeBank(banks[i][j], pre_at); 130810214Sandreas.hansson@arm.com } else { 130910214Sandreas.hansson@arm.com banks[i][j].actAllowedAt = 131010214Sandreas.hansson@arm.com std::max(banks[i][j].actAllowedAt, act_allowed_at); 131110214Sandreas.hansson@arm.com banks[i][j].preAllowedAt = 131210214Sandreas.hansson@arm.com std::max(banks[i][j].preAllowedAt, pre_at); 131310208Sandreas.hansson@arm.com } 131410207Sandreas.hansson@arm.com } 131510207Sandreas.hansson@arm.com } 131610208Sandreas.hansson@arm.com } else { 131710208Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 131810208Sandreas.hansson@arm.com 131910208Sandreas.hansson@arm.com // go ahead and kick the power state machine into gear if 132010208Sandreas.hansson@arm.com // we are already idle 132110208Sandreas.hansson@arm.com schedulePowerEvent(PWR_REF, curTick()); 13229975SN/A } 13239975SN/A 132410208Sandreas.hansson@arm.com refreshState = REF_RUN; 132510208Sandreas.hansson@arm.com assert(numBanksActive == 0); 13269243SN/A 132710208Sandreas.hansson@arm.com // wait for all banks to be precharged, at which point the 132810208Sandreas.hansson@arm.com // power state machine will transition to the idle state, and 132910208Sandreas.hansson@arm.com // automatically move to a refresh, at that point it will also 133010208Sandreas.hansson@arm.com // call this method to get the refresh event loop going again 133110207Sandreas.hansson@arm.com return; 133210207Sandreas.hansson@arm.com } 133310207Sandreas.hansson@arm.com 133410207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 133510207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 133610207Sandreas.hansson@arm.com // should never get here with any banks active 133710207Sandreas.hansson@arm.com assert(numBanksActive == 0); 133810208Sandreas.hansson@arm.com assert(pwrState == PWR_REF); 133910207Sandreas.hansson@arm.com 134010211Sandreas.hansson@arm.com Tick ref_done_at = curTick() + tRFC; 134110207Sandreas.hansson@arm.com 134210207Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 134310207Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 134410211Sandreas.hansson@arm.com banks[i][j].actAllowedAt = ref_done_at; 134510207Sandreas.hansson@arm.com } 134610207Sandreas.hansson@arm.com } 134710207Sandreas.hansson@arm.com 134810207Sandreas.hansson@arm.com // make sure we did not wait so long that we cannot make up 134910207Sandreas.hansson@arm.com // for it 135010211Sandreas.hansson@arm.com if (refreshDueAt + tREFI < ref_done_at) { 135110207Sandreas.hansson@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 135210207Sandreas.hansson@arm.com } 135310207Sandreas.hansson@arm.com 135410207Sandreas.hansson@arm.com // compensate for the delay in actually performing the refresh 135510207Sandreas.hansson@arm.com // when scheduling the next one 135610207Sandreas.hansson@arm.com schedule(refreshEvent, refreshDueAt + tREFI - tRP); 135710207Sandreas.hansson@arm.com 135810208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 135910207Sandreas.hansson@arm.com 136010208Sandreas.hansson@arm.com // move to the idle power state once the refresh is done, this 136110208Sandreas.hansson@arm.com // will also move the refresh state machine to the refresh 136210208Sandreas.hansson@arm.com // idle state 136310211Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, ref_done_at); 136410207Sandreas.hansson@arm.com 136510208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n", 136610211Sandreas.hansson@arm.com ref_done_at, refreshDueAt + tREFI); 136710208Sandreas.hansson@arm.com } 136810208Sandreas.hansson@arm.com} 136910208Sandreas.hansson@arm.com 137010208Sandreas.hansson@arm.comvoid 137110208Sandreas.hansson@arm.comDRAMCtrl::schedulePowerEvent(PowerState pwr_state, Tick tick) 137210208Sandreas.hansson@arm.com{ 137310208Sandreas.hansson@arm.com // respect causality 137410208Sandreas.hansson@arm.com assert(tick >= curTick()); 137510208Sandreas.hansson@arm.com 137610208Sandreas.hansson@arm.com if (!powerEvent.scheduled()) { 137710208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 137810208Sandreas.hansson@arm.com tick, pwr_state); 137910208Sandreas.hansson@arm.com 138010208Sandreas.hansson@arm.com // insert the new transition 138110208Sandreas.hansson@arm.com pwrStateTrans = pwr_state; 138210208Sandreas.hansson@arm.com 138310208Sandreas.hansson@arm.com schedule(powerEvent, tick); 138410208Sandreas.hansson@arm.com } else { 138510208Sandreas.hansson@arm.com panic("Scheduled power event at %llu to state %d, " 138610208Sandreas.hansson@arm.com "with scheduled event at %llu to %d\n", tick, pwr_state, 138710208Sandreas.hansson@arm.com powerEvent.when(), pwrStateTrans); 138810208Sandreas.hansson@arm.com } 138910208Sandreas.hansson@arm.com} 139010208Sandreas.hansson@arm.com 139110208Sandreas.hansson@arm.comvoid 139210208Sandreas.hansson@arm.comDRAMCtrl::processPowerEvent() 139310208Sandreas.hansson@arm.com{ 139410208Sandreas.hansson@arm.com // remember where we were, and for how long 139510208Sandreas.hansson@arm.com Tick duration = curTick() - pwrStateTick; 139610208Sandreas.hansson@arm.com PowerState prev_state = pwrState; 139710208Sandreas.hansson@arm.com 139810208Sandreas.hansson@arm.com // update the accounting 139910208Sandreas.hansson@arm.com pwrStateTime[prev_state] += duration; 140010208Sandreas.hansson@arm.com 140110208Sandreas.hansson@arm.com pwrState = pwrStateTrans; 140210208Sandreas.hansson@arm.com pwrStateTick = curTick(); 140310208Sandreas.hansson@arm.com 140410208Sandreas.hansson@arm.com if (pwrState == PWR_IDLE) { 140510208Sandreas.hansson@arm.com DPRINTF(DRAMState, "All banks precharged\n"); 140610208Sandreas.hansson@arm.com 140710208Sandreas.hansson@arm.com // if we were refreshing, make sure we start scheduling requests again 140810208Sandreas.hansson@arm.com if (prev_state == PWR_REF) { 140910208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 141010208Sandreas.hansson@arm.com assert(pwrState == PWR_IDLE); 141110208Sandreas.hansson@arm.com 141210208Sandreas.hansson@arm.com // kick things into action again 141310208Sandreas.hansson@arm.com refreshState = REF_IDLE; 141410208Sandreas.hansson@arm.com assert(!nextReqEvent.scheduled()); 141510208Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 141610208Sandreas.hansson@arm.com } else { 141710208Sandreas.hansson@arm.com assert(prev_state == PWR_ACT); 141810208Sandreas.hansson@arm.com 141910208Sandreas.hansson@arm.com // if we have a pending refresh, and are now moving to 142010208Sandreas.hansson@arm.com // the idle state, direclty transition to a refresh 142110208Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 142210208Sandreas.hansson@arm.com // there should be nothing waiting at this point 142310208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 142410208Sandreas.hansson@arm.com 142510208Sandreas.hansson@arm.com // update the state in zero time and proceed below 142610208Sandreas.hansson@arm.com pwrState = PWR_REF; 142710208Sandreas.hansson@arm.com } 142810208Sandreas.hansson@arm.com } 142910208Sandreas.hansson@arm.com } 143010208Sandreas.hansson@arm.com 143110208Sandreas.hansson@arm.com // we transition to the refresh state, let the refresh state 143210208Sandreas.hansson@arm.com // machine know of this state update and let it deal with the 143310208Sandreas.hansson@arm.com // scheduling of the next power state transition as well as the 143410208Sandreas.hansson@arm.com // following refresh 143510208Sandreas.hansson@arm.com if (pwrState == PWR_REF) { 143610208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refreshing\n"); 143710208Sandreas.hansson@arm.com // kick the refresh event loop into action again, and that 143810208Sandreas.hansson@arm.com // in turn will schedule a transition to the idle power 143910208Sandreas.hansson@arm.com // state once the refresh is done 144010208Sandreas.hansson@arm.com assert(refreshState == REF_RUN); 144110208Sandreas.hansson@arm.com processRefreshEvent(); 144210207Sandreas.hansson@arm.com } 14439243SN/A} 14449243SN/A 14459243SN/Avoid 144610146Sandreas.hansson@arm.comDRAMCtrl::regStats() 14479243SN/A{ 14489243SN/A using namespace Stats; 14499243SN/A 14509243SN/A AbstractMemory::regStats(); 14519243SN/A 14529243SN/A readReqs 14539243SN/A .name(name() + ".readReqs") 14549977SN/A .desc("Number of read requests accepted"); 14559243SN/A 14569243SN/A writeReqs 14579243SN/A .name(name() + ".writeReqs") 14589977SN/A .desc("Number of write requests accepted"); 14599831SN/A 14609831SN/A readBursts 14619831SN/A .name(name() + ".readBursts") 14629977SN/A .desc("Number of DRAM read bursts, " 14639977SN/A "including those serviced by the write queue"); 14649831SN/A 14659831SN/A writeBursts 14669831SN/A .name(name() + ".writeBursts") 14679977SN/A .desc("Number of DRAM write bursts, " 14689977SN/A "including those merged in the write queue"); 14699243SN/A 14709243SN/A servicedByWrQ 14719243SN/A .name(name() + ".servicedByWrQ") 14729977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 14739977SN/A 14749977SN/A mergedWrBursts 14759977SN/A .name(name() + ".mergedWrBursts") 14769977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 14779243SN/A 14789243SN/A neitherReadNorWrite 14799977SN/A .name(name() + ".neitherReadNorWriteReqs") 14809977SN/A .desc("Number of requests that are neither read nor write"); 14819243SN/A 14829977SN/A perBankRdBursts 14839243SN/A .init(banksPerRank * ranksPerChannel) 14849977SN/A .name(name() + ".perBankRdBursts") 14859977SN/A .desc("Per bank write bursts"); 14869243SN/A 14879977SN/A perBankWrBursts 14889243SN/A .init(banksPerRank * ranksPerChannel) 14899977SN/A .name(name() + ".perBankWrBursts") 14909977SN/A .desc("Per bank write bursts"); 14919243SN/A 14929243SN/A avgRdQLen 14939243SN/A .name(name() + ".avgRdQLen") 14949977SN/A .desc("Average read queue length when enqueuing") 14959243SN/A .precision(2); 14969243SN/A 14979243SN/A avgWrQLen 14989243SN/A .name(name() + ".avgWrQLen") 14999977SN/A .desc("Average write queue length when enqueuing") 15009243SN/A .precision(2); 15019243SN/A 15029243SN/A totQLat 15039243SN/A .name(name() + ".totQLat") 15049977SN/A .desc("Total ticks spent queuing"); 15059243SN/A 15069243SN/A totBusLat 15079243SN/A .name(name() + ".totBusLat") 15089977SN/A .desc("Total ticks spent in databus transfers"); 15099243SN/A 15109243SN/A totMemAccLat 15119243SN/A .name(name() + ".totMemAccLat") 15129977SN/A .desc("Total ticks spent from burst creation until serviced " 15139977SN/A "by the DRAM"); 15149243SN/A 15159243SN/A avgQLat 15169243SN/A .name(name() + ".avgQLat") 15179977SN/A .desc("Average queueing delay per DRAM burst") 15189243SN/A .precision(2); 15199243SN/A 15209831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 15219243SN/A 15229243SN/A avgBusLat 15239243SN/A .name(name() + ".avgBusLat") 15249977SN/A .desc("Average bus latency per DRAM burst") 15259243SN/A .precision(2); 15269243SN/A 15279831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 15289243SN/A 15299243SN/A avgMemAccLat 15309243SN/A .name(name() + ".avgMemAccLat") 15319977SN/A .desc("Average memory access latency per DRAM burst") 15329243SN/A .precision(2); 15339243SN/A 15349831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 15359243SN/A 15369243SN/A numRdRetry 15379243SN/A .name(name() + ".numRdRetry") 15389977SN/A .desc("Number of times read queue was full causing retry"); 15399243SN/A 15409243SN/A numWrRetry 15419243SN/A .name(name() + ".numWrRetry") 15429977SN/A .desc("Number of times write queue was full causing retry"); 15439243SN/A 15449243SN/A readRowHits 15459243SN/A .name(name() + ".readRowHits") 15469243SN/A .desc("Number of row buffer hits during reads"); 15479243SN/A 15489243SN/A writeRowHits 15499243SN/A .name(name() + ".writeRowHits") 15509243SN/A .desc("Number of row buffer hits during writes"); 15519243SN/A 15529243SN/A readRowHitRate 15539243SN/A .name(name() + ".readRowHitRate") 15549243SN/A .desc("Row buffer hit rate for reads") 15559243SN/A .precision(2); 15569243SN/A 15579831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 15589243SN/A 15599243SN/A writeRowHitRate 15609243SN/A .name(name() + ".writeRowHitRate") 15619243SN/A .desc("Row buffer hit rate for writes") 15629243SN/A .precision(2); 15639243SN/A 15649977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 15659243SN/A 15669243SN/A readPktSize 15679831SN/A .init(ceilLog2(burstSize) + 1) 15689243SN/A .name(name() + ".readPktSize") 15699977SN/A .desc("Read request sizes (log2)"); 15709243SN/A 15719243SN/A writePktSize 15729831SN/A .init(ceilLog2(burstSize) + 1) 15739243SN/A .name(name() + ".writePktSize") 15749977SN/A .desc("Write request sizes (log2)"); 15759243SN/A 15769243SN/A rdQLenPdf 15779567SN/A .init(readBufferSize) 15789243SN/A .name(name() + ".rdQLenPdf") 15799243SN/A .desc("What read queue length does an incoming req see"); 15809243SN/A 15819243SN/A wrQLenPdf 15829567SN/A .init(writeBufferSize) 15839243SN/A .name(name() + ".wrQLenPdf") 15849243SN/A .desc("What write queue length does an incoming req see"); 15859243SN/A 15869727SN/A bytesPerActivate 158710141SN/A .init(maxAccessesPerRow) 15889727SN/A .name(name() + ".bytesPerActivate") 15899727SN/A .desc("Bytes accessed per row activation") 15909727SN/A .flags(nozero); 15919243SN/A 159210147Sandreas.hansson@arm.com rdPerTurnAround 159310147Sandreas.hansson@arm.com .init(readBufferSize) 159410147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 159510147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 159610147Sandreas.hansson@arm.com .flags(nozero); 159710147Sandreas.hansson@arm.com 159810147Sandreas.hansson@arm.com wrPerTurnAround 159910147Sandreas.hansson@arm.com .init(writeBufferSize) 160010147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 160110147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 160210147Sandreas.hansson@arm.com .flags(nozero); 160310147Sandreas.hansson@arm.com 16049975SN/A bytesReadDRAM 16059975SN/A .name(name() + ".bytesReadDRAM") 16069975SN/A .desc("Total number of bytes read from DRAM"); 16079975SN/A 16089975SN/A bytesReadWrQ 16099975SN/A .name(name() + ".bytesReadWrQ") 16109975SN/A .desc("Total number of bytes read from write queue"); 16119243SN/A 16129243SN/A bytesWritten 16139243SN/A .name(name() + ".bytesWritten") 16149977SN/A .desc("Total number of bytes written to DRAM"); 16159243SN/A 16169977SN/A bytesReadSys 16179977SN/A .name(name() + ".bytesReadSys") 16189977SN/A .desc("Total read bytes from the system interface side"); 16199243SN/A 16209977SN/A bytesWrittenSys 16219977SN/A .name(name() + ".bytesWrittenSys") 16229977SN/A .desc("Total written bytes from the system interface side"); 16239243SN/A 16249243SN/A avgRdBW 16259243SN/A .name(name() + ".avgRdBW") 16269977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 16279243SN/A .precision(2); 16289243SN/A 16299977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 16309243SN/A 16319243SN/A avgWrBW 16329243SN/A .name(name() + ".avgWrBW") 16339977SN/A .desc("Average achieved write bandwidth in MiByte/s") 16349243SN/A .precision(2); 16359243SN/A 16369243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 16379243SN/A 16389977SN/A avgRdBWSys 16399977SN/A .name(name() + ".avgRdBWSys") 16409977SN/A .desc("Average system read bandwidth in MiByte/s") 16419243SN/A .precision(2); 16429243SN/A 16439977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 16449243SN/A 16459977SN/A avgWrBWSys 16469977SN/A .name(name() + ".avgWrBWSys") 16479977SN/A .desc("Average system write bandwidth in MiByte/s") 16489243SN/A .precision(2); 16499243SN/A 16509977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 16519243SN/A 16529243SN/A peakBW 16539243SN/A .name(name() + ".peakBW") 16549977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 16559243SN/A .precision(2); 16569243SN/A 16579831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 16589243SN/A 16599243SN/A busUtil 16609243SN/A .name(name() + ".busUtil") 16619243SN/A .desc("Data bus utilization in percentage") 16629243SN/A .precision(2); 16639243SN/A 16649243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 16659243SN/A 16669243SN/A totGap 16679243SN/A .name(name() + ".totGap") 16689243SN/A .desc("Total gap between requests"); 16699243SN/A 16709243SN/A avgGap 16719243SN/A .name(name() + ".avgGap") 16729243SN/A .desc("Average gap between requests") 16739243SN/A .precision(2); 16749243SN/A 16759243SN/A avgGap = totGap / (readReqs + writeReqs); 16769975SN/A 16779975SN/A // Stats for DRAM Power calculation based on Micron datasheet 16789975SN/A busUtilRead 16799975SN/A .name(name() + ".busUtilRead") 16809975SN/A .desc("Data bus utilization in percentage for reads") 16819975SN/A .precision(2); 16829975SN/A 16839975SN/A busUtilRead = avgRdBW / peakBW * 100; 16849975SN/A 16859975SN/A busUtilWrite 16869975SN/A .name(name() + ".busUtilWrite") 16879975SN/A .desc("Data bus utilization in percentage for writes") 16889975SN/A .precision(2); 16899975SN/A 16909975SN/A busUtilWrite = avgWrBW / peakBW * 100; 16919975SN/A 16929975SN/A pageHitRate 16939975SN/A .name(name() + ".pageHitRate") 16949975SN/A .desc("Row buffer hit rate, read and write combined") 16959975SN/A .precision(2); 16969975SN/A 16979977SN/A pageHitRate = (writeRowHits + readRowHits) / 16989977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 16999975SN/A 170010208Sandreas.hansson@arm.com pwrStateTime 170110208Sandreas.hansson@arm.com .init(5) 170210208Sandreas.hansson@arm.com .name(name() + ".memoryStateTime") 170310208Sandreas.hansson@arm.com .desc("Time in different power states"); 170410208Sandreas.hansson@arm.com pwrStateTime.subname(0, "IDLE"); 170510208Sandreas.hansson@arm.com pwrStateTime.subname(1, "REF"); 170610208Sandreas.hansson@arm.com pwrStateTime.subname(2, "PRE_PDN"); 170710208Sandreas.hansson@arm.com pwrStateTime.subname(3, "ACT"); 170810208Sandreas.hansson@arm.com pwrStateTime.subname(4, "ACT_PDN"); 17099243SN/A} 17109243SN/A 17119243SN/Avoid 171210146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 17139243SN/A{ 17149243SN/A // rely on the abstract memory 17159243SN/A functionalAccess(pkt); 17169243SN/A} 17179243SN/A 17189294SN/ABaseSlavePort& 171910146Sandreas.hansson@arm.comDRAMCtrl::getSlavePort(const string &if_name, PortID idx) 17209243SN/A{ 17219243SN/A if (if_name != "port") { 17229243SN/A return MemObject::getSlavePort(if_name, idx); 17239243SN/A } else { 17249243SN/A return port; 17259243SN/A } 17269243SN/A} 17279243SN/A 17289243SN/Aunsigned int 172910146Sandreas.hansson@arm.comDRAMCtrl::drain(DrainManager *dm) 17309243SN/A{ 17319342SN/A unsigned int count = port.drain(dm); 17329243SN/A 17339243SN/A // if there is anything in any of our internal queues, keep track 17349243SN/A // of that as well 17359567SN/A if (!(writeQueue.empty() && readQueue.empty() && 17369567SN/A respQueue.empty())) { 17379352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 17389567SN/A " resp: %d\n", writeQueue.size(), readQueue.size(), 17399567SN/A respQueue.size()); 17409243SN/A ++count; 17419342SN/A drainManager = dm; 174210206Sandreas.hansson@arm.com 17439352SN/A // the only part that is not drained automatically over time 174410206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 174510206Sandreas.hansson@arm.com if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 174610206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 174710206Sandreas.hansson@arm.com } 17489243SN/A } 17499243SN/A 17509243SN/A if (count) 17519342SN/A setDrainState(Drainable::Draining); 17529243SN/A else 17539342SN/A setDrainState(Drainable::Drained); 17549243SN/A return count; 17559243SN/A} 17569243SN/A 175710146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 17589243SN/A : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 17599243SN/A memory(_memory) 17609243SN/A{ } 17619243SN/A 17629243SN/AAddrRangeList 176310146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 17649243SN/A{ 17659243SN/A AddrRangeList ranges; 17669243SN/A ranges.push_back(memory.getAddrRange()); 17679243SN/A return ranges; 17689243SN/A} 17699243SN/A 17709243SN/Avoid 177110146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 17729243SN/A{ 17739243SN/A pkt->pushLabel(memory.name()); 17749243SN/A 17759243SN/A if (!queue.checkFunctional(pkt)) { 17769243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 17779243SN/A // calls recvAtomic() and throws away the latency; we can save a 17789243SN/A // little here by just not calculating the latency. 17799243SN/A memory.recvFunctional(pkt); 17809243SN/A } 17819243SN/A 17829243SN/A pkt->popLabel(); 17839243SN/A} 17849243SN/A 17859243SN/ATick 178610146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 17879243SN/A{ 17889243SN/A return memory.recvAtomic(pkt); 17899243SN/A} 17909243SN/A 17919243SN/Abool 179210146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 17939243SN/A{ 17949243SN/A // pass it to the memory controller 17959243SN/A return memory.recvTimingReq(pkt); 17969243SN/A} 17979243SN/A 179810146Sandreas.hansson@arm.comDRAMCtrl* 179910146Sandreas.hansson@arm.comDRAMCtrlParams::create() 18009243SN/A{ 180110146Sandreas.hansson@arm.com return new DRAMCtrl(this); 18029243SN/A} 1803