dram_ctrl.cc revision 10212
19243SN/A/* 210206Sandreas.hansson@arm.com * Copyright (c) 2010-2014 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 439243SN/A */ 449243SN/A 4510146Sandreas.hansson@arm.com#include "base/bitfield.hh" 469356SN/A#include "base/trace.hh" 4710146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 4810208Sandreas.hansson@arm.com#include "debug/DRAMState.hh" 499352SN/A#include "debug/Drain.hh" 5010146Sandreas.hansson@arm.com#include "mem/dram_ctrl.hh" 519814SN/A#include "sim/system.hh" 529243SN/A 539243SN/Ausing namespace std; 549243SN/A 5510146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 569243SN/A AbstractMemory(p), 579243SN/A port(name() + ".port", *this), 589243SN/A retryRdReq(false), retryWrReq(false), 5910211Sandreas.hansson@arm.com busState(READ), 6010208Sandreas.hansson@arm.com nextReqEvent(this), respondEvent(this), activateEvent(this), 6110208Sandreas.hansson@arm.com prechargeEvent(this), refreshEvent(this), powerEvent(this), 6210208Sandreas.hansson@arm.com drainManager(NULL), 639831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 649831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 659831SN/A devicesPerRank(p->devices_per_rank), 669831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 679831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 6810140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 699243SN/A ranksPerChannel(p->ranks_per_channel), 709566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 719243SN/A readBufferSize(p->read_buffer_size), 729243SN/A writeBufferSize(p->write_buffer_size), 7310140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 7410140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 7510147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 7610147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 7710206Sandreas.hansson@arm.com tWTR(p->tWTR), tRTW(p->tRTW), tBURST(p->tBURST), 7810210Sandreas.hansson@arm.com tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), tWR(p->tWR), 7910212Sandreas.hansson@arm.com tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 809488SN/A tXAW(p->tXAW), activationLimit(p->activation_limit), 819243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 829243SN/A pageMgmt(p->page_policy), 8310141SN/A maxAccessesPerRow(p->max_accesses_per_row), 849726SN/A frontendLatency(p->static_frontend_latency), 859726SN/A backendLatency(p->static_backend_latency), 8610208Sandreas.hansson@arm.com busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE), 8710208Sandreas.hansson@arm.com pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), prevArrival(0), 8810208Sandreas.hansson@arm.com nextReqTime(0), pwrStateTick(0), numBanksActive(0) 899243SN/A{ 909243SN/A // create the bank states based on the dimensions of the ranks and 919243SN/A // banks 929243SN/A banks.resize(ranksPerChannel); 939969SN/A actTicks.resize(ranksPerChannel); 949243SN/A for (size_t c = 0; c < ranksPerChannel; ++c) { 959243SN/A banks[c].resize(banksPerRank); 969969SN/A actTicks[c].resize(activationLimit, 0); 979243SN/A } 989243SN/A 9910140SN/A // perform a basic check of the write thresholds 10010140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 10110140SN/A fatal("Write buffer low threshold %d must be smaller than the " 10210140SN/A "high threshold %d\n", p->write_low_thresh_perc, 10310140SN/A p->write_high_thresh_perc); 1049243SN/A 1059243SN/A // determine the rows per bank by looking at the total capacity 1069567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1079243SN/A 1089243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1099243SN/A AbstractMemory::size()); 1109831SN/A 1119831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1129831SN/A rowBufferSize, columnsPerRowBuffer); 1139831SN/A 1149831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1159243SN/A 1169566SN/A if (range.interleaved()) { 1179566SN/A if (channels != range.stripes()) 11810143SN/A fatal("%s has %d interleaved address stripes but %d channel(s)\n", 1199566SN/A name(), range.stripes(), channels); 1209566SN/A 12110136SN/A if (addrMapping == Enums::RoRaBaChCo) { 1229831SN/A if (rowBufferSize != range.granularity()) { 12310143SN/A fatal("Interleaving of %s doesn't match RoRaBaChCo " 12410136SN/A "address map\n", name()); 1259566SN/A } 12610136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 12710136SN/A if (system()->cacheLineSize() != range.granularity()) { 12810143SN/A fatal("Interleaving of %s doesn't match RoRaBaCoCh " 12910136SN/A "address map\n", name()); 1309669SN/A } 13110136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 13210136SN/A if (system()->cacheLineSize() != range.granularity()) 13310143SN/A fatal("Interleaving of %s doesn't match RoCoRaBaCh " 13410136SN/A "address map\n", name()); 1359566SN/A } 1369566SN/A } 13710207Sandreas.hansson@arm.com 13810207Sandreas.hansson@arm.com // some basic sanity checks 13910207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 14010207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 14110207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 14210207Sandreas.hansson@arm.com } 1439243SN/A} 1449243SN/A 1459243SN/Avoid 14610146Sandreas.hansson@arm.comDRAMCtrl::init() 14710140SN/A{ 14810140SN/A if (!port.isConnected()) { 14910146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 15010140SN/A } else { 15110140SN/A port.sendRangeChange(); 15210140SN/A } 15310140SN/A} 15410140SN/A 15510140SN/Avoid 15610146Sandreas.hansson@arm.comDRAMCtrl::startup() 1579243SN/A{ 15810143SN/A // update the start tick for the precharge accounting to the 15910143SN/A // current tick 16010208Sandreas.hansson@arm.com pwrStateTick = curTick(); 16110143SN/A 16210206Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 16310206Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 16410206Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 16510206Sandreas.hansson@arm.com // start of simulation 16610206Sandreas.hansson@arm.com busBusyUntil = curTick() + tRP + tRCD + tCL; 16710206Sandreas.hansson@arm.com 1689243SN/A // print the configuration of the controller 1699243SN/A printParams(); 1709243SN/A 17110207Sandreas.hansson@arm.com // kick off the refresh, and give ourselves enough time to 17210207Sandreas.hansson@arm.com // precharge 17310207Sandreas.hansson@arm.com schedule(refreshEvent, curTick() + tREFI - tRP); 1749243SN/A} 1759243SN/A 1769243SN/ATick 17710146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 1789243SN/A{ 1799243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 1809243SN/A 1819243SN/A // do the actual memory access and turn the packet into a response 1829243SN/A access(pkt); 1839243SN/A 1849243SN/A Tick latency = 0; 1859243SN/A if (!pkt->memInhibitAsserted() && pkt->hasData()) { 1869243SN/A // this value is not supposed to be accurate, just enough to 1879243SN/A // keep things going, mimic a closed page 1889243SN/A latency = tRP + tRCD + tCL; 1899243SN/A } 1909243SN/A return latency; 1919243SN/A} 1929243SN/A 1939243SN/Abool 19410146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 1959243SN/A{ 1969831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 1979831SN/A readBufferSize, readQueue.size() + respQueue.size(), 1989831SN/A neededEntries); 1999243SN/A 2009831SN/A return 2019831SN/A (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 2029243SN/A} 2039243SN/A 2049243SN/Abool 20510146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 2069243SN/A{ 2079831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 2089831SN/A writeBufferSize, writeQueue.size(), neededEntries); 2099831SN/A return (writeQueue.size() + neededEntries) > writeBufferSize; 2109243SN/A} 2119243SN/A 21210146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 21310146Sandreas.hansson@arm.comDRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 21410143SN/A bool isRead) 2159243SN/A{ 2169669SN/A // decode the address based on the address mapping scheme, with 21710136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 21810136SN/A // channel, respectively 2199243SN/A uint8_t rank; 2209967SN/A uint8_t bank; 2219243SN/A uint16_t row; 2229243SN/A 2239243SN/A // truncate the address to the access granularity 2249831SN/A Addr addr = dramPktAddr / burstSize; 2259243SN/A 2269491SN/A // we have removed the lowest order address bits that denote the 2279831SN/A // position within the column 22810136SN/A if (addrMapping == Enums::RoRaBaChCo) { 2299491SN/A // the lowest order bits denote the column to ensure that 2309491SN/A // sequential cache lines occupy the same row 2319831SN/A addr = addr / columnsPerRowBuffer; 2329243SN/A 2339669SN/A // take out the channel part of the address 2349566SN/A addr = addr / channels; 2359566SN/A 2369669SN/A // after the channel bits, get the bank bits to interleave 2379669SN/A // over the banks 2389669SN/A bank = addr % banksPerRank; 2399669SN/A addr = addr / banksPerRank; 2409669SN/A 2419669SN/A // after the bank, we get the rank bits which thus interleaves 2429669SN/A // over the ranks 2439669SN/A rank = addr % ranksPerChannel; 2449669SN/A addr = addr / ranksPerChannel; 2459669SN/A 2469669SN/A // lastly, get the row bits 2479669SN/A row = addr % rowsPerBank; 2489669SN/A addr = addr / rowsPerBank; 24910136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 2509669SN/A // take out the channel part of the address 2519669SN/A addr = addr / channels; 2529669SN/A 2539669SN/A // next, the column 2549831SN/A addr = addr / columnsPerRowBuffer; 2559669SN/A 2569669SN/A // after the column bits, we get the bank bits to interleave 2579491SN/A // over the banks 2589243SN/A bank = addr % banksPerRank; 2599243SN/A addr = addr / banksPerRank; 2609243SN/A 2619491SN/A // after the bank, we get the rank bits which thus interleaves 2629491SN/A // over the ranks 2639243SN/A rank = addr % ranksPerChannel; 2649243SN/A addr = addr / ranksPerChannel; 2659243SN/A 2669491SN/A // lastly, get the row bits 2679243SN/A row = addr % rowsPerBank; 2689243SN/A addr = addr / rowsPerBank; 26910136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 2709491SN/A // optimise for closed page mode and utilise maximum 2719491SN/A // parallelism of the DRAM (at the cost of power) 2729491SN/A 2739566SN/A // take out the channel part of the address, not that this has 2749566SN/A // to match with how accesses are interleaved between the 2759566SN/A // controllers in the address mapping 2769566SN/A addr = addr / channels; 2779566SN/A 2789491SN/A // start with the bank bits, as this provides the maximum 2799491SN/A // opportunity for parallelism between requests 2809243SN/A bank = addr % banksPerRank; 2819243SN/A addr = addr / banksPerRank; 2829243SN/A 2839491SN/A // next get the rank bits 2849243SN/A rank = addr % ranksPerChannel; 2859243SN/A addr = addr / ranksPerChannel; 2869243SN/A 2879491SN/A // next the column bits which we do not need to keep track of 2889491SN/A // and simply skip past 2899831SN/A addr = addr / columnsPerRowBuffer; 2909243SN/A 2919491SN/A // lastly, get the row bits 2929243SN/A row = addr % rowsPerBank; 2939243SN/A addr = addr / rowsPerBank; 2949243SN/A } else 2959243SN/A panic("Unknown address mapping policy chosen!"); 2969243SN/A 2979243SN/A assert(rank < ranksPerChannel); 2989243SN/A assert(bank < banksPerRank); 2999243SN/A assert(row < rowsPerBank); 3009243SN/A 3019243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 3029831SN/A dramPktAddr, rank, bank, row); 3039243SN/A 3049243SN/A // create the corresponding DRAM packet with the entry time and 3059567SN/A // ready time set to the current tick, the latter will be updated 3069567SN/A // later 3079967SN/A uint16_t bank_id = banksPerRank * rank + bank; 3089967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 3099967SN/A size, banks[rank][bank]); 3109243SN/A} 3119243SN/A 3129243SN/Avoid 31310146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 3149243SN/A{ 3159243SN/A // only add to the read queue here. whenever the request is 3169243SN/A // eventually done, set the readyTime, and call schedule() 3179243SN/A assert(!pkt->isWrite()); 3189243SN/A 3199831SN/A assert(pktCount != 0); 3209831SN/A 3219831SN/A // if the request size is larger than burst size, the pkt is split into 3229831SN/A // multiple DRAM packets 3239831SN/A // Note if the pkt starting address is not aligened to burst size, the 3249831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 3259831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 3269831SN/A // check read packets against packets in write queue. 3279243SN/A Addr addr = pkt->getAddr(); 3289831SN/A unsigned pktsServicedByWrQ = 0; 3299831SN/A BurstHelper* burst_helper = NULL; 3309831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 3319831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 3329831SN/A pkt->getAddr() + pkt->getSize()) - addr; 3339831SN/A readPktSize[ceilLog2(size)]++; 3349831SN/A readBursts++; 3359243SN/A 3369831SN/A // First check write buffer to see if the data is already at 3379831SN/A // the controller 3389831SN/A bool foundInWrQ = false; 3399833SN/A for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) { 3409832SN/A // check if the read is subsumed in the write entry we are 3419832SN/A // looking at 3429832SN/A if ((*i)->addr <= addr && 3439832SN/A (addr + size) <= ((*i)->addr + (*i)->size)) { 3449831SN/A foundInWrQ = true; 3459831SN/A servicedByWrQ++; 3469831SN/A pktsServicedByWrQ++; 3479831SN/A DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 3489831SN/A "write queue\n", addr, size); 3499975SN/A bytesReadWrQ += burstSize; 3509831SN/A break; 3519831SN/A } 3529243SN/A } 3539831SN/A 3549831SN/A // If not found in the write q, make a DRAM packet and 3559831SN/A // push it onto the read queue 3569831SN/A if (!foundInWrQ) { 3579831SN/A 3589831SN/A // Make the burst helper for split packets 3599831SN/A if (pktCount > 1 && burst_helper == NULL) { 3609831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 3619831SN/A "dram requests\n", pkt->getAddr(), pktCount); 3629831SN/A burst_helper = new BurstHelper(pktCount); 3639831SN/A } 3649831SN/A 3659966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 3669831SN/A dram_pkt->burstHelper = burst_helper; 3679831SN/A 3689831SN/A assert(!readQueueFull(1)); 3699831SN/A rdQLenPdf[readQueue.size() + respQueue.size()]++; 3709831SN/A 3719831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 3729831SN/A 3739831SN/A readQueue.push_back(dram_pkt); 3749831SN/A 3759831SN/A // Update stats 3769831SN/A avgRdQLen = readQueue.size() + respQueue.size(); 3779831SN/A } 3789831SN/A 3799831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 3809831SN/A addr = (addr | (burstSize - 1)) + 1; 3819243SN/A } 3829243SN/A 3839831SN/A // If all packets are serviced by write queue, we send the repsonse back 3849831SN/A if (pktsServicedByWrQ == pktCount) { 3859831SN/A accessAndRespond(pkt, frontendLatency); 3869831SN/A return; 3879831SN/A } 3889243SN/A 3899831SN/A // Update how many split packets are serviced by write queue 3909831SN/A if (burst_helper != NULL) 3919831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 3929243SN/A 39310206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 39410206Sandreas.hansson@arm.com // queue, do so now 39510206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 3969567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 3979567SN/A schedule(nextReqEvent, curTick()); 3989243SN/A } 3999243SN/A} 4009243SN/A 4019243SN/Avoid 40210146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 4039243SN/A{ 4049243SN/A // only add to the write queue here. whenever the request is 4059243SN/A // eventually done, set the readyTime, and call schedule() 4069243SN/A assert(pkt->isWrite()); 4079243SN/A 4089831SN/A // if the request size is larger than burst size, the pkt is split into 4099831SN/A // multiple DRAM packets 4109831SN/A Addr addr = pkt->getAddr(); 4119831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4129831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4139831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4149831SN/A writePktSize[ceilLog2(size)]++; 4159831SN/A writeBursts++; 4169243SN/A 4179832SN/A // see if we can merge with an existing item in the write 4189838SN/A // queue and keep track of whether we have merged or not so we 4199838SN/A // can stop at that point and also avoid enqueueing a new 4209838SN/A // request 4219832SN/A bool merged = false; 4229832SN/A auto w = writeQueue.begin(); 4239243SN/A 4249832SN/A while(!merged && w != writeQueue.end()) { 4259832SN/A // either of the two could be first, if they are the same 4269832SN/A // it does not matter which way we go 4279832SN/A if ((*w)->addr >= addr) { 4289838SN/A // the existing one starts after the new one, figure 4299838SN/A // out where the new one ends with respect to the 4309838SN/A // existing one 4319832SN/A if ((addr + size) >= ((*w)->addr + (*w)->size)) { 4329832SN/A // check if the existing one is completely 4339832SN/A // subsumed in the new one 4349832SN/A DPRINTF(DRAM, "Merging write covering existing burst\n"); 4359832SN/A merged = true; 4369832SN/A // update both the address and the size 4379832SN/A (*w)->addr = addr; 4389832SN/A (*w)->size = size; 4399832SN/A } else if ((addr + size) >= (*w)->addr && 4409832SN/A ((*w)->addr + (*w)->size - addr) <= burstSize) { 4419832SN/A // the new one is just before or partially 4429832SN/A // overlapping with the existing one, and together 4439832SN/A // they fit within a burst 4449832SN/A DPRINTF(DRAM, "Merging write before existing burst\n"); 4459832SN/A merged = true; 4469832SN/A // the existing queue item needs to be adjusted with 4479832SN/A // respect to both address and size 44810047SN/A (*w)->size = (*w)->addr + (*w)->size - addr; 4499832SN/A (*w)->addr = addr; 4509832SN/A } 4519832SN/A } else { 4529838SN/A // the new one starts after the current one, figure 4539838SN/A // out where the existing one ends with respect to the 4549838SN/A // new one 4559832SN/A if (((*w)->addr + (*w)->size) >= (addr + size)) { 4569832SN/A // check if the new one is completely subsumed in the 4579832SN/A // existing one 4589832SN/A DPRINTF(DRAM, "Merging write into existing burst\n"); 4599832SN/A merged = true; 4609832SN/A // no adjustments necessary 4619832SN/A } else if (((*w)->addr + (*w)->size) >= addr && 4629832SN/A (addr + size - (*w)->addr) <= burstSize) { 4639832SN/A // the existing one is just before or partially 4649832SN/A // overlapping with the new one, and together 4659832SN/A // they fit within a burst 4669832SN/A DPRINTF(DRAM, "Merging write after existing burst\n"); 4679832SN/A merged = true; 4689832SN/A // the address is right, and only the size has 4699832SN/A // to be adjusted 4709832SN/A (*w)->size = addr + size - (*w)->addr; 4719832SN/A } 4729832SN/A } 4739832SN/A ++w; 4749832SN/A } 4759243SN/A 4769832SN/A // if the item was not merged we need to create a new write 4779832SN/A // and enqueue it 4789832SN/A if (!merged) { 4799966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 4809243SN/A 4819832SN/A assert(writeQueue.size() < writeBufferSize); 4829832SN/A wrQLenPdf[writeQueue.size()]++; 4839243SN/A 4849832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 4859831SN/A 4869832SN/A writeQueue.push_back(dram_pkt); 4879831SN/A 4889832SN/A // Update stats 4899832SN/A avgWrQLen = writeQueue.size(); 4909977SN/A } else { 4919977SN/A // keep track of the fact that this burst effectively 4929977SN/A // disappeared as it was merged with an existing one 4939977SN/A mergedWrBursts++; 4949832SN/A } 4959832SN/A 4969831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 4979831SN/A addr = (addr | (burstSize - 1)) + 1; 4989831SN/A } 4999243SN/A 5009243SN/A // we do not wait for the writes to be send to the actual memory, 5019243SN/A // but instead take responsibility for the consistency here and 5029243SN/A // snoop the write queue for any upcoming reads 5039831SN/A // @todo, if a pkt size is larger than burst size, we might need a 5049831SN/A // different front end latency 5059726SN/A accessAndRespond(pkt, frontendLatency); 5069243SN/A 50710206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 50810206Sandreas.hansson@arm.com // queue, do so now 50910206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 51010206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 51110206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 5129243SN/A } 5139243SN/A} 5149243SN/A 5159243SN/Avoid 51610146Sandreas.hansson@arm.comDRAMCtrl::printParams() const 5179243SN/A{ 5189243SN/A // Sanity check print of important parameters 5199243SN/A DPRINTF(DRAM, 5209243SN/A "Memory controller %s physical organization\n" \ 5219831SN/A "Number of devices per rank %d\n" \ 5229831SN/A "Device bus width (in bits) %d\n" \ 52310143SN/A "DRAM data bus burst (bytes) %d\n" \ 52410143SN/A "Row buffer size (bytes) %d\n" \ 5259831SN/A "Columns per row buffer %d\n" \ 5269831SN/A "Rows per bank %d\n" \ 5279831SN/A "Banks per rank %d\n" \ 5289831SN/A "Ranks per channel %d\n" \ 52910143SN/A "Total mem capacity (bytes) %u\n", 5309831SN/A name(), devicesPerRank, deviceBusWidth, burstSize, rowBufferSize, 5319831SN/A columnsPerRowBuffer, rowsPerBank, banksPerRank, ranksPerChannel, 5329831SN/A rowBufferSize * rowsPerBank * banksPerRank * ranksPerChannel); 5339243SN/A 5349243SN/A string scheduler = memSchedPolicy == Enums::fcfs ? "FCFS" : "FR-FCFS"; 53510136SN/A string address_mapping = addrMapping == Enums::RoRaBaChCo ? "RoRaBaChCo" : 53610136SN/A (addrMapping == Enums::RoRaBaCoCh ? "RoRaBaCoCh" : "RoCoRaBaCh"); 5379973SN/A string page_policy = pageMgmt == Enums::open ? "OPEN" : 53810144SN/A (pageMgmt == Enums::open_adaptive ? "OPEN (adaptive)" : 53910144SN/A (pageMgmt == Enums::close_adaptive ? "CLOSE (adaptive)" : "CLOSE")); 5409243SN/A 5419243SN/A DPRINTF(DRAM, 5429243SN/A "Memory controller %s characteristics\n" \ 5439243SN/A "Read buffer size %d\n" \ 5449243SN/A "Write buffer size %d\n" \ 54510140SN/A "Write high thresh %d\n" \ 54610140SN/A "Write low thresh %d\n" \ 5479243SN/A "Scheduler %s\n" \ 5489243SN/A "Address mapping %s\n" \ 5499243SN/A "Page policy %s\n", 5509972SN/A name(), readBufferSize, writeBufferSize, writeHighThreshold, 55110140SN/A writeLowThreshold, scheduler, address_mapping, page_policy); 5529243SN/A 5539243SN/A DPRINTF(DRAM, "Memory controller %s timing specs\n" \ 5549567SN/A "tRCD %d ticks\n" \ 5559567SN/A "tCL %d ticks\n" \ 5569567SN/A "tRP %d ticks\n" \ 5579567SN/A "tBURST %d ticks\n" \ 5589567SN/A "tRFC %d ticks\n" \ 5599567SN/A "tREFI %d ticks\n" \ 5609567SN/A "tWTR %d ticks\n" \ 56110206Sandreas.hansson@arm.com "tRTW %d ticks\n" \ 56210210Sandreas.hansson@arm.com "tWR %d ticks\n" \ 56310212Sandreas.hansson@arm.com "tRTP %d ticks\n" \ 5649567SN/A "tXAW (%d) %d ticks\n", 5659567SN/A name(), tRCD, tCL, tRP, tBURST, tRFC, tREFI, tWTR, 56610212Sandreas.hansson@arm.com tRTW, tWR, tRTP, activationLimit, tXAW); 5679243SN/A} 5689243SN/A 5699243SN/Avoid 57010146Sandreas.hansson@arm.comDRAMCtrl::printQs() const { 5719243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 5729833SN/A for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 5739243SN/A DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 5749243SN/A } 5759243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 5769833SN/A for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 5779243SN/A DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 5789243SN/A } 5799243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 5809833SN/A for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 5819243SN/A DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 5829243SN/A } 5839243SN/A} 5849243SN/A 5859243SN/Abool 58610146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 5879243SN/A{ 5889349SN/A /// @todo temporary hack to deal with memory corruption issues until 5899349SN/A /// 4-phase transactions are complete 5909349SN/A for (int x = 0; x < pendingDelete.size(); x++) 5919349SN/A delete pendingDelete[x]; 5929349SN/A pendingDelete.clear(); 5939349SN/A 5949243SN/A // This is where we enter from the outside world 5959567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 5969831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 5979243SN/A 5989567SN/A // simply drop inhibited packets for now 5999567SN/A if (pkt->memInhibitAsserted()) { 60010143SN/A DPRINTF(DRAM, "Inhibited packet -- Dropping it now\n"); 6019567SN/A pendingDelete.push_back(pkt); 6029567SN/A return true; 6039567SN/A } 6049243SN/A 6059243SN/A // Calc avg gap between requests 6069243SN/A if (prevArrival != 0) { 6079243SN/A totGap += curTick() - prevArrival; 6089243SN/A } 6099243SN/A prevArrival = curTick(); 6109243SN/A 6119831SN/A 6129831SN/A // Find out how many dram packets a pkt translates to 6139831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 6149831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 6159831SN/A // multiple dram packets 6169243SN/A unsigned size = pkt->getSize(); 6179831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 6189831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 6199243SN/A 6209243SN/A // check local buffers and do not accept if full 6219243SN/A if (pkt->isRead()) { 6229567SN/A assert(size != 0); 6239831SN/A if (readQueueFull(dram_pkt_count)) { 6249567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 6259243SN/A // remember that we have to retry this port 6269243SN/A retryRdReq = true; 6279243SN/A numRdRetry++; 6289243SN/A return false; 6299243SN/A } else { 6309831SN/A addToReadQueue(pkt, dram_pkt_count); 6319243SN/A readReqs++; 6329977SN/A bytesReadSys += size; 6339243SN/A } 6349243SN/A } else if (pkt->isWrite()) { 6359567SN/A assert(size != 0); 6369831SN/A if (writeQueueFull(dram_pkt_count)) { 6379567SN/A DPRINTF(DRAM, "Write queue full, not accepting\n"); 6389243SN/A // remember that we have to retry this port 6399243SN/A retryWrReq = true; 6409243SN/A numWrRetry++; 6419243SN/A return false; 6429243SN/A } else { 6439831SN/A addToWriteQueue(pkt, dram_pkt_count); 6449243SN/A writeReqs++; 6459977SN/A bytesWrittenSys += size; 6469243SN/A } 6479243SN/A } else { 6489243SN/A DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 6499243SN/A neitherReadNorWrite++; 6509726SN/A accessAndRespond(pkt, 1); 6519243SN/A } 6529243SN/A 6539243SN/A return true; 6549243SN/A} 6559243SN/A 6569243SN/Avoid 65710146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 6589243SN/A{ 6599243SN/A DPRINTF(DRAM, 6609243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 6619243SN/A 6629831SN/A DRAMPacket* dram_pkt = respQueue.front(); 6639243SN/A 6649831SN/A if (dram_pkt->burstHelper) { 6659831SN/A // it is a split packet 6669831SN/A dram_pkt->burstHelper->burstsServiced++; 6679831SN/A if (dram_pkt->burstHelper->burstsServiced == 66810143SN/A dram_pkt->burstHelper->burstCount) { 6699831SN/A // we have now serviced all children packets of a system packet 6709831SN/A // so we can now respond to the requester 6719831SN/A // @todo we probably want to have a different front end and back 6729831SN/A // end latency for split packets 6739831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6749831SN/A delete dram_pkt->burstHelper; 6759831SN/A dram_pkt->burstHelper = NULL; 6769831SN/A } 6779831SN/A } else { 6789831SN/A // it is not a split packet 6799831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6809831SN/A } 6819243SN/A 6829831SN/A delete respQueue.front(); 6839831SN/A respQueue.pop_front(); 6849243SN/A 6859831SN/A if (!respQueue.empty()) { 6869831SN/A assert(respQueue.front()->readyTime >= curTick()); 6879831SN/A assert(!respondEvent.scheduled()); 6889831SN/A schedule(respondEvent, respQueue.front()->readyTime); 6899831SN/A } else { 6909831SN/A // if there is nothing left in any queue, signal a drain 6919831SN/A if (writeQueue.empty() && readQueue.empty() && 6929831SN/A drainManager) { 6939831SN/A drainManager->signalDrainDone(); 6949831SN/A drainManager = NULL; 6959831SN/A } 6969831SN/A } 6979567SN/A 6989831SN/A // We have made a location in the queue available at this point, 6999831SN/A // so if there is a read that was forced to wait, retry now 7009831SN/A if (retryRdReq) { 7019831SN/A retryRdReq = false; 7029831SN/A port.sendRetry(); 7039831SN/A } 7049243SN/A} 7059243SN/A 7069243SN/Avoid 70710206Sandreas.hansson@arm.comDRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue) 7089243SN/A{ 70910206Sandreas.hansson@arm.com // This method does the arbitration between requests. The chosen 71010206Sandreas.hansson@arm.com // packet is simply moved to the head of the queue. The other 71110206Sandreas.hansson@arm.com // methods know that this is the place to look. For example, with 71210206Sandreas.hansson@arm.com // FCFS, this method does nothing 71310206Sandreas.hansson@arm.com assert(!queue.empty()); 7149243SN/A 71510206Sandreas.hansson@arm.com if (queue.size() == 1) { 71610206Sandreas.hansson@arm.com DPRINTF(DRAM, "Single request, nothing to do\n"); 7179243SN/A return; 7189243SN/A } 7199243SN/A 7209243SN/A if (memSchedPolicy == Enums::fcfs) { 7219243SN/A // Do nothing, since the correct request is already head 7229243SN/A } else if (memSchedPolicy == Enums::frfcfs) { 72310206Sandreas.hansson@arm.com reorderQueue(queue); 7249243SN/A } else 7259243SN/A panic("No scheduling policy chosen\n"); 7269243SN/A} 7279243SN/A 7289243SN/Avoid 72910146Sandreas.hansson@arm.comDRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue) 7309974SN/A{ 7319974SN/A // Only determine this when needed 7329974SN/A uint64_t earliest_banks = 0; 7339974SN/A 7349974SN/A // Search for row hits first, if no row hit is found then schedule the 7359974SN/A // packet to one of the earliest banks available 7369974SN/A bool found_earliest_pkt = false; 7379974SN/A auto selected_pkt_it = queue.begin(); 7389974SN/A 7399974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 7409974SN/A DRAMPacket* dram_pkt = *i; 7419974SN/A const Bank& bank = dram_pkt->bankRef; 7429974SN/A // Check if it is a row hit 7439974SN/A if (bank.openRow == dram_pkt->row) { 74410211Sandreas.hansson@arm.com // FCFS within the hits 7459974SN/A DPRINTF(DRAM, "Row buffer hit\n"); 7469974SN/A selected_pkt_it = i; 7479974SN/A break; 7489974SN/A } else if (!found_earliest_pkt) { 7499974SN/A // No row hit, go for first ready 7509974SN/A if (earliest_banks == 0) 75110211Sandreas.hansson@arm.com earliest_banks = minBankActAt(queue); 75210211Sandreas.hansson@arm.com 75310211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue an 75410211Sandreas.hansson@arm.com // activate, this is calculated in minBankActAt and could 75510211Sandreas.hansson@arm.com // be cached 75610211Sandreas.hansson@arm.com Tick act_at = bank.openRow == Bank::NO_ROW ? 75710211Sandreas.hansson@arm.com bank.actAllowedAt : 75810211Sandreas.hansson@arm.com std::max(bank.preAllowedAt, curTick()) + tRP; 7599974SN/A 7609974SN/A // Bank is ready or is the first available bank 76110211Sandreas.hansson@arm.com if (act_at <= curTick() || 7629974SN/A bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) { 7639974SN/A // Remember the packet to be scheduled to one of the earliest 76410211Sandreas.hansson@arm.com // banks available, FCFS amongst the earliest banks 7659974SN/A selected_pkt_it = i; 7669974SN/A found_earliest_pkt = true; 7679974SN/A } 7689974SN/A } 7699974SN/A } 7709974SN/A 7719974SN/A DRAMPacket* selected_pkt = *selected_pkt_it; 7729974SN/A queue.erase(selected_pkt_it); 7739974SN/A queue.push_front(selected_pkt); 7749974SN/A} 7759974SN/A 7769974SN/Avoid 77710146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 7789243SN/A{ 7799243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 7809243SN/A 7819243SN/A bool needsResponse = pkt->needsResponse(); 7829243SN/A // do the actual memory access which also turns the packet into a 7839243SN/A // response 7849243SN/A access(pkt); 7859243SN/A 7869243SN/A // turn packet around to go back to requester if response expected 7879243SN/A if (needsResponse) { 7889243SN/A // access already turned the packet into a response 7899243SN/A assert(pkt->isResponse()); 7909243SN/A 7919549SN/A // @todo someone should pay for this 7929549SN/A pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; 7939549SN/A 7949726SN/A // queue the packet in the response queue to be sent out after 7959726SN/A // the static latency has passed 7969726SN/A port.schedTimingResp(pkt, curTick() + static_latency); 7979243SN/A } else { 7989587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 7999587SN/A // is still having a pointer to it 8009587SN/A pendingDelete.push_back(pkt); 8019243SN/A } 8029243SN/A 8039243SN/A DPRINTF(DRAM, "Done\n"); 8049243SN/A 8059243SN/A return; 8069243SN/A} 8079243SN/A 8089243SN/Avoid 80910210Sandreas.hansson@arm.comDRAMCtrl::activateBank(Tick act_tick, uint8_t rank, uint8_t bank, 81010210Sandreas.hansson@arm.com uint16_t row, Bank& bank_ref) 8119488SN/A{ 8129969SN/A assert(0 <= rank && rank < ranksPerChannel); 8139969SN/A assert(actTicks[rank].size() == activationLimit); 8149488SN/A 8159488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 8169488SN/A 81710207Sandreas.hansson@arm.com // update the open row 81810210Sandreas.hansson@arm.com assert(bank_ref.openRow == Bank::NO_ROW); 81910210Sandreas.hansson@arm.com bank_ref.openRow = row; 82010207Sandreas.hansson@arm.com 82110207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 82210207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 82310207Sandreas.hansson@arm.com // precharge 82410210Sandreas.hansson@arm.com bank_ref.bytesAccessed = 0; 82510210Sandreas.hansson@arm.com bank_ref.rowAccesses = 0; 82610207Sandreas.hansson@arm.com 82710207Sandreas.hansson@arm.com ++numBanksActive; 82810207Sandreas.hansson@arm.com assert(numBanksActive <= banksPerRank * ranksPerChannel); 82910207Sandreas.hansson@arm.com 83010207Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank at tick %lld, now got %d active\n", 83110207Sandreas.hansson@arm.com act_tick, numBanksActive); 8329975SN/A 83310211Sandreas.hansson@arm.com // The next access has to respect tRAS for this bank 83410211Sandreas.hansson@arm.com bank_ref.preAllowedAt = act_tick + tRAS; 83510211Sandreas.hansson@arm.com 83610211Sandreas.hansson@arm.com // Respect the row-to-column command delay 83710211Sandreas.hansson@arm.com bank_ref.colAllowedAt = act_tick + tRCD; 83810211Sandreas.hansson@arm.com 8399971SN/A // start by enforcing tRRD 8409971SN/A for(int i = 0; i < banksPerRank; i++) { 84110210Sandreas.hansson@arm.com // next activate to any bank in this rank must not happen 84210210Sandreas.hansson@arm.com // before tRRD 84310210Sandreas.hansson@arm.com banks[rank][i].actAllowedAt = std::max(act_tick + tRRD, 84410210Sandreas.hansson@arm.com banks[rank][i].actAllowedAt); 8459971SN/A } 84610208Sandreas.hansson@arm.com 8479971SN/A // next, we deal with tXAW, if the activation limit is disabled 8489971SN/A // then we are done 8499969SN/A if (actTicks[rank].empty()) 8509824SN/A return; 8519824SN/A 8529488SN/A // sanity check 8539969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 85410210Sandreas.hansson@arm.com panic("Got %d activates in window %d (%llu - %llu) which is smaller " 85510210Sandreas.hansson@arm.com "than %llu\n", activationLimit, act_tick - actTicks[rank].back(), 85610210Sandreas.hansson@arm.com act_tick, actTicks[rank].back(), tXAW); 8579488SN/A } 8589488SN/A 8599488SN/A // shift the times used for the book keeping, the last element 8609488SN/A // (highest index) is the oldest one and hence the lowest value 8619969SN/A actTicks[rank].pop_back(); 8629488SN/A 8639488SN/A // record an new activation (in the future) 8649969SN/A actTicks[rank].push_front(act_tick); 8659488SN/A 8669488SN/A // cannot activate more than X times in time window tXAW, push the 8679488SN/A // next one (the X + 1'st activate) to be tXAW away from the 8689488SN/A // oldest in our window of X 8699969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 8709488SN/A DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate no earlier " 87110210Sandreas.hansson@arm.com "than %llu\n", activationLimit, actTicks[rank].back() + tXAW); 8729488SN/A for(int j = 0; j < banksPerRank; j++) 8739488SN/A // next activate must not happen before end of window 87410210Sandreas.hansson@arm.com banks[rank][j].actAllowedAt = 87510210Sandreas.hansson@arm.com std::max(actTicks[rank].back() + tXAW, 87610210Sandreas.hansson@arm.com banks[rank][j].actAllowedAt); 8779488SN/A } 87810208Sandreas.hansson@arm.com 87910208Sandreas.hansson@arm.com // at the point when this activate takes place, make sure we 88010208Sandreas.hansson@arm.com // transition to the active power state 88110208Sandreas.hansson@arm.com if (!activateEvent.scheduled()) 88210208Sandreas.hansson@arm.com schedule(activateEvent, act_tick); 88310208Sandreas.hansson@arm.com else if (activateEvent.when() > act_tick) 88410208Sandreas.hansson@arm.com // move it sooner in time 88510208Sandreas.hansson@arm.com reschedule(activateEvent, act_tick); 88610208Sandreas.hansson@arm.com} 88710208Sandreas.hansson@arm.com 88810208Sandreas.hansson@arm.comvoid 88910208Sandreas.hansson@arm.comDRAMCtrl::processActivateEvent() 89010208Sandreas.hansson@arm.com{ 89110208Sandreas.hansson@arm.com // we should transition to the active state as soon as any bank is active 89210208Sandreas.hansson@arm.com if (pwrState != PWR_ACT) 89310208Sandreas.hansson@arm.com // note that at this point numBanksActive could be back at 89410208Sandreas.hansson@arm.com // zero again due to a precharge scheduled in the future 89510208Sandreas.hansson@arm.com schedulePowerEvent(PWR_ACT, curTick()); 8969488SN/A} 8979488SN/A 8989488SN/Avoid 89910211Sandreas.hansson@arm.comDRAMCtrl::prechargeBank(Bank& bank, Tick pre_at) 90010207Sandreas.hansson@arm.com{ 90110207Sandreas.hansson@arm.com // make sure the bank has an open row 90210207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 90310207Sandreas.hansson@arm.com 90410207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 90510207Sandreas.hansson@arm.com // the page 90610207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 90710207Sandreas.hansson@arm.com 90810207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 90910207Sandreas.hansson@arm.com 91010211Sandreas.hansson@arm.com Tick pre_done_at = pre_at + tRP; 91110211Sandreas.hansson@arm.com 91210211Sandreas.hansson@arm.com bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at); 91310207Sandreas.hansson@arm.com 91410207Sandreas.hansson@arm.com assert(numBanksActive != 0); 91510207Sandreas.hansson@arm.com --numBanksActive; 91610207Sandreas.hansson@arm.com 91710211Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging bank at tick %lld, now got %d active\n", 91810211Sandreas.hansson@arm.com pre_at, numBanksActive); 91910207Sandreas.hansson@arm.com 92010208Sandreas.hansson@arm.com // if we look at the current number of active banks we might be 92110208Sandreas.hansson@arm.com // tempted to think the DRAM is now idle, however this can be 92210208Sandreas.hansson@arm.com // undone by an activate that is scheduled to happen before we 92310208Sandreas.hansson@arm.com // would have reached the idle state, so schedule an event and 92410208Sandreas.hansson@arm.com // rather check once we actually make it to the point in time when 92510208Sandreas.hansson@arm.com // the (last) precharge takes place 92610208Sandreas.hansson@arm.com if (!prechargeEvent.scheduled()) 92710211Sandreas.hansson@arm.com schedule(prechargeEvent, pre_done_at); 92810211Sandreas.hansson@arm.com else if (prechargeEvent.when() < pre_done_at) 92910211Sandreas.hansson@arm.com reschedule(prechargeEvent, pre_done_at); 93010208Sandreas.hansson@arm.com} 93110208Sandreas.hansson@arm.com 93210208Sandreas.hansson@arm.comvoid 93310208Sandreas.hansson@arm.comDRAMCtrl::processPrechargeEvent() 93410208Sandreas.hansson@arm.com{ 93510207Sandreas.hansson@arm.com // if we reached zero, then special conditions apply as we track 93610207Sandreas.hansson@arm.com // if all banks are precharged for the power models 93710207Sandreas.hansson@arm.com if (numBanksActive == 0) { 93810208Sandreas.hansson@arm.com // we should transition to the idle state when the last bank 93910208Sandreas.hansson@arm.com // is precharged 94010208Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 94110207Sandreas.hansson@arm.com } 94210207Sandreas.hansson@arm.com} 94310207Sandreas.hansson@arm.com 94410207Sandreas.hansson@arm.comvoid 94510146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 9469243SN/A{ 9479243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 9489243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 9499243SN/A 95010211Sandreas.hansson@arm.com // get the bank 9519967SN/A Bank& bank = dram_pkt->bankRef; 9529243SN/A 95310211Sandreas.hansson@arm.com // for the state we need to track if it is a row hit or not 95410211Sandreas.hansson@arm.com bool row_hit = true; 95510211Sandreas.hansson@arm.com 95610211Sandreas.hansson@arm.com // respect any constraints on the command (e.g. tRCD or tCCD) 95710211Sandreas.hansson@arm.com Tick cmd_at = std::max(bank.colAllowedAt, curTick()); 95810211Sandreas.hansson@arm.com 95910211Sandreas.hansson@arm.com // Determine the access latency and update the bank state 96010211Sandreas.hansson@arm.com if (bank.openRow == dram_pkt->row) { 96110211Sandreas.hansson@arm.com // nothing to do 96210209Sandreas.hansson@arm.com } else { 96310211Sandreas.hansson@arm.com row_hit = false; 96410211Sandreas.hansson@arm.com 96510209Sandreas.hansson@arm.com // If there is a page open, precharge it. 96610209Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 96710211Sandreas.hansson@arm.com prechargeBank(bank, std::max(bank.preAllowedAt, curTick())); 9689488SN/A } 9699973SN/A 97010211Sandreas.hansson@arm.com // next we need to account for the delay in activating the 97110211Sandreas.hansson@arm.com // page 97210211Sandreas.hansson@arm.com Tick act_tick = std::max(bank.actAllowedAt, curTick()); 9739973SN/A 97410210Sandreas.hansson@arm.com // Record the activation and deal with all the global timing 97510210Sandreas.hansson@arm.com // constraints caused be a new activation (tRRD and tXAW) 97610211Sandreas.hansson@arm.com activateBank(act_tick, dram_pkt->rank, dram_pkt->bank, 97710210Sandreas.hansson@arm.com dram_pkt->row, bank); 97810210Sandreas.hansson@arm.com 97910211Sandreas.hansson@arm.com // issue the command as early as possible 98010211Sandreas.hansson@arm.com cmd_at = bank.colAllowedAt; 98110209Sandreas.hansson@arm.com } 98210209Sandreas.hansson@arm.com 98310211Sandreas.hansson@arm.com // we need to wait until the bus is available before we can issue 98410211Sandreas.hansson@arm.com // the command 98510211Sandreas.hansson@arm.com cmd_at = std::max(cmd_at, busBusyUntil - tCL); 98610211Sandreas.hansson@arm.com 98710211Sandreas.hansson@arm.com // update the packet ready time 98810211Sandreas.hansson@arm.com dram_pkt->readyTime = cmd_at + tCL + tBURST; 98910211Sandreas.hansson@arm.com 99010211Sandreas.hansson@arm.com // only one burst can use the bus at any one point in time 99110211Sandreas.hansson@arm.com assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 99210211Sandreas.hansson@arm.com 99310211Sandreas.hansson@arm.com // not strictly necessary, but update the time for the next 99410211Sandreas.hansson@arm.com // read/write (add a max with tCCD here) 99510211Sandreas.hansson@arm.com bank.colAllowedAt = cmd_at + tBURST; 99610211Sandreas.hansson@arm.com 99710212Sandreas.hansson@arm.com // If this is a write, we also need to respect the write recovery 99810212Sandreas.hansson@arm.com // time before a precharge, in the case of a read, respect the 99910212Sandreas.hansson@arm.com // read to precharge constraint 100010212Sandreas.hansson@arm.com bank.preAllowedAt = std::max(bank.preAllowedAt, 100110212Sandreas.hansson@arm.com dram_pkt->isRead ? cmd_at + tRTP : 100210212Sandreas.hansson@arm.com dram_pkt->readyTime + tWR); 100310210Sandreas.hansson@arm.com 100410209Sandreas.hansson@arm.com // increment the bytes accessed and the accesses per row 100510209Sandreas.hansson@arm.com bank.bytesAccessed += burstSize; 100610209Sandreas.hansson@arm.com ++bank.rowAccesses; 100710209Sandreas.hansson@arm.com 100810209Sandreas.hansson@arm.com // if we reached the max, then issue with an auto-precharge 100910209Sandreas.hansson@arm.com bool auto_precharge = pageMgmt == Enums::close || 101010209Sandreas.hansson@arm.com bank.rowAccesses == maxAccessesPerRow; 101110209Sandreas.hansson@arm.com 101210209Sandreas.hansson@arm.com // if we did not hit the limit, we might still want to 101310209Sandreas.hansson@arm.com // auto-precharge 101410209Sandreas.hansson@arm.com if (!auto_precharge && 101510209Sandreas.hansson@arm.com (pageMgmt == Enums::open_adaptive || 101610209Sandreas.hansson@arm.com pageMgmt == Enums::close_adaptive)) { 101710209Sandreas.hansson@arm.com // a twist on the open and close page policies: 101810209Sandreas.hansson@arm.com // 1) open_adaptive page policy does not blindly keep the 101910209Sandreas.hansson@arm.com // page open, but close it if there are no row hits, and there 102010209Sandreas.hansson@arm.com // are bank conflicts in the queue 102110209Sandreas.hansson@arm.com // 2) close_adaptive page policy does not blindly close the 102210209Sandreas.hansson@arm.com // page, but closes it only if there are no row hits in the queue. 102310209Sandreas.hansson@arm.com // In this case, only force an auto precharge when there 102410209Sandreas.hansson@arm.com // are no same page hits in the queue 102510209Sandreas.hansson@arm.com bool got_more_hits = false; 102610209Sandreas.hansson@arm.com bool got_bank_conflict = false; 102710209Sandreas.hansson@arm.com 102810209Sandreas.hansson@arm.com // either look at the read queue or write queue 102910209Sandreas.hansson@arm.com const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 103010209Sandreas.hansson@arm.com writeQueue; 103110209Sandreas.hansson@arm.com auto p = queue.begin(); 103210209Sandreas.hansson@arm.com // make sure we are not considering the packet that we are 103310209Sandreas.hansson@arm.com // currently dealing with (which is the head of the queue) 103410209Sandreas.hansson@arm.com ++p; 103510209Sandreas.hansson@arm.com 103610209Sandreas.hansson@arm.com // keep on looking until we have found required condition or 103710209Sandreas.hansson@arm.com // reached the end 103810209Sandreas.hansson@arm.com while (!(got_more_hits && 103910209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive)) && 104010209Sandreas.hansson@arm.com p != queue.end()) { 104110209Sandreas.hansson@arm.com bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 104210209Sandreas.hansson@arm.com (dram_pkt->bank == (*p)->bank); 104310209Sandreas.hansson@arm.com bool same_row = dram_pkt->row == (*p)->row; 104410209Sandreas.hansson@arm.com got_more_hits |= same_rank_bank && same_row; 104510209Sandreas.hansson@arm.com got_bank_conflict |= same_rank_bank && !same_row; 10469973SN/A ++p; 104710141SN/A } 104810141SN/A 104910209Sandreas.hansson@arm.com // auto pre-charge when either 105010209Sandreas.hansson@arm.com // 1) open_adaptive policy, we have not got any more hits, and 105110209Sandreas.hansson@arm.com // have a bank conflict 105210209Sandreas.hansson@arm.com // 2) close_adaptive policy and we have not got any more hits 105310209Sandreas.hansson@arm.com auto_precharge = !got_more_hits && 105410209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive); 105510209Sandreas.hansson@arm.com } 105610142SN/A 105710209Sandreas.hansson@arm.com // if this access should use auto-precharge, then we are 105810209Sandreas.hansson@arm.com // closing the row 105910209Sandreas.hansson@arm.com if (auto_precharge) { 106010211Sandreas.hansson@arm.com prechargeBank(bank, std::max(curTick(), bank.preAllowedAt)); 10619973SN/A 106210209Sandreas.hansson@arm.com DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 106310209Sandreas.hansson@arm.com } 10649963SN/A 10659243SN/A // Update bus state 10669243SN/A busBusyUntil = dram_pkt->readyTime; 10679243SN/A 106810211Sandreas.hansson@arm.com DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n", 106910211Sandreas.hansson@arm.com dram_pkt->addr, dram_pkt->readyTime, busBusyUntil); 10709243SN/A 107110206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 107210206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 107310206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 107410206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 107510206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 10769972SN/A 107710206Sandreas.hansson@arm.com // Update the stats and schedule the next request 10789977SN/A if (dram_pkt->isRead) { 107910147Sandreas.hansson@arm.com ++readsThisTime; 108010211Sandreas.hansson@arm.com if (row_hit) 10819977SN/A readRowHits++; 10829977SN/A bytesReadDRAM += burstSize; 10839977SN/A perBankRdBursts[dram_pkt->bankId]++; 108410206Sandreas.hansson@arm.com 108510206Sandreas.hansson@arm.com // Update latency stats 108610206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 108710206Sandreas.hansson@arm.com totBusLat += tBURST; 108810211Sandreas.hansson@arm.com totQLat += cmd_at - dram_pkt->entryTime; 10899977SN/A } else { 109010147Sandreas.hansson@arm.com ++writesThisTime; 109110211Sandreas.hansson@arm.com if (row_hit) 10929977SN/A writeRowHits++; 10939977SN/A bytesWritten += burstSize; 10949977SN/A perBankWrBursts[dram_pkt->bankId]++; 10959243SN/A } 10969243SN/A} 10979243SN/A 10989243SN/Avoid 109910146Sandreas.hansson@arm.comDRAMCtrl::moveToRespQ() 11009243SN/A{ 11019243SN/A // Remove from read queue 11029567SN/A DRAMPacket* dram_pkt = readQueue.front(); 11039567SN/A readQueue.pop_front(); 11049243SN/A 11059832SN/A // sanity check 11069832SN/A assert(dram_pkt->size <= burstSize); 11079832SN/A 11089243SN/A // Insert into response queue sorted by readyTime 11099243SN/A // It will be sent back to the requestor at its 11109243SN/A // readyTime 11119567SN/A if (respQueue.empty()) { 11129567SN/A respQueue.push_front(dram_pkt); 11139243SN/A assert(!respondEvent.scheduled()); 11149243SN/A assert(dram_pkt->readyTime >= curTick()); 11159567SN/A schedule(respondEvent, dram_pkt->readyTime); 11169243SN/A } else { 11179243SN/A bool done = false; 11189833SN/A auto i = respQueue.begin(); 11199567SN/A while (!done && i != respQueue.end()) { 11209243SN/A if ((*i)->readyTime > dram_pkt->readyTime) { 11219567SN/A respQueue.insert(i, dram_pkt); 11229243SN/A done = true; 11239243SN/A } 11249243SN/A ++i; 11259243SN/A } 11269243SN/A 11279243SN/A if (!done) 11289567SN/A respQueue.push_back(dram_pkt); 11299243SN/A 11309243SN/A assert(respondEvent.scheduled()); 11319243SN/A 11329567SN/A if (respQueue.front()->readyTime < respondEvent.when()) { 11339567SN/A assert(respQueue.front()->readyTime >= curTick()); 11349567SN/A reschedule(respondEvent, respQueue.front()->readyTime); 11359243SN/A } 11369243SN/A } 11379243SN/A} 11389243SN/A 11399243SN/Avoid 114010206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 11419243SN/A{ 114210206Sandreas.hansson@arm.com if (busState == READ_TO_WRITE) { 114310206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 114410206Sandreas.hansson@arm.com "waiting\n", readsThisTime, readQueue.size()); 11459243SN/A 114610206Sandreas.hansson@arm.com // sample and reset the read-related stats as we are now 114710206Sandreas.hansson@arm.com // transitioning to writes, and all reads are done 114810206Sandreas.hansson@arm.com rdPerTurnAround.sample(readsThisTime); 114910206Sandreas.hansson@arm.com readsThisTime = 0; 115010206Sandreas.hansson@arm.com 115110206Sandreas.hansson@arm.com // now proceed to do the actual writes 115210206Sandreas.hansson@arm.com busState = WRITE; 115310206Sandreas.hansson@arm.com } else if (busState == WRITE_TO_READ) { 115410206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 115510206Sandreas.hansson@arm.com "waiting\n", writesThisTime, writeQueue.size()); 115610206Sandreas.hansson@arm.com 115710206Sandreas.hansson@arm.com wrPerTurnAround.sample(writesThisTime); 115810206Sandreas.hansson@arm.com writesThisTime = 0; 115910206Sandreas.hansson@arm.com 116010206Sandreas.hansson@arm.com busState = READ; 116110206Sandreas.hansson@arm.com } 116210206Sandreas.hansson@arm.com 116310207Sandreas.hansson@arm.com if (refreshState != REF_IDLE) { 116410207Sandreas.hansson@arm.com // if a refresh waiting for this event loop to finish, then hand 116510207Sandreas.hansson@arm.com // over now, and do not schedule a new nextReqEvent 116610207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 116710207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 116810207Sandreas.hansson@arm.com 116910207Sandreas.hansson@arm.com refreshState = REF_PRE; 117010207Sandreas.hansson@arm.com 117110207Sandreas.hansson@arm.com // hand control back to the refresh event loop 117210207Sandreas.hansson@arm.com schedule(refreshEvent, curTick()); 117310207Sandreas.hansson@arm.com } 117410207Sandreas.hansson@arm.com 117510207Sandreas.hansson@arm.com // let the refresh finish before issuing any further requests 117610207Sandreas.hansson@arm.com return; 117710207Sandreas.hansson@arm.com } 117810207Sandreas.hansson@arm.com 117910206Sandreas.hansson@arm.com // when we get here it is either a read or a write 118010206Sandreas.hansson@arm.com if (busState == READ) { 118110206Sandreas.hansson@arm.com 118210206Sandreas.hansson@arm.com // track if we should switch or not 118310206Sandreas.hansson@arm.com bool switch_to_writes = false; 118410206Sandreas.hansson@arm.com 118510206Sandreas.hansson@arm.com if (readQueue.empty()) { 118610206Sandreas.hansson@arm.com // In the case there is no read request to go next, 118710206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 118810206Sandreas.hansson@arm.com // if we are draining) 118910206Sandreas.hansson@arm.com if (!writeQueue.empty() && 119010206Sandreas.hansson@arm.com (drainManager || writeQueue.size() > writeLowThreshold)) { 119110206Sandreas.hansson@arm.com 119210206Sandreas.hansson@arm.com switch_to_writes = true; 119310206Sandreas.hansson@arm.com } else { 119410206Sandreas.hansson@arm.com // check if we are drained 119510206Sandreas.hansson@arm.com if (respQueue.empty () && drainManager) { 119610206Sandreas.hansson@arm.com drainManager->signalDrainDone(); 119710206Sandreas.hansson@arm.com drainManager = NULL; 119810206Sandreas.hansson@arm.com } 119910206Sandreas.hansson@arm.com 120010206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 120110206Sandreas.hansson@arm.com // event for the next request 120210206Sandreas.hansson@arm.com return; 120310206Sandreas.hansson@arm.com } 120410206Sandreas.hansson@arm.com } else { 120510206Sandreas.hansson@arm.com // Figure out which read request goes next, and move it to the 120610206Sandreas.hansson@arm.com // front of the read queue 120710206Sandreas.hansson@arm.com chooseNext(readQueue); 120810206Sandreas.hansson@arm.com 120910206Sandreas.hansson@arm.com doDRAMAccess(readQueue.front()); 121010206Sandreas.hansson@arm.com 121110206Sandreas.hansson@arm.com // At this point we're done dealing with the request 121210206Sandreas.hansson@arm.com // It will be moved to a separate response queue with a 121310206Sandreas.hansson@arm.com // correct readyTime, and eventually be sent back at that 121410206Sandreas.hansson@arm.com // time 121510206Sandreas.hansson@arm.com moveToRespQ(); 121610206Sandreas.hansson@arm.com 121710206Sandreas.hansson@arm.com // we have so many writes that we have to transition 121810206Sandreas.hansson@arm.com if (writeQueue.size() > writeHighThreshold) { 121910206Sandreas.hansson@arm.com switch_to_writes = true; 122010206Sandreas.hansson@arm.com } 122110206Sandreas.hansson@arm.com } 122210206Sandreas.hansson@arm.com 122310206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 122410206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 122510206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 122610206Sandreas.hansson@arm.com if (switch_to_writes) { 122710206Sandreas.hansson@arm.com // transition to writing 122810206Sandreas.hansson@arm.com busState = READ_TO_WRITE; 122910206Sandreas.hansson@arm.com 123010206Sandreas.hansson@arm.com // add a bubble to the data bus, as defined by the 123110206Sandreas.hansson@arm.com // tRTW parameter 123210206Sandreas.hansson@arm.com busBusyUntil += tRTW; 123310206Sandreas.hansson@arm.com 123410206Sandreas.hansson@arm.com // update the minimum timing between the requests, 123510206Sandreas.hansson@arm.com // this shifts us back in time far enough to do any 123610206Sandreas.hansson@arm.com // bank preparation 123710206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 123810206Sandreas.hansson@arm.com } 12399352SN/A } else { 124010206Sandreas.hansson@arm.com chooseNext(writeQueue); 124110206Sandreas.hansson@arm.com DRAMPacket* dram_pkt = writeQueue.front(); 124210206Sandreas.hansson@arm.com // sanity check 124310206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 124410206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 124510206Sandreas.hansson@arm.com 124610206Sandreas.hansson@arm.com writeQueue.pop_front(); 124710206Sandreas.hansson@arm.com delete dram_pkt; 124810206Sandreas.hansson@arm.com 124910206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 125010206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 125110206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 125210206Sandreas.hansson@arm.com // writes, then switch to reads. 125310206Sandreas.hansson@arm.com if (writeQueue.empty() || 125410206Sandreas.hansson@arm.com (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 125510206Sandreas.hansson@arm.com !drainManager) || 125610206Sandreas.hansson@arm.com (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 125710206Sandreas.hansson@arm.com // turn the bus back around for reads again 125810206Sandreas.hansson@arm.com busState = WRITE_TO_READ; 125910206Sandreas.hansson@arm.com 126010206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 126110206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 126210206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 126310206Sandreas.hansson@arm.com // nothing to do 126410206Sandreas.hansson@arm.com 126510206Sandreas.hansson@arm.com // here we get a bit creative and shift the bus busy time not 126610206Sandreas.hansson@arm.com // just the tWTR, but also a CAS latency to capture the fact 126710206Sandreas.hansson@arm.com // that we are allowed to prepare a new bank, but not issue a 126810206Sandreas.hansson@arm.com // read command until after tWTR, in essence we capture a 126910206Sandreas.hansson@arm.com // bubble on the data bus that is tWTR + tCL 127010206Sandreas.hansson@arm.com busBusyUntil += tWTR + tCL; 127110206Sandreas.hansson@arm.com 127210206Sandreas.hansson@arm.com // update the minimum timing between the requests, this shifts 127310206Sandreas.hansson@arm.com // us back in time far enough to do any bank preparation 127410206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 127510206Sandreas.hansson@arm.com } 127610206Sandreas.hansson@arm.com } 127710206Sandreas.hansson@arm.com 127810206Sandreas.hansson@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 127910206Sandreas.hansson@arm.com 128010206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 128110206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 128210206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 128310206Sandreas.hansson@arm.com // the next request processing 128410206Sandreas.hansson@arm.com if (retryWrReq && writeQueue.size() < writeBufferSize) { 128510206Sandreas.hansson@arm.com retryWrReq = false; 128610206Sandreas.hansson@arm.com port.sendRetry(); 12879352SN/A } 12889243SN/A} 12899243SN/A 12909967SN/Auint64_t 129110211Sandreas.hansson@arm.comDRAMCtrl::minBankActAt(const deque<DRAMPacket*>& queue) const 12929967SN/A{ 12939967SN/A uint64_t bank_mask = 0; 129410211Sandreas.hansson@arm.com Tick min_act_at = MaxTick; 12959967SN/A 129610211Sandreas.hansson@arm.com // deterimne if we have queued transactions targetting a 12979967SN/A // bank in question 12989967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 12999967SN/A for (auto p = queue.begin(); p != queue.end(); ++p) { 13009967SN/A got_waiting[(*p)->bankId] = true; 13019967SN/A } 13029967SN/A 13039967SN/A for (int i = 0; i < ranksPerChannel; i++) { 13049967SN/A for (int j = 0; j < banksPerRank; j++) { 130510211Sandreas.hansson@arm.com uint8_t bank_id = i * banksPerRank + j; 130610211Sandreas.hansson@arm.com 13079967SN/A // if we have waiting requests for the bank, and it is 13089967SN/A // amongst the first available, update the mask 130910211Sandreas.hansson@arm.com if (got_waiting[bank_id]) { 131010211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue 131110211Sandreas.hansson@arm.com // an activate, ignoring any rank-to-rank switching 131210211Sandreas.hansson@arm.com // cost 131310211Sandreas.hansson@arm.com Tick act_at = banks[i][j].openRow == Bank::NO_ROW ? 131410211Sandreas.hansson@arm.com banks[i][j].actAllowedAt : 131510211Sandreas.hansson@arm.com std::max(banks[i][j].preAllowedAt, curTick()) + tRP; 131610211Sandreas.hansson@arm.com 131710211Sandreas.hansson@arm.com if (act_at <= min_act_at) { 131810211Sandreas.hansson@arm.com // reset bank mask if new minimum is found 131910211Sandreas.hansson@arm.com if (act_at < min_act_at) 132010211Sandreas.hansson@arm.com bank_mask = 0; 132110211Sandreas.hansson@arm.com // set the bit corresponding to the available bank 132210211Sandreas.hansson@arm.com replaceBits(bank_mask, bank_id, bank_id, 1); 132310211Sandreas.hansson@arm.com min_act_at = act_at; 132410211Sandreas.hansson@arm.com } 13259967SN/A } 13269967SN/A } 13279967SN/A } 132810211Sandreas.hansson@arm.com 13299967SN/A return bank_mask; 13309967SN/A} 13319967SN/A 13329243SN/Avoid 133310146Sandreas.hansson@arm.comDRAMCtrl::processRefreshEvent() 13349243SN/A{ 133510207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 133610207Sandreas.hansson@arm.com if (refreshState == REF_IDLE) { 133710207Sandreas.hansson@arm.com // remember when the refresh is due 133810207Sandreas.hansson@arm.com refreshDueAt = curTick(); 13399243SN/A 134010207Sandreas.hansson@arm.com // proceed to drain 134110207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 13429243SN/A 134310207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 134410207Sandreas.hansson@arm.com } 134510207Sandreas.hansson@arm.com 134610207Sandreas.hansson@arm.com // let any scheduled read or write go ahead, after which it will 134710207Sandreas.hansson@arm.com // hand control back to this event loop 134810207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 134910207Sandreas.hansson@arm.com if (nextReqEvent.scheduled()) { 135010207Sandreas.hansson@arm.com // hand control over to the request loop until it is 135110207Sandreas.hansson@arm.com // evaluated next 135210207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 135310207Sandreas.hansson@arm.com 135410207Sandreas.hansson@arm.com return; 135510207Sandreas.hansson@arm.com } else { 135610207Sandreas.hansson@arm.com refreshState = REF_PRE; 135710207Sandreas.hansson@arm.com } 135810207Sandreas.hansson@arm.com } 135910207Sandreas.hansson@arm.com 136010207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 136110207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 136210208Sandreas.hansson@arm.com // precharge any active bank if we are not already in the idle 136310208Sandreas.hansson@arm.com // state 136410208Sandreas.hansson@arm.com if (pwrState != PWR_IDLE) { 136510208Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 136610208Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 136710208Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 136810208Sandreas.hansson@arm.com if (banks[i][j].openRow != Bank::NO_ROW) { 136910208Sandreas.hansson@arm.com // respect both causality and any existing bank 137010208Sandreas.hansson@arm.com // constraints 137110211Sandreas.hansson@arm.com Tick pre_at = std::max(banks[i][j].preAllowedAt, 137210211Sandreas.hansson@arm.com curTick()); 137310207Sandreas.hansson@arm.com 137410211Sandreas.hansson@arm.com prechargeBank(banks[i][j], pre_at); 137510208Sandreas.hansson@arm.com } 137610207Sandreas.hansson@arm.com } 137710207Sandreas.hansson@arm.com } 137810208Sandreas.hansson@arm.com } else { 137910208Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 138010208Sandreas.hansson@arm.com 138110208Sandreas.hansson@arm.com // go ahead and kick the power state machine into gear if 138210208Sandreas.hansson@arm.com // we are already idle 138310208Sandreas.hansson@arm.com schedulePowerEvent(PWR_REF, curTick()); 13849975SN/A } 13859975SN/A 138610208Sandreas.hansson@arm.com refreshState = REF_RUN; 138710208Sandreas.hansson@arm.com assert(numBanksActive == 0); 13889243SN/A 138910208Sandreas.hansson@arm.com // wait for all banks to be precharged, at which point the 139010208Sandreas.hansson@arm.com // power state machine will transition to the idle state, and 139110208Sandreas.hansson@arm.com // automatically move to a refresh, at that point it will also 139210208Sandreas.hansson@arm.com // call this method to get the refresh event loop going again 139310207Sandreas.hansson@arm.com return; 139410207Sandreas.hansson@arm.com } 139510207Sandreas.hansson@arm.com 139610207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 139710207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 139810207Sandreas.hansson@arm.com // should never get here with any banks active 139910207Sandreas.hansson@arm.com assert(numBanksActive == 0); 140010208Sandreas.hansson@arm.com assert(pwrState == PWR_REF); 140110207Sandreas.hansson@arm.com 140210211Sandreas.hansson@arm.com Tick ref_done_at = curTick() + tRFC; 140310207Sandreas.hansson@arm.com 140410207Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 140510207Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 140610211Sandreas.hansson@arm.com banks[i][j].actAllowedAt = ref_done_at; 140710207Sandreas.hansson@arm.com } 140810207Sandreas.hansson@arm.com } 140910207Sandreas.hansson@arm.com 141010207Sandreas.hansson@arm.com // make sure we did not wait so long that we cannot make up 141110207Sandreas.hansson@arm.com // for it 141210211Sandreas.hansson@arm.com if (refreshDueAt + tREFI < ref_done_at) { 141310207Sandreas.hansson@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 141410207Sandreas.hansson@arm.com } 141510207Sandreas.hansson@arm.com 141610207Sandreas.hansson@arm.com // compensate for the delay in actually performing the refresh 141710207Sandreas.hansson@arm.com // when scheduling the next one 141810207Sandreas.hansson@arm.com schedule(refreshEvent, refreshDueAt + tREFI - tRP); 141910207Sandreas.hansson@arm.com 142010208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 142110207Sandreas.hansson@arm.com 142210208Sandreas.hansson@arm.com // move to the idle power state once the refresh is done, this 142310208Sandreas.hansson@arm.com // will also move the refresh state machine to the refresh 142410208Sandreas.hansson@arm.com // idle state 142510211Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, ref_done_at); 142610207Sandreas.hansson@arm.com 142710208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n", 142810211Sandreas.hansson@arm.com ref_done_at, refreshDueAt + tREFI); 142910208Sandreas.hansson@arm.com } 143010208Sandreas.hansson@arm.com} 143110208Sandreas.hansson@arm.com 143210208Sandreas.hansson@arm.comvoid 143310208Sandreas.hansson@arm.comDRAMCtrl::schedulePowerEvent(PowerState pwr_state, Tick tick) 143410208Sandreas.hansson@arm.com{ 143510208Sandreas.hansson@arm.com // respect causality 143610208Sandreas.hansson@arm.com assert(tick >= curTick()); 143710208Sandreas.hansson@arm.com 143810208Sandreas.hansson@arm.com if (!powerEvent.scheduled()) { 143910208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 144010208Sandreas.hansson@arm.com tick, pwr_state); 144110208Sandreas.hansson@arm.com 144210208Sandreas.hansson@arm.com // insert the new transition 144310208Sandreas.hansson@arm.com pwrStateTrans = pwr_state; 144410208Sandreas.hansson@arm.com 144510208Sandreas.hansson@arm.com schedule(powerEvent, tick); 144610208Sandreas.hansson@arm.com } else { 144710208Sandreas.hansson@arm.com panic("Scheduled power event at %llu to state %d, " 144810208Sandreas.hansson@arm.com "with scheduled event at %llu to %d\n", tick, pwr_state, 144910208Sandreas.hansson@arm.com powerEvent.when(), pwrStateTrans); 145010208Sandreas.hansson@arm.com } 145110208Sandreas.hansson@arm.com} 145210208Sandreas.hansson@arm.com 145310208Sandreas.hansson@arm.comvoid 145410208Sandreas.hansson@arm.comDRAMCtrl::processPowerEvent() 145510208Sandreas.hansson@arm.com{ 145610208Sandreas.hansson@arm.com // remember where we were, and for how long 145710208Sandreas.hansson@arm.com Tick duration = curTick() - pwrStateTick; 145810208Sandreas.hansson@arm.com PowerState prev_state = pwrState; 145910208Sandreas.hansson@arm.com 146010208Sandreas.hansson@arm.com // update the accounting 146110208Sandreas.hansson@arm.com pwrStateTime[prev_state] += duration; 146210208Sandreas.hansson@arm.com 146310208Sandreas.hansson@arm.com pwrState = pwrStateTrans; 146410208Sandreas.hansson@arm.com pwrStateTick = curTick(); 146510208Sandreas.hansson@arm.com 146610208Sandreas.hansson@arm.com if (pwrState == PWR_IDLE) { 146710208Sandreas.hansson@arm.com DPRINTF(DRAMState, "All banks precharged\n"); 146810208Sandreas.hansson@arm.com 146910208Sandreas.hansson@arm.com // if we were refreshing, make sure we start scheduling requests again 147010208Sandreas.hansson@arm.com if (prev_state == PWR_REF) { 147110208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 147210208Sandreas.hansson@arm.com assert(pwrState == PWR_IDLE); 147310208Sandreas.hansson@arm.com 147410208Sandreas.hansson@arm.com // kick things into action again 147510208Sandreas.hansson@arm.com refreshState = REF_IDLE; 147610208Sandreas.hansson@arm.com assert(!nextReqEvent.scheduled()); 147710208Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 147810208Sandreas.hansson@arm.com } else { 147910208Sandreas.hansson@arm.com assert(prev_state == PWR_ACT); 148010208Sandreas.hansson@arm.com 148110208Sandreas.hansson@arm.com // if we have a pending refresh, and are now moving to 148210208Sandreas.hansson@arm.com // the idle state, direclty transition to a refresh 148310208Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 148410208Sandreas.hansson@arm.com // there should be nothing waiting at this point 148510208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 148610208Sandreas.hansson@arm.com 148710208Sandreas.hansson@arm.com // update the state in zero time and proceed below 148810208Sandreas.hansson@arm.com pwrState = PWR_REF; 148910208Sandreas.hansson@arm.com } 149010208Sandreas.hansson@arm.com } 149110208Sandreas.hansson@arm.com } 149210208Sandreas.hansson@arm.com 149310208Sandreas.hansson@arm.com // we transition to the refresh state, let the refresh state 149410208Sandreas.hansson@arm.com // machine know of this state update and let it deal with the 149510208Sandreas.hansson@arm.com // scheduling of the next power state transition as well as the 149610208Sandreas.hansson@arm.com // following refresh 149710208Sandreas.hansson@arm.com if (pwrState == PWR_REF) { 149810208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refreshing\n"); 149910208Sandreas.hansson@arm.com // kick the refresh event loop into action again, and that 150010208Sandreas.hansson@arm.com // in turn will schedule a transition to the idle power 150110208Sandreas.hansson@arm.com // state once the refresh is done 150210208Sandreas.hansson@arm.com assert(refreshState == REF_RUN); 150310208Sandreas.hansson@arm.com processRefreshEvent(); 150410207Sandreas.hansson@arm.com } 15059243SN/A} 15069243SN/A 15079243SN/Avoid 150810146Sandreas.hansson@arm.comDRAMCtrl::regStats() 15099243SN/A{ 15109243SN/A using namespace Stats; 15119243SN/A 15129243SN/A AbstractMemory::regStats(); 15139243SN/A 15149243SN/A readReqs 15159243SN/A .name(name() + ".readReqs") 15169977SN/A .desc("Number of read requests accepted"); 15179243SN/A 15189243SN/A writeReqs 15199243SN/A .name(name() + ".writeReqs") 15209977SN/A .desc("Number of write requests accepted"); 15219831SN/A 15229831SN/A readBursts 15239831SN/A .name(name() + ".readBursts") 15249977SN/A .desc("Number of DRAM read bursts, " 15259977SN/A "including those serviced by the write queue"); 15269831SN/A 15279831SN/A writeBursts 15289831SN/A .name(name() + ".writeBursts") 15299977SN/A .desc("Number of DRAM write bursts, " 15309977SN/A "including those merged in the write queue"); 15319243SN/A 15329243SN/A servicedByWrQ 15339243SN/A .name(name() + ".servicedByWrQ") 15349977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 15359977SN/A 15369977SN/A mergedWrBursts 15379977SN/A .name(name() + ".mergedWrBursts") 15389977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 15399243SN/A 15409243SN/A neitherReadNorWrite 15419977SN/A .name(name() + ".neitherReadNorWriteReqs") 15429977SN/A .desc("Number of requests that are neither read nor write"); 15439243SN/A 15449977SN/A perBankRdBursts 15459243SN/A .init(banksPerRank * ranksPerChannel) 15469977SN/A .name(name() + ".perBankRdBursts") 15479977SN/A .desc("Per bank write bursts"); 15489243SN/A 15499977SN/A perBankWrBursts 15509243SN/A .init(banksPerRank * ranksPerChannel) 15519977SN/A .name(name() + ".perBankWrBursts") 15529977SN/A .desc("Per bank write bursts"); 15539243SN/A 15549243SN/A avgRdQLen 15559243SN/A .name(name() + ".avgRdQLen") 15569977SN/A .desc("Average read queue length when enqueuing") 15579243SN/A .precision(2); 15589243SN/A 15599243SN/A avgWrQLen 15609243SN/A .name(name() + ".avgWrQLen") 15619977SN/A .desc("Average write queue length when enqueuing") 15629243SN/A .precision(2); 15639243SN/A 15649243SN/A totQLat 15659243SN/A .name(name() + ".totQLat") 15669977SN/A .desc("Total ticks spent queuing"); 15679243SN/A 15689243SN/A totBusLat 15699243SN/A .name(name() + ".totBusLat") 15709977SN/A .desc("Total ticks spent in databus transfers"); 15719243SN/A 15729243SN/A totMemAccLat 15739243SN/A .name(name() + ".totMemAccLat") 15749977SN/A .desc("Total ticks spent from burst creation until serviced " 15759977SN/A "by the DRAM"); 15769243SN/A 15779243SN/A avgQLat 15789243SN/A .name(name() + ".avgQLat") 15799977SN/A .desc("Average queueing delay per DRAM burst") 15809243SN/A .precision(2); 15819243SN/A 15829831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 15839243SN/A 15849243SN/A avgBusLat 15859243SN/A .name(name() + ".avgBusLat") 15869977SN/A .desc("Average bus latency per DRAM burst") 15879243SN/A .precision(2); 15889243SN/A 15899831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 15909243SN/A 15919243SN/A avgMemAccLat 15929243SN/A .name(name() + ".avgMemAccLat") 15939977SN/A .desc("Average memory access latency per DRAM burst") 15949243SN/A .precision(2); 15959243SN/A 15969831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 15979243SN/A 15989243SN/A numRdRetry 15999243SN/A .name(name() + ".numRdRetry") 16009977SN/A .desc("Number of times read queue was full causing retry"); 16019243SN/A 16029243SN/A numWrRetry 16039243SN/A .name(name() + ".numWrRetry") 16049977SN/A .desc("Number of times write queue was full causing retry"); 16059243SN/A 16069243SN/A readRowHits 16079243SN/A .name(name() + ".readRowHits") 16089243SN/A .desc("Number of row buffer hits during reads"); 16099243SN/A 16109243SN/A writeRowHits 16119243SN/A .name(name() + ".writeRowHits") 16129243SN/A .desc("Number of row buffer hits during writes"); 16139243SN/A 16149243SN/A readRowHitRate 16159243SN/A .name(name() + ".readRowHitRate") 16169243SN/A .desc("Row buffer hit rate for reads") 16179243SN/A .precision(2); 16189243SN/A 16199831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 16209243SN/A 16219243SN/A writeRowHitRate 16229243SN/A .name(name() + ".writeRowHitRate") 16239243SN/A .desc("Row buffer hit rate for writes") 16249243SN/A .precision(2); 16259243SN/A 16269977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 16279243SN/A 16289243SN/A readPktSize 16299831SN/A .init(ceilLog2(burstSize) + 1) 16309243SN/A .name(name() + ".readPktSize") 16319977SN/A .desc("Read request sizes (log2)"); 16329243SN/A 16339243SN/A writePktSize 16349831SN/A .init(ceilLog2(burstSize) + 1) 16359243SN/A .name(name() + ".writePktSize") 16369977SN/A .desc("Write request sizes (log2)"); 16379243SN/A 16389243SN/A rdQLenPdf 16399567SN/A .init(readBufferSize) 16409243SN/A .name(name() + ".rdQLenPdf") 16419243SN/A .desc("What read queue length does an incoming req see"); 16429243SN/A 16439243SN/A wrQLenPdf 16449567SN/A .init(writeBufferSize) 16459243SN/A .name(name() + ".wrQLenPdf") 16469243SN/A .desc("What write queue length does an incoming req see"); 16479243SN/A 16489727SN/A bytesPerActivate 164910141SN/A .init(maxAccessesPerRow) 16509727SN/A .name(name() + ".bytesPerActivate") 16519727SN/A .desc("Bytes accessed per row activation") 16529727SN/A .flags(nozero); 16539243SN/A 165410147Sandreas.hansson@arm.com rdPerTurnAround 165510147Sandreas.hansson@arm.com .init(readBufferSize) 165610147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 165710147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 165810147Sandreas.hansson@arm.com .flags(nozero); 165910147Sandreas.hansson@arm.com 166010147Sandreas.hansson@arm.com wrPerTurnAround 166110147Sandreas.hansson@arm.com .init(writeBufferSize) 166210147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 166310147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 166410147Sandreas.hansson@arm.com .flags(nozero); 166510147Sandreas.hansson@arm.com 16669975SN/A bytesReadDRAM 16679975SN/A .name(name() + ".bytesReadDRAM") 16689975SN/A .desc("Total number of bytes read from DRAM"); 16699975SN/A 16709975SN/A bytesReadWrQ 16719975SN/A .name(name() + ".bytesReadWrQ") 16729975SN/A .desc("Total number of bytes read from write queue"); 16739243SN/A 16749243SN/A bytesWritten 16759243SN/A .name(name() + ".bytesWritten") 16769977SN/A .desc("Total number of bytes written to DRAM"); 16779243SN/A 16789977SN/A bytesReadSys 16799977SN/A .name(name() + ".bytesReadSys") 16809977SN/A .desc("Total read bytes from the system interface side"); 16819243SN/A 16829977SN/A bytesWrittenSys 16839977SN/A .name(name() + ".bytesWrittenSys") 16849977SN/A .desc("Total written bytes from the system interface side"); 16859243SN/A 16869243SN/A avgRdBW 16879243SN/A .name(name() + ".avgRdBW") 16889977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 16899243SN/A .precision(2); 16909243SN/A 16919977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 16929243SN/A 16939243SN/A avgWrBW 16949243SN/A .name(name() + ".avgWrBW") 16959977SN/A .desc("Average achieved write bandwidth in MiByte/s") 16969243SN/A .precision(2); 16979243SN/A 16989243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 16999243SN/A 17009977SN/A avgRdBWSys 17019977SN/A .name(name() + ".avgRdBWSys") 17029977SN/A .desc("Average system read bandwidth in MiByte/s") 17039243SN/A .precision(2); 17049243SN/A 17059977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 17069243SN/A 17079977SN/A avgWrBWSys 17089977SN/A .name(name() + ".avgWrBWSys") 17099977SN/A .desc("Average system write bandwidth in MiByte/s") 17109243SN/A .precision(2); 17119243SN/A 17129977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 17139243SN/A 17149243SN/A peakBW 17159243SN/A .name(name() + ".peakBW") 17169977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 17179243SN/A .precision(2); 17189243SN/A 17199831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 17209243SN/A 17219243SN/A busUtil 17229243SN/A .name(name() + ".busUtil") 17239243SN/A .desc("Data bus utilization in percentage") 17249243SN/A .precision(2); 17259243SN/A 17269243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 17279243SN/A 17289243SN/A totGap 17299243SN/A .name(name() + ".totGap") 17309243SN/A .desc("Total gap between requests"); 17319243SN/A 17329243SN/A avgGap 17339243SN/A .name(name() + ".avgGap") 17349243SN/A .desc("Average gap between requests") 17359243SN/A .precision(2); 17369243SN/A 17379243SN/A avgGap = totGap / (readReqs + writeReqs); 17389975SN/A 17399975SN/A // Stats for DRAM Power calculation based on Micron datasheet 17409975SN/A busUtilRead 17419975SN/A .name(name() + ".busUtilRead") 17429975SN/A .desc("Data bus utilization in percentage for reads") 17439975SN/A .precision(2); 17449975SN/A 17459975SN/A busUtilRead = avgRdBW / peakBW * 100; 17469975SN/A 17479975SN/A busUtilWrite 17489975SN/A .name(name() + ".busUtilWrite") 17499975SN/A .desc("Data bus utilization in percentage for writes") 17509975SN/A .precision(2); 17519975SN/A 17529975SN/A busUtilWrite = avgWrBW / peakBW * 100; 17539975SN/A 17549975SN/A pageHitRate 17559975SN/A .name(name() + ".pageHitRate") 17569975SN/A .desc("Row buffer hit rate, read and write combined") 17579975SN/A .precision(2); 17589975SN/A 17599977SN/A pageHitRate = (writeRowHits + readRowHits) / 17609977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 17619975SN/A 176210208Sandreas.hansson@arm.com pwrStateTime 176310208Sandreas.hansson@arm.com .init(5) 176410208Sandreas.hansson@arm.com .name(name() + ".memoryStateTime") 176510208Sandreas.hansson@arm.com .desc("Time in different power states"); 176610208Sandreas.hansson@arm.com pwrStateTime.subname(0, "IDLE"); 176710208Sandreas.hansson@arm.com pwrStateTime.subname(1, "REF"); 176810208Sandreas.hansson@arm.com pwrStateTime.subname(2, "PRE_PDN"); 176910208Sandreas.hansson@arm.com pwrStateTime.subname(3, "ACT"); 177010208Sandreas.hansson@arm.com pwrStateTime.subname(4, "ACT_PDN"); 17719243SN/A} 17729243SN/A 17739243SN/Avoid 177410146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 17759243SN/A{ 17769243SN/A // rely on the abstract memory 17779243SN/A functionalAccess(pkt); 17789243SN/A} 17799243SN/A 17809294SN/ABaseSlavePort& 178110146Sandreas.hansson@arm.comDRAMCtrl::getSlavePort(const string &if_name, PortID idx) 17829243SN/A{ 17839243SN/A if (if_name != "port") { 17849243SN/A return MemObject::getSlavePort(if_name, idx); 17859243SN/A } else { 17869243SN/A return port; 17879243SN/A } 17889243SN/A} 17899243SN/A 17909243SN/Aunsigned int 179110146Sandreas.hansson@arm.comDRAMCtrl::drain(DrainManager *dm) 17929243SN/A{ 17939342SN/A unsigned int count = port.drain(dm); 17949243SN/A 17959243SN/A // if there is anything in any of our internal queues, keep track 17969243SN/A // of that as well 17979567SN/A if (!(writeQueue.empty() && readQueue.empty() && 17989567SN/A respQueue.empty())) { 17999352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 18009567SN/A " resp: %d\n", writeQueue.size(), readQueue.size(), 18019567SN/A respQueue.size()); 18029243SN/A ++count; 18039342SN/A drainManager = dm; 180410206Sandreas.hansson@arm.com 18059352SN/A // the only part that is not drained automatically over time 180610206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 180710206Sandreas.hansson@arm.com if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 180810206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 180910206Sandreas.hansson@arm.com } 18109243SN/A } 18119243SN/A 18129243SN/A if (count) 18139342SN/A setDrainState(Drainable::Draining); 18149243SN/A else 18159342SN/A setDrainState(Drainable::Drained); 18169243SN/A return count; 18179243SN/A} 18189243SN/A 181910146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 18209243SN/A : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 18219243SN/A memory(_memory) 18229243SN/A{ } 18239243SN/A 18249243SN/AAddrRangeList 182510146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 18269243SN/A{ 18279243SN/A AddrRangeList ranges; 18289243SN/A ranges.push_back(memory.getAddrRange()); 18299243SN/A return ranges; 18309243SN/A} 18319243SN/A 18329243SN/Avoid 183310146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 18349243SN/A{ 18359243SN/A pkt->pushLabel(memory.name()); 18369243SN/A 18379243SN/A if (!queue.checkFunctional(pkt)) { 18389243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 18399243SN/A // calls recvAtomic() and throws away the latency; we can save a 18409243SN/A // little here by just not calculating the latency. 18419243SN/A memory.recvFunctional(pkt); 18429243SN/A } 18439243SN/A 18449243SN/A pkt->popLabel(); 18459243SN/A} 18469243SN/A 18479243SN/ATick 184810146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 18499243SN/A{ 18509243SN/A return memory.recvAtomic(pkt); 18519243SN/A} 18529243SN/A 18539243SN/Abool 185410146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 18559243SN/A{ 18569243SN/A // pass it to the memory controller 18579243SN/A return memory.recvTimingReq(pkt); 18589243SN/A} 18599243SN/A 186010146Sandreas.hansson@arm.comDRAMCtrl* 186110146Sandreas.hansson@arm.comDRAMCtrlParams::create() 18629243SN/A{ 186310146Sandreas.hansson@arm.com return new DRAMCtrl(this); 18649243SN/A} 1865