dram_ctrl.cc revision 10210
19243SN/A/* 210206Sandreas.hansson@arm.com * Copyright (c) 2010-2014 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 439243SN/A */ 449243SN/A 4510146Sandreas.hansson@arm.com#include "base/bitfield.hh" 469356SN/A#include "base/trace.hh" 4710146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 4810208Sandreas.hansson@arm.com#include "debug/DRAMState.hh" 499352SN/A#include "debug/Drain.hh" 5010146Sandreas.hansson@arm.com#include "mem/dram_ctrl.hh" 519814SN/A#include "sim/system.hh" 529243SN/A 539243SN/Ausing namespace std; 549243SN/A 5510146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 569243SN/A AbstractMemory(p), 579243SN/A port(name() + ".port", *this), 589243SN/A retryRdReq(false), retryWrReq(false), 5910206Sandreas.hansson@arm.com rowHitFlag(false), busState(READ), 6010208Sandreas.hansson@arm.com nextReqEvent(this), respondEvent(this), activateEvent(this), 6110208Sandreas.hansson@arm.com prechargeEvent(this), refreshEvent(this), powerEvent(this), 6210208Sandreas.hansson@arm.com drainManager(NULL), 639831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 649831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 659831SN/A devicesPerRank(p->devices_per_rank), 669831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 679831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 6810140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 699243SN/A ranksPerChannel(p->ranks_per_channel), 709566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 719243SN/A readBufferSize(p->read_buffer_size), 729243SN/A writeBufferSize(p->write_buffer_size), 7310140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 7410140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 7510147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 7610147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 7710206Sandreas.hansson@arm.com tWTR(p->tWTR), tRTW(p->tRTW), tBURST(p->tBURST), 7810210Sandreas.hansson@arm.com tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), tWR(p->tWR), 799971SN/A tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 809488SN/A tXAW(p->tXAW), activationLimit(p->activation_limit), 819243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 829243SN/A pageMgmt(p->page_policy), 8310141SN/A maxAccessesPerRow(p->max_accesses_per_row), 849726SN/A frontendLatency(p->static_frontend_latency), 859726SN/A backendLatency(p->static_backend_latency), 8610208Sandreas.hansson@arm.com busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE), 8710208Sandreas.hansson@arm.com pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), prevArrival(0), 8810208Sandreas.hansson@arm.com nextReqTime(0), pwrStateTick(0), numBanksActive(0) 899243SN/A{ 909243SN/A // create the bank states based on the dimensions of the ranks and 919243SN/A // banks 929243SN/A banks.resize(ranksPerChannel); 939969SN/A actTicks.resize(ranksPerChannel); 949243SN/A for (size_t c = 0; c < ranksPerChannel; ++c) { 959243SN/A banks[c].resize(banksPerRank); 969969SN/A actTicks[c].resize(activationLimit, 0); 979243SN/A } 989243SN/A 9910140SN/A // perform a basic check of the write thresholds 10010140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 10110140SN/A fatal("Write buffer low threshold %d must be smaller than the " 10210140SN/A "high threshold %d\n", p->write_low_thresh_perc, 10310140SN/A p->write_high_thresh_perc); 1049243SN/A 1059243SN/A // determine the rows per bank by looking at the total capacity 1069567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1079243SN/A 1089243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1099243SN/A AbstractMemory::size()); 1109831SN/A 1119831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1129831SN/A rowBufferSize, columnsPerRowBuffer); 1139831SN/A 1149831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1159243SN/A 1169566SN/A if (range.interleaved()) { 1179566SN/A if (channels != range.stripes()) 11810143SN/A fatal("%s has %d interleaved address stripes but %d channel(s)\n", 1199566SN/A name(), range.stripes(), channels); 1209566SN/A 12110136SN/A if (addrMapping == Enums::RoRaBaChCo) { 1229831SN/A if (rowBufferSize != range.granularity()) { 12310143SN/A fatal("Interleaving of %s doesn't match RoRaBaChCo " 12410136SN/A "address map\n", name()); 1259566SN/A } 12610136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 12710136SN/A if (system()->cacheLineSize() != range.granularity()) { 12810143SN/A fatal("Interleaving of %s doesn't match RoRaBaCoCh " 12910136SN/A "address map\n", name()); 1309669SN/A } 13110136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 13210136SN/A if (system()->cacheLineSize() != range.granularity()) 13310143SN/A fatal("Interleaving of %s doesn't match RoCoRaBaCh " 13410136SN/A "address map\n", name()); 1359566SN/A } 1369566SN/A } 13710207Sandreas.hansson@arm.com 13810207Sandreas.hansson@arm.com // some basic sanity checks 13910207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 14010207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 14110207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 14210207Sandreas.hansson@arm.com } 1439243SN/A} 1449243SN/A 1459243SN/Avoid 14610146Sandreas.hansson@arm.comDRAMCtrl::init() 14710140SN/A{ 14810140SN/A if (!port.isConnected()) { 14910146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 15010140SN/A } else { 15110140SN/A port.sendRangeChange(); 15210140SN/A } 15310140SN/A} 15410140SN/A 15510140SN/Avoid 15610146Sandreas.hansson@arm.comDRAMCtrl::startup() 1579243SN/A{ 15810143SN/A // update the start tick for the precharge accounting to the 15910143SN/A // current tick 16010208Sandreas.hansson@arm.com pwrStateTick = curTick(); 16110143SN/A 16210206Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 16310206Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 16410206Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 16510206Sandreas.hansson@arm.com // start of simulation 16610206Sandreas.hansson@arm.com busBusyUntil = curTick() + tRP + tRCD + tCL; 16710206Sandreas.hansson@arm.com 1689243SN/A // print the configuration of the controller 1699243SN/A printParams(); 1709243SN/A 17110207Sandreas.hansson@arm.com // kick off the refresh, and give ourselves enough time to 17210207Sandreas.hansson@arm.com // precharge 17310207Sandreas.hansson@arm.com schedule(refreshEvent, curTick() + tREFI - tRP); 1749243SN/A} 1759243SN/A 1769243SN/ATick 17710146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 1789243SN/A{ 1799243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 1809243SN/A 1819243SN/A // do the actual memory access and turn the packet into a response 1829243SN/A access(pkt); 1839243SN/A 1849243SN/A Tick latency = 0; 1859243SN/A if (!pkt->memInhibitAsserted() && pkt->hasData()) { 1869243SN/A // this value is not supposed to be accurate, just enough to 1879243SN/A // keep things going, mimic a closed page 1889243SN/A latency = tRP + tRCD + tCL; 1899243SN/A } 1909243SN/A return latency; 1919243SN/A} 1929243SN/A 1939243SN/Abool 19410146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 1959243SN/A{ 1969831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 1979831SN/A readBufferSize, readQueue.size() + respQueue.size(), 1989831SN/A neededEntries); 1999243SN/A 2009831SN/A return 2019831SN/A (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 2029243SN/A} 2039243SN/A 2049243SN/Abool 20510146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 2069243SN/A{ 2079831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 2089831SN/A writeBufferSize, writeQueue.size(), neededEntries); 2099831SN/A return (writeQueue.size() + neededEntries) > writeBufferSize; 2109243SN/A} 2119243SN/A 21210146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 21310146Sandreas.hansson@arm.comDRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 21410143SN/A bool isRead) 2159243SN/A{ 2169669SN/A // decode the address based on the address mapping scheme, with 21710136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 21810136SN/A // channel, respectively 2199243SN/A uint8_t rank; 2209967SN/A uint8_t bank; 2219243SN/A uint16_t row; 2229243SN/A 2239243SN/A // truncate the address to the access granularity 2249831SN/A Addr addr = dramPktAddr / burstSize; 2259243SN/A 2269491SN/A // we have removed the lowest order address bits that denote the 2279831SN/A // position within the column 22810136SN/A if (addrMapping == Enums::RoRaBaChCo) { 2299491SN/A // the lowest order bits denote the column to ensure that 2309491SN/A // sequential cache lines occupy the same row 2319831SN/A addr = addr / columnsPerRowBuffer; 2329243SN/A 2339669SN/A // take out the channel part of the address 2349566SN/A addr = addr / channels; 2359566SN/A 2369669SN/A // after the channel bits, get the bank bits to interleave 2379669SN/A // over the banks 2389669SN/A bank = addr % banksPerRank; 2399669SN/A addr = addr / banksPerRank; 2409669SN/A 2419669SN/A // after the bank, we get the rank bits which thus interleaves 2429669SN/A // over the ranks 2439669SN/A rank = addr % ranksPerChannel; 2449669SN/A addr = addr / ranksPerChannel; 2459669SN/A 2469669SN/A // lastly, get the row bits 2479669SN/A row = addr % rowsPerBank; 2489669SN/A addr = addr / rowsPerBank; 24910136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 2509669SN/A // take out the channel part of the address 2519669SN/A addr = addr / channels; 2529669SN/A 2539669SN/A // next, the column 2549831SN/A addr = addr / columnsPerRowBuffer; 2559669SN/A 2569669SN/A // after the column bits, we get the bank bits to interleave 2579491SN/A // over the banks 2589243SN/A bank = addr % banksPerRank; 2599243SN/A addr = addr / banksPerRank; 2609243SN/A 2619491SN/A // after the bank, we get the rank bits which thus interleaves 2629491SN/A // over the ranks 2639243SN/A rank = addr % ranksPerChannel; 2649243SN/A addr = addr / ranksPerChannel; 2659243SN/A 2669491SN/A // lastly, get the row bits 2679243SN/A row = addr % rowsPerBank; 2689243SN/A addr = addr / rowsPerBank; 26910136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 2709491SN/A // optimise for closed page mode and utilise maximum 2719491SN/A // parallelism of the DRAM (at the cost of power) 2729491SN/A 2739566SN/A // take out the channel part of the address, not that this has 2749566SN/A // to match with how accesses are interleaved between the 2759566SN/A // controllers in the address mapping 2769566SN/A addr = addr / channels; 2779566SN/A 2789491SN/A // start with the bank bits, as this provides the maximum 2799491SN/A // opportunity for parallelism between requests 2809243SN/A bank = addr % banksPerRank; 2819243SN/A addr = addr / banksPerRank; 2829243SN/A 2839491SN/A // next get the rank bits 2849243SN/A rank = addr % ranksPerChannel; 2859243SN/A addr = addr / ranksPerChannel; 2869243SN/A 2879491SN/A // next the column bits which we do not need to keep track of 2889491SN/A // and simply skip past 2899831SN/A addr = addr / columnsPerRowBuffer; 2909243SN/A 2919491SN/A // lastly, get the row bits 2929243SN/A row = addr % rowsPerBank; 2939243SN/A addr = addr / rowsPerBank; 2949243SN/A } else 2959243SN/A panic("Unknown address mapping policy chosen!"); 2969243SN/A 2979243SN/A assert(rank < ranksPerChannel); 2989243SN/A assert(bank < banksPerRank); 2999243SN/A assert(row < rowsPerBank); 3009243SN/A 3019243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 3029831SN/A dramPktAddr, rank, bank, row); 3039243SN/A 3049243SN/A // create the corresponding DRAM packet with the entry time and 3059567SN/A // ready time set to the current tick, the latter will be updated 3069567SN/A // later 3079967SN/A uint16_t bank_id = banksPerRank * rank + bank; 3089967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 3099967SN/A size, banks[rank][bank]); 3109243SN/A} 3119243SN/A 3129243SN/Avoid 31310146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 3149243SN/A{ 3159243SN/A // only add to the read queue here. whenever the request is 3169243SN/A // eventually done, set the readyTime, and call schedule() 3179243SN/A assert(!pkt->isWrite()); 3189243SN/A 3199831SN/A assert(pktCount != 0); 3209831SN/A 3219831SN/A // if the request size is larger than burst size, the pkt is split into 3229831SN/A // multiple DRAM packets 3239831SN/A // Note if the pkt starting address is not aligened to burst size, the 3249831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 3259831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 3269831SN/A // check read packets against packets in write queue. 3279243SN/A Addr addr = pkt->getAddr(); 3289831SN/A unsigned pktsServicedByWrQ = 0; 3299831SN/A BurstHelper* burst_helper = NULL; 3309831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 3319831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 3329831SN/A pkt->getAddr() + pkt->getSize()) - addr; 3339831SN/A readPktSize[ceilLog2(size)]++; 3349831SN/A readBursts++; 3359243SN/A 3369831SN/A // First check write buffer to see if the data is already at 3379831SN/A // the controller 3389831SN/A bool foundInWrQ = false; 3399833SN/A for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) { 3409832SN/A // check if the read is subsumed in the write entry we are 3419832SN/A // looking at 3429832SN/A if ((*i)->addr <= addr && 3439832SN/A (addr + size) <= ((*i)->addr + (*i)->size)) { 3449831SN/A foundInWrQ = true; 3459831SN/A servicedByWrQ++; 3469831SN/A pktsServicedByWrQ++; 3479831SN/A DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 3489831SN/A "write queue\n", addr, size); 3499975SN/A bytesReadWrQ += burstSize; 3509831SN/A break; 3519831SN/A } 3529243SN/A } 3539831SN/A 3549831SN/A // If not found in the write q, make a DRAM packet and 3559831SN/A // push it onto the read queue 3569831SN/A if (!foundInWrQ) { 3579831SN/A 3589831SN/A // Make the burst helper for split packets 3599831SN/A if (pktCount > 1 && burst_helper == NULL) { 3609831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 3619831SN/A "dram requests\n", pkt->getAddr(), pktCount); 3629831SN/A burst_helper = new BurstHelper(pktCount); 3639831SN/A } 3649831SN/A 3659966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 3669831SN/A dram_pkt->burstHelper = burst_helper; 3679831SN/A 3689831SN/A assert(!readQueueFull(1)); 3699831SN/A rdQLenPdf[readQueue.size() + respQueue.size()]++; 3709831SN/A 3719831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 3729831SN/A 3739831SN/A readQueue.push_back(dram_pkt); 3749831SN/A 3759831SN/A // Update stats 3769831SN/A avgRdQLen = readQueue.size() + respQueue.size(); 3779831SN/A } 3789831SN/A 3799831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 3809831SN/A addr = (addr | (burstSize - 1)) + 1; 3819243SN/A } 3829243SN/A 3839831SN/A // If all packets are serviced by write queue, we send the repsonse back 3849831SN/A if (pktsServicedByWrQ == pktCount) { 3859831SN/A accessAndRespond(pkt, frontendLatency); 3869831SN/A return; 3879831SN/A } 3889243SN/A 3899831SN/A // Update how many split packets are serviced by write queue 3909831SN/A if (burst_helper != NULL) 3919831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 3929243SN/A 39310206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 39410206Sandreas.hansson@arm.com // queue, do so now 39510206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 3969567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 3979567SN/A schedule(nextReqEvent, curTick()); 3989243SN/A } 3999243SN/A} 4009243SN/A 4019243SN/Avoid 40210146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 4039243SN/A{ 4049243SN/A // only add to the write queue here. whenever the request is 4059243SN/A // eventually done, set the readyTime, and call schedule() 4069243SN/A assert(pkt->isWrite()); 4079243SN/A 4089831SN/A // if the request size is larger than burst size, the pkt is split into 4099831SN/A // multiple DRAM packets 4109831SN/A Addr addr = pkt->getAddr(); 4119831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4129831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4139831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4149831SN/A writePktSize[ceilLog2(size)]++; 4159831SN/A writeBursts++; 4169243SN/A 4179832SN/A // see if we can merge with an existing item in the write 4189838SN/A // queue and keep track of whether we have merged or not so we 4199838SN/A // can stop at that point and also avoid enqueueing a new 4209838SN/A // request 4219832SN/A bool merged = false; 4229832SN/A auto w = writeQueue.begin(); 4239243SN/A 4249832SN/A while(!merged && w != writeQueue.end()) { 4259832SN/A // either of the two could be first, if they are the same 4269832SN/A // it does not matter which way we go 4279832SN/A if ((*w)->addr >= addr) { 4289838SN/A // the existing one starts after the new one, figure 4299838SN/A // out where the new one ends with respect to the 4309838SN/A // existing one 4319832SN/A if ((addr + size) >= ((*w)->addr + (*w)->size)) { 4329832SN/A // check if the existing one is completely 4339832SN/A // subsumed in the new one 4349832SN/A DPRINTF(DRAM, "Merging write covering existing burst\n"); 4359832SN/A merged = true; 4369832SN/A // update both the address and the size 4379832SN/A (*w)->addr = addr; 4389832SN/A (*w)->size = size; 4399832SN/A } else if ((addr + size) >= (*w)->addr && 4409832SN/A ((*w)->addr + (*w)->size - addr) <= burstSize) { 4419832SN/A // the new one is just before or partially 4429832SN/A // overlapping with the existing one, and together 4439832SN/A // they fit within a burst 4449832SN/A DPRINTF(DRAM, "Merging write before existing burst\n"); 4459832SN/A merged = true; 4469832SN/A // the existing queue item needs to be adjusted with 4479832SN/A // respect to both address and size 44810047SN/A (*w)->size = (*w)->addr + (*w)->size - addr; 4499832SN/A (*w)->addr = addr; 4509832SN/A } 4519832SN/A } else { 4529838SN/A // the new one starts after the current one, figure 4539838SN/A // out where the existing one ends with respect to the 4549838SN/A // new one 4559832SN/A if (((*w)->addr + (*w)->size) >= (addr + size)) { 4569832SN/A // check if the new one is completely subsumed in the 4579832SN/A // existing one 4589832SN/A DPRINTF(DRAM, "Merging write into existing burst\n"); 4599832SN/A merged = true; 4609832SN/A // no adjustments necessary 4619832SN/A } else if (((*w)->addr + (*w)->size) >= addr && 4629832SN/A (addr + size - (*w)->addr) <= burstSize) { 4639832SN/A // the existing one is just before or partially 4649832SN/A // overlapping with the new one, and together 4659832SN/A // they fit within a burst 4669832SN/A DPRINTF(DRAM, "Merging write after existing burst\n"); 4679832SN/A merged = true; 4689832SN/A // the address is right, and only the size has 4699832SN/A // to be adjusted 4709832SN/A (*w)->size = addr + size - (*w)->addr; 4719832SN/A } 4729832SN/A } 4739832SN/A ++w; 4749832SN/A } 4759243SN/A 4769832SN/A // if the item was not merged we need to create a new write 4779832SN/A // and enqueue it 4789832SN/A if (!merged) { 4799966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 4809243SN/A 4819832SN/A assert(writeQueue.size() < writeBufferSize); 4829832SN/A wrQLenPdf[writeQueue.size()]++; 4839243SN/A 4849832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 4859831SN/A 4869832SN/A writeQueue.push_back(dram_pkt); 4879831SN/A 4889832SN/A // Update stats 4899832SN/A avgWrQLen = writeQueue.size(); 4909977SN/A } else { 4919977SN/A // keep track of the fact that this burst effectively 4929977SN/A // disappeared as it was merged with an existing one 4939977SN/A mergedWrBursts++; 4949832SN/A } 4959832SN/A 4969831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 4979831SN/A addr = (addr | (burstSize - 1)) + 1; 4989831SN/A } 4999243SN/A 5009243SN/A // we do not wait for the writes to be send to the actual memory, 5019243SN/A // but instead take responsibility for the consistency here and 5029243SN/A // snoop the write queue for any upcoming reads 5039831SN/A // @todo, if a pkt size is larger than burst size, we might need a 5049831SN/A // different front end latency 5059726SN/A accessAndRespond(pkt, frontendLatency); 5069243SN/A 50710206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 50810206Sandreas.hansson@arm.com // queue, do so now 50910206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 51010206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 51110206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 5129243SN/A } 5139243SN/A} 5149243SN/A 5159243SN/Avoid 51610146Sandreas.hansson@arm.comDRAMCtrl::printParams() const 5179243SN/A{ 5189243SN/A // Sanity check print of important parameters 5199243SN/A DPRINTF(DRAM, 5209243SN/A "Memory controller %s physical organization\n" \ 5219831SN/A "Number of devices per rank %d\n" \ 5229831SN/A "Device bus width (in bits) %d\n" \ 52310143SN/A "DRAM data bus burst (bytes) %d\n" \ 52410143SN/A "Row buffer size (bytes) %d\n" \ 5259831SN/A "Columns per row buffer %d\n" \ 5269831SN/A "Rows per bank %d\n" \ 5279831SN/A "Banks per rank %d\n" \ 5289831SN/A "Ranks per channel %d\n" \ 52910143SN/A "Total mem capacity (bytes) %u\n", 5309831SN/A name(), devicesPerRank, deviceBusWidth, burstSize, rowBufferSize, 5319831SN/A columnsPerRowBuffer, rowsPerBank, banksPerRank, ranksPerChannel, 5329831SN/A rowBufferSize * rowsPerBank * banksPerRank * ranksPerChannel); 5339243SN/A 5349243SN/A string scheduler = memSchedPolicy == Enums::fcfs ? "FCFS" : "FR-FCFS"; 53510136SN/A string address_mapping = addrMapping == Enums::RoRaBaChCo ? "RoRaBaChCo" : 53610136SN/A (addrMapping == Enums::RoRaBaCoCh ? "RoRaBaCoCh" : "RoCoRaBaCh"); 5379973SN/A string page_policy = pageMgmt == Enums::open ? "OPEN" : 53810144SN/A (pageMgmt == Enums::open_adaptive ? "OPEN (adaptive)" : 53910144SN/A (pageMgmt == Enums::close_adaptive ? "CLOSE (adaptive)" : "CLOSE")); 5409243SN/A 5419243SN/A DPRINTF(DRAM, 5429243SN/A "Memory controller %s characteristics\n" \ 5439243SN/A "Read buffer size %d\n" \ 5449243SN/A "Write buffer size %d\n" \ 54510140SN/A "Write high thresh %d\n" \ 54610140SN/A "Write low thresh %d\n" \ 5479243SN/A "Scheduler %s\n" \ 5489243SN/A "Address mapping %s\n" \ 5499243SN/A "Page policy %s\n", 5509972SN/A name(), readBufferSize, writeBufferSize, writeHighThreshold, 55110140SN/A writeLowThreshold, scheduler, address_mapping, page_policy); 5529243SN/A 5539243SN/A DPRINTF(DRAM, "Memory controller %s timing specs\n" \ 5549567SN/A "tRCD %d ticks\n" \ 5559567SN/A "tCL %d ticks\n" \ 5569567SN/A "tRP %d ticks\n" \ 5579567SN/A "tBURST %d ticks\n" \ 5589567SN/A "tRFC %d ticks\n" \ 5599567SN/A "tREFI %d ticks\n" \ 5609567SN/A "tWTR %d ticks\n" \ 56110206Sandreas.hansson@arm.com "tRTW %d ticks\n" \ 56210210Sandreas.hansson@arm.com "tWR %d ticks\n" \ 5639567SN/A "tXAW (%d) %d ticks\n", 5649567SN/A name(), tRCD, tCL, tRP, tBURST, tRFC, tREFI, tWTR, 56510210Sandreas.hansson@arm.com tRTW, tWR, activationLimit, tXAW); 5669243SN/A} 5679243SN/A 5689243SN/Avoid 56910146Sandreas.hansson@arm.comDRAMCtrl::printQs() const { 5709243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 5719833SN/A for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 5729243SN/A DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 5739243SN/A } 5749243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 5759833SN/A for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 5769243SN/A DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 5779243SN/A } 5789243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 5799833SN/A for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 5809243SN/A DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 5819243SN/A } 5829243SN/A} 5839243SN/A 5849243SN/Abool 58510146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 5869243SN/A{ 5879349SN/A /// @todo temporary hack to deal with memory corruption issues until 5889349SN/A /// 4-phase transactions are complete 5899349SN/A for (int x = 0; x < pendingDelete.size(); x++) 5909349SN/A delete pendingDelete[x]; 5919349SN/A pendingDelete.clear(); 5929349SN/A 5939243SN/A // This is where we enter from the outside world 5949567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 5959831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 5969243SN/A 5979567SN/A // simply drop inhibited packets for now 5989567SN/A if (pkt->memInhibitAsserted()) { 59910143SN/A DPRINTF(DRAM, "Inhibited packet -- Dropping it now\n"); 6009567SN/A pendingDelete.push_back(pkt); 6019567SN/A return true; 6029567SN/A } 6039243SN/A 6049243SN/A // Calc avg gap between requests 6059243SN/A if (prevArrival != 0) { 6069243SN/A totGap += curTick() - prevArrival; 6079243SN/A } 6089243SN/A prevArrival = curTick(); 6099243SN/A 6109831SN/A 6119831SN/A // Find out how many dram packets a pkt translates to 6129831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 6139831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 6149831SN/A // multiple dram packets 6159243SN/A unsigned size = pkt->getSize(); 6169831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 6179831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 6189243SN/A 6199243SN/A // check local buffers and do not accept if full 6209243SN/A if (pkt->isRead()) { 6219567SN/A assert(size != 0); 6229831SN/A if (readQueueFull(dram_pkt_count)) { 6239567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 6249243SN/A // remember that we have to retry this port 6259243SN/A retryRdReq = true; 6269243SN/A numRdRetry++; 6279243SN/A return false; 6289243SN/A } else { 6299831SN/A addToReadQueue(pkt, dram_pkt_count); 6309243SN/A readReqs++; 6319977SN/A bytesReadSys += size; 6329243SN/A } 6339243SN/A } else if (pkt->isWrite()) { 6349567SN/A assert(size != 0); 6359831SN/A if (writeQueueFull(dram_pkt_count)) { 6369567SN/A DPRINTF(DRAM, "Write queue full, not accepting\n"); 6379243SN/A // remember that we have to retry this port 6389243SN/A retryWrReq = true; 6399243SN/A numWrRetry++; 6409243SN/A return false; 6419243SN/A } else { 6429831SN/A addToWriteQueue(pkt, dram_pkt_count); 6439243SN/A writeReqs++; 6449977SN/A bytesWrittenSys += size; 6459243SN/A } 6469243SN/A } else { 6479243SN/A DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 6489243SN/A neitherReadNorWrite++; 6499726SN/A accessAndRespond(pkt, 1); 6509243SN/A } 6519243SN/A 6529243SN/A return true; 6539243SN/A} 6549243SN/A 6559243SN/Avoid 65610146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 6579243SN/A{ 6589243SN/A DPRINTF(DRAM, 6599243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 6609243SN/A 6619831SN/A DRAMPacket* dram_pkt = respQueue.front(); 6629243SN/A 6639831SN/A if (dram_pkt->burstHelper) { 6649831SN/A // it is a split packet 6659831SN/A dram_pkt->burstHelper->burstsServiced++; 6669831SN/A if (dram_pkt->burstHelper->burstsServiced == 66710143SN/A dram_pkt->burstHelper->burstCount) { 6689831SN/A // we have now serviced all children packets of a system packet 6699831SN/A // so we can now respond to the requester 6709831SN/A // @todo we probably want to have a different front end and back 6719831SN/A // end latency for split packets 6729831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6739831SN/A delete dram_pkt->burstHelper; 6749831SN/A dram_pkt->burstHelper = NULL; 6759831SN/A } 6769831SN/A } else { 6779831SN/A // it is not a split packet 6789831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6799831SN/A } 6809243SN/A 6819831SN/A delete respQueue.front(); 6829831SN/A respQueue.pop_front(); 6839243SN/A 6849831SN/A if (!respQueue.empty()) { 6859831SN/A assert(respQueue.front()->readyTime >= curTick()); 6869831SN/A assert(!respondEvent.scheduled()); 6879831SN/A schedule(respondEvent, respQueue.front()->readyTime); 6889831SN/A } else { 6899831SN/A // if there is nothing left in any queue, signal a drain 6909831SN/A if (writeQueue.empty() && readQueue.empty() && 6919831SN/A drainManager) { 6929831SN/A drainManager->signalDrainDone(); 6939831SN/A drainManager = NULL; 6949831SN/A } 6959831SN/A } 6969567SN/A 6979831SN/A // We have made a location in the queue available at this point, 6989831SN/A // so if there is a read that was forced to wait, retry now 6999831SN/A if (retryRdReq) { 7009831SN/A retryRdReq = false; 7019831SN/A port.sendRetry(); 7029831SN/A } 7039243SN/A} 7049243SN/A 7059243SN/Avoid 70610206Sandreas.hansson@arm.comDRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue) 7079243SN/A{ 70810206Sandreas.hansson@arm.com // This method does the arbitration between requests. The chosen 70910206Sandreas.hansson@arm.com // packet is simply moved to the head of the queue. The other 71010206Sandreas.hansson@arm.com // methods know that this is the place to look. For example, with 71110206Sandreas.hansson@arm.com // FCFS, this method does nothing 71210206Sandreas.hansson@arm.com assert(!queue.empty()); 7139243SN/A 71410206Sandreas.hansson@arm.com if (queue.size() == 1) { 71510206Sandreas.hansson@arm.com DPRINTF(DRAM, "Single request, nothing to do\n"); 7169243SN/A return; 7179243SN/A } 7189243SN/A 7199243SN/A if (memSchedPolicy == Enums::fcfs) { 7209243SN/A // Do nothing, since the correct request is already head 7219243SN/A } else if (memSchedPolicy == Enums::frfcfs) { 72210206Sandreas.hansson@arm.com reorderQueue(queue); 7239243SN/A } else 7249243SN/A panic("No scheduling policy chosen\n"); 7259243SN/A} 7269243SN/A 7279243SN/Avoid 72810146Sandreas.hansson@arm.comDRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue) 7299974SN/A{ 7309974SN/A // Only determine this when needed 7319974SN/A uint64_t earliest_banks = 0; 7329974SN/A 7339974SN/A // Search for row hits first, if no row hit is found then schedule the 7349974SN/A // packet to one of the earliest banks available 7359974SN/A bool found_earliest_pkt = false; 7369974SN/A auto selected_pkt_it = queue.begin(); 7379974SN/A 7389974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 7399974SN/A DRAMPacket* dram_pkt = *i; 7409974SN/A const Bank& bank = dram_pkt->bankRef; 7419974SN/A // Check if it is a row hit 7429974SN/A if (bank.openRow == dram_pkt->row) { 7439974SN/A DPRINTF(DRAM, "Row buffer hit\n"); 7449974SN/A selected_pkt_it = i; 7459974SN/A break; 7469974SN/A } else if (!found_earliest_pkt) { 7479974SN/A // No row hit, go for first ready 7489974SN/A if (earliest_banks == 0) 7499974SN/A earliest_banks = minBankFreeAt(queue); 7509974SN/A 7519974SN/A // Bank is ready or is the first available bank 7529974SN/A if (bank.freeAt <= curTick() || 7539974SN/A bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) { 7549974SN/A // Remember the packet to be scheduled to one of the earliest 7559974SN/A // banks available 7569974SN/A selected_pkt_it = i; 7579974SN/A found_earliest_pkt = true; 7589974SN/A } 7599974SN/A } 7609974SN/A } 7619974SN/A 7629974SN/A DRAMPacket* selected_pkt = *selected_pkt_it; 7639974SN/A queue.erase(selected_pkt_it); 7649974SN/A queue.push_front(selected_pkt); 7659974SN/A} 7669974SN/A 7679974SN/Avoid 76810146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 7699243SN/A{ 7709243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 7719243SN/A 7729243SN/A bool needsResponse = pkt->needsResponse(); 7739243SN/A // do the actual memory access which also turns the packet into a 7749243SN/A // response 7759243SN/A access(pkt); 7769243SN/A 7779243SN/A // turn packet around to go back to requester if response expected 7789243SN/A if (needsResponse) { 7799243SN/A // access already turned the packet into a response 7809243SN/A assert(pkt->isResponse()); 7819243SN/A 7829549SN/A // @todo someone should pay for this 7839549SN/A pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; 7849549SN/A 7859726SN/A // queue the packet in the response queue to be sent out after 7869726SN/A // the static latency has passed 7879726SN/A port.schedTimingResp(pkt, curTick() + static_latency); 7889243SN/A } else { 7899587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 7909587SN/A // is still having a pointer to it 7919587SN/A pendingDelete.push_back(pkt); 7929243SN/A } 7939243SN/A 7949243SN/A DPRINTF(DRAM, "Done\n"); 7959243SN/A 7969243SN/A return; 7979243SN/A} 7989243SN/A 7999243SN/Apair<Tick, Tick> 80010146Sandreas.hansson@arm.comDRAMCtrl::estimateLatency(DRAMPacket* dram_pkt, Tick inTime) 8019243SN/A{ 8029243SN/A // If a request reaches a bank at tick 'inTime', how much time 8039243SN/A // *after* that does it take to finish the request, depending 8049243SN/A // on bank status and page open policy. Note that this method 8059243SN/A // considers only the time taken for the actual read or write 8069243SN/A // to complete, NOT any additional time thereafter for tRAS or 8079243SN/A // tRP. 8089243SN/A Tick accLat = 0; 8099243SN/A Tick bankLat = 0; 8109243SN/A rowHitFlag = false; 8119243SN/A 8129967SN/A const Bank& bank = dram_pkt->bankRef; 8139243SN/A 81410209Sandreas.hansson@arm.com if (bank.openRow == dram_pkt->row) { 81510209Sandreas.hansson@arm.com // When we have a row-buffer hit, 81610209Sandreas.hansson@arm.com // we don't care about tRAS having expired or not, 81710209Sandreas.hansson@arm.com // but do care about bank being free for access 81810209Sandreas.hansson@arm.com rowHitFlag = true; 8199243SN/A 82010209Sandreas.hansson@arm.com // When a series of requests arrive to the same row, 82110209Sandreas.hansson@arm.com // DDR systems are capable of streaming data continuously 82210209Sandreas.hansson@arm.com // at maximum bandwidth (subject to tCCD). Here, we approximate 82310209Sandreas.hansson@arm.com // this condition, and assume that if whenever a bank is already 82410209Sandreas.hansson@arm.com // busy and a new request comes in, it can be completed with no 82510209Sandreas.hansson@arm.com // penalty beyond waiting for the existing read to complete. 82610209Sandreas.hansson@arm.com if (bank.freeAt > inTime) { 82710209Sandreas.hansson@arm.com accLat += bank.freeAt - inTime; 82810209Sandreas.hansson@arm.com bankLat += 0; 8299243SN/A } else { 83010209Sandreas.hansson@arm.com // CAS latency only 83110209Sandreas.hansson@arm.com accLat += tCL; 83210209Sandreas.hansson@arm.com bankLat += tCL; 83310209Sandreas.hansson@arm.com } 83410209Sandreas.hansson@arm.com } else { 83510210Sandreas.hansson@arm.com // Row-buffer miss, need to potentially close an existing row, 83610210Sandreas.hansson@arm.com // then open the new one, then add CAS latency 83710210Sandreas.hansson@arm.com Tick free_at = bank.freeAt; 83810210Sandreas.hansson@arm.com Tick precharge_delay = 0; 8399243SN/A 84010210Sandreas.hansson@arm.com // Check if we first need to precharge 84110210Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 84210210Sandreas.hansson@arm.com free_at = std::max(bank.preAllowedAt, free_at); 84310210Sandreas.hansson@arm.com precharge_delay = tRP; 84410210Sandreas.hansson@arm.com } 8459243SN/A 84610210Sandreas.hansson@arm.com // If the earliest time to issue the command is in the future, 84710210Sandreas.hansson@arm.com // add it to the access latency 84810210Sandreas.hansson@arm.com if (free_at > inTime) 84910210Sandreas.hansson@arm.com accLat += free_at - inTime; 8509243SN/A 85110210Sandreas.hansson@arm.com // We also need to account for the earliest activation time, 85210210Sandreas.hansson@arm.com // and potentially add that as well to the access latency 85310210Sandreas.hansson@arm.com Tick act_at = inTime + accLat + precharge_delay; 85410210Sandreas.hansson@arm.com if (act_at < bank.actAllowedAt) 85510210Sandreas.hansson@arm.com accLat += bank.actAllowedAt - act_at; 8569969SN/A 85710209Sandreas.hansson@arm.com accLat += precharge_delay + tRCD + tCL; 85810209Sandreas.hansson@arm.com bankLat += precharge_delay + tRCD + tCL; 85910209Sandreas.hansson@arm.com } 8609243SN/A 8619487SN/A DPRINTF(DRAM, "Returning < %lld, %lld > from estimateLatency()\n", 8629487SN/A bankLat, accLat); 8639243SN/A 8649243SN/A return make_pair(bankLat, accLat); 8659243SN/A} 8669243SN/A 8679243SN/Avoid 86810210Sandreas.hansson@arm.comDRAMCtrl::activateBank(Tick act_tick, uint8_t rank, uint8_t bank, 86910210Sandreas.hansson@arm.com uint16_t row, Bank& bank_ref) 8709488SN/A{ 8719969SN/A assert(0 <= rank && rank < ranksPerChannel); 8729969SN/A assert(actTicks[rank].size() == activationLimit); 8739488SN/A 8749488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 8759488SN/A 87610207Sandreas.hansson@arm.com // update the open row 87710210Sandreas.hansson@arm.com assert(bank_ref.openRow == Bank::NO_ROW); 87810210Sandreas.hansson@arm.com bank_ref.openRow = row; 87910207Sandreas.hansson@arm.com 88010207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 88110207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 88210207Sandreas.hansson@arm.com // precharge 88310210Sandreas.hansson@arm.com bank_ref.bytesAccessed = 0; 88410210Sandreas.hansson@arm.com bank_ref.rowAccesses = 0; 88510207Sandreas.hansson@arm.com 88610207Sandreas.hansson@arm.com ++numBanksActive; 88710207Sandreas.hansson@arm.com assert(numBanksActive <= banksPerRank * ranksPerChannel); 88810207Sandreas.hansson@arm.com 88910207Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank at tick %lld, now got %d active\n", 89010207Sandreas.hansson@arm.com act_tick, numBanksActive); 8919975SN/A 8929971SN/A // start by enforcing tRRD 8939971SN/A for(int i = 0; i < banksPerRank; i++) { 89410210Sandreas.hansson@arm.com // next activate to any bank in this rank must not happen 89510210Sandreas.hansson@arm.com // before tRRD 89610210Sandreas.hansson@arm.com banks[rank][i].actAllowedAt = std::max(act_tick + tRRD, 89710210Sandreas.hansson@arm.com banks[rank][i].actAllowedAt); 8989971SN/A } 89910208Sandreas.hansson@arm.com 9009971SN/A // next, we deal with tXAW, if the activation limit is disabled 9019971SN/A // then we are done 9029969SN/A if (actTicks[rank].empty()) 9039824SN/A return; 9049824SN/A 9059488SN/A // sanity check 9069969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 90710210Sandreas.hansson@arm.com panic("Got %d activates in window %d (%llu - %llu) which is smaller " 90810210Sandreas.hansson@arm.com "than %llu\n", activationLimit, act_tick - actTicks[rank].back(), 90910210Sandreas.hansson@arm.com act_tick, actTicks[rank].back(), tXAW); 9109488SN/A } 9119488SN/A 9129488SN/A // shift the times used for the book keeping, the last element 9139488SN/A // (highest index) is the oldest one and hence the lowest value 9149969SN/A actTicks[rank].pop_back(); 9159488SN/A 9169488SN/A // record an new activation (in the future) 9179969SN/A actTicks[rank].push_front(act_tick); 9189488SN/A 9199488SN/A // cannot activate more than X times in time window tXAW, push the 9209488SN/A // next one (the X + 1'st activate) to be tXAW away from the 9219488SN/A // oldest in our window of X 9229969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 9239488SN/A DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate no earlier " 92410210Sandreas.hansson@arm.com "than %llu\n", activationLimit, actTicks[rank].back() + tXAW); 9259488SN/A for(int j = 0; j < banksPerRank; j++) 9269488SN/A // next activate must not happen before end of window 92710210Sandreas.hansson@arm.com banks[rank][j].actAllowedAt = 92810210Sandreas.hansson@arm.com std::max(actTicks[rank].back() + tXAW, 92910210Sandreas.hansson@arm.com banks[rank][j].actAllowedAt); 9309488SN/A } 93110208Sandreas.hansson@arm.com 93210208Sandreas.hansson@arm.com // at the point when this activate takes place, make sure we 93310208Sandreas.hansson@arm.com // transition to the active power state 93410208Sandreas.hansson@arm.com if (!activateEvent.scheduled()) 93510208Sandreas.hansson@arm.com schedule(activateEvent, act_tick); 93610208Sandreas.hansson@arm.com else if (activateEvent.when() > act_tick) 93710208Sandreas.hansson@arm.com // move it sooner in time 93810208Sandreas.hansson@arm.com reschedule(activateEvent, act_tick); 93910208Sandreas.hansson@arm.com} 94010208Sandreas.hansson@arm.com 94110208Sandreas.hansson@arm.comvoid 94210208Sandreas.hansson@arm.comDRAMCtrl::processActivateEvent() 94310208Sandreas.hansson@arm.com{ 94410208Sandreas.hansson@arm.com // we should transition to the active state as soon as any bank is active 94510208Sandreas.hansson@arm.com if (pwrState != PWR_ACT) 94610208Sandreas.hansson@arm.com // note that at this point numBanksActive could be back at 94710208Sandreas.hansson@arm.com // zero again due to a precharge scheduled in the future 94810208Sandreas.hansson@arm.com schedulePowerEvent(PWR_ACT, curTick()); 9499488SN/A} 9509488SN/A 9519488SN/Avoid 95210207Sandreas.hansson@arm.comDRAMCtrl::prechargeBank(Bank& bank, Tick free_at) 95310207Sandreas.hansson@arm.com{ 95410207Sandreas.hansson@arm.com // make sure the bank has an open row 95510207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 95610207Sandreas.hansson@arm.com 95710207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 95810207Sandreas.hansson@arm.com // the page 95910207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 96010207Sandreas.hansson@arm.com 96110207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 96210207Sandreas.hansson@arm.com 96310207Sandreas.hansson@arm.com bank.freeAt = free_at; 96410207Sandreas.hansson@arm.com 96510207Sandreas.hansson@arm.com assert(numBanksActive != 0); 96610207Sandreas.hansson@arm.com --numBanksActive; 96710207Sandreas.hansson@arm.com 96810207Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharged bank, done at tick %lld, now got %d active\n", 96910207Sandreas.hansson@arm.com bank.freeAt, numBanksActive); 97010207Sandreas.hansson@arm.com 97110208Sandreas.hansson@arm.com // if we look at the current number of active banks we might be 97210208Sandreas.hansson@arm.com // tempted to think the DRAM is now idle, however this can be 97310208Sandreas.hansson@arm.com // undone by an activate that is scheduled to happen before we 97410208Sandreas.hansson@arm.com // would have reached the idle state, so schedule an event and 97510208Sandreas.hansson@arm.com // rather check once we actually make it to the point in time when 97610208Sandreas.hansson@arm.com // the (last) precharge takes place 97710208Sandreas.hansson@arm.com if (!prechargeEvent.scheduled()) 97810208Sandreas.hansson@arm.com schedule(prechargeEvent, free_at); 97910208Sandreas.hansson@arm.com else if (prechargeEvent.when() < free_at) 98010208Sandreas.hansson@arm.com reschedule(prechargeEvent, free_at); 98110208Sandreas.hansson@arm.com} 98210208Sandreas.hansson@arm.com 98310208Sandreas.hansson@arm.comvoid 98410208Sandreas.hansson@arm.comDRAMCtrl::processPrechargeEvent() 98510208Sandreas.hansson@arm.com{ 98610207Sandreas.hansson@arm.com // if we reached zero, then special conditions apply as we track 98710207Sandreas.hansson@arm.com // if all banks are precharged for the power models 98810207Sandreas.hansson@arm.com if (numBanksActive == 0) { 98910208Sandreas.hansson@arm.com // we should transition to the idle state when the last bank 99010208Sandreas.hansson@arm.com // is precharged 99110208Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 99210207Sandreas.hansson@arm.com } 99310207Sandreas.hansson@arm.com} 99410207Sandreas.hansson@arm.com 99510207Sandreas.hansson@arm.comvoid 99610146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 9979243SN/A{ 9989243SN/A 9999243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 10009243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 10019243SN/A 10029243SN/A // estimate the bank and access latency 10039243SN/A pair<Tick, Tick> lat = estimateLatency(dram_pkt, curTick()); 10049243SN/A Tick bankLat = lat.first; 10059243SN/A Tick accessLat = lat.second; 10069963SN/A Tick actTick; 10079243SN/A 10089243SN/A // This request was woken up at this time based on a prior call 10099243SN/A // to estimateLatency(). However, between then and now, both the 10109243SN/A // accessLatency and/or busBusyUntil may have changed. We need 10119243SN/A // to correct for that. 10129243SN/A Tick addDelay = (curTick() + accessLat < busBusyUntil) ? 10139243SN/A busBusyUntil - (curTick() + accessLat) : 0; 10149243SN/A 101510210Sandreas.hansson@arm.com // Update request parameters 101610210Sandreas.hansson@arm.com dram_pkt->readyTime = curTick() + addDelay + accessLat + tBURST; 101710210Sandreas.hansson@arm.com 101810210Sandreas.hansson@arm.com DPRINTF(DRAM, "Req %lld: curtick is %lld accessLat is %d " \ 101910210Sandreas.hansson@arm.com "readytime is %lld busbusyuntil is %lld. " \ 102010210Sandreas.hansson@arm.com "Scheduling at readyTime\n", dram_pkt->addr, 102110210Sandreas.hansson@arm.com curTick(), accessLat, dram_pkt->readyTime, busBusyUntil); 102210210Sandreas.hansson@arm.com 102310210Sandreas.hansson@arm.com // Make sure requests are not overlapping on the databus 102410210Sandreas.hansson@arm.com assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 102510210Sandreas.hansson@arm.com 10269967SN/A Bank& bank = dram_pkt->bankRef; 10279243SN/A 10289243SN/A // Update bank state 102910209Sandreas.hansson@arm.com if (rowHitFlag) { 103010209Sandreas.hansson@arm.com bank.freeAt = curTick() + addDelay + accessLat; 103110209Sandreas.hansson@arm.com } else { 103210209Sandreas.hansson@arm.com // If there is a page open, precharge it. 103310209Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 103410209Sandreas.hansson@arm.com prechargeBank(bank, std::max(std::max(bank.freeAt, 103510210Sandreas.hansson@arm.com bank.preAllowedAt), 103610209Sandreas.hansson@arm.com curTick()) + tRP); 10379488SN/A } 10389973SN/A 103910209Sandreas.hansson@arm.com // Any precharge is already part of the latency 104010209Sandreas.hansson@arm.com // estimation, so update the bank free time 104110209Sandreas.hansson@arm.com bank.freeAt = curTick() + addDelay + accessLat; 104210141SN/A 104310209Sandreas.hansson@arm.com // any waiting for banks account for in freeAt 104410209Sandreas.hansson@arm.com actTick = bank.freeAt - tCL - tRCD; 104510141SN/A 104610210Sandreas.hansson@arm.com // The next access has to respect tRAS for this bank 104710210Sandreas.hansson@arm.com bank.preAllowedAt = actTick + tRAS; 10489973SN/A 104910210Sandreas.hansson@arm.com // Record the activation and deal with all the global timing 105010210Sandreas.hansson@arm.com // constraints caused be a new activation (tRRD and tXAW) 105110210Sandreas.hansson@arm.com activateBank(actTick, dram_pkt->rank, dram_pkt->bank, 105210210Sandreas.hansson@arm.com dram_pkt->row, bank); 105310210Sandreas.hansson@arm.com 105410209Sandreas.hansson@arm.com } 105510209Sandreas.hansson@arm.com 105610210Sandreas.hansson@arm.com // If this is a write, we also need to respect the write 105710210Sandreas.hansson@arm.com // recovery time before a precharge 105810210Sandreas.hansson@arm.com if (!dram_pkt->isRead) { 105910210Sandreas.hansson@arm.com bank.preAllowedAt = std::max(bank.preAllowedAt, 106010210Sandreas.hansson@arm.com dram_pkt->readyTime + tWR); 106110210Sandreas.hansson@arm.com } 106210210Sandreas.hansson@arm.com 106310210Sandreas.hansson@arm.com // We also have to respect tRP, and any constraints on when we may 106410210Sandreas.hansson@arm.com // precharge the bank, in the case of reads this is really only 106510210Sandreas.hansson@arm.com // going to cause any change if we did not have a row hit and are 106610210Sandreas.hansson@arm.com // now forced to respect tRAS 106710210Sandreas.hansson@arm.com bank.actAllowedAt = std::max(bank.actAllowedAt, 106810210Sandreas.hansson@arm.com bank.preAllowedAt + tRP); 106910210Sandreas.hansson@arm.com 107010209Sandreas.hansson@arm.com // increment the bytes accessed and the accesses per row 107110209Sandreas.hansson@arm.com bank.bytesAccessed += burstSize; 107210209Sandreas.hansson@arm.com ++bank.rowAccesses; 107310209Sandreas.hansson@arm.com 107410209Sandreas.hansson@arm.com // if we reached the max, then issue with an auto-precharge 107510209Sandreas.hansson@arm.com bool auto_precharge = pageMgmt == Enums::close || 107610209Sandreas.hansson@arm.com bank.rowAccesses == maxAccessesPerRow; 107710209Sandreas.hansson@arm.com 107810209Sandreas.hansson@arm.com // if we did not hit the limit, we might still want to 107910209Sandreas.hansson@arm.com // auto-precharge 108010209Sandreas.hansson@arm.com if (!auto_precharge && 108110209Sandreas.hansson@arm.com (pageMgmt == Enums::open_adaptive || 108210209Sandreas.hansson@arm.com pageMgmt == Enums::close_adaptive)) { 108310209Sandreas.hansson@arm.com // a twist on the open and close page policies: 108410209Sandreas.hansson@arm.com // 1) open_adaptive page policy does not blindly keep the 108510209Sandreas.hansson@arm.com // page open, but close it if there are no row hits, and there 108610209Sandreas.hansson@arm.com // are bank conflicts in the queue 108710209Sandreas.hansson@arm.com // 2) close_adaptive page policy does not blindly close the 108810209Sandreas.hansson@arm.com // page, but closes it only if there are no row hits in the queue. 108910209Sandreas.hansson@arm.com // In this case, only force an auto precharge when there 109010209Sandreas.hansson@arm.com // are no same page hits in the queue 109110209Sandreas.hansson@arm.com bool got_more_hits = false; 109210209Sandreas.hansson@arm.com bool got_bank_conflict = false; 109310209Sandreas.hansson@arm.com 109410209Sandreas.hansson@arm.com // either look at the read queue or write queue 109510209Sandreas.hansson@arm.com const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 109610209Sandreas.hansson@arm.com writeQueue; 109710209Sandreas.hansson@arm.com auto p = queue.begin(); 109810209Sandreas.hansson@arm.com // make sure we are not considering the packet that we are 109910209Sandreas.hansson@arm.com // currently dealing with (which is the head of the queue) 110010209Sandreas.hansson@arm.com ++p; 110110209Sandreas.hansson@arm.com 110210209Sandreas.hansson@arm.com // keep on looking until we have found required condition or 110310209Sandreas.hansson@arm.com // reached the end 110410209Sandreas.hansson@arm.com while (!(got_more_hits && 110510209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive)) && 110610209Sandreas.hansson@arm.com p != queue.end()) { 110710209Sandreas.hansson@arm.com bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 110810209Sandreas.hansson@arm.com (dram_pkt->bank == (*p)->bank); 110910209Sandreas.hansson@arm.com bool same_row = dram_pkt->row == (*p)->row; 111010209Sandreas.hansson@arm.com got_more_hits |= same_rank_bank && same_row; 111110209Sandreas.hansson@arm.com got_bank_conflict |= same_rank_bank && !same_row; 11129973SN/A ++p; 111310141SN/A } 111410141SN/A 111510209Sandreas.hansson@arm.com // auto pre-charge when either 111610209Sandreas.hansson@arm.com // 1) open_adaptive policy, we have not got any more hits, and 111710209Sandreas.hansson@arm.com // have a bank conflict 111810209Sandreas.hansson@arm.com // 2) close_adaptive policy and we have not got any more hits 111910209Sandreas.hansson@arm.com auto_precharge = !got_more_hits && 112010209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive); 112110209Sandreas.hansson@arm.com } 112210142SN/A 112310209Sandreas.hansson@arm.com // if this access should use auto-precharge, then we are 112410209Sandreas.hansson@arm.com // closing the row 112510209Sandreas.hansson@arm.com if (auto_precharge) { 112610210Sandreas.hansson@arm.com prechargeBank(bank, std::max(bank.freeAt, bank.preAllowedAt) + tRP); 11279973SN/A 112810209Sandreas.hansson@arm.com DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 112910209Sandreas.hansson@arm.com } 11309963SN/A 113110209Sandreas.hansson@arm.com DPRINTF(DRAM, "doDRAMAccess::bank.freeAt is %lld\n", bank.freeAt); 11329243SN/A 11339243SN/A // Update bus state 11349243SN/A busBusyUntil = dram_pkt->readyTime; 11359243SN/A 11369243SN/A DPRINTF(DRAM,"Access time is %lld\n", 11379243SN/A dram_pkt->readyTime - dram_pkt->entryTime); 11389243SN/A 113910206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 114010206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 114110206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 114210206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 114310206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 11449972SN/A 114510206Sandreas.hansson@arm.com // Update the stats and schedule the next request 11469977SN/A if (dram_pkt->isRead) { 114710147Sandreas.hansson@arm.com ++readsThisTime; 11489977SN/A if (rowHitFlag) 11499977SN/A readRowHits++; 11509977SN/A bytesReadDRAM += burstSize; 11519977SN/A perBankRdBursts[dram_pkt->bankId]++; 115210206Sandreas.hansson@arm.com 115310206Sandreas.hansson@arm.com // Update latency stats 115410206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 115510206Sandreas.hansson@arm.com totBankLat += bankLat; 115610206Sandreas.hansson@arm.com totBusLat += tBURST; 115710206Sandreas.hansson@arm.com totQLat += dram_pkt->readyTime - dram_pkt->entryTime - bankLat - 115810206Sandreas.hansson@arm.com tBURST; 11599977SN/A } else { 116010147Sandreas.hansson@arm.com ++writesThisTime; 11619977SN/A if (rowHitFlag) 11629977SN/A writeRowHits++; 11639977SN/A bytesWritten += burstSize; 11649977SN/A perBankWrBursts[dram_pkt->bankId]++; 11659243SN/A } 11669243SN/A} 11679243SN/A 11689243SN/Avoid 116910146Sandreas.hansson@arm.comDRAMCtrl::moveToRespQ() 11709243SN/A{ 11719243SN/A // Remove from read queue 11729567SN/A DRAMPacket* dram_pkt = readQueue.front(); 11739567SN/A readQueue.pop_front(); 11749243SN/A 11759832SN/A // sanity check 11769832SN/A assert(dram_pkt->size <= burstSize); 11779832SN/A 11789243SN/A // Insert into response queue sorted by readyTime 11799243SN/A // It will be sent back to the requestor at its 11809243SN/A // readyTime 11819567SN/A if (respQueue.empty()) { 11829567SN/A respQueue.push_front(dram_pkt); 11839243SN/A assert(!respondEvent.scheduled()); 11849243SN/A assert(dram_pkt->readyTime >= curTick()); 11859567SN/A schedule(respondEvent, dram_pkt->readyTime); 11869243SN/A } else { 11879243SN/A bool done = false; 11889833SN/A auto i = respQueue.begin(); 11899567SN/A while (!done && i != respQueue.end()) { 11909243SN/A if ((*i)->readyTime > dram_pkt->readyTime) { 11919567SN/A respQueue.insert(i, dram_pkt); 11929243SN/A done = true; 11939243SN/A } 11949243SN/A ++i; 11959243SN/A } 11969243SN/A 11979243SN/A if (!done) 11989567SN/A respQueue.push_back(dram_pkt); 11999243SN/A 12009243SN/A assert(respondEvent.scheduled()); 12019243SN/A 12029567SN/A if (respQueue.front()->readyTime < respondEvent.when()) { 12039567SN/A assert(respQueue.front()->readyTime >= curTick()); 12049567SN/A reschedule(respondEvent, respQueue.front()->readyTime); 12059243SN/A } 12069243SN/A } 12079243SN/A} 12089243SN/A 12099243SN/Avoid 121010206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 12119243SN/A{ 121210206Sandreas.hansson@arm.com if (busState == READ_TO_WRITE) { 121310206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 121410206Sandreas.hansson@arm.com "waiting\n", readsThisTime, readQueue.size()); 12159243SN/A 121610206Sandreas.hansson@arm.com // sample and reset the read-related stats as we are now 121710206Sandreas.hansson@arm.com // transitioning to writes, and all reads are done 121810206Sandreas.hansson@arm.com rdPerTurnAround.sample(readsThisTime); 121910206Sandreas.hansson@arm.com readsThisTime = 0; 122010206Sandreas.hansson@arm.com 122110206Sandreas.hansson@arm.com // now proceed to do the actual writes 122210206Sandreas.hansson@arm.com busState = WRITE; 122310206Sandreas.hansson@arm.com } else if (busState == WRITE_TO_READ) { 122410206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 122510206Sandreas.hansson@arm.com "waiting\n", writesThisTime, writeQueue.size()); 122610206Sandreas.hansson@arm.com 122710206Sandreas.hansson@arm.com wrPerTurnAround.sample(writesThisTime); 122810206Sandreas.hansson@arm.com writesThisTime = 0; 122910206Sandreas.hansson@arm.com 123010206Sandreas.hansson@arm.com busState = READ; 123110206Sandreas.hansson@arm.com } 123210206Sandreas.hansson@arm.com 123310207Sandreas.hansson@arm.com if (refreshState != REF_IDLE) { 123410207Sandreas.hansson@arm.com // if a refresh waiting for this event loop to finish, then hand 123510207Sandreas.hansson@arm.com // over now, and do not schedule a new nextReqEvent 123610207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 123710207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 123810207Sandreas.hansson@arm.com 123910207Sandreas.hansson@arm.com refreshState = REF_PRE; 124010207Sandreas.hansson@arm.com 124110207Sandreas.hansson@arm.com // hand control back to the refresh event loop 124210207Sandreas.hansson@arm.com schedule(refreshEvent, curTick()); 124310207Sandreas.hansson@arm.com } 124410207Sandreas.hansson@arm.com 124510207Sandreas.hansson@arm.com // let the refresh finish before issuing any further requests 124610207Sandreas.hansson@arm.com return; 124710207Sandreas.hansson@arm.com } 124810207Sandreas.hansson@arm.com 124910206Sandreas.hansson@arm.com // when we get here it is either a read or a write 125010206Sandreas.hansson@arm.com if (busState == READ) { 125110206Sandreas.hansson@arm.com 125210206Sandreas.hansson@arm.com // track if we should switch or not 125310206Sandreas.hansson@arm.com bool switch_to_writes = false; 125410206Sandreas.hansson@arm.com 125510206Sandreas.hansson@arm.com if (readQueue.empty()) { 125610206Sandreas.hansson@arm.com // In the case there is no read request to go next, 125710206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 125810206Sandreas.hansson@arm.com // if we are draining) 125910206Sandreas.hansson@arm.com if (!writeQueue.empty() && 126010206Sandreas.hansson@arm.com (drainManager || writeQueue.size() > writeLowThreshold)) { 126110206Sandreas.hansson@arm.com 126210206Sandreas.hansson@arm.com switch_to_writes = true; 126310206Sandreas.hansson@arm.com } else { 126410206Sandreas.hansson@arm.com // check if we are drained 126510206Sandreas.hansson@arm.com if (respQueue.empty () && drainManager) { 126610206Sandreas.hansson@arm.com drainManager->signalDrainDone(); 126710206Sandreas.hansson@arm.com drainManager = NULL; 126810206Sandreas.hansson@arm.com } 126910206Sandreas.hansson@arm.com 127010206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 127110206Sandreas.hansson@arm.com // event for the next request 127210206Sandreas.hansson@arm.com return; 127310206Sandreas.hansson@arm.com } 127410206Sandreas.hansson@arm.com } else { 127510206Sandreas.hansson@arm.com // Figure out which read request goes next, and move it to the 127610206Sandreas.hansson@arm.com // front of the read queue 127710206Sandreas.hansson@arm.com chooseNext(readQueue); 127810206Sandreas.hansson@arm.com 127910206Sandreas.hansson@arm.com doDRAMAccess(readQueue.front()); 128010206Sandreas.hansson@arm.com 128110206Sandreas.hansson@arm.com // At this point we're done dealing with the request 128210206Sandreas.hansson@arm.com // It will be moved to a separate response queue with a 128310206Sandreas.hansson@arm.com // correct readyTime, and eventually be sent back at that 128410206Sandreas.hansson@arm.com // time 128510206Sandreas.hansson@arm.com moveToRespQ(); 128610206Sandreas.hansson@arm.com 128710206Sandreas.hansson@arm.com // we have so many writes that we have to transition 128810206Sandreas.hansson@arm.com if (writeQueue.size() > writeHighThreshold) { 128910206Sandreas.hansson@arm.com switch_to_writes = true; 129010206Sandreas.hansson@arm.com } 129110206Sandreas.hansson@arm.com } 129210206Sandreas.hansson@arm.com 129310206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 129410206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 129510206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 129610206Sandreas.hansson@arm.com if (switch_to_writes) { 129710206Sandreas.hansson@arm.com // transition to writing 129810206Sandreas.hansson@arm.com busState = READ_TO_WRITE; 129910206Sandreas.hansson@arm.com 130010206Sandreas.hansson@arm.com // add a bubble to the data bus, as defined by the 130110206Sandreas.hansson@arm.com // tRTW parameter 130210206Sandreas.hansson@arm.com busBusyUntil += tRTW; 130310206Sandreas.hansson@arm.com 130410206Sandreas.hansson@arm.com // update the minimum timing between the requests, 130510206Sandreas.hansson@arm.com // this shifts us back in time far enough to do any 130610206Sandreas.hansson@arm.com // bank preparation 130710206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 130810206Sandreas.hansson@arm.com } 13099352SN/A } else { 131010206Sandreas.hansson@arm.com chooseNext(writeQueue); 131110206Sandreas.hansson@arm.com DRAMPacket* dram_pkt = writeQueue.front(); 131210206Sandreas.hansson@arm.com // sanity check 131310206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 131410206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 131510206Sandreas.hansson@arm.com 131610206Sandreas.hansson@arm.com writeQueue.pop_front(); 131710206Sandreas.hansson@arm.com delete dram_pkt; 131810206Sandreas.hansson@arm.com 131910206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 132010206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 132110206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 132210206Sandreas.hansson@arm.com // writes, then switch to reads. 132310206Sandreas.hansson@arm.com if (writeQueue.empty() || 132410206Sandreas.hansson@arm.com (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 132510206Sandreas.hansson@arm.com !drainManager) || 132610206Sandreas.hansson@arm.com (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 132710206Sandreas.hansson@arm.com // turn the bus back around for reads again 132810206Sandreas.hansson@arm.com busState = WRITE_TO_READ; 132910206Sandreas.hansson@arm.com 133010206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 133110206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 133210206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 133310206Sandreas.hansson@arm.com // nothing to do 133410206Sandreas.hansson@arm.com 133510206Sandreas.hansson@arm.com // here we get a bit creative and shift the bus busy time not 133610206Sandreas.hansson@arm.com // just the tWTR, but also a CAS latency to capture the fact 133710206Sandreas.hansson@arm.com // that we are allowed to prepare a new bank, but not issue a 133810206Sandreas.hansson@arm.com // read command until after tWTR, in essence we capture a 133910206Sandreas.hansson@arm.com // bubble on the data bus that is tWTR + tCL 134010206Sandreas.hansson@arm.com busBusyUntil += tWTR + tCL; 134110206Sandreas.hansson@arm.com 134210206Sandreas.hansson@arm.com // update the minimum timing between the requests, this shifts 134310206Sandreas.hansson@arm.com // us back in time far enough to do any bank preparation 134410206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 134510206Sandreas.hansson@arm.com } 134610206Sandreas.hansson@arm.com } 134710206Sandreas.hansson@arm.com 134810206Sandreas.hansson@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 134910206Sandreas.hansson@arm.com 135010206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 135110206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 135210206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 135310206Sandreas.hansson@arm.com // the next request processing 135410206Sandreas.hansson@arm.com if (retryWrReq && writeQueue.size() < writeBufferSize) { 135510206Sandreas.hansson@arm.com retryWrReq = false; 135610206Sandreas.hansson@arm.com port.sendRetry(); 13579352SN/A } 13589243SN/A} 13599243SN/A 13609967SN/Auint64_t 136110146Sandreas.hansson@arm.comDRAMCtrl::minBankFreeAt(const deque<DRAMPacket*>& queue) const 13629967SN/A{ 13639967SN/A uint64_t bank_mask = 0; 13649967SN/A Tick freeAt = MaxTick; 13659967SN/A 13669967SN/A // detemrine if we have queued transactions targetting the 13679967SN/A // bank in question 13689967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 13699967SN/A for (auto p = queue.begin(); p != queue.end(); ++p) { 13709967SN/A got_waiting[(*p)->bankId] = true; 13719967SN/A } 13729967SN/A 13739967SN/A for (int i = 0; i < ranksPerChannel; i++) { 13749967SN/A for (int j = 0; j < banksPerRank; j++) { 13759967SN/A // if we have waiting requests for the bank, and it is 13769967SN/A // amongst the first available, update the mask 13779967SN/A if (got_waiting[i * banksPerRank + j] && 13789967SN/A banks[i][j].freeAt <= freeAt) { 13799967SN/A // reset bank mask if new minimum is found 13809967SN/A if (banks[i][j].freeAt < freeAt) 13819967SN/A bank_mask = 0; 13829967SN/A // set the bit corresponding to the available bank 13839967SN/A uint8_t bit_index = i * ranksPerChannel + j; 13849967SN/A replaceBits(bank_mask, bit_index, bit_index, 1); 13859967SN/A freeAt = banks[i][j].freeAt; 13869967SN/A } 13879967SN/A } 13889967SN/A } 13899967SN/A return bank_mask; 13909967SN/A} 13919967SN/A 13929243SN/Avoid 139310146Sandreas.hansson@arm.comDRAMCtrl::processRefreshEvent() 13949243SN/A{ 139510207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 139610207Sandreas.hansson@arm.com if (refreshState == REF_IDLE) { 139710207Sandreas.hansson@arm.com // remember when the refresh is due 139810207Sandreas.hansson@arm.com refreshDueAt = curTick(); 13999243SN/A 140010207Sandreas.hansson@arm.com // proceed to drain 140110207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 14029243SN/A 140310207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 140410207Sandreas.hansson@arm.com } 140510207Sandreas.hansson@arm.com 140610207Sandreas.hansson@arm.com // let any scheduled read or write go ahead, after which it will 140710207Sandreas.hansson@arm.com // hand control back to this event loop 140810207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 140910207Sandreas.hansson@arm.com if (nextReqEvent.scheduled()) { 141010207Sandreas.hansson@arm.com // hand control over to the request loop until it is 141110207Sandreas.hansson@arm.com // evaluated next 141210207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 141310207Sandreas.hansson@arm.com 141410207Sandreas.hansson@arm.com return; 141510207Sandreas.hansson@arm.com } else { 141610207Sandreas.hansson@arm.com refreshState = REF_PRE; 141710207Sandreas.hansson@arm.com } 141810207Sandreas.hansson@arm.com } 141910207Sandreas.hansson@arm.com 142010207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 142110207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 142210208Sandreas.hansson@arm.com // precharge any active bank if we are not already in the idle 142310208Sandreas.hansson@arm.com // state 142410208Sandreas.hansson@arm.com if (pwrState != PWR_IDLE) { 142510208Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 142610208Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 142710208Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 142810208Sandreas.hansson@arm.com if (banks[i][j].openRow != Bank::NO_ROW) { 142910208Sandreas.hansson@arm.com // respect both causality and any existing bank 143010208Sandreas.hansson@arm.com // constraints 143110208Sandreas.hansson@arm.com Tick free_at = 143210208Sandreas.hansson@arm.com std::max(std::max(banks[i][j].freeAt, 143310210Sandreas.hansson@arm.com banks[i][j].preAllowedAt), 143410208Sandreas.hansson@arm.com curTick()) + tRP; 143510207Sandreas.hansson@arm.com 143610208Sandreas.hansson@arm.com prechargeBank(banks[i][j], free_at); 143710208Sandreas.hansson@arm.com } 143810207Sandreas.hansson@arm.com } 143910207Sandreas.hansson@arm.com } 144010208Sandreas.hansson@arm.com } else { 144110208Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 144210208Sandreas.hansson@arm.com 144310208Sandreas.hansson@arm.com // go ahead and kick the power state machine into gear if 144410208Sandreas.hansson@arm.com // we are already idle 144510208Sandreas.hansson@arm.com schedulePowerEvent(PWR_REF, curTick()); 14469975SN/A } 14479975SN/A 144810208Sandreas.hansson@arm.com refreshState = REF_RUN; 144910208Sandreas.hansson@arm.com assert(numBanksActive == 0); 14509243SN/A 145110208Sandreas.hansson@arm.com // wait for all banks to be precharged, at which point the 145210208Sandreas.hansson@arm.com // power state machine will transition to the idle state, and 145310208Sandreas.hansson@arm.com // automatically move to a refresh, at that point it will also 145410208Sandreas.hansson@arm.com // call this method to get the refresh event loop going again 145510207Sandreas.hansson@arm.com return; 145610207Sandreas.hansson@arm.com } 145710207Sandreas.hansson@arm.com 145810207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 145910207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 146010207Sandreas.hansson@arm.com // should never get here with any banks active 146110207Sandreas.hansson@arm.com assert(numBanksActive == 0); 146210208Sandreas.hansson@arm.com assert(pwrState == PWR_REF); 146310207Sandreas.hansson@arm.com 146410207Sandreas.hansson@arm.com Tick banksFree = curTick() + tRFC; 146510207Sandreas.hansson@arm.com 146610207Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 146710207Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 146810207Sandreas.hansson@arm.com banks[i][j].freeAt = banksFree; 146910207Sandreas.hansson@arm.com } 147010207Sandreas.hansson@arm.com } 147110207Sandreas.hansson@arm.com 147210207Sandreas.hansson@arm.com // make sure we did not wait so long that we cannot make up 147310207Sandreas.hansson@arm.com // for it 147410207Sandreas.hansson@arm.com if (refreshDueAt + tREFI < banksFree) { 147510207Sandreas.hansson@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 147610207Sandreas.hansson@arm.com } 147710207Sandreas.hansson@arm.com 147810207Sandreas.hansson@arm.com // compensate for the delay in actually performing the refresh 147910207Sandreas.hansson@arm.com // when scheduling the next one 148010207Sandreas.hansson@arm.com schedule(refreshEvent, refreshDueAt + tREFI - tRP); 148110207Sandreas.hansson@arm.com 148210208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 148310207Sandreas.hansson@arm.com 148410208Sandreas.hansson@arm.com // move to the idle power state once the refresh is done, this 148510208Sandreas.hansson@arm.com // will also move the refresh state machine to the refresh 148610208Sandreas.hansson@arm.com // idle state 148710208Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, banksFree); 148810207Sandreas.hansson@arm.com 148910208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n", 149010208Sandreas.hansson@arm.com banksFree, refreshDueAt + tREFI); 149110208Sandreas.hansson@arm.com } 149210208Sandreas.hansson@arm.com} 149310208Sandreas.hansson@arm.com 149410208Sandreas.hansson@arm.comvoid 149510208Sandreas.hansson@arm.comDRAMCtrl::schedulePowerEvent(PowerState pwr_state, Tick tick) 149610208Sandreas.hansson@arm.com{ 149710208Sandreas.hansson@arm.com // respect causality 149810208Sandreas.hansson@arm.com assert(tick >= curTick()); 149910208Sandreas.hansson@arm.com 150010208Sandreas.hansson@arm.com if (!powerEvent.scheduled()) { 150110208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 150210208Sandreas.hansson@arm.com tick, pwr_state); 150310208Sandreas.hansson@arm.com 150410208Sandreas.hansson@arm.com // insert the new transition 150510208Sandreas.hansson@arm.com pwrStateTrans = pwr_state; 150610208Sandreas.hansson@arm.com 150710208Sandreas.hansson@arm.com schedule(powerEvent, tick); 150810208Sandreas.hansson@arm.com } else { 150910208Sandreas.hansson@arm.com panic("Scheduled power event at %llu to state %d, " 151010208Sandreas.hansson@arm.com "with scheduled event at %llu to %d\n", tick, pwr_state, 151110208Sandreas.hansson@arm.com powerEvent.when(), pwrStateTrans); 151210208Sandreas.hansson@arm.com } 151310208Sandreas.hansson@arm.com} 151410208Sandreas.hansson@arm.com 151510208Sandreas.hansson@arm.comvoid 151610208Sandreas.hansson@arm.comDRAMCtrl::processPowerEvent() 151710208Sandreas.hansson@arm.com{ 151810208Sandreas.hansson@arm.com // remember where we were, and for how long 151910208Sandreas.hansson@arm.com Tick duration = curTick() - pwrStateTick; 152010208Sandreas.hansson@arm.com PowerState prev_state = pwrState; 152110208Sandreas.hansson@arm.com 152210208Sandreas.hansson@arm.com // update the accounting 152310208Sandreas.hansson@arm.com pwrStateTime[prev_state] += duration; 152410208Sandreas.hansson@arm.com 152510208Sandreas.hansson@arm.com pwrState = pwrStateTrans; 152610208Sandreas.hansson@arm.com pwrStateTick = curTick(); 152710208Sandreas.hansson@arm.com 152810208Sandreas.hansson@arm.com if (pwrState == PWR_IDLE) { 152910208Sandreas.hansson@arm.com DPRINTF(DRAMState, "All banks precharged\n"); 153010208Sandreas.hansson@arm.com 153110208Sandreas.hansson@arm.com // if we were refreshing, make sure we start scheduling requests again 153210208Sandreas.hansson@arm.com if (prev_state == PWR_REF) { 153310208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 153410208Sandreas.hansson@arm.com assert(pwrState == PWR_IDLE); 153510208Sandreas.hansson@arm.com 153610208Sandreas.hansson@arm.com // kick things into action again 153710208Sandreas.hansson@arm.com refreshState = REF_IDLE; 153810208Sandreas.hansson@arm.com assert(!nextReqEvent.scheduled()); 153910208Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 154010208Sandreas.hansson@arm.com } else { 154110208Sandreas.hansson@arm.com assert(prev_state == PWR_ACT); 154210208Sandreas.hansson@arm.com 154310208Sandreas.hansson@arm.com // if we have a pending refresh, and are now moving to 154410208Sandreas.hansson@arm.com // the idle state, direclty transition to a refresh 154510208Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 154610208Sandreas.hansson@arm.com // there should be nothing waiting at this point 154710208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 154810208Sandreas.hansson@arm.com 154910208Sandreas.hansson@arm.com // update the state in zero time and proceed below 155010208Sandreas.hansson@arm.com pwrState = PWR_REF; 155110208Sandreas.hansson@arm.com } 155210208Sandreas.hansson@arm.com } 155310208Sandreas.hansson@arm.com } 155410208Sandreas.hansson@arm.com 155510208Sandreas.hansson@arm.com // we transition to the refresh state, let the refresh state 155610208Sandreas.hansson@arm.com // machine know of this state update and let it deal with the 155710208Sandreas.hansson@arm.com // scheduling of the next power state transition as well as the 155810208Sandreas.hansson@arm.com // following refresh 155910208Sandreas.hansson@arm.com if (pwrState == PWR_REF) { 156010208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refreshing\n"); 156110208Sandreas.hansson@arm.com // kick the refresh event loop into action again, and that 156210208Sandreas.hansson@arm.com // in turn will schedule a transition to the idle power 156310208Sandreas.hansson@arm.com // state once the refresh is done 156410208Sandreas.hansson@arm.com assert(refreshState == REF_RUN); 156510208Sandreas.hansson@arm.com processRefreshEvent(); 156610207Sandreas.hansson@arm.com } 15679243SN/A} 15689243SN/A 15699243SN/Avoid 157010146Sandreas.hansson@arm.comDRAMCtrl::regStats() 15719243SN/A{ 15729243SN/A using namespace Stats; 15739243SN/A 15749243SN/A AbstractMemory::regStats(); 15759243SN/A 15769243SN/A readReqs 15779243SN/A .name(name() + ".readReqs") 15789977SN/A .desc("Number of read requests accepted"); 15799243SN/A 15809243SN/A writeReqs 15819243SN/A .name(name() + ".writeReqs") 15829977SN/A .desc("Number of write requests accepted"); 15839831SN/A 15849831SN/A readBursts 15859831SN/A .name(name() + ".readBursts") 15869977SN/A .desc("Number of DRAM read bursts, " 15879977SN/A "including those serviced by the write queue"); 15889831SN/A 15899831SN/A writeBursts 15909831SN/A .name(name() + ".writeBursts") 15919977SN/A .desc("Number of DRAM write bursts, " 15929977SN/A "including those merged in the write queue"); 15939243SN/A 15949243SN/A servicedByWrQ 15959243SN/A .name(name() + ".servicedByWrQ") 15969977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 15979977SN/A 15989977SN/A mergedWrBursts 15999977SN/A .name(name() + ".mergedWrBursts") 16009977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 16019243SN/A 16029243SN/A neitherReadNorWrite 16039977SN/A .name(name() + ".neitherReadNorWriteReqs") 16049977SN/A .desc("Number of requests that are neither read nor write"); 16059243SN/A 16069977SN/A perBankRdBursts 16079243SN/A .init(banksPerRank * ranksPerChannel) 16089977SN/A .name(name() + ".perBankRdBursts") 16099977SN/A .desc("Per bank write bursts"); 16109243SN/A 16119977SN/A perBankWrBursts 16129243SN/A .init(banksPerRank * ranksPerChannel) 16139977SN/A .name(name() + ".perBankWrBursts") 16149977SN/A .desc("Per bank write bursts"); 16159243SN/A 16169243SN/A avgRdQLen 16179243SN/A .name(name() + ".avgRdQLen") 16189977SN/A .desc("Average read queue length when enqueuing") 16199243SN/A .precision(2); 16209243SN/A 16219243SN/A avgWrQLen 16229243SN/A .name(name() + ".avgWrQLen") 16239977SN/A .desc("Average write queue length when enqueuing") 16249243SN/A .precision(2); 16259243SN/A 16269243SN/A totQLat 16279243SN/A .name(name() + ".totQLat") 16289977SN/A .desc("Total ticks spent queuing"); 16299243SN/A 16309243SN/A totBankLat 16319243SN/A .name(name() + ".totBankLat") 16329977SN/A .desc("Total ticks spent accessing banks"); 16339243SN/A 16349243SN/A totBusLat 16359243SN/A .name(name() + ".totBusLat") 16369977SN/A .desc("Total ticks spent in databus transfers"); 16379243SN/A 16389243SN/A totMemAccLat 16399243SN/A .name(name() + ".totMemAccLat") 16409977SN/A .desc("Total ticks spent from burst creation until serviced " 16419977SN/A "by the DRAM"); 16429243SN/A 16439243SN/A avgQLat 16449243SN/A .name(name() + ".avgQLat") 16459977SN/A .desc("Average queueing delay per DRAM burst") 16469243SN/A .precision(2); 16479243SN/A 16489831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 16499243SN/A 16509243SN/A avgBankLat 16519243SN/A .name(name() + ".avgBankLat") 16529977SN/A .desc("Average bank access latency per DRAM burst") 16539243SN/A .precision(2); 16549243SN/A 16559831SN/A avgBankLat = totBankLat / (readBursts - servicedByWrQ); 16569243SN/A 16579243SN/A avgBusLat 16589243SN/A .name(name() + ".avgBusLat") 16599977SN/A .desc("Average bus latency per DRAM burst") 16609243SN/A .precision(2); 16619243SN/A 16629831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 16639243SN/A 16649243SN/A avgMemAccLat 16659243SN/A .name(name() + ".avgMemAccLat") 16669977SN/A .desc("Average memory access latency per DRAM burst") 16679243SN/A .precision(2); 16689243SN/A 16699831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 16709243SN/A 16719243SN/A numRdRetry 16729243SN/A .name(name() + ".numRdRetry") 16739977SN/A .desc("Number of times read queue was full causing retry"); 16749243SN/A 16759243SN/A numWrRetry 16769243SN/A .name(name() + ".numWrRetry") 16779977SN/A .desc("Number of times write queue was full causing retry"); 16789243SN/A 16799243SN/A readRowHits 16809243SN/A .name(name() + ".readRowHits") 16819243SN/A .desc("Number of row buffer hits during reads"); 16829243SN/A 16839243SN/A writeRowHits 16849243SN/A .name(name() + ".writeRowHits") 16859243SN/A .desc("Number of row buffer hits during writes"); 16869243SN/A 16879243SN/A readRowHitRate 16889243SN/A .name(name() + ".readRowHitRate") 16899243SN/A .desc("Row buffer hit rate for reads") 16909243SN/A .precision(2); 16919243SN/A 16929831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 16939243SN/A 16949243SN/A writeRowHitRate 16959243SN/A .name(name() + ".writeRowHitRate") 16969243SN/A .desc("Row buffer hit rate for writes") 16979243SN/A .precision(2); 16989243SN/A 16999977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 17009243SN/A 17019243SN/A readPktSize 17029831SN/A .init(ceilLog2(burstSize) + 1) 17039243SN/A .name(name() + ".readPktSize") 17049977SN/A .desc("Read request sizes (log2)"); 17059243SN/A 17069243SN/A writePktSize 17079831SN/A .init(ceilLog2(burstSize) + 1) 17089243SN/A .name(name() + ".writePktSize") 17099977SN/A .desc("Write request sizes (log2)"); 17109243SN/A 17119243SN/A rdQLenPdf 17129567SN/A .init(readBufferSize) 17139243SN/A .name(name() + ".rdQLenPdf") 17149243SN/A .desc("What read queue length does an incoming req see"); 17159243SN/A 17169243SN/A wrQLenPdf 17179567SN/A .init(writeBufferSize) 17189243SN/A .name(name() + ".wrQLenPdf") 17199243SN/A .desc("What write queue length does an incoming req see"); 17209243SN/A 17219727SN/A bytesPerActivate 172210141SN/A .init(maxAccessesPerRow) 17239727SN/A .name(name() + ".bytesPerActivate") 17249727SN/A .desc("Bytes accessed per row activation") 17259727SN/A .flags(nozero); 17269243SN/A 172710147Sandreas.hansson@arm.com rdPerTurnAround 172810147Sandreas.hansson@arm.com .init(readBufferSize) 172910147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 173010147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 173110147Sandreas.hansson@arm.com .flags(nozero); 173210147Sandreas.hansson@arm.com 173310147Sandreas.hansson@arm.com wrPerTurnAround 173410147Sandreas.hansson@arm.com .init(writeBufferSize) 173510147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 173610147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 173710147Sandreas.hansson@arm.com .flags(nozero); 173810147Sandreas.hansson@arm.com 17399975SN/A bytesReadDRAM 17409975SN/A .name(name() + ".bytesReadDRAM") 17419975SN/A .desc("Total number of bytes read from DRAM"); 17429975SN/A 17439975SN/A bytesReadWrQ 17449975SN/A .name(name() + ".bytesReadWrQ") 17459975SN/A .desc("Total number of bytes read from write queue"); 17469243SN/A 17479243SN/A bytesWritten 17489243SN/A .name(name() + ".bytesWritten") 17499977SN/A .desc("Total number of bytes written to DRAM"); 17509243SN/A 17519977SN/A bytesReadSys 17529977SN/A .name(name() + ".bytesReadSys") 17539977SN/A .desc("Total read bytes from the system interface side"); 17549243SN/A 17559977SN/A bytesWrittenSys 17569977SN/A .name(name() + ".bytesWrittenSys") 17579977SN/A .desc("Total written bytes from the system interface side"); 17589243SN/A 17599243SN/A avgRdBW 17609243SN/A .name(name() + ".avgRdBW") 17619977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 17629243SN/A .precision(2); 17639243SN/A 17649977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 17659243SN/A 17669243SN/A avgWrBW 17679243SN/A .name(name() + ".avgWrBW") 17689977SN/A .desc("Average achieved write bandwidth in MiByte/s") 17699243SN/A .precision(2); 17709243SN/A 17719243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 17729243SN/A 17739977SN/A avgRdBWSys 17749977SN/A .name(name() + ".avgRdBWSys") 17759977SN/A .desc("Average system read bandwidth in MiByte/s") 17769243SN/A .precision(2); 17779243SN/A 17789977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 17799243SN/A 17809977SN/A avgWrBWSys 17819977SN/A .name(name() + ".avgWrBWSys") 17829977SN/A .desc("Average system write bandwidth in MiByte/s") 17839243SN/A .precision(2); 17849243SN/A 17859977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 17869243SN/A 17879243SN/A peakBW 17889243SN/A .name(name() + ".peakBW") 17899977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 17909243SN/A .precision(2); 17919243SN/A 17929831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 17939243SN/A 17949243SN/A busUtil 17959243SN/A .name(name() + ".busUtil") 17969243SN/A .desc("Data bus utilization in percentage") 17979243SN/A .precision(2); 17989243SN/A 17999243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 18009243SN/A 18019243SN/A totGap 18029243SN/A .name(name() + ".totGap") 18039243SN/A .desc("Total gap between requests"); 18049243SN/A 18059243SN/A avgGap 18069243SN/A .name(name() + ".avgGap") 18079243SN/A .desc("Average gap between requests") 18089243SN/A .precision(2); 18099243SN/A 18109243SN/A avgGap = totGap / (readReqs + writeReqs); 18119975SN/A 18129975SN/A // Stats for DRAM Power calculation based on Micron datasheet 18139975SN/A busUtilRead 18149975SN/A .name(name() + ".busUtilRead") 18159975SN/A .desc("Data bus utilization in percentage for reads") 18169975SN/A .precision(2); 18179975SN/A 18189975SN/A busUtilRead = avgRdBW / peakBW * 100; 18199975SN/A 18209975SN/A busUtilWrite 18219975SN/A .name(name() + ".busUtilWrite") 18229975SN/A .desc("Data bus utilization in percentage for writes") 18239975SN/A .precision(2); 18249975SN/A 18259975SN/A busUtilWrite = avgWrBW / peakBW * 100; 18269975SN/A 18279975SN/A pageHitRate 18289975SN/A .name(name() + ".pageHitRate") 18299975SN/A .desc("Row buffer hit rate, read and write combined") 18309975SN/A .precision(2); 18319975SN/A 18329977SN/A pageHitRate = (writeRowHits + readRowHits) / 18339977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 18349975SN/A 183510208Sandreas.hansson@arm.com pwrStateTime 183610208Sandreas.hansson@arm.com .init(5) 183710208Sandreas.hansson@arm.com .name(name() + ".memoryStateTime") 183810208Sandreas.hansson@arm.com .desc("Time in different power states"); 183910208Sandreas.hansson@arm.com pwrStateTime.subname(0, "IDLE"); 184010208Sandreas.hansson@arm.com pwrStateTime.subname(1, "REF"); 184110208Sandreas.hansson@arm.com pwrStateTime.subname(2, "PRE_PDN"); 184210208Sandreas.hansson@arm.com pwrStateTime.subname(3, "ACT"); 184310208Sandreas.hansson@arm.com pwrStateTime.subname(4, "ACT_PDN"); 18449243SN/A} 18459243SN/A 18469243SN/Avoid 184710146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 18489243SN/A{ 18499243SN/A // rely on the abstract memory 18509243SN/A functionalAccess(pkt); 18519243SN/A} 18529243SN/A 18539294SN/ABaseSlavePort& 185410146Sandreas.hansson@arm.comDRAMCtrl::getSlavePort(const string &if_name, PortID idx) 18559243SN/A{ 18569243SN/A if (if_name != "port") { 18579243SN/A return MemObject::getSlavePort(if_name, idx); 18589243SN/A } else { 18599243SN/A return port; 18609243SN/A } 18619243SN/A} 18629243SN/A 18639243SN/Aunsigned int 186410146Sandreas.hansson@arm.comDRAMCtrl::drain(DrainManager *dm) 18659243SN/A{ 18669342SN/A unsigned int count = port.drain(dm); 18679243SN/A 18689243SN/A // if there is anything in any of our internal queues, keep track 18699243SN/A // of that as well 18709567SN/A if (!(writeQueue.empty() && readQueue.empty() && 18719567SN/A respQueue.empty())) { 18729352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 18739567SN/A " resp: %d\n", writeQueue.size(), readQueue.size(), 18749567SN/A respQueue.size()); 18759243SN/A ++count; 18769342SN/A drainManager = dm; 187710206Sandreas.hansson@arm.com 18789352SN/A // the only part that is not drained automatically over time 187910206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 188010206Sandreas.hansson@arm.com if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 188110206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 188210206Sandreas.hansson@arm.com } 18839243SN/A } 18849243SN/A 18859243SN/A if (count) 18869342SN/A setDrainState(Drainable::Draining); 18879243SN/A else 18889342SN/A setDrainState(Drainable::Drained); 18899243SN/A return count; 18909243SN/A} 18919243SN/A 189210146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 18939243SN/A : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 18949243SN/A memory(_memory) 18959243SN/A{ } 18969243SN/A 18979243SN/AAddrRangeList 189810146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 18999243SN/A{ 19009243SN/A AddrRangeList ranges; 19019243SN/A ranges.push_back(memory.getAddrRange()); 19029243SN/A return ranges; 19039243SN/A} 19049243SN/A 19059243SN/Avoid 190610146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 19079243SN/A{ 19089243SN/A pkt->pushLabel(memory.name()); 19099243SN/A 19109243SN/A if (!queue.checkFunctional(pkt)) { 19119243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 19129243SN/A // calls recvAtomic() and throws away the latency; we can save a 19139243SN/A // little here by just not calculating the latency. 19149243SN/A memory.recvFunctional(pkt); 19159243SN/A } 19169243SN/A 19179243SN/A pkt->popLabel(); 19189243SN/A} 19199243SN/A 19209243SN/ATick 192110146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 19229243SN/A{ 19239243SN/A return memory.recvAtomic(pkt); 19249243SN/A} 19259243SN/A 19269243SN/Abool 192710146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 19289243SN/A{ 19299243SN/A // pass it to the memory controller 19309243SN/A return memory.recvTimingReq(pkt); 19319243SN/A} 19329243SN/A 193310146Sandreas.hansson@arm.comDRAMCtrl* 193410146Sandreas.hansson@arm.comDRAMCtrlParams::create() 19359243SN/A{ 193610146Sandreas.hansson@arm.com return new DRAMCtrl(this); 19379243SN/A} 1938