dram_ctrl.cc revision 10209
19243SN/A/* 210206Sandreas.hansson@arm.com * Copyright (c) 2010-2014 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 439243SN/A */ 449243SN/A 4510146Sandreas.hansson@arm.com#include "base/bitfield.hh" 469356SN/A#include "base/trace.hh" 4710146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 4810208Sandreas.hansson@arm.com#include "debug/DRAMState.hh" 499352SN/A#include "debug/Drain.hh" 5010146Sandreas.hansson@arm.com#include "mem/dram_ctrl.hh" 519814SN/A#include "sim/system.hh" 529243SN/A 539243SN/Ausing namespace std; 549243SN/A 5510146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 569243SN/A AbstractMemory(p), 579243SN/A port(name() + ".port", *this), 589243SN/A retryRdReq(false), retryWrReq(false), 5910206Sandreas.hansson@arm.com rowHitFlag(false), busState(READ), 6010208Sandreas.hansson@arm.com nextReqEvent(this), respondEvent(this), activateEvent(this), 6110208Sandreas.hansson@arm.com prechargeEvent(this), refreshEvent(this), powerEvent(this), 6210208Sandreas.hansson@arm.com drainManager(NULL), 639831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 649831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 659831SN/A devicesPerRank(p->devices_per_rank), 669831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 679831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 6810140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 699243SN/A ranksPerChannel(p->ranks_per_channel), 709566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 719243SN/A readBufferSize(p->read_buffer_size), 729243SN/A writeBufferSize(p->write_buffer_size), 7310140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 7410140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 7510147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 7610147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 7710206Sandreas.hansson@arm.com tWTR(p->tWTR), tRTW(p->tRTW), tBURST(p->tBURST), 789963SN/A tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), 799971SN/A tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 809488SN/A tXAW(p->tXAW), activationLimit(p->activation_limit), 819243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 829243SN/A pageMgmt(p->page_policy), 8310141SN/A maxAccessesPerRow(p->max_accesses_per_row), 849726SN/A frontendLatency(p->static_frontend_latency), 859726SN/A backendLatency(p->static_backend_latency), 8610208Sandreas.hansson@arm.com busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE), 8710208Sandreas.hansson@arm.com pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), prevArrival(0), 8810208Sandreas.hansson@arm.com nextReqTime(0), pwrStateTick(0), numBanksActive(0) 899243SN/A{ 909243SN/A // create the bank states based on the dimensions of the ranks and 919243SN/A // banks 929243SN/A banks.resize(ranksPerChannel); 939969SN/A actTicks.resize(ranksPerChannel); 949243SN/A for (size_t c = 0; c < ranksPerChannel; ++c) { 959243SN/A banks[c].resize(banksPerRank); 969969SN/A actTicks[c].resize(activationLimit, 0); 979243SN/A } 989243SN/A 9910140SN/A // perform a basic check of the write thresholds 10010140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 10110140SN/A fatal("Write buffer low threshold %d must be smaller than the " 10210140SN/A "high threshold %d\n", p->write_low_thresh_perc, 10310140SN/A p->write_high_thresh_perc); 1049243SN/A 1059243SN/A // determine the rows per bank by looking at the total capacity 1069567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1079243SN/A 1089243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1099243SN/A AbstractMemory::size()); 1109831SN/A 1119831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1129831SN/A rowBufferSize, columnsPerRowBuffer); 1139831SN/A 1149831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1159243SN/A 1169566SN/A if (range.interleaved()) { 1179566SN/A if (channels != range.stripes()) 11810143SN/A fatal("%s has %d interleaved address stripes but %d channel(s)\n", 1199566SN/A name(), range.stripes(), channels); 1209566SN/A 12110136SN/A if (addrMapping == Enums::RoRaBaChCo) { 1229831SN/A if (rowBufferSize != range.granularity()) { 12310143SN/A fatal("Interleaving of %s doesn't match RoRaBaChCo " 12410136SN/A "address map\n", name()); 1259566SN/A } 12610136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 12710136SN/A if (system()->cacheLineSize() != range.granularity()) { 12810143SN/A fatal("Interleaving of %s doesn't match RoRaBaCoCh " 12910136SN/A "address map\n", name()); 1309669SN/A } 13110136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 13210136SN/A if (system()->cacheLineSize() != range.granularity()) 13310143SN/A fatal("Interleaving of %s doesn't match RoCoRaBaCh " 13410136SN/A "address map\n", name()); 1359566SN/A } 1369566SN/A } 13710207Sandreas.hansson@arm.com 13810207Sandreas.hansson@arm.com // some basic sanity checks 13910207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 14010207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 14110207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 14210207Sandreas.hansson@arm.com } 1439243SN/A} 1449243SN/A 1459243SN/Avoid 14610146Sandreas.hansson@arm.comDRAMCtrl::init() 14710140SN/A{ 14810140SN/A if (!port.isConnected()) { 14910146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 15010140SN/A } else { 15110140SN/A port.sendRangeChange(); 15210140SN/A } 15310140SN/A} 15410140SN/A 15510140SN/Avoid 15610146Sandreas.hansson@arm.comDRAMCtrl::startup() 1579243SN/A{ 15810143SN/A // update the start tick for the precharge accounting to the 15910143SN/A // current tick 16010208Sandreas.hansson@arm.com pwrStateTick = curTick(); 16110143SN/A 16210206Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 16310206Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 16410206Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 16510206Sandreas.hansson@arm.com // start of simulation 16610206Sandreas.hansson@arm.com busBusyUntil = curTick() + tRP + tRCD + tCL; 16710206Sandreas.hansson@arm.com 1689243SN/A // print the configuration of the controller 1699243SN/A printParams(); 1709243SN/A 17110207Sandreas.hansson@arm.com // kick off the refresh, and give ourselves enough time to 17210207Sandreas.hansson@arm.com // precharge 17310207Sandreas.hansson@arm.com schedule(refreshEvent, curTick() + tREFI - tRP); 1749243SN/A} 1759243SN/A 1769243SN/ATick 17710146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 1789243SN/A{ 1799243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 1809243SN/A 1819243SN/A // do the actual memory access and turn the packet into a response 1829243SN/A access(pkt); 1839243SN/A 1849243SN/A Tick latency = 0; 1859243SN/A if (!pkt->memInhibitAsserted() && pkt->hasData()) { 1869243SN/A // this value is not supposed to be accurate, just enough to 1879243SN/A // keep things going, mimic a closed page 1889243SN/A latency = tRP + tRCD + tCL; 1899243SN/A } 1909243SN/A return latency; 1919243SN/A} 1929243SN/A 1939243SN/Abool 19410146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 1959243SN/A{ 1969831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 1979831SN/A readBufferSize, readQueue.size() + respQueue.size(), 1989831SN/A neededEntries); 1999243SN/A 2009831SN/A return 2019831SN/A (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 2029243SN/A} 2039243SN/A 2049243SN/Abool 20510146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 2069243SN/A{ 2079831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 2089831SN/A writeBufferSize, writeQueue.size(), neededEntries); 2099831SN/A return (writeQueue.size() + neededEntries) > writeBufferSize; 2109243SN/A} 2119243SN/A 21210146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 21310146Sandreas.hansson@arm.comDRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 21410143SN/A bool isRead) 2159243SN/A{ 2169669SN/A // decode the address based on the address mapping scheme, with 21710136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 21810136SN/A // channel, respectively 2199243SN/A uint8_t rank; 2209967SN/A uint8_t bank; 2219243SN/A uint16_t row; 2229243SN/A 2239243SN/A // truncate the address to the access granularity 2249831SN/A Addr addr = dramPktAddr / burstSize; 2259243SN/A 2269491SN/A // we have removed the lowest order address bits that denote the 2279831SN/A // position within the column 22810136SN/A if (addrMapping == Enums::RoRaBaChCo) { 2299491SN/A // the lowest order bits denote the column to ensure that 2309491SN/A // sequential cache lines occupy the same row 2319831SN/A addr = addr / columnsPerRowBuffer; 2329243SN/A 2339669SN/A // take out the channel part of the address 2349566SN/A addr = addr / channels; 2359566SN/A 2369669SN/A // after the channel bits, get the bank bits to interleave 2379669SN/A // over the banks 2389669SN/A bank = addr % banksPerRank; 2399669SN/A addr = addr / banksPerRank; 2409669SN/A 2419669SN/A // after the bank, we get the rank bits which thus interleaves 2429669SN/A // over the ranks 2439669SN/A rank = addr % ranksPerChannel; 2449669SN/A addr = addr / ranksPerChannel; 2459669SN/A 2469669SN/A // lastly, get the row bits 2479669SN/A row = addr % rowsPerBank; 2489669SN/A addr = addr / rowsPerBank; 24910136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 2509669SN/A // take out the channel part of the address 2519669SN/A addr = addr / channels; 2529669SN/A 2539669SN/A // next, the column 2549831SN/A addr = addr / columnsPerRowBuffer; 2559669SN/A 2569669SN/A // after the column bits, we get the bank bits to interleave 2579491SN/A // over the banks 2589243SN/A bank = addr % banksPerRank; 2599243SN/A addr = addr / banksPerRank; 2609243SN/A 2619491SN/A // after the bank, we get the rank bits which thus interleaves 2629491SN/A // over the ranks 2639243SN/A rank = addr % ranksPerChannel; 2649243SN/A addr = addr / ranksPerChannel; 2659243SN/A 2669491SN/A // lastly, get the row bits 2679243SN/A row = addr % rowsPerBank; 2689243SN/A addr = addr / rowsPerBank; 26910136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 2709491SN/A // optimise for closed page mode and utilise maximum 2719491SN/A // parallelism of the DRAM (at the cost of power) 2729491SN/A 2739566SN/A // take out the channel part of the address, not that this has 2749566SN/A // to match with how accesses are interleaved between the 2759566SN/A // controllers in the address mapping 2769566SN/A addr = addr / channels; 2779566SN/A 2789491SN/A // start with the bank bits, as this provides the maximum 2799491SN/A // opportunity for parallelism between requests 2809243SN/A bank = addr % banksPerRank; 2819243SN/A addr = addr / banksPerRank; 2829243SN/A 2839491SN/A // next get the rank bits 2849243SN/A rank = addr % ranksPerChannel; 2859243SN/A addr = addr / ranksPerChannel; 2869243SN/A 2879491SN/A // next the column bits which we do not need to keep track of 2889491SN/A // and simply skip past 2899831SN/A addr = addr / columnsPerRowBuffer; 2909243SN/A 2919491SN/A // lastly, get the row bits 2929243SN/A row = addr % rowsPerBank; 2939243SN/A addr = addr / rowsPerBank; 2949243SN/A } else 2959243SN/A panic("Unknown address mapping policy chosen!"); 2969243SN/A 2979243SN/A assert(rank < ranksPerChannel); 2989243SN/A assert(bank < banksPerRank); 2999243SN/A assert(row < rowsPerBank); 3009243SN/A 3019243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 3029831SN/A dramPktAddr, rank, bank, row); 3039243SN/A 3049243SN/A // create the corresponding DRAM packet with the entry time and 3059567SN/A // ready time set to the current tick, the latter will be updated 3069567SN/A // later 3079967SN/A uint16_t bank_id = banksPerRank * rank + bank; 3089967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 3099967SN/A size, banks[rank][bank]); 3109243SN/A} 3119243SN/A 3129243SN/Avoid 31310146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 3149243SN/A{ 3159243SN/A // only add to the read queue here. whenever the request is 3169243SN/A // eventually done, set the readyTime, and call schedule() 3179243SN/A assert(!pkt->isWrite()); 3189243SN/A 3199831SN/A assert(pktCount != 0); 3209831SN/A 3219831SN/A // if the request size is larger than burst size, the pkt is split into 3229831SN/A // multiple DRAM packets 3239831SN/A // Note if the pkt starting address is not aligened to burst size, the 3249831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 3259831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 3269831SN/A // check read packets against packets in write queue. 3279243SN/A Addr addr = pkt->getAddr(); 3289831SN/A unsigned pktsServicedByWrQ = 0; 3299831SN/A BurstHelper* burst_helper = NULL; 3309831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 3319831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 3329831SN/A pkt->getAddr() + pkt->getSize()) - addr; 3339831SN/A readPktSize[ceilLog2(size)]++; 3349831SN/A readBursts++; 3359243SN/A 3369831SN/A // First check write buffer to see if the data is already at 3379831SN/A // the controller 3389831SN/A bool foundInWrQ = false; 3399833SN/A for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) { 3409832SN/A // check if the read is subsumed in the write entry we are 3419832SN/A // looking at 3429832SN/A if ((*i)->addr <= addr && 3439832SN/A (addr + size) <= ((*i)->addr + (*i)->size)) { 3449831SN/A foundInWrQ = true; 3459831SN/A servicedByWrQ++; 3469831SN/A pktsServicedByWrQ++; 3479831SN/A DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 3489831SN/A "write queue\n", addr, size); 3499975SN/A bytesReadWrQ += burstSize; 3509831SN/A break; 3519831SN/A } 3529243SN/A } 3539831SN/A 3549831SN/A // If not found in the write q, make a DRAM packet and 3559831SN/A // push it onto the read queue 3569831SN/A if (!foundInWrQ) { 3579831SN/A 3589831SN/A // Make the burst helper for split packets 3599831SN/A if (pktCount > 1 && burst_helper == NULL) { 3609831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 3619831SN/A "dram requests\n", pkt->getAddr(), pktCount); 3629831SN/A burst_helper = new BurstHelper(pktCount); 3639831SN/A } 3649831SN/A 3659966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 3669831SN/A dram_pkt->burstHelper = burst_helper; 3679831SN/A 3689831SN/A assert(!readQueueFull(1)); 3699831SN/A rdQLenPdf[readQueue.size() + respQueue.size()]++; 3709831SN/A 3719831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 3729831SN/A 3739831SN/A readQueue.push_back(dram_pkt); 3749831SN/A 3759831SN/A // Update stats 3769831SN/A avgRdQLen = readQueue.size() + respQueue.size(); 3779831SN/A } 3789831SN/A 3799831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 3809831SN/A addr = (addr | (burstSize - 1)) + 1; 3819243SN/A } 3829243SN/A 3839831SN/A // If all packets are serviced by write queue, we send the repsonse back 3849831SN/A if (pktsServicedByWrQ == pktCount) { 3859831SN/A accessAndRespond(pkt, frontendLatency); 3869831SN/A return; 3879831SN/A } 3889243SN/A 3899831SN/A // Update how many split packets are serviced by write queue 3909831SN/A if (burst_helper != NULL) 3919831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 3929243SN/A 39310206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 39410206Sandreas.hansson@arm.com // queue, do so now 39510206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 3969567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 3979567SN/A schedule(nextReqEvent, curTick()); 3989243SN/A } 3999243SN/A} 4009243SN/A 4019243SN/Avoid 40210146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 4039243SN/A{ 4049243SN/A // only add to the write queue here. whenever the request is 4059243SN/A // eventually done, set the readyTime, and call schedule() 4069243SN/A assert(pkt->isWrite()); 4079243SN/A 4089831SN/A // if the request size is larger than burst size, the pkt is split into 4099831SN/A // multiple DRAM packets 4109831SN/A Addr addr = pkt->getAddr(); 4119831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4129831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4139831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4149831SN/A writePktSize[ceilLog2(size)]++; 4159831SN/A writeBursts++; 4169243SN/A 4179832SN/A // see if we can merge with an existing item in the write 4189838SN/A // queue and keep track of whether we have merged or not so we 4199838SN/A // can stop at that point and also avoid enqueueing a new 4209838SN/A // request 4219832SN/A bool merged = false; 4229832SN/A auto w = writeQueue.begin(); 4239243SN/A 4249832SN/A while(!merged && w != writeQueue.end()) { 4259832SN/A // either of the two could be first, if they are the same 4269832SN/A // it does not matter which way we go 4279832SN/A if ((*w)->addr >= addr) { 4289838SN/A // the existing one starts after the new one, figure 4299838SN/A // out where the new one ends with respect to the 4309838SN/A // existing one 4319832SN/A if ((addr + size) >= ((*w)->addr + (*w)->size)) { 4329832SN/A // check if the existing one is completely 4339832SN/A // subsumed in the new one 4349832SN/A DPRINTF(DRAM, "Merging write covering existing burst\n"); 4359832SN/A merged = true; 4369832SN/A // update both the address and the size 4379832SN/A (*w)->addr = addr; 4389832SN/A (*w)->size = size; 4399832SN/A } else if ((addr + size) >= (*w)->addr && 4409832SN/A ((*w)->addr + (*w)->size - addr) <= burstSize) { 4419832SN/A // the new one is just before or partially 4429832SN/A // overlapping with the existing one, and together 4439832SN/A // they fit within a burst 4449832SN/A DPRINTF(DRAM, "Merging write before existing burst\n"); 4459832SN/A merged = true; 4469832SN/A // the existing queue item needs to be adjusted with 4479832SN/A // respect to both address and size 44810047SN/A (*w)->size = (*w)->addr + (*w)->size - addr; 4499832SN/A (*w)->addr = addr; 4509832SN/A } 4519832SN/A } else { 4529838SN/A // the new one starts after the current one, figure 4539838SN/A // out where the existing one ends with respect to the 4549838SN/A // new one 4559832SN/A if (((*w)->addr + (*w)->size) >= (addr + size)) { 4569832SN/A // check if the new one is completely subsumed in the 4579832SN/A // existing one 4589832SN/A DPRINTF(DRAM, "Merging write into existing burst\n"); 4599832SN/A merged = true; 4609832SN/A // no adjustments necessary 4619832SN/A } else if (((*w)->addr + (*w)->size) >= addr && 4629832SN/A (addr + size - (*w)->addr) <= burstSize) { 4639832SN/A // the existing one is just before or partially 4649832SN/A // overlapping with the new one, and together 4659832SN/A // they fit within a burst 4669832SN/A DPRINTF(DRAM, "Merging write after existing burst\n"); 4679832SN/A merged = true; 4689832SN/A // the address is right, and only the size has 4699832SN/A // to be adjusted 4709832SN/A (*w)->size = addr + size - (*w)->addr; 4719832SN/A } 4729832SN/A } 4739832SN/A ++w; 4749832SN/A } 4759243SN/A 4769832SN/A // if the item was not merged we need to create a new write 4779832SN/A // and enqueue it 4789832SN/A if (!merged) { 4799966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 4809243SN/A 4819832SN/A assert(writeQueue.size() < writeBufferSize); 4829832SN/A wrQLenPdf[writeQueue.size()]++; 4839243SN/A 4849832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 4859831SN/A 4869832SN/A writeQueue.push_back(dram_pkt); 4879831SN/A 4889832SN/A // Update stats 4899832SN/A avgWrQLen = writeQueue.size(); 4909977SN/A } else { 4919977SN/A // keep track of the fact that this burst effectively 4929977SN/A // disappeared as it was merged with an existing one 4939977SN/A mergedWrBursts++; 4949832SN/A } 4959832SN/A 4969831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 4979831SN/A addr = (addr | (burstSize - 1)) + 1; 4989831SN/A } 4999243SN/A 5009243SN/A // we do not wait for the writes to be send to the actual memory, 5019243SN/A // but instead take responsibility for the consistency here and 5029243SN/A // snoop the write queue for any upcoming reads 5039831SN/A // @todo, if a pkt size is larger than burst size, we might need a 5049831SN/A // different front end latency 5059726SN/A accessAndRespond(pkt, frontendLatency); 5069243SN/A 50710206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 50810206Sandreas.hansson@arm.com // queue, do so now 50910206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 51010206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 51110206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 5129243SN/A } 5139243SN/A} 5149243SN/A 5159243SN/Avoid 51610146Sandreas.hansson@arm.comDRAMCtrl::printParams() const 5179243SN/A{ 5189243SN/A // Sanity check print of important parameters 5199243SN/A DPRINTF(DRAM, 5209243SN/A "Memory controller %s physical organization\n" \ 5219831SN/A "Number of devices per rank %d\n" \ 5229831SN/A "Device bus width (in bits) %d\n" \ 52310143SN/A "DRAM data bus burst (bytes) %d\n" \ 52410143SN/A "Row buffer size (bytes) %d\n" \ 5259831SN/A "Columns per row buffer %d\n" \ 5269831SN/A "Rows per bank %d\n" \ 5279831SN/A "Banks per rank %d\n" \ 5289831SN/A "Ranks per channel %d\n" \ 52910143SN/A "Total mem capacity (bytes) %u\n", 5309831SN/A name(), devicesPerRank, deviceBusWidth, burstSize, rowBufferSize, 5319831SN/A columnsPerRowBuffer, rowsPerBank, banksPerRank, ranksPerChannel, 5329831SN/A rowBufferSize * rowsPerBank * banksPerRank * ranksPerChannel); 5339243SN/A 5349243SN/A string scheduler = memSchedPolicy == Enums::fcfs ? "FCFS" : "FR-FCFS"; 53510136SN/A string address_mapping = addrMapping == Enums::RoRaBaChCo ? "RoRaBaChCo" : 53610136SN/A (addrMapping == Enums::RoRaBaCoCh ? "RoRaBaCoCh" : "RoCoRaBaCh"); 5379973SN/A string page_policy = pageMgmt == Enums::open ? "OPEN" : 53810144SN/A (pageMgmt == Enums::open_adaptive ? "OPEN (adaptive)" : 53910144SN/A (pageMgmt == Enums::close_adaptive ? "CLOSE (adaptive)" : "CLOSE")); 5409243SN/A 5419243SN/A DPRINTF(DRAM, 5429243SN/A "Memory controller %s characteristics\n" \ 5439243SN/A "Read buffer size %d\n" \ 5449243SN/A "Write buffer size %d\n" \ 54510140SN/A "Write high thresh %d\n" \ 54610140SN/A "Write low thresh %d\n" \ 5479243SN/A "Scheduler %s\n" \ 5489243SN/A "Address mapping %s\n" \ 5499243SN/A "Page policy %s\n", 5509972SN/A name(), readBufferSize, writeBufferSize, writeHighThreshold, 55110140SN/A writeLowThreshold, scheduler, address_mapping, page_policy); 5529243SN/A 5539243SN/A DPRINTF(DRAM, "Memory controller %s timing specs\n" \ 5549567SN/A "tRCD %d ticks\n" \ 5559567SN/A "tCL %d ticks\n" \ 5569567SN/A "tRP %d ticks\n" \ 5579567SN/A "tBURST %d ticks\n" \ 5589567SN/A "tRFC %d ticks\n" \ 5599567SN/A "tREFI %d ticks\n" \ 5609567SN/A "tWTR %d ticks\n" \ 56110206Sandreas.hansson@arm.com "tRTW %d ticks\n" \ 5629567SN/A "tXAW (%d) %d ticks\n", 5639567SN/A name(), tRCD, tCL, tRP, tBURST, tRFC, tREFI, tWTR, 56410206Sandreas.hansson@arm.com tRTW, activationLimit, tXAW); 5659243SN/A} 5669243SN/A 5679243SN/Avoid 56810146Sandreas.hansson@arm.comDRAMCtrl::printQs() const { 5699243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 5709833SN/A for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 5719243SN/A DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 5729243SN/A } 5739243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 5749833SN/A for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 5759243SN/A DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 5769243SN/A } 5779243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 5789833SN/A for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 5799243SN/A DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 5809243SN/A } 5819243SN/A} 5829243SN/A 5839243SN/Abool 58410146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 5859243SN/A{ 5869349SN/A /// @todo temporary hack to deal with memory corruption issues until 5879349SN/A /// 4-phase transactions are complete 5889349SN/A for (int x = 0; x < pendingDelete.size(); x++) 5899349SN/A delete pendingDelete[x]; 5909349SN/A pendingDelete.clear(); 5919349SN/A 5929243SN/A // This is where we enter from the outside world 5939567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 5949831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 5959243SN/A 5969567SN/A // simply drop inhibited packets for now 5979567SN/A if (pkt->memInhibitAsserted()) { 59810143SN/A DPRINTF(DRAM, "Inhibited packet -- Dropping it now\n"); 5999567SN/A pendingDelete.push_back(pkt); 6009567SN/A return true; 6019567SN/A } 6029243SN/A 6039243SN/A // Calc avg gap between requests 6049243SN/A if (prevArrival != 0) { 6059243SN/A totGap += curTick() - prevArrival; 6069243SN/A } 6079243SN/A prevArrival = curTick(); 6089243SN/A 6099831SN/A 6109831SN/A // Find out how many dram packets a pkt translates to 6119831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 6129831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 6139831SN/A // multiple dram packets 6149243SN/A unsigned size = pkt->getSize(); 6159831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 6169831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 6179243SN/A 6189243SN/A // check local buffers and do not accept if full 6199243SN/A if (pkt->isRead()) { 6209567SN/A assert(size != 0); 6219831SN/A if (readQueueFull(dram_pkt_count)) { 6229567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 6239243SN/A // remember that we have to retry this port 6249243SN/A retryRdReq = true; 6259243SN/A numRdRetry++; 6269243SN/A return false; 6279243SN/A } else { 6289831SN/A addToReadQueue(pkt, dram_pkt_count); 6299243SN/A readReqs++; 6309977SN/A bytesReadSys += size; 6319243SN/A } 6329243SN/A } else if (pkt->isWrite()) { 6339567SN/A assert(size != 0); 6349831SN/A if (writeQueueFull(dram_pkt_count)) { 6359567SN/A DPRINTF(DRAM, "Write queue full, not accepting\n"); 6369243SN/A // remember that we have to retry this port 6379243SN/A retryWrReq = true; 6389243SN/A numWrRetry++; 6399243SN/A return false; 6409243SN/A } else { 6419831SN/A addToWriteQueue(pkt, dram_pkt_count); 6429243SN/A writeReqs++; 6439977SN/A bytesWrittenSys += size; 6449243SN/A } 6459243SN/A } else { 6469243SN/A DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 6479243SN/A neitherReadNorWrite++; 6489726SN/A accessAndRespond(pkt, 1); 6499243SN/A } 6509243SN/A 6519243SN/A return true; 6529243SN/A} 6539243SN/A 6549243SN/Avoid 65510146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 6569243SN/A{ 6579243SN/A DPRINTF(DRAM, 6589243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 6599243SN/A 6609831SN/A DRAMPacket* dram_pkt = respQueue.front(); 6619243SN/A 6629831SN/A if (dram_pkt->burstHelper) { 6639831SN/A // it is a split packet 6649831SN/A dram_pkt->burstHelper->burstsServiced++; 6659831SN/A if (dram_pkt->burstHelper->burstsServiced == 66610143SN/A dram_pkt->burstHelper->burstCount) { 6679831SN/A // we have now serviced all children packets of a system packet 6689831SN/A // so we can now respond to the requester 6699831SN/A // @todo we probably want to have a different front end and back 6709831SN/A // end latency for split packets 6719831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6729831SN/A delete dram_pkt->burstHelper; 6739831SN/A dram_pkt->burstHelper = NULL; 6749831SN/A } 6759831SN/A } else { 6769831SN/A // it is not a split packet 6779831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6789831SN/A } 6799243SN/A 6809831SN/A delete respQueue.front(); 6819831SN/A respQueue.pop_front(); 6829243SN/A 6839831SN/A if (!respQueue.empty()) { 6849831SN/A assert(respQueue.front()->readyTime >= curTick()); 6859831SN/A assert(!respondEvent.scheduled()); 6869831SN/A schedule(respondEvent, respQueue.front()->readyTime); 6879831SN/A } else { 6889831SN/A // if there is nothing left in any queue, signal a drain 6899831SN/A if (writeQueue.empty() && readQueue.empty() && 6909831SN/A drainManager) { 6919831SN/A drainManager->signalDrainDone(); 6929831SN/A drainManager = NULL; 6939831SN/A } 6949831SN/A } 6959567SN/A 6969831SN/A // We have made a location in the queue available at this point, 6979831SN/A // so if there is a read that was forced to wait, retry now 6989831SN/A if (retryRdReq) { 6999831SN/A retryRdReq = false; 7009831SN/A port.sendRetry(); 7019831SN/A } 7029243SN/A} 7039243SN/A 7049243SN/Avoid 70510206Sandreas.hansson@arm.comDRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue) 7069243SN/A{ 70710206Sandreas.hansson@arm.com // This method does the arbitration between requests. The chosen 70810206Sandreas.hansson@arm.com // packet is simply moved to the head of the queue. The other 70910206Sandreas.hansson@arm.com // methods know that this is the place to look. For example, with 71010206Sandreas.hansson@arm.com // FCFS, this method does nothing 71110206Sandreas.hansson@arm.com assert(!queue.empty()); 7129243SN/A 71310206Sandreas.hansson@arm.com if (queue.size() == 1) { 71410206Sandreas.hansson@arm.com DPRINTF(DRAM, "Single request, nothing to do\n"); 7159243SN/A return; 7169243SN/A } 7179243SN/A 7189243SN/A if (memSchedPolicy == Enums::fcfs) { 7199243SN/A // Do nothing, since the correct request is already head 7209243SN/A } else if (memSchedPolicy == Enums::frfcfs) { 72110206Sandreas.hansson@arm.com reorderQueue(queue); 7229243SN/A } else 7239243SN/A panic("No scheduling policy chosen\n"); 7249243SN/A} 7259243SN/A 7269243SN/Avoid 72710146Sandreas.hansson@arm.comDRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue) 7289974SN/A{ 7299974SN/A // Only determine this when needed 7309974SN/A uint64_t earliest_banks = 0; 7319974SN/A 7329974SN/A // Search for row hits first, if no row hit is found then schedule the 7339974SN/A // packet to one of the earliest banks available 7349974SN/A bool found_earliest_pkt = false; 7359974SN/A auto selected_pkt_it = queue.begin(); 7369974SN/A 7379974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 7389974SN/A DRAMPacket* dram_pkt = *i; 7399974SN/A const Bank& bank = dram_pkt->bankRef; 7409974SN/A // Check if it is a row hit 7419974SN/A if (bank.openRow == dram_pkt->row) { 7429974SN/A DPRINTF(DRAM, "Row buffer hit\n"); 7439974SN/A selected_pkt_it = i; 7449974SN/A break; 7459974SN/A } else if (!found_earliest_pkt) { 7469974SN/A // No row hit, go for first ready 7479974SN/A if (earliest_banks == 0) 7489974SN/A earliest_banks = minBankFreeAt(queue); 7499974SN/A 7509974SN/A // Bank is ready or is the first available bank 7519974SN/A if (bank.freeAt <= curTick() || 7529974SN/A bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) { 7539974SN/A // Remember the packet to be scheduled to one of the earliest 7549974SN/A // banks available 7559974SN/A selected_pkt_it = i; 7569974SN/A found_earliest_pkt = true; 7579974SN/A } 7589974SN/A } 7599974SN/A } 7609974SN/A 7619974SN/A DRAMPacket* selected_pkt = *selected_pkt_it; 7629974SN/A queue.erase(selected_pkt_it); 7639974SN/A queue.push_front(selected_pkt); 7649974SN/A} 7659974SN/A 7669974SN/Avoid 76710146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 7689243SN/A{ 7699243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 7709243SN/A 7719243SN/A bool needsResponse = pkt->needsResponse(); 7729243SN/A // do the actual memory access which also turns the packet into a 7739243SN/A // response 7749243SN/A access(pkt); 7759243SN/A 7769243SN/A // turn packet around to go back to requester if response expected 7779243SN/A if (needsResponse) { 7789243SN/A // access already turned the packet into a response 7799243SN/A assert(pkt->isResponse()); 7809243SN/A 7819549SN/A // @todo someone should pay for this 7829549SN/A pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; 7839549SN/A 7849726SN/A // queue the packet in the response queue to be sent out after 7859726SN/A // the static latency has passed 7869726SN/A port.schedTimingResp(pkt, curTick() + static_latency); 7879243SN/A } else { 7889587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 7899587SN/A // is still having a pointer to it 7909587SN/A pendingDelete.push_back(pkt); 7919243SN/A } 7929243SN/A 7939243SN/A DPRINTF(DRAM, "Done\n"); 7949243SN/A 7959243SN/A return; 7969243SN/A} 7979243SN/A 7989243SN/Apair<Tick, Tick> 79910146Sandreas.hansson@arm.comDRAMCtrl::estimateLatency(DRAMPacket* dram_pkt, Tick inTime) 8009243SN/A{ 8019243SN/A // If a request reaches a bank at tick 'inTime', how much time 8029243SN/A // *after* that does it take to finish the request, depending 8039243SN/A // on bank status and page open policy. Note that this method 8049243SN/A // considers only the time taken for the actual read or write 8059243SN/A // to complete, NOT any additional time thereafter for tRAS or 8069243SN/A // tRP. 8079243SN/A Tick accLat = 0; 8089243SN/A Tick bankLat = 0; 8099243SN/A rowHitFlag = false; 8109969SN/A Tick potentialActTick; 8119243SN/A 8129967SN/A const Bank& bank = dram_pkt->bankRef; 8139243SN/A 81410209Sandreas.hansson@arm.com if (bank.openRow == dram_pkt->row) { 81510209Sandreas.hansson@arm.com // When we have a row-buffer hit, 81610209Sandreas.hansson@arm.com // we don't care about tRAS having expired or not, 81710209Sandreas.hansson@arm.com // but do care about bank being free for access 81810209Sandreas.hansson@arm.com rowHitFlag = true; 8199243SN/A 82010209Sandreas.hansson@arm.com // When a series of requests arrive to the same row, 82110209Sandreas.hansson@arm.com // DDR systems are capable of streaming data continuously 82210209Sandreas.hansson@arm.com // at maximum bandwidth (subject to tCCD). Here, we approximate 82310209Sandreas.hansson@arm.com // this condition, and assume that if whenever a bank is already 82410209Sandreas.hansson@arm.com // busy and a new request comes in, it can be completed with no 82510209Sandreas.hansson@arm.com // penalty beyond waiting for the existing read to complete. 82610209Sandreas.hansson@arm.com if (bank.freeAt > inTime) { 82710209Sandreas.hansson@arm.com accLat += bank.freeAt - inTime; 82810209Sandreas.hansson@arm.com bankLat += 0; 8299243SN/A } else { 83010209Sandreas.hansson@arm.com // CAS latency only 83110209Sandreas.hansson@arm.com accLat += tCL; 83210209Sandreas.hansson@arm.com bankLat += tCL; 83310209Sandreas.hansson@arm.com } 83410209Sandreas.hansson@arm.com } else { 83510209Sandreas.hansson@arm.com // Row-buffer miss, need to close existing row 83610209Sandreas.hansson@arm.com // once tRAS has expired, then open the new one, 83710209Sandreas.hansson@arm.com // then add cas latency. 83810209Sandreas.hansson@arm.com Tick freeTime = std::max(bank.tRASDoneAt, bank.freeAt); 8399243SN/A 84010209Sandreas.hansson@arm.com if (freeTime > inTime) 84110209Sandreas.hansson@arm.com accLat += freeTime - inTime; 8429243SN/A 84310209Sandreas.hansson@arm.com // If the there is no open row, then there is no precharge 84410209Sandreas.hansson@arm.com // delay, otherwise go with tRP 84510209Sandreas.hansson@arm.com Tick precharge_delay = bank.openRow == Bank::NO_ROW ? 0 : tRP; 8469243SN/A 8479969SN/A //The bank is free, and you may be able to activate 84810209Sandreas.hansson@arm.com potentialActTick = inTime + accLat + precharge_delay; 8499969SN/A if (potentialActTick < bank.actAllowedAt) 8509969SN/A accLat += bank.actAllowedAt - potentialActTick; 8519969SN/A 85210209Sandreas.hansson@arm.com accLat += precharge_delay + tRCD + tCL; 85310209Sandreas.hansson@arm.com bankLat += precharge_delay + tRCD + tCL; 85410209Sandreas.hansson@arm.com } 8559243SN/A 8569487SN/A DPRINTF(DRAM, "Returning < %lld, %lld > from estimateLatency()\n", 8579487SN/A bankLat, accLat); 8589243SN/A 8599243SN/A return make_pair(bankLat, accLat); 8609243SN/A} 8619243SN/A 8629243SN/Avoid 86310207Sandreas.hansson@arm.comDRAMCtrl::recordActivate(Tick act_tick, uint8_t rank, uint8_t bank, 86410207Sandreas.hansson@arm.com uint16_t row) 8659488SN/A{ 8669969SN/A assert(0 <= rank && rank < ranksPerChannel); 8679969SN/A assert(actTicks[rank].size() == activationLimit); 8689488SN/A 8699488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 8709488SN/A 87110207Sandreas.hansson@arm.com // update the open row 87210207Sandreas.hansson@arm.com assert(banks[rank][bank].openRow == Bank::NO_ROW); 87310207Sandreas.hansson@arm.com banks[rank][bank].openRow = row; 87410207Sandreas.hansson@arm.com 87510207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 87610207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 87710207Sandreas.hansson@arm.com // precharge 87810207Sandreas.hansson@arm.com banks[rank][bank].bytesAccessed = 0; 87910207Sandreas.hansson@arm.com banks[rank][bank].rowAccesses = 0; 88010207Sandreas.hansson@arm.com 88110207Sandreas.hansson@arm.com ++numBanksActive; 88210207Sandreas.hansson@arm.com assert(numBanksActive <= banksPerRank * ranksPerChannel); 88310207Sandreas.hansson@arm.com 88410207Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank at tick %lld, now got %d active\n", 88510207Sandreas.hansson@arm.com act_tick, numBanksActive); 8869975SN/A 8879971SN/A // start by enforcing tRRD 8889971SN/A for(int i = 0; i < banksPerRank; i++) { 8899971SN/A // next activate must not happen before tRRD 8909971SN/A banks[rank][i].actAllowedAt = act_tick + tRRD; 8919971SN/A } 89210208Sandreas.hansson@arm.com 8939971SN/A // tRC should be added to activation tick of the bank currently accessed, 8949971SN/A // where tRC = tRAS + tRP, this is just for a check as actAllowedAt for same 8959971SN/A // bank is already captured by bank.freeAt and bank.tRASDoneAt 8969971SN/A banks[rank][bank].actAllowedAt = act_tick + tRAS + tRP; 8979971SN/A 8989971SN/A // next, we deal with tXAW, if the activation limit is disabled 8999971SN/A // then we are done 9009969SN/A if (actTicks[rank].empty()) 9019824SN/A return; 9029824SN/A 9039488SN/A // sanity check 9049969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 9059825SN/A // @todo For now, stick with a warning 9069825SN/A warn("Got %d activates in window %d (%d - %d) which is smaller " 9079969SN/A "than %d\n", activationLimit, act_tick - actTicks[rank].back(), 9089969SN/A act_tick, actTicks[rank].back(), tXAW); 9099488SN/A } 9109488SN/A 9119488SN/A // shift the times used for the book keeping, the last element 9129488SN/A // (highest index) is the oldest one and hence the lowest value 9139969SN/A actTicks[rank].pop_back(); 9149488SN/A 9159488SN/A // record an new activation (in the future) 9169969SN/A actTicks[rank].push_front(act_tick); 9179488SN/A 9189488SN/A // cannot activate more than X times in time window tXAW, push the 9199488SN/A // next one (the X + 1'st activate) to be tXAW away from the 9209488SN/A // oldest in our window of X 9219969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 9229488SN/A DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate no earlier " 9239969SN/A "than %d\n", activationLimit, actTicks[rank].back() + tXAW); 9249488SN/A for(int j = 0; j < banksPerRank; j++) 9259488SN/A // next activate must not happen before end of window 9269969SN/A banks[rank][j].actAllowedAt = actTicks[rank].back() + tXAW; 9279488SN/A } 92810208Sandreas.hansson@arm.com 92910208Sandreas.hansson@arm.com // at the point when this activate takes place, make sure we 93010208Sandreas.hansson@arm.com // transition to the active power state 93110208Sandreas.hansson@arm.com if (!activateEvent.scheduled()) 93210208Sandreas.hansson@arm.com schedule(activateEvent, act_tick); 93310208Sandreas.hansson@arm.com else if (activateEvent.when() > act_tick) 93410208Sandreas.hansson@arm.com // move it sooner in time 93510208Sandreas.hansson@arm.com reschedule(activateEvent, act_tick); 93610208Sandreas.hansson@arm.com} 93710208Sandreas.hansson@arm.com 93810208Sandreas.hansson@arm.comvoid 93910208Sandreas.hansson@arm.comDRAMCtrl::processActivateEvent() 94010208Sandreas.hansson@arm.com{ 94110208Sandreas.hansson@arm.com // we should transition to the active state as soon as any bank is active 94210208Sandreas.hansson@arm.com if (pwrState != PWR_ACT) 94310208Sandreas.hansson@arm.com // note that at this point numBanksActive could be back at 94410208Sandreas.hansson@arm.com // zero again due to a precharge scheduled in the future 94510208Sandreas.hansson@arm.com schedulePowerEvent(PWR_ACT, curTick()); 9469488SN/A} 9479488SN/A 9489488SN/Avoid 94910207Sandreas.hansson@arm.comDRAMCtrl::prechargeBank(Bank& bank, Tick free_at) 95010207Sandreas.hansson@arm.com{ 95110207Sandreas.hansson@arm.com // make sure the bank has an open row 95210207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 95310207Sandreas.hansson@arm.com 95410207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 95510207Sandreas.hansson@arm.com // the page 95610207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 95710207Sandreas.hansson@arm.com 95810207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 95910207Sandreas.hansson@arm.com 96010207Sandreas.hansson@arm.com bank.freeAt = free_at; 96110207Sandreas.hansson@arm.com 96210207Sandreas.hansson@arm.com assert(numBanksActive != 0); 96310207Sandreas.hansson@arm.com --numBanksActive; 96410207Sandreas.hansson@arm.com 96510207Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharged bank, done at tick %lld, now got %d active\n", 96610207Sandreas.hansson@arm.com bank.freeAt, numBanksActive); 96710207Sandreas.hansson@arm.com 96810208Sandreas.hansson@arm.com // if we look at the current number of active banks we might be 96910208Sandreas.hansson@arm.com // tempted to think the DRAM is now idle, however this can be 97010208Sandreas.hansson@arm.com // undone by an activate that is scheduled to happen before we 97110208Sandreas.hansson@arm.com // would have reached the idle state, so schedule an event and 97210208Sandreas.hansson@arm.com // rather check once we actually make it to the point in time when 97310208Sandreas.hansson@arm.com // the (last) precharge takes place 97410208Sandreas.hansson@arm.com if (!prechargeEvent.scheduled()) 97510208Sandreas.hansson@arm.com schedule(prechargeEvent, free_at); 97610208Sandreas.hansson@arm.com else if (prechargeEvent.when() < free_at) 97710208Sandreas.hansson@arm.com reschedule(prechargeEvent, free_at); 97810208Sandreas.hansson@arm.com} 97910208Sandreas.hansson@arm.com 98010208Sandreas.hansson@arm.comvoid 98110208Sandreas.hansson@arm.comDRAMCtrl::processPrechargeEvent() 98210208Sandreas.hansson@arm.com{ 98310207Sandreas.hansson@arm.com // if we reached zero, then special conditions apply as we track 98410207Sandreas.hansson@arm.com // if all banks are precharged for the power models 98510207Sandreas.hansson@arm.com if (numBanksActive == 0) { 98610208Sandreas.hansson@arm.com // we should transition to the idle state when the last bank 98710208Sandreas.hansson@arm.com // is precharged 98810208Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 98910207Sandreas.hansson@arm.com } 99010207Sandreas.hansson@arm.com} 99110207Sandreas.hansson@arm.com 99210207Sandreas.hansson@arm.comvoid 99310146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 9949243SN/A{ 9959243SN/A 9969243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 9979243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 9989243SN/A 9999243SN/A // estimate the bank and access latency 10009243SN/A pair<Tick, Tick> lat = estimateLatency(dram_pkt, curTick()); 10019243SN/A Tick bankLat = lat.first; 10029243SN/A Tick accessLat = lat.second; 10039963SN/A Tick actTick; 10049243SN/A 10059243SN/A // This request was woken up at this time based on a prior call 10069243SN/A // to estimateLatency(). However, between then and now, both the 10079243SN/A // accessLatency and/or busBusyUntil may have changed. We need 10089243SN/A // to correct for that. 10099243SN/A 10109243SN/A Tick addDelay = (curTick() + accessLat < busBusyUntil) ? 10119243SN/A busBusyUntil - (curTick() + accessLat) : 0; 10129243SN/A 10139967SN/A Bank& bank = dram_pkt->bankRef; 10149243SN/A 10159243SN/A // Update bank state 101610209Sandreas.hansson@arm.com if (rowHitFlag) { 101710209Sandreas.hansson@arm.com bank.freeAt = curTick() + addDelay + accessLat; 101810209Sandreas.hansson@arm.com } else { 101910209Sandreas.hansson@arm.com // If there is a page open, precharge it. 102010209Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 102110209Sandreas.hansson@arm.com prechargeBank(bank, std::max(std::max(bank.freeAt, 102210209Sandreas.hansson@arm.com bank.tRASDoneAt), 102310209Sandreas.hansson@arm.com curTick()) + tRP); 10249488SN/A } 10259973SN/A 102610209Sandreas.hansson@arm.com // Any precharge is already part of the latency 102710209Sandreas.hansson@arm.com // estimation, so update the bank free time 102810209Sandreas.hansson@arm.com bank.freeAt = curTick() + addDelay + accessLat; 102910141SN/A 103010209Sandreas.hansson@arm.com // any waiting for banks account for in freeAt 103110209Sandreas.hansson@arm.com actTick = bank.freeAt - tCL - tRCD; 103210141SN/A 103310209Sandreas.hansson@arm.com // If you activated a new row do to this access, the next access 103410209Sandreas.hansson@arm.com // will have to respect tRAS for this bank 103510209Sandreas.hansson@arm.com bank.tRASDoneAt = actTick + tRAS; 10369973SN/A 103710209Sandreas.hansson@arm.com recordActivate(actTick, dram_pkt->rank, dram_pkt->bank, 103810209Sandreas.hansson@arm.com dram_pkt->row); 103910209Sandreas.hansson@arm.com } 104010209Sandreas.hansson@arm.com 104110209Sandreas.hansson@arm.com // increment the bytes accessed and the accesses per row 104210209Sandreas.hansson@arm.com bank.bytesAccessed += burstSize; 104310209Sandreas.hansson@arm.com ++bank.rowAccesses; 104410209Sandreas.hansson@arm.com 104510209Sandreas.hansson@arm.com // if we reached the max, then issue with an auto-precharge 104610209Sandreas.hansson@arm.com bool auto_precharge = pageMgmt == Enums::close || 104710209Sandreas.hansson@arm.com bank.rowAccesses == maxAccessesPerRow; 104810209Sandreas.hansson@arm.com 104910209Sandreas.hansson@arm.com // if we did not hit the limit, we might still want to 105010209Sandreas.hansson@arm.com // auto-precharge 105110209Sandreas.hansson@arm.com if (!auto_precharge && 105210209Sandreas.hansson@arm.com (pageMgmt == Enums::open_adaptive || 105310209Sandreas.hansson@arm.com pageMgmt == Enums::close_adaptive)) { 105410209Sandreas.hansson@arm.com // a twist on the open and close page policies: 105510209Sandreas.hansson@arm.com // 1) open_adaptive page policy does not blindly keep the 105610209Sandreas.hansson@arm.com // page open, but close it if there are no row hits, and there 105710209Sandreas.hansson@arm.com // are bank conflicts in the queue 105810209Sandreas.hansson@arm.com // 2) close_adaptive page policy does not blindly close the 105910209Sandreas.hansson@arm.com // page, but closes it only if there are no row hits in the queue. 106010209Sandreas.hansson@arm.com // In this case, only force an auto precharge when there 106110209Sandreas.hansson@arm.com // are no same page hits in the queue 106210209Sandreas.hansson@arm.com bool got_more_hits = false; 106310209Sandreas.hansson@arm.com bool got_bank_conflict = false; 106410209Sandreas.hansson@arm.com 106510209Sandreas.hansson@arm.com // either look at the read queue or write queue 106610209Sandreas.hansson@arm.com const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 106710209Sandreas.hansson@arm.com writeQueue; 106810209Sandreas.hansson@arm.com auto p = queue.begin(); 106910209Sandreas.hansson@arm.com // make sure we are not considering the packet that we are 107010209Sandreas.hansson@arm.com // currently dealing with (which is the head of the queue) 107110209Sandreas.hansson@arm.com ++p; 107210209Sandreas.hansson@arm.com 107310209Sandreas.hansson@arm.com // keep on looking until we have found required condition or 107410209Sandreas.hansson@arm.com // reached the end 107510209Sandreas.hansson@arm.com while (!(got_more_hits && 107610209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive)) && 107710209Sandreas.hansson@arm.com p != queue.end()) { 107810209Sandreas.hansson@arm.com bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 107910209Sandreas.hansson@arm.com (dram_pkt->bank == (*p)->bank); 108010209Sandreas.hansson@arm.com bool same_row = dram_pkt->row == (*p)->row; 108110209Sandreas.hansson@arm.com got_more_hits |= same_rank_bank && same_row; 108210209Sandreas.hansson@arm.com got_bank_conflict |= same_rank_bank && !same_row; 10839973SN/A ++p; 108410141SN/A } 108510141SN/A 108610209Sandreas.hansson@arm.com // auto pre-charge when either 108710209Sandreas.hansson@arm.com // 1) open_adaptive policy, we have not got any more hits, and 108810209Sandreas.hansson@arm.com // have a bank conflict 108910209Sandreas.hansson@arm.com // 2) close_adaptive policy and we have not got any more hits 109010209Sandreas.hansson@arm.com auto_precharge = !got_more_hits && 109110209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive); 109210209Sandreas.hansson@arm.com } 109310142SN/A 109410209Sandreas.hansson@arm.com // if this access should use auto-precharge, then we are 109510209Sandreas.hansson@arm.com // closing the row 109610209Sandreas.hansson@arm.com if (auto_precharge) { 109710209Sandreas.hansson@arm.com prechargeBank(bank, std::max(bank.freeAt, bank.tRASDoneAt) + tRP); 10989973SN/A 109910209Sandreas.hansson@arm.com DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 110010209Sandreas.hansson@arm.com } 11019963SN/A 110210209Sandreas.hansson@arm.com DPRINTF(DRAM, "doDRAMAccess::bank.freeAt is %lld\n", bank.freeAt); 11039243SN/A 11049243SN/A // Update request parameters 11059243SN/A dram_pkt->readyTime = curTick() + addDelay + accessLat + tBURST; 11069243SN/A 11079243SN/A DPRINTF(DRAM, "Req %lld: curtick is %lld accessLat is %d " \ 11089243SN/A "readytime is %lld busbusyuntil is %lld. " \ 11099243SN/A "Scheduling at readyTime\n", dram_pkt->addr, 11109243SN/A curTick(), accessLat, dram_pkt->readyTime, busBusyUntil); 11119243SN/A 11129243SN/A // Make sure requests are not overlapping on the databus 111310206Sandreas.hansson@arm.com assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 11149243SN/A 11159243SN/A // Update bus state 11169243SN/A busBusyUntil = dram_pkt->readyTime; 11179243SN/A 11189243SN/A DPRINTF(DRAM,"Access time is %lld\n", 11199243SN/A dram_pkt->readyTime - dram_pkt->entryTime); 11209243SN/A 112110206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 112210206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 112310206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 112410206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 112510206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 11269972SN/A 112710206Sandreas.hansson@arm.com // Update the stats and schedule the next request 11289977SN/A if (dram_pkt->isRead) { 112910147Sandreas.hansson@arm.com ++readsThisTime; 11309977SN/A if (rowHitFlag) 11319977SN/A readRowHits++; 11329977SN/A bytesReadDRAM += burstSize; 11339977SN/A perBankRdBursts[dram_pkt->bankId]++; 113410206Sandreas.hansson@arm.com 113510206Sandreas.hansson@arm.com // Update latency stats 113610206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 113710206Sandreas.hansson@arm.com totBankLat += bankLat; 113810206Sandreas.hansson@arm.com totBusLat += tBURST; 113910206Sandreas.hansson@arm.com totQLat += dram_pkt->readyTime - dram_pkt->entryTime - bankLat - 114010206Sandreas.hansson@arm.com tBURST; 11419977SN/A } else { 114210147Sandreas.hansson@arm.com ++writesThisTime; 11439977SN/A if (rowHitFlag) 11449977SN/A writeRowHits++; 11459977SN/A bytesWritten += burstSize; 11469977SN/A perBankWrBursts[dram_pkt->bankId]++; 11479243SN/A } 11489243SN/A} 11499243SN/A 11509243SN/Avoid 115110146Sandreas.hansson@arm.comDRAMCtrl::moveToRespQ() 11529243SN/A{ 11539243SN/A // Remove from read queue 11549567SN/A DRAMPacket* dram_pkt = readQueue.front(); 11559567SN/A readQueue.pop_front(); 11569243SN/A 11579832SN/A // sanity check 11589832SN/A assert(dram_pkt->size <= burstSize); 11599832SN/A 11609243SN/A // Insert into response queue sorted by readyTime 11619243SN/A // It will be sent back to the requestor at its 11629243SN/A // readyTime 11639567SN/A if (respQueue.empty()) { 11649567SN/A respQueue.push_front(dram_pkt); 11659243SN/A assert(!respondEvent.scheduled()); 11669243SN/A assert(dram_pkt->readyTime >= curTick()); 11679567SN/A schedule(respondEvent, dram_pkt->readyTime); 11689243SN/A } else { 11699243SN/A bool done = false; 11709833SN/A auto i = respQueue.begin(); 11719567SN/A while (!done && i != respQueue.end()) { 11729243SN/A if ((*i)->readyTime > dram_pkt->readyTime) { 11739567SN/A respQueue.insert(i, dram_pkt); 11749243SN/A done = true; 11759243SN/A } 11769243SN/A ++i; 11779243SN/A } 11789243SN/A 11799243SN/A if (!done) 11809567SN/A respQueue.push_back(dram_pkt); 11819243SN/A 11829243SN/A assert(respondEvent.scheduled()); 11839243SN/A 11849567SN/A if (respQueue.front()->readyTime < respondEvent.when()) { 11859567SN/A assert(respQueue.front()->readyTime >= curTick()); 11869567SN/A reschedule(respondEvent, respQueue.front()->readyTime); 11879243SN/A } 11889243SN/A } 11899243SN/A} 11909243SN/A 11919243SN/Avoid 119210206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 11939243SN/A{ 119410206Sandreas.hansson@arm.com if (busState == READ_TO_WRITE) { 119510206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 119610206Sandreas.hansson@arm.com "waiting\n", readsThisTime, readQueue.size()); 11979243SN/A 119810206Sandreas.hansson@arm.com // sample and reset the read-related stats as we are now 119910206Sandreas.hansson@arm.com // transitioning to writes, and all reads are done 120010206Sandreas.hansson@arm.com rdPerTurnAround.sample(readsThisTime); 120110206Sandreas.hansson@arm.com readsThisTime = 0; 120210206Sandreas.hansson@arm.com 120310206Sandreas.hansson@arm.com // now proceed to do the actual writes 120410206Sandreas.hansson@arm.com busState = WRITE; 120510206Sandreas.hansson@arm.com } else if (busState == WRITE_TO_READ) { 120610206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 120710206Sandreas.hansson@arm.com "waiting\n", writesThisTime, writeQueue.size()); 120810206Sandreas.hansson@arm.com 120910206Sandreas.hansson@arm.com wrPerTurnAround.sample(writesThisTime); 121010206Sandreas.hansson@arm.com writesThisTime = 0; 121110206Sandreas.hansson@arm.com 121210206Sandreas.hansson@arm.com busState = READ; 121310206Sandreas.hansson@arm.com } 121410206Sandreas.hansson@arm.com 121510207Sandreas.hansson@arm.com if (refreshState != REF_IDLE) { 121610207Sandreas.hansson@arm.com // if a refresh waiting for this event loop to finish, then hand 121710207Sandreas.hansson@arm.com // over now, and do not schedule a new nextReqEvent 121810207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 121910207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 122010207Sandreas.hansson@arm.com 122110207Sandreas.hansson@arm.com refreshState = REF_PRE; 122210207Sandreas.hansson@arm.com 122310207Sandreas.hansson@arm.com // hand control back to the refresh event loop 122410207Sandreas.hansson@arm.com schedule(refreshEvent, curTick()); 122510207Sandreas.hansson@arm.com } 122610207Sandreas.hansson@arm.com 122710207Sandreas.hansson@arm.com // let the refresh finish before issuing any further requests 122810207Sandreas.hansson@arm.com return; 122910207Sandreas.hansson@arm.com } 123010207Sandreas.hansson@arm.com 123110206Sandreas.hansson@arm.com // when we get here it is either a read or a write 123210206Sandreas.hansson@arm.com if (busState == READ) { 123310206Sandreas.hansson@arm.com 123410206Sandreas.hansson@arm.com // track if we should switch or not 123510206Sandreas.hansson@arm.com bool switch_to_writes = false; 123610206Sandreas.hansson@arm.com 123710206Sandreas.hansson@arm.com if (readQueue.empty()) { 123810206Sandreas.hansson@arm.com // In the case there is no read request to go next, 123910206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 124010206Sandreas.hansson@arm.com // if we are draining) 124110206Sandreas.hansson@arm.com if (!writeQueue.empty() && 124210206Sandreas.hansson@arm.com (drainManager || writeQueue.size() > writeLowThreshold)) { 124310206Sandreas.hansson@arm.com 124410206Sandreas.hansson@arm.com switch_to_writes = true; 124510206Sandreas.hansson@arm.com } else { 124610206Sandreas.hansson@arm.com // check if we are drained 124710206Sandreas.hansson@arm.com if (respQueue.empty () && drainManager) { 124810206Sandreas.hansson@arm.com drainManager->signalDrainDone(); 124910206Sandreas.hansson@arm.com drainManager = NULL; 125010206Sandreas.hansson@arm.com } 125110206Sandreas.hansson@arm.com 125210206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 125310206Sandreas.hansson@arm.com // event for the next request 125410206Sandreas.hansson@arm.com return; 125510206Sandreas.hansson@arm.com } 125610206Sandreas.hansson@arm.com } else { 125710206Sandreas.hansson@arm.com // Figure out which read request goes next, and move it to the 125810206Sandreas.hansson@arm.com // front of the read queue 125910206Sandreas.hansson@arm.com chooseNext(readQueue); 126010206Sandreas.hansson@arm.com 126110206Sandreas.hansson@arm.com doDRAMAccess(readQueue.front()); 126210206Sandreas.hansson@arm.com 126310206Sandreas.hansson@arm.com // At this point we're done dealing with the request 126410206Sandreas.hansson@arm.com // It will be moved to a separate response queue with a 126510206Sandreas.hansson@arm.com // correct readyTime, and eventually be sent back at that 126610206Sandreas.hansson@arm.com // time 126710206Sandreas.hansson@arm.com moveToRespQ(); 126810206Sandreas.hansson@arm.com 126910206Sandreas.hansson@arm.com // we have so many writes that we have to transition 127010206Sandreas.hansson@arm.com if (writeQueue.size() > writeHighThreshold) { 127110206Sandreas.hansson@arm.com switch_to_writes = true; 127210206Sandreas.hansson@arm.com } 127310206Sandreas.hansson@arm.com } 127410206Sandreas.hansson@arm.com 127510206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 127610206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 127710206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 127810206Sandreas.hansson@arm.com if (switch_to_writes) { 127910206Sandreas.hansson@arm.com // transition to writing 128010206Sandreas.hansson@arm.com busState = READ_TO_WRITE; 128110206Sandreas.hansson@arm.com 128210206Sandreas.hansson@arm.com // add a bubble to the data bus, as defined by the 128310206Sandreas.hansson@arm.com // tRTW parameter 128410206Sandreas.hansson@arm.com busBusyUntil += tRTW; 128510206Sandreas.hansson@arm.com 128610206Sandreas.hansson@arm.com // update the minimum timing between the requests, 128710206Sandreas.hansson@arm.com // this shifts us back in time far enough to do any 128810206Sandreas.hansson@arm.com // bank preparation 128910206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 129010206Sandreas.hansson@arm.com } 12919352SN/A } else { 129210206Sandreas.hansson@arm.com chooseNext(writeQueue); 129310206Sandreas.hansson@arm.com DRAMPacket* dram_pkt = writeQueue.front(); 129410206Sandreas.hansson@arm.com // sanity check 129510206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 129610206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 129710206Sandreas.hansson@arm.com 129810206Sandreas.hansson@arm.com writeQueue.pop_front(); 129910206Sandreas.hansson@arm.com delete dram_pkt; 130010206Sandreas.hansson@arm.com 130110206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 130210206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 130310206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 130410206Sandreas.hansson@arm.com // writes, then switch to reads. 130510206Sandreas.hansson@arm.com if (writeQueue.empty() || 130610206Sandreas.hansson@arm.com (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 130710206Sandreas.hansson@arm.com !drainManager) || 130810206Sandreas.hansson@arm.com (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 130910206Sandreas.hansson@arm.com // turn the bus back around for reads again 131010206Sandreas.hansson@arm.com busState = WRITE_TO_READ; 131110206Sandreas.hansson@arm.com 131210206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 131310206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 131410206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 131510206Sandreas.hansson@arm.com // nothing to do 131610206Sandreas.hansson@arm.com 131710206Sandreas.hansson@arm.com // here we get a bit creative and shift the bus busy time not 131810206Sandreas.hansson@arm.com // just the tWTR, but also a CAS latency to capture the fact 131910206Sandreas.hansson@arm.com // that we are allowed to prepare a new bank, but not issue a 132010206Sandreas.hansson@arm.com // read command until after tWTR, in essence we capture a 132110206Sandreas.hansson@arm.com // bubble on the data bus that is tWTR + tCL 132210206Sandreas.hansson@arm.com busBusyUntil += tWTR + tCL; 132310206Sandreas.hansson@arm.com 132410206Sandreas.hansson@arm.com // update the minimum timing between the requests, this shifts 132510206Sandreas.hansson@arm.com // us back in time far enough to do any bank preparation 132610206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 132710206Sandreas.hansson@arm.com } 132810206Sandreas.hansson@arm.com } 132910206Sandreas.hansson@arm.com 133010206Sandreas.hansson@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 133110206Sandreas.hansson@arm.com 133210206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 133310206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 133410206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 133510206Sandreas.hansson@arm.com // the next request processing 133610206Sandreas.hansson@arm.com if (retryWrReq && writeQueue.size() < writeBufferSize) { 133710206Sandreas.hansson@arm.com retryWrReq = false; 133810206Sandreas.hansson@arm.com port.sendRetry(); 13399352SN/A } 13409243SN/A} 13419243SN/A 13429967SN/Auint64_t 134310146Sandreas.hansson@arm.comDRAMCtrl::minBankFreeAt(const deque<DRAMPacket*>& queue) const 13449967SN/A{ 13459967SN/A uint64_t bank_mask = 0; 13469967SN/A Tick freeAt = MaxTick; 13479967SN/A 13489967SN/A // detemrine if we have queued transactions targetting the 13499967SN/A // bank in question 13509967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 13519967SN/A for (auto p = queue.begin(); p != queue.end(); ++p) { 13529967SN/A got_waiting[(*p)->bankId] = true; 13539967SN/A } 13549967SN/A 13559967SN/A for (int i = 0; i < ranksPerChannel; i++) { 13569967SN/A for (int j = 0; j < banksPerRank; j++) { 13579967SN/A // if we have waiting requests for the bank, and it is 13589967SN/A // amongst the first available, update the mask 13599967SN/A if (got_waiting[i * banksPerRank + j] && 13609967SN/A banks[i][j].freeAt <= freeAt) { 13619967SN/A // reset bank mask if new minimum is found 13629967SN/A if (banks[i][j].freeAt < freeAt) 13639967SN/A bank_mask = 0; 13649967SN/A // set the bit corresponding to the available bank 13659967SN/A uint8_t bit_index = i * ranksPerChannel + j; 13669967SN/A replaceBits(bank_mask, bit_index, bit_index, 1); 13679967SN/A freeAt = banks[i][j].freeAt; 13689967SN/A } 13699967SN/A } 13709967SN/A } 13719967SN/A return bank_mask; 13729967SN/A} 13739967SN/A 13749243SN/Avoid 137510146Sandreas.hansson@arm.comDRAMCtrl::processRefreshEvent() 13769243SN/A{ 137710207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 137810207Sandreas.hansson@arm.com if (refreshState == REF_IDLE) { 137910207Sandreas.hansson@arm.com // remember when the refresh is due 138010207Sandreas.hansson@arm.com refreshDueAt = curTick(); 13819243SN/A 138210207Sandreas.hansson@arm.com // proceed to drain 138310207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 13849243SN/A 138510207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 138610207Sandreas.hansson@arm.com } 138710207Sandreas.hansson@arm.com 138810207Sandreas.hansson@arm.com // let any scheduled read or write go ahead, after which it will 138910207Sandreas.hansson@arm.com // hand control back to this event loop 139010207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 139110207Sandreas.hansson@arm.com if (nextReqEvent.scheduled()) { 139210207Sandreas.hansson@arm.com // hand control over to the request loop until it is 139310207Sandreas.hansson@arm.com // evaluated next 139410207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 139510207Sandreas.hansson@arm.com 139610207Sandreas.hansson@arm.com return; 139710207Sandreas.hansson@arm.com } else { 139810207Sandreas.hansson@arm.com refreshState = REF_PRE; 139910207Sandreas.hansson@arm.com } 140010207Sandreas.hansson@arm.com } 140110207Sandreas.hansson@arm.com 140210207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 140310207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 140410208Sandreas.hansson@arm.com // precharge any active bank if we are not already in the idle 140510208Sandreas.hansson@arm.com // state 140610208Sandreas.hansson@arm.com if (pwrState != PWR_IDLE) { 140710208Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 140810208Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 140910208Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 141010208Sandreas.hansson@arm.com if (banks[i][j].openRow != Bank::NO_ROW) { 141110208Sandreas.hansson@arm.com // respect both causality and any existing bank 141210208Sandreas.hansson@arm.com // constraints 141310208Sandreas.hansson@arm.com Tick free_at = 141410208Sandreas.hansson@arm.com std::max(std::max(banks[i][j].freeAt, 141510208Sandreas.hansson@arm.com banks[i][j].tRASDoneAt), 141610208Sandreas.hansson@arm.com curTick()) + tRP; 141710207Sandreas.hansson@arm.com 141810208Sandreas.hansson@arm.com prechargeBank(banks[i][j], free_at); 141910208Sandreas.hansson@arm.com } 142010207Sandreas.hansson@arm.com } 142110207Sandreas.hansson@arm.com } 142210208Sandreas.hansson@arm.com } else { 142310208Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 142410208Sandreas.hansson@arm.com 142510208Sandreas.hansson@arm.com // go ahead and kick the power state machine into gear if 142610208Sandreas.hansson@arm.com // we are already idle 142710208Sandreas.hansson@arm.com schedulePowerEvent(PWR_REF, curTick()); 14289975SN/A } 14299975SN/A 143010208Sandreas.hansson@arm.com refreshState = REF_RUN; 143110208Sandreas.hansson@arm.com assert(numBanksActive == 0); 14329243SN/A 143310208Sandreas.hansson@arm.com // wait for all banks to be precharged, at which point the 143410208Sandreas.hansson@arm.com // power state machine will transition to the idle state, and 143510208Sandreas.hansson@arm.com // automatically move to a refresh, at that point it will also 143610208Sandreas.hansson@arm.com // call this method to get the refresh event loop going again 143710207Sandreas.hansson@arm.com return; 143810207Sandreas.hansson@arm.com } 143910207Sandreas.hansson@arm.com 144010207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 144110207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 144210207Sandreas.hansson@arm.com // should never get here with any banks active 144310207Sandreas.hansson@arm.com assert(numBanksActive == 0); 144410208Sandreas.hansson@arm.com assert(pwrState == PWR_REF); 144510207Sandreas.hansson@arm.com 144610207Sandreas.hansson@arm.com Tick banksFree = curTick() + tRFC; 144710207Sandreas.hansson@arm.com 144810207Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 144910207Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 145010207Sandreas.hansson@arm.com banks[i][j].freeAt = banksFree; 145110207Sandreas.hansson@arm.com } 145210207Sandreas.hansson@arm.com } 145310207Sandreas.hansson@arm.com 145410207Sandreas.hansson@arm.com // make sure we did not wait so long that we cannot make up 145510207Sandreas.hansson@arm.com // for it 145610207Sandreas.hansson@arm.com if (refreshDueAt + tREFI < banksFree) { 145710207Sandreas.hansson@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 145810207Sandreas.hansson@arm.com } 145910207Sandreas.hansson@arm.com 146010207Sandreas.hansson@arm.com // compensate for the delay in actually performing the refresh 146110207Sandreas.hansson@arm.com // when scheduling the next one 146210207Sandreas.hansson@arm.com schedule(refreshEvent, refreshDueAt + tREFI - tRP); 146310207Sandreas.hansson@arm.com 146410208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 146510207Sandreas.hansson@arm.com 146610208Sandreas.hansson@arm.com // move to the idle power state once the refresh is done, this 146710208Sandreas.hansson@arm.com // will also move the refresh state machine to the refresh 146810208Sandreas.hansson@arm.com // idle state 146910208Sandreas.hansson@arm.com schedulePowerEvent(PWR_IDLE, banksFree); 147010207Sandreas.hansson@arm.com 147110208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n", 147210208Sandreas.hansson@arm.com banksFree, refreshDueAt + tREFI); 147310208Sandreas.hansson@arm.com } 147410208Sandreas.hansson@arm.com} 147510208Sandreas.hansson@arm.com 147610208Sandreas.hansson@arm.comvoid 147710208Sandreas.hansson@arm.comDRAMCtrl::schedulePowerEvent(PowerState pwr_state, Tick tick) 147810208Sandreas.hansson@arm.com{ 147910208Sandreas.hansson@arm.com // respect causality 148010208Sandreas.hansson@arm.com assert(tick >= curTick()); 148110208Sandreas.hansson@arm.com 148210208Sandreas.hansson@arm.com if (!powerEvent.scheduled()) { 148310208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 148410208Sandreas.hansson@arm.com tick, pwr_state); 148510208Sandreas.hansson@arm.com 148610208Sandreas.hansson@arm.com // insert the new transition 148710208Sandreas.hansson@arm.com pwrStateTrans = pwr_state; 148810208Sandreas.hansson@arm.com 148910208Sandreas.hansson@arm.com schedule(powerEvent, tick); 149010208Sandreas.hansson@arm.com } else { 149110208Sandreas.hansson@arm.com panic("Scheduled power event at %llu to state %d, " 149210208Sandreas.hansson@arm.com "with scheduled event at %llu to %d\n", tick, pwr_state, 149310208Sandreas.hansson@arm.com powerEvent.when(), pwrStateTrans); 149410208Sandreas.hansson@arm.com } 149510208Sandreas.hansson@arm.com} 149610208Sandreas.hansson@arm.com 149710208Sandreas.hansson@arm.comvoid 149810208Sandreas.hansson@arm.comDRAMCtrl::processPowerEvent() 149910208Sandreas.hansson@arm.com{ 150010208Sandreas.hansson@arm.com // remember where we were, and for how long 150110208Sandreas.hansson@arm.com Tick duration = curTick() - pwrStateTick; 150210208Sandreas.hansson@arm.com PowerState prev_state = pwrState; 150310208Sandreas.hansson@arm.com 150410208Sandreas.hansson@arm.com // update the accounting 150510208Sandreas.hansson@arm.com pwrStateTime[prev_state] += duration; 150610208Sandreas.hansson@arm.com 150710208Sandreas.hansson@arm.com pwrState = pwrStateTrans; 150810208Sandreas.hansson@arm.com pwrStateTick = curTick(); 150910208Sandreas.hansson@arm.com 151010208Sandreas.hansson@arm.com if (pwrState == PWR_IDLE) { 151110208Sandreas.hansson@arm.com DPRINTF(DRAMState, "All banks precharged\n"); 151210208Sandreas.hansson@arm.com 151310208Sandreas.hansson@arm.com // if we were refreshing, make sure we start scheduling requests again 151410208Sandreas.hansson@arm.com if (prev_state == PWR_REF) { 151510208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 151610208Sandreas.hansson@arm.com assert(pwrState == PWR_IDLE); 151710208Sandreas.hansson@arm.com 151810208Sandreas.hansson@arm.com // kick things into action again 151910208Sandreas.hansson@arm.com refreshState = REF_IDLE; 152010208Sandreas.hansson@arm.com assert(!nextReqEvent.scheduled()); 152110208Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 152210208Sandreas.hansson@arm.com } else { 152310208Sandreas.hansson@arm.com assert(prev_state == PWR_ACT); 152410208Sandreas.hansson@arm.com 152510208Sandreas.hansson@arm.com // if we have a pending refresh, and are now moving to 152610208Sandreas.hansson@arm.com // the idle state, direclty transition to a refresh 152710208Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 152810208Sandreas.hansson@arm.com // there should be nothing waiting at this point 152910208Sandreas.hansson@arm.com assert(!powerEvent.scheduled()); 153010208Sandreas.hansson@arm.com 153110208Sandreas.hansson@arm.com // update the state in zero time and proceed below 153210208Sandreas.hansson@arm.com pwrState = PWR_REF; 153310208Sandreas.hansson@arm.com } 153410208Sandreas.hansson@arm.com } 153510208Sandreas.hansson@arm.com } 153610208Sandreas.hansson@arm.com 153710208Sandreas.hansson@arm.com // we transition to the refresh state, let the refresh state 153810208Sandreas.hansson@arm.com // machine know of this state update and let it deal with the 153910208Sandreas.hansson@arm.com // scheduling of the next power state transition as well as the 154010208Sandreas.hansson@arm.com // following refresh 154110208Sandreas.hansson@arm.com if (pwrState == PWR_REF) { 154210208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Refreshing\n"); 154310208Sandreas.hansson@arm.com // kick the refresh event loop into action again, and that 154410208Sandreas.hansson@arm.com // in turn will schedule a transition to the idle power 154510208Sandreas.hansson@arm.com // state once the refresh is done 154610208Sandreas.hansson@arm.com assert(refreshState == REF_RUN); 154710208Sandreas.hansson@arm.com processRefreshEvent(); 154810207Sandreas.hansson@arm.com } 15499243SN/A} 15509243SN/A 15519243SN/Avoid 155210146Sandreas.hansson@arm.comDRAMCtrl::regStats() 15539243SN/A{ 15549243SN/A using namespace Stats; 15559243SN/A 15569243SN/A AbstractMemory::regStats(); 15579243SN/A 15589243SN/A readReqs 15599243SN/A .name(name() + ".readReqs") 15609977SN/A .desc("Number of read requests accepted"); 15619243SN/A 15629243SN/A writeReqs 15639243SN/A .name(name() + ".writeReqs") 15649977SN/A .desc("Number of write requests accepted"); 15659831SN/A 15669831SN/A readBursts 15679831SN/A .name(name() + ".readBursts") 15689977SN/A .desc("Number of DRAM read bursts, " 15699977SN/A "including those serviced by the write queue"); 15709831SN/A 15719831SN/A writeBursts 15729831SN/A .name(name() + ".writeBursts") 15739977SN/A .desc("Number of DRAM write bursts, " 15749977SN/A "including those merged in the write queue"); 15759243SN/A 15769243SN/A servicedByWrQ 15779243SN/A .name(name() + ".servicedByWrQ") 15789977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 15799977SN/A 15809977SN/A mergedWrBursts 15819977SN/A .name(name() + ".mergedWrBursts") 15829977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 15839243SN/A 15849243SN/A neitherReadNorWrite 15859977SN/A .name(name() + ".neitherReadNorWriteReqs") 15869977SN/A .desc("Number of requests that are neither read nor write"); 15879243SN/A 15889977SN/A perBankRdBursts 15899243SN/A .init(banksPerRank * ranksPerChannel) 15909977SN/A .name(name() + ".perBankRdBursts") 15919977SN/A .desc("Per bank write bursts"); 15929243SN/A 15939977SN/A perBankWrBursts 15949243SN/A .init(banksPerRank * ranksPerChannel) 15959977SN/A .name(name() + ".perBankWrBursts") 15969977SN/A .desc("Per bank write bursts"); 15979243SN/A 15989243SN/A avgRdQLen 15999243SN/A .name(name() + ".avgRdQLen") 16009977SN/A .desc("Average read queue length when enqueuing") 16019243SN/A .precision(2); 16029243SN/A 16039243SN/A avgWrQLen 16049243SN/A .name(name() + ".avgWrQLen") 16059977SN/A .desc("Average write queue length when enqueuing") 16069243SN/A .precision(2); 16079243SN/A 16089243SN/A totQLat 16099243SN/A .name(name() + ".totQLat") 16109977SN/A .desc("Total ticks spent queuing"); 16119243SN/A 16129243SN/A totBankLat 16139243SN/A .name(name() + ".totBankLat") 16149977SN/A .desc("Total ticks spent accessing banks"); 16159243SN/A 16169243SN/A totBusLat 16179243SN/A .name(name() + ".totBusLat") 16189977SN/A .desc("Total ticks spent in databus transfers"); 16199243SN/A 16209243SN/A totMemAccLat 16219243SN/A .name(name() + ".totMemAccLat") 16229977SN/A .desc("Total ticks spent from burst creation until serviced " 16239977SN/A "by the DRAM"); 16249243SN/A 16259243SN/A avgQLat 16269243SN/A .name(name() + ".avgQLat") 16279977SN/A .desc("Average queueing delay per DRAM burst") 16289243SN/A .precision(2); 16299243SN/A 16309831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 16319243SN/A 16329243SN/A avgBankLat 16339243SN/A .name(name() + ".avgBankLat") 16349977SN/A .desc("Average bank access latency per DRAM burst") 16359243SN/A .precision(2); 16369243SN/A 16379831SN/A avgBankLat = totBankLat / (readBursts - servicedByWrQ); 16389243SN/A 16399243SN/A avgBusLat 16409243SN/A .name(name() + ".avgBusLat") 16419977SN/A .desc("Average bus latency per DRAM burst") 16429243SN/A .precision(2); 16439243SN/A 16449831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 16459243SN/A 16469243SN/A avgMemAccLat 16479243SN/A .name(name() + ".avgMemAccLat") 16489977SN/A .desc("Average memory access latency per DRAM burst") 16499243SN/A .precision(2); 16509243SN/A 16519831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 16529243SN/A 16539243SN/A numRdRetry 16549243SN/A .name(name() + ".numRdRetry") 16559977SN/A .desc("Number of times read queue was full causing retry"); 16569243SN/A 16579243SN/A numWrRetry 16589243SN/A .name(name() + ".numWrRetry") 16599977SN/A .desc("Number of times write queue was full causing retry"); 16609243SN/A 16619243SN/A readRowHits 16629243SN/A .name(name() + ".readRowHits") 16639243SN/A .desc("Number of row buffer hits during reads"); 16649243SN/A 16659243SN/A writeRowHits 16669243SN/A .name(name() + ".writeRowHits") 16679243SN/A .desc("Number of row buffer hits during writes"); 16689243SN/A 16699243SN/A readRowHitRate 16709243SN/A .name(name() + ".readRowHitRate") 16719243SN/A .desc("Row buffer hit rate for reads") 16729243SN/A .precision(2); 16739243SN/A 16749831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 16759243SN/A 16769243SN/A writeRowHitRate 16779243SN/A .name(name() + ".writeRowHitRate") 16789243SN/A .desc("Row buffer hit rate for writes") 16799243SN/A .precision(2); 16809243SN/A 16819977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 16829243SN/A 16839243SN/A readPktSize 16849831SN/A .init(ceilLog2(burstSize) + 1) 16859243SN/A .name(name() + ".readPktSize") 16869977SN/A .desc("Read request sizes (log2)"); 16879243SN/A 16889243SN/A writePktSize 16899831SN/A .init(ceilLog2(burstSize) + 1) 16909243SN/A .name(name() + ".writePktSize") 16919977SN/A .desc("Write request sizes (log2)"); 16929243SN/A 16939243SN/A rdQLenPdf 16949567SN/A .init(readBufferSize) 16959243SN/A .name(name() + ".rdQLenPdf") 16969243SN/A .desc("What read queue length does an incoming req see"); 16979243SN/A 16989243SN/A wrQLenPdf 16999567SN/A .init(writeBufferSize) 17009243SN/A .name(name() + ".wrQLenPdf") 17019243SN/A .desc("What write queue length does an incoming req see"); 17029243SN/A 17039727SN/A bytesPerActivate 170410141SN/A .init(maxAccessesPerRow) 17059727SN/A .name(name() + ".bytesPerActivate") 17069727SN/A .desc("Bytes accessed per row activation") 17079727SN/A .flags(nozero); 17089243SN/A 170910147Sandreas.hansson@arm.com rdPerTurnAround 171010147Sandreas.hansson@arm.com .init(readBufferSize) 171110147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 171210147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 171310147Sandreas.hansson@arm.com .flags(nozero); 171410147Sandreas.hansson@arm.com 171510147Sandreas.hansson@arm.com wrPerTurnAround 171610147Sandreas.hansson@arm.com .init(writeBufferSize) 171710147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 171810147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 171910147Sandreas.hansson@arm.com .flags(nozero); 172010147Sandreas.hansson@arm.com 17219975SN/A bytesReadDRAM 17229975SN/A .name(name() + ".bytesReadDRAM") 17239975SN/A .desc("Total number of bytes read from DRAM"); 17249975SN/A 17259975SN/A bytesReadWrQ 17269975SN/A .name(name() + ".bytesReadWrQ") 17279975SN/A .desc("Total number of bytes read from write queue"); 17289243SN/A 17299243SN/A bytesWritten 17309243SN/A .name(name() + ".bytesWritten") 17319977SN/A .desc("Total number of bytes written to DRAM"); 17329243SN/A 17339977SN/A bytesReadSys 17349977SN/A .name(name() + ".bytesReadSys") 17359977SN/A .desc("Total read bytes from the system interface side"); 17369243SN/A 17379977SN/A bytesWrittenSys 17389977SN/A .name(name() + ".bytesWrittenSys") 17399977SN/A .desc("Total written bytes from the system interface side"); 17409243SN/A 17419243SN/A avgRdBW 17429243SN/A .name(name() + ".avgRdBW") 17439977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 17449243SN/A .precision(2); 17459243SN/A 17469977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 17479243SN/A 17489243SN/A avgWrBW 17499243SN/A .name(name() + ".avgWrBW") 17509977SN/A .desc("Average achieved write bandwidth in MiByte/s") 17519243SN/A .precision(2); 17529243SN/A 17539243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 17549243SN/A 17559977SN/A avgRdBWSys 17569977SN/A .name(name() + ".avgRdBWSys") 17579977SN/A .desc("Average system read bandwidth in MiByte/s") 17589243SN/A .precision(2); 17599243SN/A 17609977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 17619243SN/A 17629977SN/A avgWrBWSys 17639977SN/A .name(name() + ".avgWrBWSys") 17649977SN/A .desc("Average system write bandwidth in MiByte/s") 17659243SN/A .precision(2); 17669243SN/A 17679977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 17689243SN/A 17699243SN/A peakBW 17709243SN/A .name(name() + ".peakBW") 17719977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 17729243SN/A .precision(2); 17739243SN/A 17749831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 17759243SN/A 17769243SN/A busUtil 17779243SN/A .name(name() + ".busUtil") 17789243SN/A .desc("Data bus utilization in percentage") 17799243SN/A .precision(2); 17809243SN/A 17819243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 17829243SN/A 17839243SN/A totGap 17849243SN/A .name(name() + ".totGap") 17859243SN/A .desc("Total gap between requests"); 17869243SN/A 17879243SN/A avgGap 17889243SN/A .name(name() + ".avgGap") 17899243SN/A .desc("Average gap between requests") 17909243SN/A .precision(2); 17919243SN/A 17929243SN/A avgGap = totGap / (readReqs + writeReqs); 17939975SN/A 17949975SN/A // Stats for DRAM Power calculation based on Micron datasheet 17959975SN/A busUtilRead 17969975SN/A .name(name() + ".busUtilRead") 17979975SN/A .desc("Data bus utilization in percentage for reads") 17989975SN/A .precision(2); 17999975SN/A 18009975SN/A busUtilRead = avgRdBW / peakBW * 100; 18019975SN/A 18029975SN/A busUtilWrite 18039975SN/A .name(name() + ".busUtilWrite") 18049975SN/A .desc("Data bus utilization in percentage for writes") 18059975SN/A .precision(2); 18069975SN/A 18079975SN/A busUtilWrite = avgWrBW / peakBW * 100; 18089975SN/A 18099975SN/A pageHitRate 18109975SN/A .name(name() + ".pageHitRate") 18119975SN/A .desc("Row buffer hit rate, read and write combined") 18129975SN/A .precision(2); 18139975SN/A 18149977SN/A pageHitRate = (writeRowHits + readRowHits) / 18159977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 18169975SN/A 181710208Sandreas.hansson@arm.com pwrStateTime 181810208Sandreas.hansson@arm.com .init(5) 181910208Sandreas.hansson@arm.com .name(name() + ".memoryStateTime") 182010208Sandreas.hansson@arm.com .desc("Time in different power states"); 182110208Sandreas.hansson@arm.com pwrStateTime.subname(0, "IDLE"); 182210208Sandreas.hansson@arm.com pwrStateTime.subname(1, "REF"); 182310208Sandreas.hansson@arm.com pwrStateTime.subname(2, "PRE_PDN"); 182410208Sandreas.hansson@arm.com pwrStateTime.subname(3, "ACT"); 182510208Sandreas.hansson@arm.com pwrStateTime.subname(4, "ACT_PDN"); 18269243SN/A} 18279243SN/A 18289243SN/Avoid 182910146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 18309243SN/A{ 18319243SN/A // rely on the abstract memory 18329243SN/A functionalAccess(pkt); 18339243SN/A} 18349243SN/A 18359294SN/ABaseSlavePort& 183610146Sandreas.hansson@arm.comDRAMCtrl::getSlavePort(const string &if_name, PortID idx) 18379243SN/A{ 18389243SN/A if (if_name != "port") { 18399243SN/A return MemObject::getSlavePort(if_name, idx); 18409243SN/A } else { 18419243SN/A return port; 18429243SN/A } 18439243SN/A} 18449243SN/A 18459243SN/Aunsigned int 184610146Sandreas.hansson@arm.comDRAMCtrl::drain(DrainManager *dm) 18479243SN/A{ 18489342SN/A unsigned int count = port.drain(dm); 18499243SN/A 18509243SN/A // if there is anything in any of our internal queues, keep track 18519243SN/A // of that as well 18529567SN/A if (!(writeQueue.empty() && readQueue.empty() && 18539567SN/A respQueue.empty())) { 18549352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 18559567SN/A " resp: %d\n", writeQueue.size(), readQueue.size(), 18569567SN/A respQueue.size()); 18579243SN/A ++count; 18589342SN/A drainManager = dm; 185910206Sandreas.hansson@arm.com 18609352SN/A // the only part that is not drained automatically over time 186110206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 186210206Sandreas.hansson@arm.com if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 186310206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 186410206Sandreas.hansson@arm.com } 18659243SN/A } 18669243SN/A 18679243SN/A if (count) 18689342SN/A setDrainState(Drainable::Draining); 18699243SN/A else 18709342SN/A setDrainState(Drainable::Drained); 18719243SN/A return count; 18729243SN/A} 18739243SN/A 187410146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 18759243SN/A : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 18769243SN/A memory(_memory) 18779243SN/A{ } 18789243SN/A 18799243SN/AAddrRangeList 188010146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 18819243SN/A{ 18829243SN/A AddrRangeList ranges; 18839243SN/A ranges.push_back(memory.getAddrRange()); 18849243SN/A return ranges; 18859243SN/A} 18869243SN/A 18879243SN/Avoid 188810146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 18899243SN/A{ 18909243SN/A pkt->pushLabel(memory.name()); 18919243SN/A 18929243SN/A if (!queue.checkFunctional(pkt)) { 18939243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 18949243SN/A // calls recvAtomic() and throws away the latency; we can save a 18959243SN/A // little here by just not calculating the latency. 18969243SN/A memory.recvFunctional(pkt); 18979243SN/A } 18989243SN/A 18999243SN/A pkt->popLabel(); 19009243SN/A} 19019243SN/A 19029243SN/ATick 190310146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 19049243SN/A{ 19059243SN/A return memory.recvAtomic(pkt); 19069243SN/A} 19079243SN/A 19089243SN/Abool 190910146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 19109243SN/A{ 19119243SN/A // pass it to the memory controller 19129243SN/A return memory.recvTimingReq(pkt); 19139243SN/A} 19149243SN/A 191510146Sandreas.hansson@arm.comDRAMCtrl* 191610146Sandreas.hansson@arm.comDRAMCtrlParams::create() 19179243SN/A{ 191810146Sandreas.hansson@arm.com return new DRAMCtrl(this); 19199243SN/A} 1920