dram_ctrl.cc revision 10207
19243SN/A/* 210206Sandreas.hansson@arm.com * Copyright (c) 2010-2014 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 439243SN/A */ 449243SN/A 4510146Sandreas.hansson@arm.com#include "base/bitfield.hh" 469356SN/A#include "base/trace.hh" 4710146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 489352SN/A#include "debug/Drain.hh" 4910146Sandreas.hansson@arm.com#include "mem/dram_ctrl.hh" 509814SN/A#include "sim/system.hh" 519243SN/A 529243SN/Ausing namespace std; 539243SN/A 5410146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 559243SN/A AbstractMemory(p), 569243SN/A port(name() + ".port", *this), 579243SN/A retryRdReq(false), retryWrReq(false), 5810206Sandreas.hansson@arm.com rowHitFlag(false), busState(READ), 5910207Sandreas.hansson@arm.com respondEvent(this), refreshEvent(this), 6010207Sandreas.hansson@arm.com nextReqEvent(this), drainManager(NULL), 619831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 629831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 639831SN/A devicesPerRank(p->devices_per_rank), 649831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 659831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 6610140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 679243SN/A ranksPerChannel(p->ranks_per_channel), 689566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 699243SN/A readBufferSize(p->read_buffer_size), 709243SN/A writeBufferSize(p->write_buffer_size), 7110140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 7210140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 7310147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 7410147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 7510206Sandreas.hansson@arm.com tWTR(p->tWTR), tRTW(p->tRTW), tBURST(p->tBURST), 769963SN/A tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), 779971SN/A tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 789488SN/A tXAW(p->tXAW), activationLimit(p->activation_limit), 799243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 809243SN/A pageMgmt(p->page_policy), 8110141SN/A maxAccessesPerRow(p->max_accesses_per_row), 829726SN/A frontendLatency(p->static_frontend_latency), 839726SN/A backendLatency(p->static_backend_latency), 8410207Sandreas.hansson@arm.com busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE), prevArrival(0), 8510207Sandreas.hansson@arm.com nextReqTime(0), idleStartTick(0), numBanksActive(0) 869243SN/A{ 879243SN/A // create the bank states based on the dimensions of the ranks and 889243SN/A // banks 899243SN/A banks.resize(ranksPerChannel); 909969SN/A actTicks.resize(ranksPerChannel); 919243SN/A for (size_t c = 0; c < ranksPerChannel; ++c) { 929243SN/A banks[c].resize(banksPerRank); 939969SN/A actTicks[c].resize(activationLimit, 0); 949243SN/A } 959243SN/A 9610140SN/A // perform a basic check of the write thresholds 9710140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 9810140SN/A fatal("Write buffer low threshold %d must be smaller than the " 9910140SN/A "high threshold %d\n", p->write_low_thresh_perc, 10010140SN/A p->write_high_thresh_perc); 1019243SN/A 1029243SN/A // determine the rows per bank by looking at the total capacity 1039567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1049243SN/A 1059243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1069243SN/A AbstractMemory::size()); 1079831SN/A 1089831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1099831SN/A rowBufferSize, columnsPerRowBuffer); 1109831SN/A 1119831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1129243SN/A 1139566SN/A if (range.interleaved()) { 1149566SN/A if (channels != range.stripes()) 11510143SN/A fatal("%s has %d interleaved address stripes but %d channel(s)\n", 1169566SN/A name(), range.stripes(), channels); 1179566SN/A 11810136SN/A if (addrMapping == Enums::RoRaBaChCo) { 1199831SN/A if (rowBufferSize != range.granularity()) { 12010143SN/A fatal("Interleaving of %s doesn't match RoRaBaChCo " 12110136SN/A "address map\n", name()); 1229566SN/A } 12310136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 12410136SN/A if (system()->cacheLineSize() != range.granularity()) { 12510143SN/A fatal("Interleaving of %s doesn't match RoRaBaCoCh " 12610136SN/A "address map\n", name()); 1279669SN/A } 12810136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 12910136SN/A if (system()->cacheLineSize() != range.granularity()) 13010143SN/A fatal("Interleaving of %s doesn't match RoCoRaBaCh " 13110136SN/A "address map\n", name()); 1329566SN/A } 1339566SN/A } 13410207Sandreas.hansson@arm.com 13510207Sandreas.hansson@arm.com // some basic sanity checks 13610207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 13710207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 13810207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 13910207Sandreas.hansson@arm.com } 1409243SN/A} 1419243SN/A 1429243SN/Avoid 14310146Sandreas.hansson@arm.comDRAMCtrl::init() 14410140SN/A{ 14510140SN/A if (!port.isConnected()) { 14610146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 14710140SN/A } else { 14810140SN/A port.sendRangeChange(); 14910140SN/A } 15010140SN/A} 15110140SN/A 15210140SN/Avoid 15310146Sandreas.hansson@arm.comDRAMCtrl::startup() 1549243SN/A{ 15510143SN/A // update the start tick for the precharge accounting to the 15610143SN/A // current tick 15710207Sandreas.hansson@arm.com idleStartTick = curTick(); 15810143SN/A 15910206Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 16010206Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 16110206Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 16210206Sandreas.hansson@arm.com // start of simulation 16310206Sandreas.hansson@arm.com busBusyUntil = curTick() + tRP + tRCD + tCL; 16410206Sandreas.hansson@arm.com 1659243SN/A // print the configuration of the controller 1669243SN/A printParams(); 1679243SN/A 16810207Sandreas.hansson@arm.com // kick off the refresh, and give ourselves enough time to 16910207Sandreas.hansson@arm.com // precharge 17010207Sandreas.hansson@arm.com schedule(refreshEvent, curTick() + tREFI - tRP); 1719243SN/A} 1729243SN/A 1739243SN/ATick 17410146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 1759243SN/A{ 1769243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 1779243SN/A 1789243SN/A // do the actual memory access and turn the packet into a response 1799243SN/A access(pkt); 1809243SN/A 1819243SN/A Tick latency = 0; 1829243SN/A if (!pkt->memInhibitAsserted() && pkt->hasData()) { 1839243SN/A // this value is not supposed to be accurate, just enough to 1849243SN/A // keep things going, mimic a closed page 1859243SN/A latency = tRP + tRCD + tCL; 1869243SN/A } 1879243SN/A return latency; 1889243SN/A} 1899243SN/A 1909243SN/Abool 19110146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 1929243SN/A{ 1939831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 1949831SN/A readBufferSize, readQueue.size() + respQueue.size(), 1959831SN/A neededEntries); 1969243SN/A 1979831SN/A return 1989831SN/A (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 1999243SN/A} 2009243SN/A 2019243SN/Abool 20210146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 2039243SN/A{ 2049831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 2059831SN/A writeBufferSize, writeQueue.size(), neededEntries); 2069831SN/A return (writeQueue.size() + neededEntries) > writeBufferSize; 2079243SN/A} 2089243SN/A 20910146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 21010146Sandreas.hansson@arm.comDRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 21110143SN/A bool isRead) 2129243SN/A{ 2139669SN/A // decode the address based on the address mapping scheme, with 21410136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 21510136SN/A // channel, respectively 2169243SN/A uint8_t rank; 2179967SN/A uint8_t bank; 2189243SN/A uint16_t row; 2199243SN/A 2209243SN/A // truncate the address to the access granularity 2219831SN/A Addr addr = dramPktAddr / burstSize; 2229243SN/A 2239491SN/A // we have removed the lowest order address bits that denote the 2249831SN/A // position within the column 22510136SN/A if (addrMapping == Enums::RoRaBaChCo) { 2269491SN/A // the lowest order bits denote the column to ensure that 2279491SN/A // sequential cache lines occupy the same row 2289831SN/A addr = addr / columnsPerRowBuffer; 2299243SN/A 2309669SN/A // take out the channel part of the address 2319566SN/A addr = addr / channels; 2329566SN/A 2339669SN/A // after the channel bits, get the bank bits to interleave 2349669SN/A // over the banks 2359669SN/A bank = addr % banksPerRank; 2369669SN/A addr = addr / banksPerRank; 2379669SN/A 2389669SN/A // after the bank, we get the rank bits which thus interleaves 2399669SN/A // over the ranks 2409669SN/A rank = addr % ranksPerChannel; 2419669SN/A addr = addr / ranksPerChannel; 2429669SN/A 2439669SN/A // lastly, get the row bits 2449669SN/A row = addr % rowsPerBank; 2459669SN/A addr = addr / rowsPerBank; 24610136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 2479669SN/A // take out the channel part of the address 2489669SN/A addr = addr / channels; 2499669SN/A 2509669SN/A // next, the column 2519831SN/A addr = addr / columnsPerRowBuffer; 2529669SN/A 2539669SN/A // after the column bits, we get the bank bits to interleave 2549491SN/A // over the banks 2559243SN/A bank = addr % banksPerRank; 2569243SN/A addr = addr / banksPerRank; 2579243SN/A 2589491SN/A // after the bank, we get the rank bits which thus interleaves 2599491SN/A // over the ranks 2609243SN/A rank = addr % ranksPerChannel; 2619243SN/A addr = addr / ranksPerChannel; 2629243SN/A 2639491SN/A // lastly, get the row bits 2649243SN/A row = addr % rowsPerBank; 2659243SN/A addr = addr / rowsPerBank; 26610136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 2679491SN/A // optimise for closed page mode and utilise maximum 2689491SN/A // parallelism of the DRAM (at the cost of power) 2699491SN/A 2709566SN/A // take out the channel part of the address, not that this has 2719566SN/A // to match with how accesses are interleaved between the 2729566SN/A // controllers in the address mapping 2739566SN/A addr = addr / channels; 2749566SN/A 2759491SN/A // start with the bank bits, as this provides the maximum 2769491SN/A // opportunity for parallelism between requests 2779243SN/A bank = addr % banksPerRank; 2789243SN/A addr = addr / banksPerRank; 2799243SN/A 2809491SN/A // next get the rank bits 2819243SN/A rank = addr % ranksPerChannel; 2829243SN/A addr = addr / ranksPerChannel; 2839243SN/A 2849491SN/A // next the column bits which we do not need to keep track of 2859491SN/A // and simply skip past 2869831SN/A addr = addr / columnsPerRowBuffer; 2879243SN/A 2889491SN/A // lastly, get the row bits 2899243SN/A row = addr % rowsPerBank; 2909243SN/A addr = addr / rowsPerBank; 2919243SN/A } else 2929243SN/A panic("Unknown address mapping policy chosen!"); 2939243SN/A 2949243SN/A assert(rank < ranksPerChannel); 2959243SN/A assert(bank < banksPerRank); 2969243SN/A assert(row < rowsPerBank); 2979243SN/A 2989243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 2999831SN/A dramPktAddr, rank, bank, row); 3009243SN/A 3019243SN/A // create the corresponding DRAM packet with the entry time and 3029567SN/A // ready time set to the current tick, the latter will be updated 3039567SN/A // later 3049967SN/A uint16_t bank_id = banksPerRank * rank + bank; 3059967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 3069967SN/A size, banks[rank][bank]); 3079243SN/A} 3089243SN/A 3099243SN/Avoid 31010146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 3119243SN/A{ 3129243SN/A // only add to the read queue here. whenever the request is 3139243SN/A // eventually done, set the readyTime, and call schedule() 3149243SN/A assert(!pkt->isWrite()); 3159243SN/A 3169831SN/A assert(pktCount != 0); 3179831SN/A 3189831SN/A // if the request size is larger than burst size, the pkt is split into 3199831SN/A // multiple DRAM packets 3209831SN/A // Note if the pkt starting address is not aligened to burst size, the 3219831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 3229831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 3239831SN/A // check read packets against packets in write queue. 3249243SN/A Addr addr = pkt->getAddr(); 3259831SN/A unsigned pktsServicedByWrQ = 0; 3269831SN/A BurstHelper* burst_helper = NULL; 3279831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 3289831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 3299831SN/A pkt->getAddr() + pkt->getSize()) - addr; 3309831SN/A readPktSize[ceilLog2(size)]++; 3319831SN/A readBursts++; 3329243SN/A 3339831SN/A // First check write buffer to see if the data is already at 3349831SN/A // the controller 3359831SN/A bool foundInWrQ = false; 3369833SN/A for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) { 3379832SN/A // check if the read is subsumed in the write entry we are 3389832SN/A // looking at 3399832SN/A if ((*i)->addr <= addr && 3409832SN/A (addr + size) <= ((*i)->addr + (*i)->size)) { 3419831SN/A foundInWrQ = true; 3429831SN/A servicedByWrQ++; 3439831SN/A pktsServicedByWrQ++; 3449831SN/A DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 3459831SN/A "write queue\n", addr, size); 3469975SN/A bytesReadWrQ += burstSize; 3479831SN/A break; 3489831SN/A } 3499243SN/A } 3509831SN/A 3519831SN/A // If not found in the write q, make a DRAM packet and 3529831SN/A // push it onto the read queue 3539831SN/A if (!foundInWrQ) { 3549831SN/A 3559831SN/A // Make the burst helper for split packets 3569831SN/A if (pktCount > 1 && burst_helper == NULL) { 3579831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 3589831SN/A "dram requests\n", pkt->getAddr(), pktCount); 3599831SN/A burst_helper = new BurstHelper(pktCount); 3609831SN/A } 3619831SN/A 3629966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 3639831SN/A dram_pkt->burstHelper = burst_helper; 3649831SN/A 3659831SN/A assert(!readQueueFull(1)); 3669831SN/A rdQLenPdf[readQueue.size() + respQueue.size()]++; 3679831SN/A 3689831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 3699831SN/A 3709831SN/A readQueue.push_back(dram_pkt); 3719831SN/A 3729831SN/A // Update stats 3739831SN/A avgRdQLen = readQueue.size() + respQueue.size(); 3749831SN/A } 3759831SN/A 3769831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 3779831SN/A addr = (addr | (burstSize - 1)) + 1; 3789243SN/A } 3799243SN/A 3809831SN/A // If all packets are serviced by write queue, we send the repsonse back 3819831SN/A if (pktsServicedByWrQ == pktCount) { 3829831SN/A accessAndRespond(pkt, frontendLatency); 3839831SN/A return; 3849831SN/A } 3859243SN/A 3869831SN/A // Update how many split packets are serviced by write queue 3879831SN/A if (burst_helper != NULL) 3889831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 3899243SN/A 39010206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 39110206Sandreas.hansson@arm.com // queue, do so now 39210206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 3939567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 3949567SN/A schedule(nextReqEvent, curTick()); 3959243SN/A } 3969243SN/A} 3979243SN/A 3989243SN/Avoid 39910146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 4009243SN/A{ 4019243SN/A // only add to the write queue here. whenever the request is 4029243SN/A // eventually done, set the readyTime, and call schedule() 4039243SN/A assert(pkt->isWrite()); 4049243SN/A 4059831SN/A // if the request size is larger than burst size, the pkt is split into 4069831SN/A // multiple DRAM packets 4079831SN/A Addr addr = pkt->getAddr(); 4089831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4099831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4109831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4119831SN/A writePktSize[ceilLog2(size)]++; 4129831SN/A writeBursts++; 4139243SN/A 4149832SN/A // see if we can merge with an existing item in the write 4159838SN/A // queue and keep track of whether we have merged or not so we 4169838SN/A // can stop at that point and also avoid enqueueing a new 4179838SN/A // request 4189832SN/A bool merged = false; 4199832SN/A auto w = writeQueue.begin(); 4209243SN/A 4219832SN/A while(!merged && w != writeQueue.end()) { 4229832SN/A // either of the two could be first, if they are the same 4239832SN/A // it does not matter which way we go 4249832SN/A if ((*w)->addr >= addr) { 4259838SN/A // the existing one starts after the new one, figure 4269838SN/A // out where the new one ends with respect to the 4279838SN/A // existing one 4289832SN/A if ((addr + size) >= ((*w)->addr + (*w)->size)) { 4299832SN/A // check if the existing one is completely 4309832SN/A // subsumed in the new one 4319832SN/A DPRINTF(DRAM, "Merging write covering existing burst\n"); 4329832SN/A merged = true; 4339832SN/A // update both the address and the size 4349832SN/A (*w)->addr = addr; 4359832SN/A (*w)->size = size; 4369832SN/A } else if ((addr + size) >= (*w)->addr && 4379832SN/A ((*w)->addr + (*w)->size - addr) <= burstSize) { 4389832SN/A // the new one is just before or partially 4399832SN/A // overlapping with the existing one, and together 4409832SN/A // they fit within a burst 4419832SN/A DPRINTF(DRAM, "Merging write before existing burst\n"); 4429832SN/A merged = true; 4439832SN/A // the existing queue item needs to be adjusted with 4449832SN/A // respect to both address and size 44510047SN/A (*w)->size = (*w)->addr + (*w)->size - addr; 4469832SN/A (*w)->addr = addr; 4479832SN/A } 4489832SN/A } else { 4499838SN/A // the new one starts after the current one, figure 4509838SN/A // out where the existing one ends with respect to the 4519838SN/A // new one 4529832SN/A if (((*w)->addr + (*w)->size) >= (addr + size)) { 4539832SN/A // check if the new one is completely subsumed in the 4549832SN/A // existing one 4559832SN/A DPRINTF(DRAM, "Merging write into existing burst\n"); 4569832SN/A merged = true; 4579832SN/A // no adjustments necessary 4589832SN/A } else if (((*w)->addr + (*w)->size) >= addr && 4599832SN/A (addr + size - (*w)->addr) <= burstSize) { 4609832SN/A // the existing one is just before or partially 4619832SN/A // overlapping with the new one, and together 4629832SN/A // they fit within a burst 4639832SN/A DPRINTF(DRAM, "Merging write after existing burst\n"); 4649832SN/A merged = true; 4659832SN/A // the address is right, and only the size has 4669832SN/A // to be adjusted 4679832SN/A (*w)->size = addr + size - (*w)->addr; 4689832SN/A } 4699832SN/A } 4709832SN/A ++w; 4719832SN/A } 4729243SN/A 4739832SN/A // if the item was not merged we need to create a new write 4749832SN/A // and enqueue it 4759832SN/A if (!merged) { 4769966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 4779243SN/A 4789832SN/A assert(writeQueue.size() < writeBufferSize); 4799832SN/A wrQLenPdf[writeQueue.size()]++; 4809243SN/A 4819832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 4829831SN/A 4839832SN/A writeQueue.push_back(dram_pkt); 4849831SN/A 4859832SN/A // Update stats 4869832SN/A avgWrQLen = writeQueue.size(); 4879977SN/A } else { 4889977SN/A // keep track of the fact that this burst effectively 4899977SN/A // disappeared as it was merged with an existing one 4909977SN/A mergedWrBursts++; 4919832SN/A } 4929832SN/A 4939831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 4949831SN/A addr = (addr | (burstSize - 1)) + 1; 4959831SN/A } 4969243SN/A 4979243SN/A // we do not wait for the writes to be send to the actual memory, 4989243SN/A // but instead take responsibility for the consistency here and 4999243SN/A // snoop the write queue for any upcoming reads 5009831SN/A // @todo, if a pkt size is larger than burst size, we might need a 5019831SN/A // different front end latency 5029726SN/A accessAndRespond(pkt, frontendLatency); 5039243SN/A 50410206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 50510206Sandreas.hansson@arm.com // queue, do so now 50610206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 50710206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 50810206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 5099243SN/A } 5109243SN/A} 5119243SN/A 5129243SN/Avoid 51310146Sandreas.hansson@arm.comDRAMCtrl::printParams() const 5149243SN/A{ 5159243SN/A // Sanity check print of important parameters 5169243SN/A DPRINTF(DRAM, 5179243SN/A "Memory controller %s physical organization\n" \ 5189831SN/A "Number of devices per rank %d\n" \ 5199831SN/A "Device bus width (in bits) %d\n" \ 52010143SN/A "DRAM data bus burst (bytes) %d\n" \ 52110143SN/A "Row buffer size (bytes) %d\n" \ 5229831SN/A "Columns per row buffer %d\n" \ 5239831SN/A "Rows per bank %d\n" \ 5249831SN/A "Banks per rank %d\n" \ 5259831SN/A "Ranks per channel %d\n" \ 52610143SN/A "Total mem capacity (bytes) %u\n", 5279831SN/A name(), devicesPerRank, deviceBusWidth, burstSize, rowBufferSize, 5289831SN/A columnsPerRowBuffer, rowsPerBank, banksPerRank, ranksPerChannel, 5299831SN/A rowBufferSize * rowsPerBank * banksPerRank * ranksPerChannel); 5309243SN/A 5319243SN/A string scheduler = memSchedPolicy == Enums::fcfs ? "FCFS" : "FR-FCFS"; 53210136SN/A string address_mapping = addrMapping == Enums::RoRaBaChCo ? "RoRaBaChCo" : 53310136SN/A (addrMapping == Enums::RoRaBaCoCh ? "RoRaBaCoCh" : "RoCoRaBaCh"); 5349973SN/A string page_policy = pageMgmt == Enums::open ? "OPEN" : 53510144SN/A (pageMgmt == Enums::open_adaptive ? "OPEN (adaptive)" : 53610144SN/A (pageMgmt == Enums::close_adaptive ? "CLOSE (adaptive)" : "CLOSE")); 5379243SN/A 5389243SN/A DPRINTF(DRAM, 5399243SN/A "Memory controller %s characteristics\n" \ 5409243SN/A "Read buffer size %d\n" \ 5419243SN/A "Write buffer size %d\n" \ 54210140SN/A "Write high thresh %d\n" \ 54310140SN/A "Write low thresh %d\n" \ 5449243SN/A "Scheduler %s\n" \ 5459243SN/A "Address mapping %s\n" \ 5469243SN/A "Page policy %s\n", 5479972SN/A name(), readBufferSize, writeBufferSize, writeHighThreshold, 54810140SN/A writeLowThreshold, scheduler, address_mapping, page_policy); 5499243SN/A 5509243SN/A DPRINTF(DRAM, "Memory controller %s timing specs\n" \ 5519567SN/A "tRCD %d ticks\n" \ 5529567SN/A "tCL %d ticks\n" \ 5539567SN/A "tRP %d ticks\n" \ 5549567SN/A "tBURST %d ticks\n" \ 5559567SN/A "tRFC %d ticks\n" \ 5569567SN/A "tREFI %d ticks\n" \ 5579567SN/A "tWTR %d ticks\n" \ 55810206Sandreas.hansson@arm.com "tRTW %d ticks\n" \ 5599567SN/A "tXAW (%d) %d ticks\n", 5609567SN/A name(), tRCD, tCL, tRP, tBURST, tRFC, tREFI, tWTR, 56110206Sandreas.hansson@arm.com tRTW, activationLimit, tXAW); 5629243SN/A} 5639243SN/A 5649243SN/Avoid 56510146Sandreas.hansson@arm.comDRAMCtrl::printQs() const { 5669243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 5679833SN/A for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 5689243SN/A DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 5699243SN/A } 5709243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 5719833SN/A for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 5729243SN/A DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 5739243SN/A } 5749243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 5759833SN/A for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 5769243SN/A DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 5779243SN/A } 5789243SN/A} 5799243SN/A 5809243SN/Abool 58110146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 5829243SN/A{ 5839349SN/A /// @todo temporary hack to deal with memory corruption issues until 5849349SN/A /// 4-phase transactions are complete 5859349SN/A for (int x = 0; x < pendingDelete.size(); x++) 5869349SN/A delete pendingDelete[x]; 5879349SN/A pendingDelete.clear(); 5889349SN/A 5899243SN/A // This is where we enter from the outside world 5909567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 5919831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 5929243SN/A 5939567SN/A // simply drop inhibited packets for now 5949567SN/A if (pkt->memInhibitAsserted()) { 59510143SN/A DPRINTF(DRAM, "Inhibited packet -- Dropping it now\n"); 5969567SN/A pendingDelete.push_back(pkt); 5979567SN/A return true; 5989567SN/A } 5999243SN/A 6009243SN/A // Calc avg gap between requests 6019243SN/A if (prevArrival != 0) { 6029243SN/A totGap += curTick() - prevArrival; 6039243SN/A } 6049243SN/A prevArrival = curTick(); 6059243SN/A 6069831SN/A 6079831SN/A // Find out how many dram packets a pkt translates to 6089831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 6099831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 6109831SN/A // multiple dram packets 6119243SN/A unsigned size = pkt->getSize(); 6129831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 6139831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 6149243SN/A 6159243SN/A // check local buffers and do not accept if full 6169243SN/A if (pkt->isRead()) { 6179567SN/A assert(size != 0); 6189831SN/A if (readQueueFull(dram_pkt_count)) { 6199567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 6209243SN/A // remember that we have to retry this port 6219243SN/A retryRdReq = true; 6229243SN/A numRdRetry++; 6239243SN/A return false; 6249243SN/A } else { 6259831SN/A addToReadQueue(pkt, dram_pkt_count); 6269243SN/A readReqs++; 6279977SN/A bytesReadSys += size; 6289243SN/A } 6299243SN/A } else if (pkt->isWrite()) { 6309567SN/A assert(size != 0); 6319831SN/A if (writeQueueFull(dram_pkt_count)) { 6329567SN/A DPRINTF(DRAM, "Write queue full, not accepting\n"); 6339243SN/A // remember that we have to retry this port 6349243SN/A retryWrReq = true; 6359243SN/A numWrRetry++; 6369243SN/A return false; 6379243SN/A } else { 6389831SN/A addToWriteQueue(pkt, dram_pkt_count); 6399243SN/A writeReqs++; 6409977SN/A bytesWrittenSys += size; 6419243SN/A } 6429243SN/A } else { 6439243SN/A DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 6449243SN/A neitherReadNorWrite++; 6459726SN/A accessAndRespond(pkt, 1); 6469243SN/A } 6479243SN/A 6489243SN/A return true; 6499243SN/A} 6509243SN/A 6519243SN/Avoid 65210146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 6539243SN/A{ 6549243SN/A DPRINTF(DRAM, 6559243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 6569243SN/A 6579831SN/A DRAMPacket* dram_pkt = respQueue.front(); 6589243SN/A 6599831SN/A if (dram_pkt->burstHelper) { 6609831SN/A // it is a split packet 6619831SN/A dram_pkt->burstHelper->burstsServiced++; 6629831SN/A if (dram_pkt->burstHelper->burstsServiced == 66310143SN/A dram_pkt->burstHelper->burstCount) { 6649831SN/A // we have now serviced all children packets of a system packet 6659831SN/A // so we can now respond to the requester 6669831SN/A // @todo we probably want to have a different front end and back 6679831SN/A // end latency for split packets 6689831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6699831SN/A delete dram_pkt->burstHelper; 6709831SN/A dram_pkt->burstHelper = NULL; 6719831SN/A } 6729831SN/A } else { 6739831SN/A // it is not a split packet 6749831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 6759831SN/A } 6769243SN/A 6779831SN/A delete respQueue.front(); 6789831SN/A respQueue.pop_front(); 6799243SN/A 6809831SN/A if (!respQueue.empty()) { 6819831SN/A assert(respQueue.front()->readyTime >= curTick()); 6829831SN/A assert(!respondEvent.scheduled()); 6839831SN/A schedule(respondEvent, respQueue.front()->readyTime); 6849831SN/A } else { 6859831SN/A // if there is nothing left in any queue, signal a drain 6869831SN/A if (writeQueue.empty() && readQueue.empty() && 6879831SN/A drainManager) { 6889831SN/A drainManager->signalDrainDone(); 6899831SN/A drainManager = NULL; 6909831SN/A } 6919831SN/A } 6929567SN/A 6939831SN/A // We have made a location in the queue available at this point, 6949831SN/A // so if there is a read that was forced to wait, retry now 6959831SN/A if (retryRdReq) { 6969831SN/A retryRdReq = false; 6979831SN/A port.sendRetry(); 6989831SN/A } 6999243SN/A} 7009243SN/A 7019243SN/Avoid 70210206Sandreas.hansson@arm.comDRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue) 7039243SN/A{ 70410206Sandreas.hansson@arm.com // This method does the arbitration between requests. The chosen 70510206Sandreas.hansson@arm.com // packet is simply moved to the head of the queue. The other 70610206Sandreas.hansson@arm.com // methods know that this is the place to look. For example, with 70710206Sandreas.hansson@arm.com // FCFS, this method does nothing 70810206Sandreas.hansson@arm.com assert(!queue.empty()); 7099243SN/A 71010206Sandreas.hansson@arm.com if (queue.size() == 1) { 71110206Sandreas.hansson@arm.com DPRINTF(DRAM, "Single request, nothing to do\n"); 7129243SN/A return; 7139243SN/A } 7149243SN/A 7159243SN/A if (memSchedPolicy == Enums::fcfs) { 7169243SN/A // Do nothing, since the correct request is already head 7179243SN/A } else if (memSchedPolicy == Enums::frfcfs) { 71810206Sandreas.hansson@arm.com reorderQueue(queue); 7199243SN/A } else 7209243SN/A panic("No scheduling policy chosen\n"); 7219243SN/A} 7229243SN/A 7239243SN/Avoid 72410146Sandreas.hansson@arm.comDRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue) 7259974SN/A{ 7269974SN/A // Only determine this when needed 7279974SN/A uint64_t earliest_banks = 0; 7289974SN/A 7299974SN/A // Search for row hits first, if no row hit is found then schedule the 7309974SN/A // packet to one of the earliest banks available 7319974SN/A bool found_earliest_pkt = false; 7329974SN/A auto selected_pkt_it = queue.begin(); 7339974SN/A 7349974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 7359974SN/A DRAMPacket* dram_pkt = *i; 7369974SN/A const Bank& bank = dram_pkt->bankRef; 7379974SN/A // Check if it is a row hit 7389974SN/A if (bank.openRow == dram_pkt->row) { 7399974SN/A DPRINTF(DRAM, "Row buffer hit\n"); 7409974SN/A selected_pkt_it = i; 7419974SN/A break; 7429974SN/A } else if (!found_earliest_pkt) { 7439974SN/A // No row hit, go for first ready 7449974SN/A if (earliest_banks == 0) 7459974SN/A earliest_banks = minBankFreeAt(queue); 7469974SN/A 7479974SN/A // Bank is ready or is the first available bank 7489974SN/A if (bank.freeAt <= curTick() || 7499974SN/A bits(earliest_banks, dram_pkt->bankId, dram_pkt->bankId)) { 7509974SN/A // Remember the packet to be scheduled to one of the earliest 7519974SN/A // banks available 7529974SN/A selected_pkt_it = i; 7539974SN/A found_earliest_pkt = true; 7549974SN/A } 7559974SN/A } 7569974SN/A } 7579974SN/A 7589974SN/A DRAMPacket* selected_pkt = *selected_pkt_it; 7599974SN/A queue.erase(selected_pkt_it); 7609974SN/A queue.push_front(selected_pkt); 7619974SN/A} 7629974SN/A 7639974SN/Avoid 76410146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 7659243SN/A{ 7669243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 7679243SN/A 7689243SN/A bool needsResponse = pkt->needsResponse(); 7699243SN/A // do the actual memory access which also turns the packet into a 7709243SN/A // response 7719243SN/A access(pkt); 7729243SN/A 7739243SN/A // turn packet around to go back to requester if response expected 7749243SN/A if (needsResponse) { 7759243SN/A // access already turned the packet into a response 7769243SN/A assert(pkt->isResponse()); 7779243SN/A 7789549SN/A // @todo someone should pay for this 7799549SN/A pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; 7809549SN/A 7819726SN/A // queue the packet in the response queue to be sent out after 7829726SN/A // the static latency has passed 7839726SN/A port.schedTimingResp(pkt, curTick() + static_latency); 7849243SN/A } else { 7859587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 7869587SN/A // is still having a pointer to it 7879587SN/A pendingDelete.push_back(pkt); 7889243SN/A } 7899243SN/A 7909243SN/A DPRINTF(DRAM, "Done\n"); 7919243SN/A 7929243SN/A return; 7939243SN/A} 7949243SN/A 7959243SN/Apair<Tick, Tick> 79610146Sandreas.hansson@arm.comDRAMCtrl::estimateLatency(DRAMPacket* dram_pkt, Tick inTime) 7979243SN/A{ 7989243SN/A // If a request reaches a bank at tick 'inTime', how much time 7999243SN/A // *after* that does it take to finish the request, depending 8009243SN/A // on bank status and page open policy. Note that this method 8019243SN/A // considers only the time taken for the actual read or write 8029243SN/A // to complete, NOT any additional time thereafter for tRAS or 8039243SN/A // tRP. 8049243SN/A Tick accLat = 0; 8059243SN/A Tick bankLat = 0; 8069243SN/A rowHitFlag = false; 8079969SN/A Tick potentialActTick; 8089243SN/A 8099967SN/A const Bank& bank = dram_pkt->bankRef; 81010144SN/A // open-page policy or close_adaptive policy 81110144SN/A if (pageMgmt == Enums::open || pageMgmt == Enums::open_adaptive || 81210144SN/A pageMgmt == Enums::close_adaptive) { 8139243SN/A if (bank.openRow == dram_pkt->row) { 8149243SN/A // When we have a row-buffer hit, 8159243SN/A // we don't care about tRAS having expired or not, 8169243SN/A // but do care about bank being free for access 8179243SN/A rowHitFlag = true; 8189243SN/A 8199965SN/A // When a series of requests arrive to the same row, 8209965SN/A // DDR systems are capable of streaming data continuously 8219965SN/A // at maximum bandwidth (subject to tCCD). Here, we approximate 8229965SN/A // this condition, and assume that if whenever a bank is already 8239965SN/A // busy and a new request comes in, it can be completed with no 8249965SN/A // penalty beyond waiting for the existing read to complete. 8259965SN/A if (bank.freeAt > inTime) { 8269965SN/A accLat += bank.freeAt - inTime; 8279966SN/A bankLat += 0; 8289965SN/A } else { 8299243SN/A // CAS latency only 8309243SN/A accLat += tCL; 8319243SN/A bankLat += tCL; 8329243SN/A } 8339243SN/A 8349243SN/A } else { 8359243SN/A // Row-buffer miss, need to close existing row 8369243SN/A // once tRAS has expired, then open the new one, 8379243SN/A // then add cas latency. 8389243SN/A Tick freeTime = std::max(bank.tRASDoneAt, bank.freeAt); 8399243SN/A 8409243SN/A if (freeTime > inTime) 8419243SN/A accLat += freeTime - inTime; 8429243SN/A 8439973SN/A // If the there is no open row (open adaptive), then there 8449973SN/A // is no precharge delay, otherwise go with tRP 84510207Sandreas.hansson@arm.com Tick precharge_delay = bank.openRow == Bank::NO_ROW ? 0 : tRP; 8469973SN/A 8479969SN/A //The bank is free, and you may be able to activate 8489973SN/A potentialActTick = inTime + accLat + precharge_delay; 8499969SN/A if (potentialActTick < bank.actAllowedAt) 8509969SN/A accLat += bank.actAllowedAt - potentialActTick; 8519969SN/A 8529973SN/A accLat += precharge_delay + tRCD + tCL; 8539973SN/A bankLat += precharge_delay + tRCD + tCL; 8549243SN/A } 8559243SN/A } else if (pageMgmt == Enums::close) { 8569243SN/A // With a close page policy, no notion of 8579243SN/A // bank.tRASDoneAt 8589243SN/A if (bank.freeAt > inTime) 8599243SN/A accLat += bank.freeAt - inTime; 8609243SN/A 8619969SN/A //The bank is free, and you may be able to activate 8629969SN/A potentialActTick = inTime + accLat; 8639969SN/A if (potentialActTick < bank.actAllowedAt) 8649969SN/A accLat += bank.actAllowedAt - potentialActTick; 8659969SN/A 8669243SN/A // page already closed, simply open the row, and 8679243SN/A // add cas latency 8689243SN/A accLat += tRCD + tCL; 8699243SN/A bankLat += tRCD + tCL; 8709243SN/A } else 8719243SN/A panic("No page management policy chosen\n"); 8729243SN/A 8739487SN/A DPRINTF(DRAM, "Returning < %lld, %lld > from estimateLatency()\n", 8749487SN/A bankLat, accLat); 8759243SN/A 8769243SN/A return make_pair(bankLat, accLat); 8779243SN/A} 8789243SN/A 8799243SN/Avoid 88010207Sandreas.hansson@arm.comDRAMCtrl::recordActivate(Tick act_tick, uint8_t rank, uint8_t bank, 88110207Sandreas.hansson@arm.com uint16_t row) 8829488SN/A{ 8839969SN/A assert(0 <= rank && rank < ranksPerChannel); 8849969SN/A assert(actTicks[rank].size() == activationLimit); 8859488SN/A 8869488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 8879488SN/A 88810207Sandreas.hansson@arm.com // idleStartTick is the tick when all the banks were 88910207Sandreas.hansson@arm.com // precharged. Thus, the difference between act_tick and 89010207Sandreas.hansson@arm.com // idleStartTick gives the time for which the DRAM is in an idle 89110207Sandreas.hansson@arm.com // state with all banks precharged. Note that we may end up 89210207Sandreas.hansson@arm.com // "changing history" by scheduling an activation before an 89310207Sandreas.hansson@arm.com // already scheduled precharge, effectively canceling it out. 89410207Sandreas.hansson@arm.com if (numBanksActive == 0 && act_tick > idleStartTick) { 89510207Sandreas.hansson@arm.com prechargeAllTime += act_tick - idleStartTick; 8969975SN/A } 8979975SN/A 89810207Sandreas.hansson@arm.com // update the open row 89910207Sandreas.hansson@arm.com assert(banks[rank][bank].openRow == Bank::NO_ROW); 90010207Sandreas.hansson@arm.com banks[rank][bank].openRow = row; 90110207Sandreas.hansson@arm.com 90210207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 90310207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 90410207Sandreas.hansson@arm.com // precharge 90510207Sandreas.hansson@arm.com banks[rank][bank].bytesAccessed = 0; 90610207Sandreas.hansson@arm.com banks[rank][bank].rowAccesses = 0; 90710207Sandreas.hansson@arm.com 90810207Sandreas.hansson@arm.com ++numBanksActive; 90910207Sandreas.hansson@arm.com assert(numBanksActive <= banksPerRank * ranksPerChannel); 91010207Sandreas.hansson@arm.com 91110207Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank at tick %lld, now got %d active\n", 91210207Sandreas.hansson@arm.com act_tick, numBanksActive); 9139975SN/A 9149971SN/A // start by enforcing tRRD 9159971SN/A for(int i = 0; i < banksPerRank; i++) { 9169971SN/A // next activate must not happen before tRRD 9179971SN/A banks[rank][i].actAllowedAt = act_tick + tRRD; 9189971SN/A } 9199971SN/A // tRC should be added to activation tick of the bank currently accessed, 9209971SN/A // where tRC = tRAS + tRP, this is just for a check as actAllowedAt for same 9219971SN/A // bank is already captured by bank.freeAt and bank.tRASDoneAt 9229971SN/A banks[rank][bank].actAllowedAt = act_tick + tRAS + tRP; 9239971SN/A 9249971SN/A // next, we deal with tXAW, if the activation limit is disabled 9259971SN/A // then we are done 9269969SN/A if (actTicks[rank].empty()) 9279824SN/A return; 9289824SN/A 9299488SN/A // sanity check 9309969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 9319825SN/A // @todo For now, stick with a warning 9329825SN/A warn("Got %d activates in window %d (%d - %d) which is smaller " 9339969SN/A "than %d\n", activationLimit, act_tick - actTicks[rank].back(), 9349969SN/A act_tick, actTicks[rank].back(), tXAW); 9359488SN/A } 9369488SN/A 9379488SN/A // shift the times used for the book keeping, the last element 9389488SN/A // (highest index) is the oldest one and hence the lowest value 9399969SN/A actTicks[rank].pop_back(); 9409488SN/A 9419488SN/A // record an new activation (in the future) 9429969SN/A actTicks[rank].push_front(act_tick); 9439488SN/A 9449488SN/A // cannot activate more than X times in time window tXAW, push the 9459488SN/A // next one (the X + 1'st activate) to be tXAW away from the 9469488SN/A // oldest in our window of X 9479969SN/A if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) { 9489488SN/A DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate no earlier " 9499969SN/A "than %d\n", activationLimit, actTicks[rank].back() + tXAW); 9509488SN/A for(int j = 0; j < banksPerRank; j++) 9519488SN/A // next activate must not happen before end of window 9529969SN/A banks[rank][j].actAllowedAt = actTicks[rank].back() + tXAW; 9539488SN/A } 9549488SN/A} 9559488SN/A 9569488SN/Avoid 95710207Sandreas.hansson@arm.comDRAMCtrl::prechargeBank(Bank& bank, Tick free_at) 95810207Sandreas.hansson@arm.com{ 95910207Sandreas.hansson@arm.com // make sure the bank has an open row 96010207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 96110207Sandreas.hansson@arm.com 96210207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 96310207Sandreas.hansson@arm.com // the page 96410207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 96510207Sandreas.hansson@arm.com 96610207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 96710207Sandreas.hansson@arm.com 96810207Sandreas.hansson@arm.com bank.freeAt = free_at; 96910207Sandreas.hansson@arm.com 97010207Sandreas.hansson@arm.com assert(numBanksActive != 0); 97110207Sandreas.hansson@arm.com --numBanksActive; 97210207Sandreas.hansson@arm.com 97310207Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharged bank, done at tick %lld, now got %d active\n", 97410207Sandreas.hansson@arm.com bank.freeAt, numBanksActive); 97510207Sandreas.hansson@arm.com 97610207Sandreas.hansson@arm.com // if we reached zero, then special conditions apply as we track 97710207Sandreas.hansson@arm.com // if all banks are precharged for the power models 97810207Sandreas.hansson@arm.com if (numBanksActive == 0) { 97910207Sandreas.hansson@arm.com idleStartTick = std::max(idleStartTick, bank.freeAt); 98010207Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks precharged at tick: %ld\n", 98110207Sandreas.hansson@arm.com idleStartTick); 98210207Sandreas.hansson@arm.com } 98310207Sandreas.hansson@arm.com} 98410207Sandreas.hansson@arm.com 98510207Sandreas.hansson@arm.comvoid 98610146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 9879243SN/A{ 9889243SN/A 9899243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 9909243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 9919243SN/A 9929243SN/A // estimate the bank and access latency 9939243SN/A pair<Tick, Tick> lat = estimateLatency(dram_pkt, curTick()); 9949243SN/A Tick bankLat = lat.first; 9959243SN/A Tick accessLat = lat.second; 9969963SN/A Tick actTick; 9979243SN/A 9989243SN/A // This request was woken up at this time based on a prior call 9999243SN/A // to estimateLatency(). However, between then and now, both the 10009243SN/A // accessLatency and/or busBusyUntil may have changed. We need 10019243SN/A // to correct for that. 10029243SN/A 10039243SN/A Tick addDelay = (curTick() + accessLat < busBusyUntil) ? 10049243SN/A busBusyUntil - (curTick() + accessLat) : 0; 10059243SN/A 10069967SN/A Bank& bank = dram_pkt->bankRef; 10079243SN/A 10089243SN/A // Update bank state 100910144SN/A if (pageMgmt == Enums::open || pageMgmt == Enums::open_adaptive || 101010144SN/A pageMgmt == Enums::close_adaptive) { 10119727SN/A 101210207Sandreas.hansson@arm.com if (rowHitFlag) { 101310207Sandreas.hansson@arm.com bank.freeAt = curTick() + addDelay + accessLat; 101410207Sandreas.hansson@arm.com } else { 101510207Sandreas.hansson@arm.com // If there is a page open, precharge it. 101610207Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 101710207Sandreas.hansson@arm.com prechargeBank(bank, std::max(std::max(bank.freeAt, 101810207Sandreas.hansson@arm.com bank.tRASDoneAt), 101910207Sandreas.hansson@arm.com curTick()) + tRP); 102010207Sandreas.hansson@arm.com } 102110207Sandreas.hansson@arm.com 102210207Sandreas.hansson@arm.com // Any precharge is already part of the latency 102310207Sandreas.hansson@arm.com // estimation, so update the bank free time 102410207Sandreas.hansson@arm.com bank.freeAt = curTick() + addDelay + accessLat; 102510207Sandreas.hansson@arm.com 10269963SN/A // any waiting for banks account for in freeAt 10279963SN/A actTick = bank.freeAt - tCL - tRCD; 102810207Sandreas.hansson@arm.com 102910207Sandreas.hansson@arm.com // If you activated a new row do to this access, the next access 103010207Sandreas.hansson@arm.com // will have to respect tRAS for this bank 10319963SN/A bank.tRASDoneAt = actTick + tRAS; 10329963SN/A 103310207Sandreas.hansson@arm.com recordActivate(actTick, dram_pkt->rank, dram_pkt->bank, 103410207Sandreas.hansson@arm.com dram_pkt->row); 10359488SN/A } 10369973SN/A 103710141SN/A // increment the bytes accessed and the accesses per row 103810141SN/A bank.bytesAccessed += burstSize; 103910141SN/A ++bank.rowAccesses; 104010141SN/A 104110141SN/A // if we reached the max, then issue with an auto-precharge 104210141SN/A bool auto_precharge = bank.rowAccesses == maxAccessesPerRow; 104310141SN/A 104410141SN/A // if we did not hit the limit, we might still want to 104510141SN/A // auto-precharge 104610144SN/A if (!auto_precharge && 104710144SN/A (pageMgmt == Enums::open_adaptive || 104810144SN/A pageMgmt == Enums::close_adaptive)) { 104910144SN/A // a twist on the open and close page policies: 105010144SN/A // 1) open_adaptive page policy does not blindly keep the 10519973SN/A // page open, but close it if there are no row hits, and there 10529973SN/A // are bank conflicts in the queue 105310144SN/A // 2) close_adaptive page policy does not blindly close the 105410144SN/A // page, but closes it only if there are no row hits in the queue. 105510144SN/A // In this case, only force an auto precharge when there 105610144SN/A // are no same page hits in the queue 10579973SN/A bool got_more_hits = false; 10589973SN/A bool got_bank_conflict = false; 10599973SN/A 10609973SN/A // either look at the read queue or write queue 10619973SN/A const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 10629973SN/A writeQueue; 10639973SN/A auto p = queue.begin(); 10649973SN/A // make sure we are not considering the packet that we are 10659973SN/A // currently dealing with (which is the head of the queue) 10669973SN/A ++p; 10679973SN/A 106810144SN/A // keep on looking until we have found required condition or 106910144SN/A // reached the end 107010144SN/A while (!(got_more_hits && 107110144SN/A (got_bank_conflict || pageMgmt == Enums::close_adaptive)) && 10729973SN/A p != queue.end()) { 10739973SN/A bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 10749973SN/A (dram_pkt->bank == (*p)->bank); 10759973SN/A bool same_row = dram_pkt->row == (*p)->row; 10769973SN/A got_more_hits |= same_rank_bank && same_row; 10779973SN/A got_bank_conflict |= same_rank_bank && !same_row; 10789973SN/A ++p; 10799973SN/A } 10809973SN/A 108110144SN/A // auto pre-charge when either 108210144SN/A // 1) open_adaptive policy, we have not got any more hits, and 108310144SN/A // have a bank conflict 108410144SN/A // 2) close_adaptive policy and we have not got any more hits 108510144SN/A auto_precharge = !got_more_hits && 108610144SN/A (got_bank_conflict || pageMgmt == Enums::close_adaptive); 108710141SN/A } 108810141SN/A 108910141SN/A // if this access should use auto-precharge, then we are 109010141SN/A // closing the row 109110141SN/A if (auto_precharge) { 109210207Sandreas.hansson@arm.com prechargeBank(bank, std::max(bank.freeAt, bank.tRASDoneAt) + tRP); 109310142SN/A 109410141SN/A DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 10959973SN/A } 10969973SN/A 10979971SN/A DPRINTF(DRAM, "doDRAMAccess::bank.freeAt is %lld\n", bank.freeAt); 10989963SN/A } else if (pageMgmt == Enums::close) { 10999963SN/A actTick = curTick() + addDelay + accessLat - tRCD - tCL; 110010207Sandreas.hansson@arm.com recordActivate(actTick, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 11019963SN/A 110210207Sandreas.hansson@arm.com bank.freeAt = actTick + tRCD + tCL; 110310207Sandreas.hansson@arm.com bank.tRASDoneAt = actTick + tRAS; 110410207Sandreas.hansson@arm.com 110510207Sandreas.hansson@arm.com // sample the relevant values when precharging 110610207Sandreas.hansson@arm.com bank.bytesAccessed = burstSize; 110710207Sandreas.hansson@arm.com bank.rowAccesses = 1; 110810207Sandreas.hansson@arm.com 110910207Sandreas.hansson@arm.com prechargeBank(bank, std::max(bank.freeAt, bank.tRASDoneAt) + tRP); 11109971SN/A DPRINTF(DRAM, "doDRAMAccess::bank.freeAt is %lld\n", bank.freeAt); 11119243SN/A } else 11129243SN/A panic("No page management policy chosen\n"); 11139243SN/A 11149243SN/A // Update request parameters 11159243SN/A dram_pkt->readyTime = curTick() + addDelay + accessLat + tBURST; 11169243SN/A 11179243SN/A 11189243SN/A DPRINTF(DRAM, "Req %lld: curtick is %lld accessLat is %d " \ 11199243SN/A "readytime is %lld busbusyuntil is %lld. " \ 11209243SN/A "Scheduling at readyTime\n", dram_pkt->addr, 11219243SN/A curTick(), accessLat, dram_pkt->readyTime, busBusyUntil); 11229243SN/A 11239243SN/A // Make sure requests are not overlapping on the databus 112410206Sandreas.hansson@arm.com assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 11259243SN/A 11269243SN/A // Update bus state 11279243SN/A busBusyUntil = dram_pkt->readyTime; 11289243SN/A 11299243SN/A DPRINTF(DRAM,"Access time is %lld\n", 11309243SN/A dram_pkt->readyTime - dram_pkt->entryTime); 11319243SN/A 113210206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 113310206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 113410206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 113510206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 113610206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 11379972SN/A 113810206Sandreas.hansson@arm.com // Update the stats and schedule the next request 11399977SN/A if (dram_pkt->isRead) { 114010147Sandreas.hansson@arm.com ++readsThisTime; 11419977SN/A if (rowHitFlag) 11429977SN/A readRowHits++; 11439977SN/A bytesReadDRAM += burstSize; 11449977SN/A perBankRdBursts[dram_pkt->bankId]++; 114510206Sandreas.hansson@arm.com 114610206Sandreas.hansson@arm.com // Update latency stats 114710206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 114810206Sandreas.hansson@arm.com totBankLat += bankLat; 114910206Sandreas.hansson@arm.com totBusLat += tBURST; 115010206Sandreas.hansson@arm.com totQLat += dram_pkt->readyTime - dram_pkt->entryTime - bankLat - 115110206Sandreas.hansson@arm.com tBURST; 11529977SN/A } else { 115310147Sandreas.hansson@arm.com ++writesThisTime; 11549977SN/A if (rowHitFlag) 11559977SN/A writeRowHits++; 11569977SN/A bytesWritten += burstSize; 11579977SN/A perBankWrBursts[dram_pkt->bankId]++; 11589243SN/A } 11599243SN/A} 11609243SN/A 11619243SN/Avoid 116210146Sandreas.hansson@arm.comDRAMCtrl::moveToRespQ() 11639243SN/A{ 11649243SN/A // Remove from read queue 11659567SN/A DRAMPacket* dram_pkt = readQueue.front(); 11669567SN/A readQueue.pop_front(); 11679243SN/A 11689832SN/A // sanity check 11699832SN/A assert(dram_pkt->size <= burstSize); 11709832SN/A 11719243SN/A // Insert into response queue sorted by readyTime 11729243SN/A // It will be sent back to the requestor at its 11739243SN/A // readyTime 11749567SN/A if (respQueue.empty()) { 11759567SN/A respQueue.push_front(dram_pkt); 11769243SN/A assert(!respondEvent.scheduled()); 11779243SN/A assert(dram_pkt->readyTime >= curTick()); 11789567SN/A schedule(respondEvent, dram_pkt->readyTime); 11799243SN/A } else { 11809243SN/A bool done = false; 11819833SN/A auto i = respQueue.begin(); 11829567SN/A while (!done && i != respQueue.end()) { 11839243SN/A if ((*i)->readyTime > dram_pkt->readyTime) { 11849567SN/A respQueue.insert(i, dram_pkt); 11859243SN/A done = true; 11869243SN/A } 11879243SN/A ++i; 11889243SN/A } 11899243SN/A 11909243SN/A if (!done) 11919567SN/A respQueue.push_back(dram_pkt); 11929243SN/A 11939243SN/A assert(respondEvent.scheduled()); 11949243SN/A 11959567SN/A if (respQueue.front()->readyTime < respondEvent.when()) { 11969567SN/A assert(respQueue.front()->readyTime >= curTick()); 11979567SN/A reschedule(respondEvent, respQueue.front()->readyTime); 11989243SN/A } 11999243SN/A } 12009243SN/A} 12019243SN/A 12029243SN/Avoid 120310206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 12049243SN/A{ 120510206Sandreas.hansson@arm.com if (busState == READ_TO_WRITE) { 120610206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 120710206Sandreas.hansson@arm.com "waiting\n", readsThisTime, readQueue.size()); 12089243SN/A 120910206Sandreas.hansson@arm.com // sample and reset the read-related stats as we are now 121010206Sandreas.hansson@arm.com // transitioning to writes, and all reads are done 121110206Sandreas.hansson@arm.com rdPerTurnAround.sample(readsThisTime); 121210206Sandreas.hansson@arm.com readsThisTime = 0; 121310206Sandreas.hansson@arm.com 121410206Sandreas.hansson@arm.com // now proceed to do the actual writes 121510206Sandreas.hansson@arm.com busState = WRITE; 121610206Sandreas.hansson@arm.com } else if (busState == WRITE_TO_READ) { 121710206Sandreas.hansson@arm.com DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 121810206Sandreas.hansson@arm.com "waiting\n", writesThisTime, writeQueue.size()); 121910206Sandreas.hansson@arm.com 122010206Sandreas.hansson@arm.com wrPerTurnAround.sample(writesThisTime); 122110206Sandreas.hansson@arm.com writesThisTime = 0; 122210206Sandreas.hansson@arm.com 122310206Sandreas.hansson@arm.com busState = READ; 122410206Sandreas.hansson@arm.com } 122510206Sandreas.hansson@arm.com 122610207Sandreas.hansson@arm.com if (refreshState != REF_IDLE) { 122710207Sandreas.hansson@arm.com // if a refresh waiting for this event loop to finish, then hand 122810207Sandreas.hansson@arm.com // over now, and do not schedule a new nextReqEvent 122910207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 123010207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 123110207Sandreas.hansson@arm.com 123210207Sandreas.hansson@arm.com refreshState = REF_PRE; 123310207Sandreas.hansson@arm.com 123410207Sandreas.hansson@arm.com // hand control back to the refresh event loop 123510207Sandreas.hansson@arm.com schedule(refreshEvent, curTick()); 123610207Sandreas.hansson@arm.com } 123710207Sandreas.hansson@arm.com 123810207Sandreas.hansson@arm.com // let the refresh finish before issuing any further requests 123910207Sandreas.hansson@arm.com return; 124010207Sandreas.hansson@arm.com } 124110207Sandreas.hansson@arm.com 124210206Sandreas.hansson@arm.com // when we get here it is either a read or a write 124310206Sandreas.hansson@arm.com if (busState == READ) { 124410206Sandreas.hansson@arm.com 124510206Sandreas.hansson@arm.com // track if we should switch or not 124610206Sandreas.hansson@arm.com bool switch_to_writes = false; 124710206Sandreas.hansson@arm.com 124810206Sandreas.hansson@arm.com if (readQueue.empty()) { 124910206Sandreas.hansson@arm.com // In the case there is no read request to go next, 125010206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 125110206Sandreas.hansson@arm.com // if we are draining) 125210206Sandreas.hansson@arm.com if (!writeQueue.empty() && 125310206Sandreas.hansson@arm.com (drainManager || writeQueue.size() > writeLowThreshold)) { 125410206Sandreas.hansson@arm.com 125510206Sandreas.hansson@arm.com switch_to_writes = true; 125610206Sandreas.hansson@arm.com } else { 125710206Sandreas.hansson@arm.com // check if we are drained 125810206Sandreas.hansson@arm.com if (respQueue.empty () && drainManager) { 125910206Sandreas.hansson@arm.com drainManager->signalDrainDone(); 126010206Sandreas.hansson@arm.com drainManager = NULL; 126110206Sandreas.hansson@arm.com } 126210206Sandreas.hansson@arm.com 126310206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 126410206Sandreas.hansson@arm.com // event for the next request 126510206Sandreas.hansson@arm.com return; 126610206Sandreas.hansson@arm.com } 126710206Sandreas.hansson@arm.com } else { 126810206Sandreas.hansson@arm.com // Figure out which read request goes next, and move it to the 126910206Sandreas.hansson@arm.com // front of the read queue 127010206Sandreas.hansson@arm.com chooseNext(readQueue); 127110206Sandreas.hansson@arm.com 127210206Sandreas.hansson@arm.com doDRAMAccess(readQueue.front()); 127310206Sandreas.hansson@arm.com 127410206Sandreas.hansson@arm.com // At this point we're done dealing with the request 127510206Sandreas.hansson@arm.com // It will be moved to a separate response queue with a 127610206Sandreas.hansson@arm.com // correct readyTime, and eventually be sent back at that 127710206Sandreas.hansson@arm.com // time 127810206Sandreas.hansson@arm.com moveToRespQ(); 127910206Sandreas.hansson@arm.com 128010206Sandreas.hansson@arm.com // we have so many writes that we have to transition 128110206Sandreas.hansson@arm.com if (writeQueue.size() > writeHighThreshold) { 128210206Sandreas.hansson@arm.com switch_to_writes = true; 128310206Sandreas.hansson@arm.com } 128410206Sandreas.hansson@arm.com } 128510206Sandreas.hansson@arm.com 128610206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 128710206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 128810206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 128910206Sandreas.hansson@arm.com if (switch_to_writes) { 129010206Sandreas.hansson@arm.com // transition to writing 129110206Sandreas.hansson@arm.com busState = READ_TO_WRITE; 129210206Sandreas.hansson@arm.com 129310206Sandreas.hansson@arm.com // add a bubble to the data bus, as defined by the 129410206Sandreas.hansson@arm.com // tRTW parameter 129510206Sandreas.hansson@arm.com busBusyUntil += tRTW; 129610206Sandreas.hansson@arm.com 129710206Sandreas.hansson@arm.com // update the minimum timing between the requests, 129810206Sandreas.hansson@arm.com // this shifts us back in time far enough to do any 129910206Sandreas.hansson@arm.com // bank preparation 130010206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 130110206Sandreas.hansson@arm.com } 13029352SN/A } else { 130310206Sandreas.hansson@arm.com chooseNext(writeQueue); 130410206Sandreas.hansson@arm.com DRAMPacket* dram_pkt = writeQueue.front(); 130510206Sandreas.hansson@arm.com // sanity check 130610206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 130710206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 130810206Sandreas.hansson@arm.com 130910206Sandreas.hansson@arm.com writeQueue.pop_front(); 131010206Sandreas.hansson@arm.com delete dram_pkt; 131110206Sandreas.hansson@arm.com 131210206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 131310206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 131410206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 131510206Sandreas.hansson@arm.com // writes, then switch to reads. 131610206Sandreas.hansson@arm.com if (writeQueue.empty() || 131710206Sandreas.hansson@arm.com (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 131810206Sandreas.hansson@arm.com !drainManager) || 131910206Sandreas.hansson@arm.com (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 132010206Sandreas.hansson@arm.com // turn the bus back around for reads again 132110206Sandreas.hansson@arm.com busState = WRITE_TO_READ; 132210206Sandreas.hansson@arm.com 132310206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 132410206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 132510206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 132610206Sandreas.hansson@arm.com // nothing to do 132710206Sandreas.hansson@arm.com 132810206Sandreas.hansson@arm.com // here we get a bit creative and shift the bus busy time not 132910206Sandreas.hansson@arm.com // just the tWTR, but also a CAS latency to capture the fact 133010206Sandreas.hansson@arm.com // that we are allowed to prepare a new bank, but not issue a 133110206Sandreas.hansson@arm.com // read command until after tWTR, in essence we capture a 133210206Sandreas.hansson@arm.com // bubble on the data bus that is tWTR + tCL 133310206Sandreas.hansson@arm.com busBusyUntil += tWTR + tCL; 133410206Sandreas.hansson@arm.com 133510206Sandreas.hansson@arm.com // update the minimum timing between the requests, this shifts 133610206Sandreas.hansson@arm.com // us back in time far enough to do any bank preparation 133710206Sandreas.hansson@arm.com nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 133810206Sandreas.hansson@arm.com } 133910206Sandreas.hansson@arm.com } 134010206Sandreas.hansson@arm.com 134110206Sandreas.hansson@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 134210206Sandreas.hansson@arm.com 134310206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 134410206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 134510206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 134610206Sandreas.hansson@arm.com // the next request processing 134710206Sandreas.hansson@arm.com if (retryWrReq && writeQueue.size() < writeBufferSize) { 134810206Sandreas.hansson@arm.com retryWrReq = false; 134910206Sandreas.hansson@arm.com port.sendRetry(); 13509352SN/A } 13519243SN/A} 13529243SN/A 13539967SN/Auint64_t 135410146Sandreas.hansson@arm.comDRAMCtrl::minBankFreeAt(const deque<DRAMPacket*>& queue) const 13559967SN/A{ 13569967SN/A uint64_t bank_mask = 0; 13579967SN/A Tick freeAt = MaxTick; 13589967SN/A 13599967SN/A // detemrine if we have queued transactions targetting the 13609967SN/A // bank in question 13619967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 13629967SN/A for (auto p = queue.begin(); p != queue.end(); ++p) { 13639967SN/A got_waiting[(*p)->bankId] = true; 13649967SN/A } 13659967SN/A 13669967SN/A for (int i = 0; i < ranksPerChannel; i++) { 13679967SN/A for (int j = 0; j < banksPerRank; j++) { 13689967SN/A // if we have waiting requests for the bank, and it is 13699967SN/A // amongst the first available, update the mask 13709967SN/A if (got_waiting[i * banksPerRank + j] && 13719967SN/A banks[i][j].freeAt <= freeAt) { 13729967SN/A // reset bank mask if new minimum is found 13739967SN/A if (banks[i][j].freeAt < freeAt) 13749967SN/A bank_mask = 0; 13759967SN/A // set the bit corresponding to the available bank 13769967SN/A uint8_t bit_index = i * ranksPerChannel + j; 13779967SN/A replaceBits(bank_mask, bit_index, bit_index, 1); 13789967SN/A freeAt = banks[i][j].freeAt; 13799967SN/A } 13809967SN/A } 13819967SN/A } 13829967SN/A return bank_mask; 13839967SN/A} 13849967SN/A 13859243SN/Avoid 138610146Sandreas.hansson@arm.comDRAMCtrl::processRefreshEvent() 13879243SN/A{ 138810207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 138910207Sandreas.hansson@arm.com if (refreshState == REF_IDLE) { 139010207Sandreas.hansson@arm.com // remember when the refresh is due 139110207Sandreas.hansson@arm.com refreshDueAt = curTick(); 13929243SN/A 139310207Sandreas.hansson@arm.com // proceed to drain 139410207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 13959243SN/A 139610207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 139710207Sandreas.hansson@arm.com } 139810207Sandreas.hansson@arm.com 139910207Sandreas.hansson@arm.com // let any scheduled read or write go ahead, after which it will 140010207Sandreas.hansson@arm.com // hand control back to this event loop 140110207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 140210207Sandreas.hansson@arm.com if (nextReqEvent.scheduled()) { 140310207Sandreas.hansson@arm.com // hand control over to the request loop until it is 140410207Sandreas.hansson@arm.com // evaluated next 140510207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 140610207Sandreas.hansson@arm.com 140710207Sandreas.hansson@arm.com return; 140810207Sandreas.hansson@arm.com } else { 140910207Sandreas.hansson@arm.com refreshState = REF_PRE; 141010207Sandreas.hansson@arm.com } 141110207Sandreas.hansson@arm.com } 141210207Sandreas.hansson@arm.com 141310207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 141410207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 141510207Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 141610207Sandreas.hansson@arm.com 141710207Sandreas.hansson@arm.com // precharge any active bank 141810207Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 141910207Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 142010207Sandreas.hansson@arm.com if (banks[i][j].openRow != Bank::NO_ROW) { 142110207Sandreas.hansson@arm.com // respect both causality and any existing bank 142210207Sandreas.hansson@arm.com // constraints 142310207Sandreas.hansson@arm.com Tick free_at = std::max(std::max(banks[i][j].freeAt, 142410207Sandreas.hansson@arm.com banks[i][j].tRASDoneAt), 142510207Sandreas.hansson@arm.com curTick()) + tRP; 142610207Sandreas.hansson@arm.com 142710207Sandreas.hansson@arm.com prechargeBank(banks[i][j], free_at); 142810207Sandreas.hansson@arm.com } 142910207Sandreas.hansson@arm.com } 14309975SN/A } 14319975SN/A 143210207Sandreas.hansson@arm.com if (numBanksActive != 0) 143310207Sandreas.hansson@arm.com panic("Refresh scheduled with %d active banks\n", numBanksActive); 14349243SN/A 143510207Sandreas.hansson@arm.com // advance the state 143610207Sandreas.hansson@arm.com refreshState = REF_RUN; 143710207Sandreas.hansson@arm.com 143810207Sandreas.hansson@arm.com // call ourselves in the future 143910207Sandreas.hansson@arm.com schedule(refreshEvent, std::max(curTick(), idleStartTick)); 144010207Sandreas.hansson@arm.com return; 144110207Sandreas.hansson@arm.com } 144210207Sandreas.hansson@arm.com 144310207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 144410207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 144510207Sandreas.hansson@arm.com // should never get here with any banks active 144610207Sandreas.hansson@arm.com assert(numBanksActive == 0); 144710207Sandreas.hansson@arm.com 144810207Sandreas.hansson@arm.com Tick banksFree = curTick() + tRFC; 144910207Sandreas.hansson@arm.com 145010207Sandreas.hansson@arm.com for (int i = 0; i < ranksPerChannel; i++) { 145110207Sandreas.hansson@arm.com for (int j = 0; j < banksPerRank; j++) { 145210207Sandreas.hansson@arm.com banks[i][j].freeAt = banksFree; 145310207Sandreas.hansson@arm.com } 145410207Sandreas.hansson@arm.com } 145510207Sandreas.hansson@arm.com 145610207Sandreas.hansson@arm.com // make sure we did not wait so long that we cannot make up 145710207Sandreas.hansson@arm.com // for it 145810207Sandreas.hansson@arm.com if (refreshDueAt + tREFI < banksFree) { 145910207Sandreas.hansson@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 146010207Sandreas.hansson@arm.com } 146110207Sandreas.hansson@arm.com 146210207Sandreas.hansson@arm.com // compensate for the delay in actually performing the refresh 146310207Sandreas.hansson@arm.com // when scheduling the next one 146410207Sandreas.hansson@arm.com schedule(refreshEvent, refreshDueAt + tREFI - tRP); 146510207Sandreas.hansson@arm.com 146610207Sandreas.hansson@arm.com // back to business as usual 146710207Sandreas.hansson@arm.com refreshState = REF_IDLE; 146810207Sandreas.hansson@arm.com 146910207Sandreas.hansson@arm.com // we are now refreshing until tRFC is done 147010207Sandreas.hansson@arm.com idleStartTick = banksFree; 147110207Sandreas.hansson@arm.com 147210207Sandreas.hansson@arm.com // kick the normal request processing loop into action again 147310207Sandreas.hansson@arm.com // as early as possible, i.e. when the request is done, the 147410207Sandreas.hansson@arm.com // scheduling of this event also prevents any new requests 147510207Sandreas.hansson@arm.com // from going ahead before the scheduled point in time 147610207Sandreas.hansson@arm.com nextReqTime = banksFree; 147710207Sandreas.hansson@arm.com schedule(nextReqEvent, nextReqTime); 147810207Sandreas.hansson@arm.com } 14799243SN/A} 14809243SN/A 14819243SN/Avoid 148210146Sandreas.hansson@arm.comDRAMCtrl::regStats() 14839243SN/A{ 14849243SN/A using namespace Stats; 14859243SN/A 14869243SN/A AbstractMemory::regStats(); 14879243SN/A 14889243SN/A readReqs 14899243SN/A .name(name() + ".readReqs") 14909977SN/A .desc("Number of read requests accepted"); 14919243SN/A 14929243SN/A writeReqs 14939243SN/A .name(name() + ".writeReqs") 14949977SN/A .desc("Number of write requests accepted"); 14959831SN/A 14969831SN/A readBursts 14979831SN/A .name(name() + ".readBursts") 14989977SN/A .desc("Number of DRAM read bursts, " 14999977SN/A "including those serviced by the write queue"); 15009831SN/A 15019831SN/A writeBursts 15029831SN/A .name(name() + ".writeBursts") 15039977SN/A .desc("Number of DRAM write bursts, " 15049977SN/A "including those merged in the write queue"); 15059243SN/A 15069243SN/A servicedByWrQ 15079243SN/A .name(name() + ".servicedByWrQ") 15089977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 15099977SN/A 15109977SN/A mergedWrBursts 15119977SN/A .name(name() + ".mergedWrBursts") 15129977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 15139243SN/A 15149243SN/A neitherReadNorWrite 15159977SN/A .name(name() + ".neitherReadNorWriteReqs") 15169977SN/A .desc("Number of requests that are neither read nor write"); 15179243SN/A 15189977SN/A perBankRdBursts 15199243SN/A .init(banksPerRank * ranksPerChannel) 15209977SN/A .name(name() + ".perBankRdBursts") 15219977SN/A .desc("Per bank write bursts"); 15229243SN/A 15239977SN/A perBankWrBursts 15249243SN/A .init(banksPerRank * ranksPerChannel) 15259977SN/A .name(name() + ".perBankWrBursts") 15269977SN/A .desc("Per bank write bursts"); 15279243SN/A 15289243SN/A avgRdQLen 15299243SN/A .name(name() + ".avgRdQLen") 15309977SN/A .desc("Average read queue length when enqueuing") 15319243SN/A .precision(2); 15329243SN/A 15339243SN/A avgWrQLen 15349243SN/A .name(name() + ".avgWrQLen") 15359977SN/A .desc("Average write queue length when enqueuing") 15369243SN/A .precision(2); 15379243SN/A 15389243SN/A totQLat 15399243SN/A .name(name() + ".totQLat") 15409977SN/A .desc("Total ticks spent queuing"); 15419243SN/A 15429243SN/A totBankLat 15439243SN/A .name(name() + ".totBankLat") 15449977SN/A .desc("Total ticks spent accessing banks"); 15459243SN/A 15469243SN/A totBusLat 15479243SN/A .name(name() + ".totBusLat") 15489977SN/A .desc("Total ticks spent in databus transfers"); 15499243SN/A 15509243SN/A totMemAccLat 15519243SN/A .name(name() + ".totMemAccLat") 15529977SN/A .desc("Total ticks spent from burst creation until serviced " 15539977SN/A "by the DRAM"); 15549243SN/A 15559243SN/A avgQLat 15569243SN/A .name(name() + ".avgQLat") 15579977SN/A .desc("Average queueing delay per DRAM burst") 15589243SN/A .precision(2); 15599243SN/A 15609831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 15619243SN/A 15629243SN/A avgBankLat 15639243SN/A .name(name() + ".avgBankLat") 15649977SN/A .desc("Average bank access latency per DRAM burst") 15659243SN/A .precision(2); 15669243SN/A 15679831SN/A avgBankLat = totBankLat / (readBursts - servicedByWrQ); 15689243SN/A 15699243SN/A avgBusLat 15709243SN/A .name(name() + ".avgBusLat") 15719977SN/A .desc("Average bus latency per DRAM burst") 15729243SN/A .precision(2); 15739243SN/A 15749831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 15759243SN/A 15769243SN/A avgMemAccLat 15779243SN/A .name(name() + ".avgMemAccLat") 15789977SN/A .desc("Average memory access latency per DRAM burst") 15799243SN/A .precision(2); 15809243SN/A 15819831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 15829243SN/A 15839243SN/A numRdRetry 15849243SN/A .name(name() + ".numRdRetry") 15859977SN/A .desc("Number of times read queue was full causing retry"); 15869243SN/A 15879243SN/A numWrRetry 15889243SN/A .name(name() + ".numWrRetry") 15899977SN/A .desc("Number of times write queue was full causing retry"); 15909243SN/A 15919243SN/A readRowHits 15929243SN/A .name(name() + ".readRowHits") 15939243SN/A .desc("Number of row buffer hits during reads"); 15949243SN/A 15959243SN/A writeRowHits 15969243SN/A .name(name() + ".writeRowHits") 15979243SN/A .desc("Number of row buffer hits during writes"); 15989243SN/A 15999243SN/A readRowHitRate 16009243SN/A .name(name() + ".readRowHitRate") 16019243SN/A .desc("Row buffer hit rate for reads") 16029243SN/A .precision(2); 16039243SN/A 16049831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 16059243SN/A 16069243SN/A writeRowHitRate 16079243SN/A .name(name() + ".writeRowHitRate") 16089243SN/A .desc("Row buffer hit rate for writes") 16099243SN/A .precision(2); 16109243SN/A 16119977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 16129243SN/A 16139243SN/A readPktSize 16149831SN/A .init(ceilLog2(burstSize) + 1) 16159243SN/A .name(name() + ".readPktSize") 16169977SN/A .desc("Read request sizes (log2)"); 16179243SN/A 16189243SN/A writePktSize 16199831SN/A .init(ceilLog2(burstSize) + 1) 16209243SN/A .name(name() + ".writePktSize") 16219977SN/A .desc("Write request sizes (log2)"); 16229243SN/A 16239243SN/A rdQLenPdf 16249567SN/A .init(readBufferSize) 16259243SN/A .name(name() + ".rdQLenPdf") 16269243SN/A .desc("What read queue length does an incoming req see"); 16279243SN/A 16289243SN/A wrQLenPdf 16299567SN/A .init(writeBufferSize) 16309243SN/A .name(name() + ".wrQLenPdf") 16319243SN/A .desc("What write queue length does an incoming req see"); 16329243SN/A 16339727SN/A bytesPerActivate 163410141SN/A .init(maxAccessesPerRow) 16359727SN/A .name(name() + ".bytesPerActivate") 16369727SN/A .desc("Bytes accessed per row activation") 16379727SN/A .flags(nozero); 16389243SN/A 163910147Sandreas.hansson@arm.com rdPerTurnAround 164010147Sandreas.hansson@arm.com .init(readBufferSize) 164110147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 164210147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 164310147Sandreas.hansson@arm.com .flags(nozero); 164410147Sandreas.hansson@arm.com 164510147Sandreas.hansson@arm.com wrPerTurnAround 164610147Sandreas.hansson@arm.com .init(writeBufferSize) 164710147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 164810147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 164910147Sandreas.hansson@arm.com .flags(nozero); 165010147Sandreas.hansson@arm.com 16519975SN/A bytesReadDRAM 16529975SN/A .name(name() + ".bytesReadDRAM") 16539975SN/A .desc("Total number of bytes read from DRAM"); 16549975SN/A 16559975SN/A bytesReadWrQ 16569975SN/A .name(name() + ".bytesReadWrQ") 16579975SN/A .desc("Total number of bytes read from write queue"); 16589243SN/A 16599243SN/A bytesWritten 16609243SN/A .name(name() + ".bytesWritten") 16619977SN/A .desc("Total number of bytes written to DRAM"); 16629243SN/A 16639977SN/A bytesReadSys 16649977SN/A .name(name() + ".bytesReadSys") 16659977SN/A .desc("Total read bytes from the system interface side"); 16669243SN/A 16679977SN/A bytesWrittenSys 16689977SN/A .name(name() + ".bytesWrittenSys") 16699977SN/A .desc("Total written bytes from the system interface side"); 16709243SN/A 16719243SN/A avgRdBW 16729243SN/A .name(name() + ".avgRdBW") 16739977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 16749243SN/A .precision(2); 16759243SN/A 16769977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 16779243SN/A 16789243SN/A avgWrBW 16799243SN/A .name(name() + ".avgWrBW") 16809977SN/A .desc("Average achieved write bandwidth in MiByte/s") 16819243SN/A .precision(2); 16829243SN/A 16839243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 16849243SN/A 16859977SN/A avgRdBWSys 16869977SN/A .name(name() + ".avgRdBWSys") 16879977SN/A .desc("Average system read bandwidth in MiByte/s") 16889243SN/A .precision(2); 16899243SN/A 16909977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 16919243SN/A 16929977SN/A avgWrBWSys 16939977SN/A .name(name() + ".avgWrBWSys") 16949977SN/A .desc("Average system write bandwidth in MiByte/s") 16959243SN/A .precision(2); 16969243SN/A 16979977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 16989243SN/A 16999243SN/A peakBW 17009243SN/A .name(name() + ".peakBW") 17019977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 17029243SN/A .precision(2); 17039243SN/A 17049831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 17059243SN/A 17069243SN/A busUtil 17079243SN/A .name(name() + ".busUtil") 17089243SN/A .desc("Data bus utilization in percentage") 17099243SN/A .precision(2); 17109243SN/A 17119243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 17129243SN/A 17139243SN/A totGap 17149243SN/A .name(name() + ".totGap") 17159243SN/A .desc("Total gap between requests"); 17169243SN/A 17179243SN/A avgGap 17189243SN/A .name(name() + ".avgGap") 17199243SN/A .desc("Average gap between requests") 17209243SN/A .precision(2); 17219243SN/A 17229243SN/A avgGap = totGap / (readReqs + writeReqs); 17239975SN/A 17249975SN/A // Stats for DRAM Power calculation based on Micron datasheet 17259975SN/A busUtilRead 17269975SN/A .name(name() + ".busUtilRead") 17279975SN/A .desc("Data bus utilization in percentage for reads") 17289975SN/A .precision(2); 17299975SN/A 17309975SN/A busUtilRead = avgRdBW / peakBW * 100; 17319975SN/A 17329975SN/A busUtilWrite 17339975SN/A .name(name() + ".busUtilWrite") 17349975SN/A .desc("Data bus utilization in percentage for writes") 17359975SN/A .precision(2); 17369975SN/A 17379975SN/A busUtilWrite = avgWrBW / peakBW * 100; 17389975SN/A 17399975SN/A pageHitRate 17409975SN/A .name(name() + ".pageHitRate") 17419975SN/A .desc("Row buffer hit rate, read and write combined") 17429975SN/A .precision(2); 17439975SN/A 17449977SN/A pageHitRate = (writeRowHits + readRowHits) / 17459977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 17469975SN/A 17479975SN/A prechargeAllPercent 17489975SN/A .name(name() + ".prechargeAllPercent") 17499975SN/A .desc("Percentage of time for which DRAM has all the banks in " 17509975SN/A "precharge state") 17519975SN/A .precision(2); 17529975SN/A 17539975SN/A prechargeAllPercent = prechargeAllTime / simTicks * 100; 17549243SN/A} 17559243SN/A 17569243SN/Avoid 175710146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 17589243SN/A{ 17599243SN/A // rely on the abstract memory 17609243SN/A functionalAccess(pkt); 17619243SN/A} 17629243SN/A 17639294SN/ABaseSlavePort& 176410146Sandreas.hansson@arm.comDRAMCtrl::getSlavePort(const string &if_name, PortID idx) 17659243SN/A{ 17669243SN/A if (if_name != "port") { 17679243SN/A return MemObject::getSlavePort(if_name, idx); 17689243SN/A } else { 17699243SN/A return port; 17709243SN/A } 17719243SN/A} 17729243SN/A 17739243SN/Aunsigned int 177410146Sandreas.hansson@arm.comDRAMCtrl::drain(DrainManager *dm) 17759243SN/A{ 17769342SN/A unsigned int count = port.drain(dm); 17779243SN/A 17789243SN/A // if there is anything in any of our internal queues, keep track 17799243SN/A // of that as well 17809567SN/A if (!(writeQueue.empty() && readQueue.empty() && 17819567SN/A respQueue.empty())) { 17829352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 17839567SN/A " resp: %d\n", writeQueue.size(), readQueue.size(), 17849567SN/A respQueue.size()); 17859243SN/A ++count; 17869342SN/A drainManager = dm; 178710206Sandreas.hansson@arm.com 17889352SN/A // the only part that is not drained automatically over time 178910206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 179010206Sandreas.hansson@arm.com if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 179110206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 179210206Sandreas.hansson@arm.com } 17939243SN/A } 17949243SN/A 17959243SN/A if (count) 17969342SN/A setDrainState(Drainable::Draining); 17979243SN/A else 17989342SN/A setDrainState(Drainable::Drained); 17999243SN/A return count; 18009243SN/A} 18019243SN/A 180210146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 18039243SN/A : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 18049243SN/A memory(_memory) 18059243SN/A{ } 18069243SN/A 18079243SN/AAddrRangeList 180810146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 18099243SN/A{ 18109243SN/A AddrRangeList ranges; 18119243SN/A ranges.push_back(memory.getAddrRange()); 18129243SN/A return ranges; 18139243SN/A} 18149243SN/A 18159243SN/Avoid 181610146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 18179243SN/A{ 18189243SN/A pkt->pushLabel(memory.name()); 18199243SN/A 18209243SN/A if (!queue.checkFunctional(pkt)) { 18219243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 18229243SN/A // calls recvAtomic() and throws away the latency; we can save a 18239243SN/A // little here by just not calculating the latency. 18249243SN/A memory.recvFunctional(pkt); 18259243SN/A } 18269243SN/A 18279243SN/A pkt->popLabel(); 18289243SN/A} 18299243SN/A 18309243SN/ATick 183110146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 18329243SN/A{ 18339243SN/A return memory.recvAtomic(pkt); 18349243SN/A} 18359243SN/A 18369243SN/Abool 183710146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 18389243SN/A{ 18399243SN/A // pass it to the memory controller 18409243SN/A return memory.recvTimingReq(pkt); 18419243SN/A} 18429243SN/A 184310146Sandreas.hansson@arm.comDRAMCtrl* 184410146Sandreas.hansson@arm.comDRAMCtrlParams::create() 18459243SN/A{ 184610146Sandreas.hansson@arm.com return new DRAMCtrl(this); 18479243SN/A} 1848