write_queue_entry.cc revision 12724:4f6fac3191d2 
1/*
2 * Copyright (c) 2012-2013, 2015-2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2010 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Erik Hallnor
42 *          Dave Greene
43 *          Andreas Hansson
44 */
45
46/**
47 * @file
48 * Miss Status and Handling Register (WriteQueueEntry) definitions.
49 */
50
51#include "mem/cache/write_queue_entry.hh"
52
53#include <algorithm>
54#include <cassert>
55#include <string>
56#include <vector>
57
58#include "base/logging.hh"
59#include "base/types.hh"
60#include "debug/Cache.hh"
61#include "mem/cache/cache.hh"
62#include "sim/core.hh"
63
64inline void
65WriteQueueEntry::TargetList::add(PacketPtr pkt, Tick readyTime,
66                                 Counter order)
67{
68    emplace_back(pkt, readyTime, order);
69}
70
71bool
72WriteQueueEntry::TargetList::checkFunctional(PacketPtr pkt)
73{
74    for (auto& t : *this) {
75        if (pkt->checkFunctional(t.pkt)) {
76            return true;
77        }
78    }
79
80    return false;
81}
82
83void
84WriteQueueEntry::TargetList::print(std::ostream &os, int verbosity,
85                                   const std::string &prefix) const
86{
87    for (auto& t : *this) {
88        ccprintf(os, "%sFromCPU: ", prefix);
89        t.pkt->print(os, verbosity, "");
90    }
91}
92
93void
94WriteQueueEntry::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
95                          Tick when_ready, Counter _order)
96{
97    blkAddr = blk_addr;
98    blkSize = blk_size;
99    isSecure = target->isSecure();
100    readyTime = when_ready;
101    order = _order;
102    assert(target);
103    _isUncacheable = target->req->isUncacheable();
104    inService = false;
105
106    // we should never have more than a single target for cacheable
107    // writes (writebacks and clean evictions)
108    panic_if(!_isUncacheable && !targets.empty(),
109             "Write queue entry %#llx should never have more than one "
110             "cacheable target", blkAddr);
111    panic_if(!((target->isWrite() && _isUncacheable) ||
112               (target->isEviction() && !_isUncacheable) ||
113               target->cmd == MemCmd::WriteClean),
114             "Write queue entry %#llx should be an uncacheable write or "
115             "a cacheable eviction or a writeclean");
116
117    targets.add(target, when_ready, _order);
118}
119
120void
121WriteQueueEntry::deallocate()
122{
123    assert(targets.empty());
124    inService = false;
125}
126
127bool
128WriteQueueEntry::checkFunctional(PacketPtr pkt)
129{
130    // For printing, we treat the WriteQueueEntry as a whole as single
131    // entity. For other requests, we iterate over the individual
132    // targets since that's where the actual data lies.
133    if (pkt->isPrint()) {
134        pkt->checkFunctional(this, blkAddr, isSecure, blkSize, nullptr);
135        return false;
136    } else {
137        return targets.checkFunctional(pkt);
138    }
139}
140
141bool
142WriteQueueEntry::sendPacket(BaseCache &cache)
143{
144    return cache.sendWriteQueuePacket(this);
145}
146
147void
148WriteQueueEntry::print(std::ostream &os, int verbosity,
149                       const std::string &prefix) const
150{
151    ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
152             prefix, blkAddr, blkAddr + blkSize - 1,
153             isSecure ? "s" : "ns",
154             _isUncacheable ? "Unc" : "",
155             inService ? "InSvc" : "");
156
157    ccprintf(os, "%s  Targets:\n", prefix);
158    targets.print(os, verbosity, prefix + "    ");
159}
160
161std::string
162WriteQueueEntry::print() const
163{
164    std::ostringstream str;
165    print(str);
166    return str.str();
167}
168