write_queue_entry.cc revision 12345:70c783a93195 
1/*
2 * Copyright (c) 2012-2013, 2015-2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2010 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Erik Hallnor
42 *          Dave Greene
43 *          Andreas Hansson
44 */
45
46/**
47 * @file
48 * Miss Status and Handling Register (WriteQueueEntry) definitions.
49 */
50
51#include "mem/cache/write_queue_entry.hh"
52
53#include <algorithm>
54#include <cassert>
55#include <string>
56#include <vector>
57
58#include "base/logging.hh"
59#include "base/types.hh"
60#include "debug/Cache.hh"
61#include "mem/cache/cache.hh"
62#include "sim/core.hh"
63
64using namespace std;
65
66inline void
67WriteQueueEntry::TargetList::add(PacketPtr pkt, Tick readyTime,
68                                 Counter order)
69{
70    emplace_back(pkt, readyTime, order);
71}
72
73bool
74WriteQueueEntry::TargetList::checkFunctional(PacketPtr pkt)
75{
76    for (auto& t : *this) {
77        if (pkt->checkFunctional(t.pkt)) {
78            return true;
79        }
80    }
81
82    return false;
83}
84
85void
86WriteQueueEntry::TargetList::print(std::ostream &os, int verbosity,
87                                   const std::string &prefix) const
88{
89    for (auto& t : *this) {
90        ccprintf(os, "%sFromCPU: ", prefix);
91        t.pkt->print(os, verbosity, "");
92    }
93}
94
95void
96WriteQueueEntry::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
97                          Tick when_ready, Counter _order)
98{
99    blkAddr = blk_addr;
100    blkSize = blk_size;
101    isSecure = target->isSecure();
102    readyTime = when_ready;
103    order = _order;
104    assert(target);
105    _isUncacheable = target->req->isUncacheable();
106    inService = false;
107
108    // we should never have more than a single target for cacheable
109    // writes (writebacks and clean evictions)
110    panic_if(!_isUncacheable && !targets.empty(),
111             "Write queue entry %#llx should never have more than one "
112             "cacheable target", blkAddr);
113    panic_if(!((target->isWrite() && _isUncacheable) ||
114               (target->isEviction() && !_isUncacheable) ||
115               target->cmd == MemCmd::WriteClean),
116             "Write queue entry %#llx should be an uncacheable write or "
117             "a cacheable eviction or a writeclean");
118
119    targets.add(target, when_ready, _order);
120}
121
122void
123WriteQueueEntry::deallocate()
124{
125    assert(targets.empty());
126    inService = false;
127}
128
129bool
130WriteQueueEntry::checkFunctional(PacketPtr pkt)
131{
132    // For printing, we treat the WriteQueueEntry as a whole as single
133    // entity. For other requests, we iterate over the individual
134    // targets since that's where the actual data lies.
135    if (pkt->isPrint()) {
136        pkt->checkFunctional(this, blkAddr, isSecure, blkSize, nullptr);
137        return false;
138    } else {
139        return targets.checkFunctional(pkt);
140    }
141}
142
143bool
144WriteQueueEntry::sendPacket(Cache &cache)
145{
146    return cache.sendWriteQueuePacket(this);
147}
148
149void
150WriteQueueEntry::print(std::ostream &os, int verbosity,
151                       const std::string &prefix) const
152{
153    ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
154             prefix, blkAddr, blkAddr + blkSize - 1,
155             isSecure ? "s" : "ns",
156             _isUncacheable ? "Unc" : "",
157             inService ? "InSvc" : "");
158
159    ccprintf(os, "%s  Targets:\n", prefix);
160    targets.print(os, verbosity, prefix + "    ");
161}
162
163std::string
164WriteQueueEntry::print() const
165{
166    ostringstream str;
167    print(str);
168    return str.str();
169}
170