fa_lru.hh revision 13378:038ea95fd793
1955SN/A/* 2955SN/A * Copyright (c) 2012-2013,2016,2018 ARM Limited 31762SN/A * All rights reserved. 4955SN/A * 5955SN/A * The license below extends only to copyright in the software and shall 6955SN/A * not be construed as granting a license to any other intellectual 7955SN/A * property including but not limited to intellectual property relating 8955SN/A * to a hardware implementation of the functionality of the software 9955SN/A * licensed hereunder. You may use the software subject to the license 10955SN/A * terms below provided that you ensure that this notice is replicated 11955SN/A * unmodified and in its entirety in all distributions of the software, 12955SN/A * modified or unmodified, in source code or in binary form. 13955SN/A * 14955SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 15955SN/A * All rights reserved. 16955SN/A * 17955SN/A * Redistribution and use in source and binary forms, with or without 18955SN/A * modification, are permitted provided that the following conditions are 19955SN/A * met: redistributions of source code must retain the above copyright 20955SN/A * notice, this list of conditions and the following disclaimer; 21955SN/A * redistributions in binary form must reproduce the above copyright 22955SN/A * notice, this list of conditions and the following disclaimer in the 23955SN/A * documentation and/or other materials provided with the distribution; 24955SN/A * neither the name of the copyright holders nor the names of its 25955SN/A * contributors may be used to endorse or promote products derived from 26955SN/A * this software without specific prior written permission. 27955SN/A * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30955SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31955SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32955SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33955SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34955SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352632Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362632Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372632Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382632Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39955SN/A * 402632Sstever@eecs.umich.edu * Authors: Erik Hallnor 412632Sstever@eecs.umich.edu * Nikos Nikoleris 422761Sstever@eecs.umich.edu */ 432632Sstever@eecs.umich.edu 442632Sstever@eecs.umich.edu/** 452632Sstever@eecs.umich.edu * @file 462761Sstever@eecs.umich.edu * Declaration of a fully associative LRU tag store. 472761Sstever@eecs.umich.edu */ 482761Sstever@eecs.umich.edu 492632Sstever@eecs.umich.edu#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__ 502632Sstever@eecs.umich.edu#define __MEM_CACHE_TAGS_FA_LRU_HH__ 512761Sstever@eecs.umich.edu 522761Sstever@eecs.umich.edu#include <cstdint> 532761Sstever@eecs.umich.edu#include <functional> 542761Sstever@eecs.umich.edu#include <string> 552761Sstever@eecs.umich.edu#include <unordered_map> 562632Sstever@eecs.umich.edu#include <vector> 572632Sstever@eecs.umich.edu 582632Sstever@eecs.umich.edu#include "base/bitfield.hh" 592632Sstever@eecs.umich.edu#include "base/intmath.hh" 602632Sstever@eecs.umich.edu#include "base/logging.hh" 612632Sstever@eecs.umich.edu#include "base/statistics.hh" 622632Sstever@eecs.umich.edu#include "base/types.hh" 63955SN/A#include "mem/cache/cache_blk.hh" 64955SN/A#include "mem/cache/tags/base.hh" 65955SN/A#include "params/FALRU.hh" 66955SN/A 67955SN/A// Uncomment to enable sanity checks for the FALRU cache and the 683918Ssaidi@eecs.umich.edu// TrackedCaches class 694202Sbinkertn@umich.edu//#define FALRU_DEBUG 704678Snate@binkert.org 71955SN/Aclass BaseCache; 722656Sstever@eecs.umich.educlass ReplaceableEntry; 732656Sstever@eecs.umich.edu 742656Sstever@eecs.umich.edu// A bitmask of the caches we are keeping track of. Currently the 752656Sstever@eecs.umich.edu// lowest bit is the smallest cache we are tracking, as it is 762656Sstever@eecs.umich.edu// specified by the corresponding parameter. The rest of the bits are 772656Sstever@eecs.umich.edu// for exponentially growing cache sizes. 782656Sstever@eecs.umich.edutypedef uint32_t CachesMask; 792653Sstever@eecs.umich.edu 802653Sstever@eecs.umich.edu/** 812653Sstever@eecs.umich.edu * A fully associative cache block. 822653Sstever@eecs.umich.edu */ 832653Sstever@eecs.umich.educlass FALRUBlk : public CacheBlk 842653Sstever@eecs.umich.edu{ 852653Sstever@eecs.umich.edu public: 862653Sstever@eecs.umich.edu FALRUBlk() : CacheBlk(), prev(nullptr), next(nullptr), inCachesMask(0) {} 872653Sstever@eecs.umich.edu 882653Sstever@eecs.umich.edu /** The previous block in LRU order. */ 894781Snate@binkert.org FALRUBlk *prev; 901852SN/A /** The next block in LRU order. */ 91955SN/A FALRUBlk *next; 92955SN/A 93955SN/A /** A bit mask of the caches that fit this block. */ 943717Sstever@eecs.umich.edu CachesMask inCachesMask; 953716Sstever@eecs.umich.edu 96955SN/A /** 971533SN/A * Pretty-print inCachesMask and other CacheBlk information. 983716Sstever@eecs.umich.edu * 991533SN/A * @return string with basic state information 1004678Snate@binkert.org */ 1014678Snate@binkert.org std::string print() const override; 1024678Snate@binkert.org}; 1034678Snate@binkert.org 1044678Snate@binkert.org/** 1054678Snate@binkert.org * A fully associative LRU cache. Keeps statistics for accesses to a number of 1064678Snate@binkert.org * cache sizes at once. 1074678Snate@binkert.org */ 1084678Snate@binkert.orgclass FALRU : public BaseTags 1094678Snate@binkert.org{ 1104678Snate@binkert.org public: 1114678Snate@binkert.org /** Typedef the block type used in this class. */ 1124678Snate@binkert.org typedef FALRUBlk BlkType; 1134678Snate@binkert.org 1144678Snate@binkert.org protected: 1154678Snate@binkert.org /** The cache blocks. */ 1164678Snate@binkert.org FALRUBlk *blks; 1174678Snate@binkert.org 1184678Snate@binkert.org /** The MRU block. */ 1194678Snate@binkert.org FALRUBlk *head; 1204678Snate@binkert.org /** The LRU block. */ 1214973Ssaidi@eecs.umich.edu FALRUBlk *tail; 1224678Snate@binkert.org 1234678Snate@binkert.org /** Hash table type mapping addresses to cache block pointers. */ 1244678Snate@binkert.org struct PairHash 1254678Snate@binkert.org { 1264678Snate@binkert.org template <class T1, class T2> 1274678Snate@binkert.org std::size_t operator()(const std::pair<T1, T2> &p) const 128955SN/A { 129955SN/A return std::hash<T1>()(p.first) ^ std::hash<T2>()(p.second); 1302632Sstever@eecs.umich.edu } 1312632Sstever@eecs.umich.edu }; 132955SN/A typedef std::pair<Addr, bool> TagHashKey; 133955SN/A typedef std::unordered_map<TagHashKey, FALRUBlk *, PairHash> TagHash; 134955SN/A 135955SN/A /** The address hash table. */ 1362632Sstever@eecs.umich.edu TagHash tagHash; 137955SN/A 1382632Sstever@eecs.umich.edu /** 1392632Sstever@eecs.umich.edu * Move a cache block to the MRU position. 1402632Sstever@eecs.umich.edu * 1412632Sstever@eecs.umich.edu * @param blk The block to promote. 1422632Sstever@eecs.umich.edu */ 1432632Sstever@eecs.umich.edu void moveToHead(FALRUBlk *blk); 1442632Sstever@eecs.umich.edu 1453053Sstever@eecs.umich.edu /** 1463053Sstever@eecs.umich.edu * Move a cache block to the LRU position. 1473053Sstever@eecs.umich.edu * 1483053Sstever@eecs.umich.edu * @param blk The block to demote. 1493053Sstever@eecs.umich.edu */ 1503053Sstever@eecs.umich.edu void moveToTail(FALRUBlk *blk); 1513053Sstever@eecs.umich.edu 1523053Sstever@eecs.umich.edu public: 1533053Sstever@eecs.umich.edu typedef FALRUParams Params; 1543053Sstever@eecs.umich.edu 1553053Sstever@eecs.umich.edu /** 1563053Sstever@eecs.umich.edu * Construct and initialize this cache tagstore. 1573053Sstever@eecs.umich.edu */ 1583053Sstever@eecs.umich.edu FALRU(const Params *p); 1593053Sstever@eecs.umich.edu ~FALRU(); 1603053Sstever@eecs.umich.edu 1612632Sstever@eecs.umich.edu /** 1622632Sstever@eecs.umich.edu * Initialize blocks and set the parent cache back pointer. 1632632Sstever@eecs.umich.edu * 1642632Sstever@eecs.umich.edu * @param _cache Pointer to parent cache. 1652632Sstever@eecs.umich.edu */ 1662632Sstever@eecs.umich.edu void tagsInit(BaseCache *_cache) override; 1673718Sstever@eecs.umich.edu 1683718Sstever@eecs.umich.edu /** 1693718Sstever@eecs.umich.edu * Register the stats for this object. 1703718Sstever@eecs.umich.edu */ 1713718Sstever@eecs.umich.edu void regStats() override; 1723718Sstever@eecs.umich.edu 1733718Sstever@eecs.umich.edu /** 1743718Sstever@eecs.umich.edu * Invalidate a cache block. 1753718Sstever@eecs.umich.edu * @param blk The block to invalidate. 1763718Sstever@eecs.umich.edu */ 1773718Sstever@eecs.umich.edu void invalidate(CacheBlk *blk) override; 1783718Sstever@eecs.umich.edu 1793718Sstever@eecs.umich.edu /** 1802634Sstever@eecs.umich.edu * Access block and update replacement data. May not succeed, in which 1812634Sstever@eecs.umich.edu * case nullptr pointer is returned. This has all the implications of a 1822632Sstever@eecs.umich.edu * cache access and should only be used as such. 1832638Sstever@eecs.umich.edu * Returns the access latency and inCachesMask flags as a side effect. 1842632Sstever@eecs.umich.edu * @param addr The address to look for. 1852632Sstever@eecs.umich.edu * @param is_secure True if the target memory space is secure. 1862632Sstever@eecs.umich.edu * @param lat The latency of the access. 1872632Sstever@eecs.umich.edu * @param in_cache_mask Mask indicating the caches in which the blk fits. 1882632Sstever@eecs.umich.edu * @return Pointer to the cache block. 1892632Sstever@eecs.umich.edu */ 1901858SN/A CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat, 1913716Sstever@eecs.umich.edu CachesMask *in_cache_mask); 1922638Sstever@eecs.umich.edu 1932638Sstever@eecs.umich.edu /** 1942638Sstever@eecs.umich.edu * Just a wrapper of above function to conform with the base interface. 1952638Sstever@eecs.umich.edu */ 1962638Sstever@eecs.umich.edu CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override; 1972638Sstever@eecs.umich.edu 1982638Sstever@eecs.umich.edu /** 1993716Sstever@eecs.umich.edu * Find the block in the cache, do not update the replacement data. 2002634Sstever@eecs.umich.edu * @param addr The address to look for. 2012634Sstever@eecs.umich.edu * @param is_secure True if the target memory space is secure. 202955SN/A * @param asid The address space ID. 203955SN/A * @return Pointer to the cache block. 204955SN/A */ 205955SN/A CacheBlk* findBlock(Addr addr, bool is_secure) const override; 206955SN/A 207955SN/A /** 208955SN/A * Find a block given set and way. 209955SN/A * 2101858SN/A * @param set The set of the block. 2111858SN/A * @param way The way of the block. 2122632Sstever@eecs.umich.edu * @return The block. 213955SN/A */ 2144781Snate@binkert.org ReplaceableEntry* findBlockBySetAndWay(int set, int way) const override; 2153643Ssaidi@eecs.umich.edu 2163643Ssaidi@eecs.umich.edu /** 2173643Ssaidi@eecs.umich.edu * Find replacement victim based on address. The list of evicted blocks 2183643Ssaidi@eecs.umich.edu * only contains the victim. 2193643Ssaidi@eecs.umich.edu * 2203643Ssaidi@eecs.umich.edu * @param addr Address to find a victim for. 2213643Ssaidi@eecs.umich.edu * @param is_secure True if the target memory space is secure. 2224494Ssaidi@eecs.umich.edu * @param evict_blks Cache blocks to be evicted. 2234494Ssaidi@eecs.umich.edu * @return Cache block to be replaced. 2243716Sstever@eecs.umich.edu */ 2251105SN/A CacheBlk* findVictim(Addr addr, const bool is_secure, 2262667Sstever@eecs.umich.edu std::vector<CacheBlk*>& evict_blks) const override; 2272667Sstever@eecs.umich.edu 2282667Sstever@eecs.umich.edu /** 2292667Sstever@eecs.umich.edu * Insert the new block into the cache and update replacement data. 2302667Sstever@eecs.umich.edu * 2312667Sstever@eecs.umich.edu * @param addr Address of the block. 2321869SN/A * @param is_secure Whether the block is in secure space or not. 2331869SN/A * @param src_master_ID The source requestor ID. 2341869SN/A * @param task_ID The new task ID. 2351869SN/A * @param blk The block to update. 2361869SN/A */ 2371065SN/A void insertBlock(const Addr addr, const bool is_secure, 2382632Sstever@eecs.umich.edu const int src_master_ID, const uint32_t task_ID, 2395199Sstever@gmail.com CacheBlk *blk) override; 2403918Ssaidi@eecs.umich.edu 2413918Ssaidi@eecs.umich.edu /** 2423940Ssaidi@eecs.umich.edu * Generate the tag from the addres. For fully associative this is just the 2434781Snate@binkert.org * block address. 2444781Snate@binkert.org * @param addr The address to get the tag from. 2453918Ssaidi@eecs.umich.edu * @return The tag. 2464781Snate@binkert.org */ 2474781Snate@binkert.org Addr extractTag(Addr addr) const override 2483918Ssaidi@eecs.umich.edu { 2494781Snate@binkert.org return blkAlign(addr); 2504781Snate@binkert.org } 2513940Ssaidi@eecs.umich.edu 2523942Ssaidi@eecs.umich.edu /** 2533940Ssaidi@eecs.umich.edu * Regenerate the block address from the tag. 2543918Ssaidi@eecs.umich.edu * 2553918Ssaidi@eecs.umich.edu * @param block The block. 256955SN/A * @return the block address. 2571858SN/A */ 2583918Ssaidi@eecs.umich.edu Addr regenerateBlkAddr(const CacheBlk* blk) const override 2593918Ssaidi@eecs.umich.edu { 2603918Ssaidi@eecs.umich.edu return blk->tag; 2613918Ssaidi@eecs.umich.edu } 2623940Ssaidi@eecs.umich.edu 2633940Ssaidi@eecs.umich.edu void forEachBlk(std::function<void(CacheBlk &)> visitor) override { 2643918Ssaidi@eecs.umich.edu for (int i = 0; i < numBlocks; i++) { 2653918Ssaidi@eecs.umich.edu visitor(blks[i]); 2663918Ssaidi@eecs.umich.edu } 2673918Ssaidi@eecs.umich.edu } 2683918Ssaidi@eecs.umich.edu 2693918Ssaidi@eecs.umich.edu bool anyBlk(std::function<bool(CacheBlk &)> visitor) override { 2703918Ssaidi@eecs.umich.edu for (int i = 0; i < numBlocks; i++) { 2713918Ssaidi@eecs.umich.edu if (visitor(blks[i])) { 2723918Ssaidi@eecs.umich.edu return true; 2733940Ssaidi@eecs.umich.edu } 2743918Ssaidi@eecs.umich.edu } 2753918Ssaidi@eecs.umich.edu return false; 2761851SN/A } 2771851SN/A 2781858SN/A private: 2795200Sstever@gmail.com /** 280955SN/A * Mechanism that allows us to simultaneously collect miss 2813053Sstever@eecs.umich.edu * statistics for multiple caches. Currently, we keep track of 2823053Sstever@eecs.umich.edu * caches from a set minimum size of interest up to the actual 2833053Sstever@eecs.umich.edu * cache size. 2843053Sstever@eecs.umich.edu */ 2853053Sstever@eecs.umich.edu class CacheTracking 2863053Sstever@eecs.umich.edu { 2873053Sstever@eecs.umich.edu public: 2883053Sstever@eecs.umich.edu CacheTracking(unsigned min_size, unsigned max_size, 2893053Sstever@eecs.umich.edu unsigned block_size) 2904742Sstever@eecs.umich.edu : blkSize(block_size), 2914742Sstever@eecs.umich.edu minTrackedSize(min_size), 2923053Sstever@eecs.umich.edu numTrackedCaches(max_size > min_size ? 2933053Sstever@eecs.umich.edu floorLog2(max_size) - floorLog2(min_size) : 0), 2943053Sstever@eecs.umich.edu inAllCachesMask(mask(numTrackedCaches)), 2953053Sstever@eecs.umich.edu boundaries(numTrackedCaches) 2963053Sstever@eecs.umich.edu { 2973053Sstever@eecs.umich.edu fatal_if(numTrackedCaches > sizeof(CachesMask) * 8, 2983053Sstever@eecs.umich.edu "Not enough bits (%s) in type CachesMask type to keep " 2993053Sstever@eecs.umich.edu "track of %d caches\n", sizeof(CachesMask), 3003053Sstever@eecs.umich.edu numTrackedCaches); 3012667Sstever@eecs.umich.edu } 3024554Sbinkertn@umich.edu 3034554Sbinkertn@umich.edu /** 3042667Sstever@eecs.umich.edu * Initialiaze cache blocks and the tracking mechanism 3054554Sbinkertn@umich.edu * 3064554Sbinkertn@umich.edu * All blocks in the cache need to be initialized once. 3074554Sbinkertn@umich.edu * 3084554Sbinkertn@umich.edu * @param blk the MRU block 3094554Sbinkertn@umich.edu * @param blk the LRU block 3104554Sbinkertn@umich.edu */ 3114554Sbinkertn@umich.edu void init(FALRUBlk *head, FALRUBlk *tail); 3124781Snate@binkert.org 3134554Sbinkertn@umich.edu /** 3144554Sbinkertn@umich.edu * Update boundaries as a block will be moved to the MRU. 3152667Sstever@eecs.umich.edu * 3164554Sbinkertn@umich.edu * For all caches that didn't fit the block before moving it, 3174554Sbinkertn@umich.edu * we move their boundaries one block closer to the MRU. We 3184554Sbinkertn@umich.edu * also update InCacheMasks as neccessary. 3194554Sbinkertn@umich.edu * 3202667Sstever@eecs.umich.edu * @param blk the block that will be moved to the head 3214554Sbinkertn@umich.edu */ 3222667Sstever@eecs.umich.edu void moveBlockToHead(FALRUBlk *blk); 3234554Sbinkertn@umich.edu 3244554Sbinkertn@umich.edu /** 3252667Sstever@eecs.umich.edu * Update boundaries as a block will be moved to the LRU. 3262638Sstever@eecs.umich.edu * 3272638Sstever@eecs.umich.edu * For all caches that fitted the block before moving it, we 3282638Sstever@eecs.umich.edu * move their boundaries one block closer to the LRU. We 3293716Sstever@eecs.umich.edu * also update InCacheMasks as neccessary. 3303716Sstever@eecs.umich.edu * 3311858SN/A * @param blk the block that will be moved to the head 3325204Sstever@gmail.com */ 3335204Sstever@gmail.com void moveBlockToTail(FALRUBlk *blk); 3345204Sstever@gmail.com 3355204Sstever@gmail.com /** 3365204Sstever@gmail.com * Notify of a block access. 3375204Sstever@gmail.com * 3385204Sstever@gmail.com * This should be called every time a block is accessed and it 3395204Sstever@gmail.com * updates statistics. If the input block is nullptr then we 3405204Sstever@gmail.com * treat the access as a miss. The block's InCacheMask 3415204Sstever@gmail.com * determines the caches in which the block fits. 3425204Sstever@gmail.com * 3435204Sstever@gmail.com * @param blk the block to record the access for 3445204Sstever@gmail.com */ 3455204Sstever@gmail.com void recordAccess(FALRUBlk *blk); 3465204Sstever@gmail.com 3475204Sstever@gmail.com /** 3485204Sstever@gmail.com * Check that the tracking mechanism is in consistent state. 3495204Sstever@gmail.com * 3505204Sstever@gmail.com * Iterate from the head (MRU) to the tail (LRU) of the list 3513118Sstever@eecs.umich.edu * of blocks and assert the inCachesMask and the boundaries 3523118Sstever@eecs.umich.edu * are in consistent state. 3533118Sstever@eecs.umich.edu * 3543118Sstever@eecs.umich.edu * @param head the MRU block of the actual cache 3553118Sstever@eecs.umich.edu * @param head the LRU block of the actual cache 3563118Sstever@eecs.umich.edu */ 3573118Sstever@eecs.umich.edu void check(const FALRUBlk *head, const FALRUBlk *tail) const; 3583118Sstever@eecs.umich.edu 3593118Sstever@eecs.umich.edu /** 3603118Sstever@eecs.umich.edu * Register the stats for this object. 3613118Sstever@eecs.umich.edu */ 3623716Sstever@eecs.umich.edu void regStats(std::string name); 3633118Sstever@eecs.umich.edu 3643118Sstever@eecs.umich.edu private: 3653118Sstever@eecs.umich.edu /** The size of the cache block */ 3663118Sstever@eecs.umich.edu const unsigned blkSize; 3673118Sstever@eecs.umich.edu /** The smallest cache we are tracking */ 3683118Sstever@eecs.umich.edu const unsigned minTrackedSize; 3693118Sstever@eecs.umich.edu /** The number of different size caches being tracked. */ 3703118Sstever@eecs.umich.edu const int numTrackedCaches; 3713118Sstever@eecs.umich.edu /** A mask for all cache being tracked. */ 3723716Sstever@eecs.umich.edu const CachesMask inAllCachesMask; 3733118Sstever@eecs.umich.edu /** Array of pointers to blocks at the cache boundaries. */ 3743118Sstever@eecs.umich.edu std::vector<FALRUBlk*> boundaries; 3753118Sstever@eecs.umich.edu 3763118Sstever@eecs.umich.edu protected: 3773118Sstever@eecs.umich.edu /** 3783118Sstever@eecs.umich.edu * @defgroup FALRUStats Fully Associative LRU specific statistics 3793118Sstever@eecs.umich.edu * The FA lru stack lets us track multiple cache sizes at once. These 3803118Sstever@eecs.umich.edu * statistics track the hits and misses for different cache sizes. 3813118Sstever@eecs.umich.edu * @{ 3823118Sstever@eecs.umich.edu */ 3833483Ssaidi@eecs.umich.edu 3843494Ssaidi@eecs.umich.edu /** Hits in each cache */ 3853494Ssaidi@eecs.umich.edu Stats::Vector hits; 3863483Ssaidi@eecs.umich.edu /** Misses in each cache */ 3873483Ssaidi@eecs.umich.edu Stats::Vector misses; 3883483Ssaidi@eecs.umich.edu /** Total number of accesses */ 3893053Sstever@eecs.umich.edu Stats::Scalar accesses; 3903053Sstever@eecs.umich.edu 3913918Ssaidi@eecs.umich.edu /** 3923053Sstever@eecs.umich.edu * @} 3933053Sstever@eecs.umich.edu */ 3943053Sstever@eecs.umich.edu }; 3953053Sstever@eecs.umich.edu CacheTracking cacheTracking; 3963053Sstever@eecs.umich.edu}; 3971858SN/A 3981858SN/A#endif // __MEM_CACHE_TAGS_FA_LRU_HH__ 3991858SN/A