fa_lru.hh revision 11869:aa9d04c7e3bb
18706Sandreas.hansson@arm.com/* 27586SAli.Saidi@arm.com * Copyright (c) 2012-2013 ARM Limited 37586SAli.Saidi@arm.com * All rights reserved. 47586SAli.Saidi@arm.com * 57586SAli.Saidi@arm.com * The license below extends only to copyright in the software and shall 67586SAli.Saidi@arm.com * not be construed as granting a license to any other intellectual 77586SAli.Saidi@arm.com * property including but not limited to intellectual property relating 87586SAli.Saidi@arm.com * to a hardware implementation of the functionality of the software 97586SAli.Saidi@arm.com * licensed hereunder. You may use the software subject to the license 107586SAli.Saidi@arm.com * terms below provided that you ensure that this notice is replicated 117586SAli.Saidi@arm.com * unmodified and in its entirety in all distributions of the software, 127586SAli.Saidi@arm.com * modified or unmodified, in source code or in binary form. 137905SBrad.Beckmann@amd.com * 145323Sgblack@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 152934Sktlim@umich.edu * All rights reserved. 162934Sktlim@umich.edu * 172934Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu * modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu * this software without specific prior written permission. 272934Sktlim@umich.edu * 282934Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302934Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322934Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu * 402934Sktlim@umich.edu * Authors: Erik Hallnor 412934Sktlim@umich.edu */ 422934Sktlim@umich.edu 432995Ssaidi@eecs.umich.edu/** 448528SAli.Saidi@ARM.com * @file 452934Sktlim@umich.edu * Declaration of a fully associative LRU tag store. 462934Sktlim@umich.edu */ 472934Sktlim@umich.edu 482934Sktlim@umich.edu#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__ 492934Sktlim@umich.edu#define __MEM_CACHE_TAGS_FA_LRU_HH__ 502934Sktlim@umich.edu 512934Sktlim@umich.edu#include <list> 522934Sktlim@umich.edu#include <unordered_map> 539036Sandreas.hansson@arm.com 546122SSteve.Reinhardt@amd.com#include "mem/cache/base.hh" 556122SSteve.Reinhardt@amd.com#include "mem/cache/blk.hh" 566122SSteve.Reinhardt@amd.com#include "mem/cache/tags/base.hh" 576122SSteve.Reinhardt@amd.com#include "mem/packet.hh" 589826Sandreas.hansson@arm.com#include "params/FALRU.hh" 598713Sandreas.hansson@arm.com 604520Ssaidi@eecs.umich.edu/** 614982Ssaidi@eecs.umich.edu * A fully associative cache block. 624520Ssaidi@eecs.umich.edu */ 634520Ssaidi@eecs.umich.educlass FALRUBlk : public CacheBlk 642934Sktlim@umich.edu{ 652934Sktlim@umich.edupublic: 663005Sstever@eecs.umich.edu /** The previous block in LRU order. */ 673005Sstever@eecs.umich.edu FALRUBlk *prev; 683304Sstever@eecs.umich.edu /** The next block in LRU order. */ 692995Ssaidi@eecs.umich.edu FALRUBlk *next; 709036Sandreas.hansson@arm.com /** Has this block been touched? */ 719036Sandreas.hansson@arm.com bool isTouched; 728713Sandreas.hansson@arm.com 738713Sandreas.hansson@arm.com /** 749164Sandreas.hansson@arm.com * A bit mask of the sizes of cache that this block is resident in. 758713Sandreas.hansson@arm.com * Each bit represents a power of 2 in MB size cache. 769826Sandreas.hansson@arm.com * If bit 0 is set, this block is in a 1MB cache 778839Sandreas.hansson@arm.com * If bit 2 is set, this block is in a 4MB cache, etc. 788839Sandreas.hansson@arm.com * There is one bit for each cache smaller than the full size (default 792934Sktlim@umich.edu * 16MB). 802934Sktlim@umich.edu */ 812995Ssaidi@eecs.umich.edu int inCache; 822934Sktlim@umich.edu}; 832934Sktlim@umich.edu 842934Sktlim@umich.edu/** 858839Sandreas.hansson@arm.com * A fully associative LRU cache. Keeps statistics for accesses to a number of 868839Sandreas.hansson@arm.com * cache sizes at once. 878839Sandreas.hansson@arm.com */ 888839Sandreas.hansson@arm.comclass FALRU : public BaseTags 898839Sandreas.hansson@arm.com{ 908839Sandreas.hansson@arm.com public: 912995Ssaidi@eecs.umich.edu /** Typedef the block type used in this class. */ 922934Sktlim@umich.edu typedef FALRUBlk BlkType; 932934Sktlim@umich.edu 942953Sktlim@umich.edu protected: 955478Snate@binkert.org /** Array of pointers to blocks at the cache size boundaries. */ 962934Sktlim@umich.edu FALRUBlk **cacheBoundaries; 973449Shsul@eecs.umich.edu /** A mask for the FALRUBlk::inCache bits. */ 982934Sktlim@umich.edu int cacheMask; 992934Sktlim@umich.edu /** The number of different size caches being tracked. */ 1002934Sktlim@umich.edu unsigned numCaches; 1018839Sandreas.hansson@arm.com 1028706Sandreas.hansson@arm.com /** The cache blocks. */ 1032934Sktlim@umich.edu FALRUBlk *blks; 1042934Sktlim@umich.edu 1059826Sandreas.hansson@arm.com /** The MRU block. */ 1066765SBrad.Beckmann@amd.com FALRUBlk *head; 1076765SBrad.Beckmann@amd.com /** The LRU block. */ 1086765SBrad.Beckmann@amd.com FALRUBlk *tail; 1096765SBrad.Beckmann@amd.com 1109826Sandreas.hansson@arm.com /** Hash table type mapping addresses to cache block pointers. */ 1119826Sandreas.hansson@arm.com typedef std::unordered_map<Addr, FALRUBlk *, std::hash<Addr> > hash_t; 1126765SBrad.Beckmann@amd.com /** Iterator into the address hash table. */ 1136765SBrad.Beckmann@amd.com typedef hash_t::const_iterator tagIterator; 1146765SBrad.Beckmann@amd.com 1156765SBrad.Beckmann@amd.com /** The address hash table. */ 1166765SBrad.Beckmann@amd.com hash_t tagHash; 1176765SBrad.Beckmann@amd.com 1189036Sandreas.hansson@arm.com /** 1196893SBrad.Beckmann@amd.com * Find the cache block for the given address. 1206765SBrad.Beckmann@amd.com * @param addr The address to find. 1216765SBrad.Beckmann@amd.com * @return The cache block of the address, if any. 1226765SBrad.Beckmann@amd.com */ 1236765SBrad.Beckmann@amd.com FALRUBlk * hashLookup(Addr addr) const; 1246765SBrad.Beckmann@amd.com 1256765SBrad.Beckmann@amd.com /** 1268839Sandreas.hansson@arm.com * Move a cache block to the MRU position. 1278839Sandreas.hansson@arm.com * @param blk The block to promote. 1288839Sandreas.hansson@arm.com */ 1298839Sandreas.hansson@arm.com void moveToHead(FALRUBlk *blk); 1306765SBrad.Beckmann@amd.com 1316893SBrad.Beckmann@amd.com /** 1327633SBrad.Beckmann@amd.com * Check to make sure all the cache boundaries are still where they should 1337633SBrad.Beckmann@amd.com * be. Used for debugging. 1346893SBrad.Beckmann@amd.com * @return True if everything is correct. 1358929Snilay@cs.wisc.edu */ 1366765SBrad.Beckmann@amd.com bool check(); 1376765SBrad.Beckmann@amd.com 1386765SBrad.Beckmann@amd.com /** 1396765SBrad.Beckmann@amd.com * @defgroup FALRUStats Fully Associative LRU specific statistics 1406765SBrad.Beckmann@amd.com * The FA lru stack lets us track multiple cache sizes at once. These 1416765SBrad.Beckmann@amd.com * statistics track the hits and misses for different cache sizes. 1426765SBrad.Beckmann@amd.com * @{ 1436765SBrad.Beckmann@amd.com */ 1446765SBrad.Beckmann@amd.com 1456765SBrad.Beckmann@amd.com /** Hits in each cache size >= 128K. */ 1466765SBrad.Beckmann@amd.com Stats::Vector hits; 1476765SBrad.Beckmann@amd.com /** Misses in each cache size >= 128K. */ 1486765SBrad.Beckmann@amd.com Stats::Vector misses; 1499826Sandreas.hansson@arm.com /** Total number of accesses. */ 1508713Sandreas.hansson@arm.com Stats::Scalar accesses; 1518713Sandreas.hansson@arm.com 1528713Sandreas.hansson@arm.com /** 1538713Sandreas.hansson@arm.com * @} 1544486Sbinkertn@umich.edu */ 1554486Sbinkertn@umich.edu 1564486Sbinkertn@umich.edupublic: 1574486Sbinkertn@umich.edu 1584486Sbinkertn@umich.edu typedef FALRUParams Params; 1594486Sbinkertn@umich.edu 1604486Sbinkertn@umich.edu /** 1613584Ssaidi@eecs.umich.edu * Construct and initialize this cache tagstore. 1623584Ssaidi@eecs.umich.edu */ 1633584Ssaidi@eecs.umich.edu FALRU(const Params *p); 1643584Ssaidi@eecs.umich.edu ~FALRU(); 1653584Ssaidi@eecs.umich.edu 1669036Sandreas.hansson@arm.com /** 1679036Sandreas.hansson@arm.com * Register the stats for this object. 1689164Sandreas.hansson@arm.com * @param name The name to prepend to the stats name. 1693743Sgblack@eecs.umich.edu */ 1704104Ssaidi@eecs.umich.edu void regStats() override; 1713743Sgblack@eecs.umich.edu 1729826Sandreas.hansson@arm.com /** 1739826Sandreas.hansson@arm.com * Invalidate a cache block. 1748839Sandreas.hansson@arm.com * @param blk The block to invalidate. 1758839Sandreas.hansson@arm.com */ 1768839Sandreas.hansson@arm.com void invalidate(CacheBlk *blk) override; 1778839Sandreas.hansson@arm.com 1788839Sandreas.hansson@arm.com /** 1798839Sandreas.hansson@arm.com * Access block and update replacement data. May not succeed, in which 1803584Ssaidi@eecs.umich.edu * case nullptr pointer is returned. This has all the implications of a 1813898Ssaidi@eecs.umich.edu * cache access and should only be used as such. 1823898Ssaidi@eecs.umich.edu * Returns the access latency and inCache flags as a side effect. 1838839Sandreas.hansson@arm.com * @param addr The address to look for. 1848713Sandreas.hansson@arm.com * @param is_secure True if the target memory space is secure. 1858713Sandreas.hansson@arm.com * @param asid The address space ID. 1868713Sandreas.hansson@arm.com * @param lat The latency of the access. 1878713Sandreas.hansson@arm.com * @param inCache The FALRUBlk::inCache flags. 1888713Sandreas.hansson@arm.com * @return Pointer to the cache block. 1898713Sandreas.hansson@arm.com */ 1908713Sandreas.hansson@arm.com CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat, 1918713Sandreas.hansson@arm.com int context_src, int *inCache); 1928713Sandreas.hansson@arm.com 1938713Sandreas.hansson@arm.com /** 1948713Sandreas.hansson@arm.com * Just a wrapper of above function to conform with the base interface. 1958713Sandreas.hansson@arm.com */ 1968713Sandreas.hansson@arm.com CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat, 1978713Sandreas.hansson@arm.com int context_src) override; 1988713Sandreas.hansson@arm.com 1998713Sandreas.hansson@arm.com /** 2008713Sandreas.hansson@arm.com * Find the block in the cache, do not update the replacement data. 2018713Sandreas.hansson@arm.com * @param addr The address to look for. 2028713Sandreas.hansson@arm.com * @param is_secure True if the target memory space is secure. 2034103Ssaidi@eecs.umich.edu * @param asid The address space ID. 2044103Ssaidi@eecs.umich.edu * @return Pointer to the cache block. 2054103Ssaidi@eecs.umich.edu */ 2063745Sgblack@eecs.umich.edu CacheBlk* findBlock(Addr addr, bool is_secure) const override; 2073745Sgblack@eecs.umich.edu 2083745Sgblack@eecs.umich.edu /** 2093584Ssaidi@eecs.umich.edu * Find a replacement block for the address provided. 2108839Sandreas.hansson@arm.com * @param pkt The request to a find a replacement candidate for. 2118706Sandreas.hansson@arm.com * @return The block to place the replacement in. 2123584Ssaidi@eecs.umich.edu */ 2133584Ssaidi@eecs.umich.edu CacheBlk* findVictim(Addr addr) override; 2149826Sandreas.hansson@arm.com 2159665Sandreas.hansson@arm.com void insertBlock(PacketPtr pkt, CacheBlk *blk) override; 2168061SAli.Saidi@ARM.com 2178061SAli.Saidi@ARM.com /** 2187586SAli.Saidi@arm.com * Find the cache block given set and way 2197586SAli.Saidi@arm.com * @param set The set of the block. 2207586SAli.Saidi@arm.com * @param way The way of the block. 2217586SAli.Saidi@arm.com * @return The cache block. 2227586SAli.Saidi@arm.com */ 2237586SAli.Saidi@arm.com CacheBlk* findBlockBySetAndWay(int set, int way) const override; 2247586SAli.Saidi@arm.com 2257586SAli.Saidi@arm.com /** 2267586SAli.Saidi@arm.com * Align an address to the block size. 2277586SAli.Saidi@arm.com * @param addr the address to align. 2289036Sandreas.hansson@arm.com * @return The aligned address. 2299036Sandreas.hansson@arm.com */ 2307586SAli.Saidi@arm.com Addr blkAlign(Addr addr) const 2319164Sandreas.hansson@arm.com { 2328839Sandreas.hansson@arm.com return (addr & ~(Addr)(blkSize-1)); 2338839Sandreas.hansson@arm.com } 2347586SAli.Saidi@arm.com 2357586SAli.Saidi@arm.com /** 2367586SAli.Saidi@arm.com * Generate the tag from the addres. For fully associative this is just the 2377586SAli.Saidi@arm.com * block address. 2387586SAli.Saidi@arm.com * @param addr The address to get the tag from. 2397586SAli.Saidi@arm.com * @return The tag. 2407586SAli.Saidi@arm.com */ 2418525SAli.Saidi@ARM.com Addr extractTag(Addr addr) const override 2428525SAli.Saidi@ARM.com { 2438870SAli.Saidi@ARM.com return blkAlign(addr); 2448870SAli.Saidi@ARM.com } 2458870SAli.Saidi@ARM.com 2467586SAli.Saidi@arm.com /** 2477586SAli.Saidi@arm.com * Return the set of an address. Only one set in a fully associative cache. 2487586SAli.Saidi@arm.com * @param addr The address to get the set from. 2497586SAli.Saidi@arm.com * @return 0. 2508528SAli.Saidi@ARM.com */ 2518528SAli.Saidi@ARM.com int extractSet(Addr addr) const override 2528528SAli.Saidi@ARM.com { 2538528SAli.Saidi@ARM.com return 0; 2548528SAli.Saidi@ARM.com } 2558528SAli.Saidi@ARM.com 2568528SAli.Saidi@ARM.com /** 2578528SAli.Saidi@ARM.com * Regenerate the block address from the tag and the set. 2588528SAli.Saidi@ARM.com * @param tag The tag of the block. 2598061SAli.Saidi@ARM.com * @param set The set the block belongs to. 2608061SAli.Saidi@ARM.com * @return the block address. 2618061SAli.Saidi@ARM.com */ 2629845SAli.Saidi@ARM.com Addr regenerateBlkAddr(Addr tag, unsigned set) const override 2639845SAli.Saidi@ARM.com { 2648061SAli.Saidi@ARM.com return (tag); 2658528SAli.Saidi@ARM.com } 2669539Satgutier@umich.edu 2679539Satgutier@umich.edu /** 2687586SAli.Saidi@arm.com * @todo Implement as in lru. Currently not used 2698894Ssaidi@eecs.umich.edu */ 2708870SAli.Saidi@ARM.com virtual std::string print() const override { return ""; } 2718870SAli.Saidi@ARM.com 2728870SAli.Saidi@ARM.com /** 2738894Ssaidi@eecs.umich.edu * Visit each block in the tag store and apply a visitor to the 2748528SAli.Saidi@ARM.com * block. 2758212SAli.Saidi@ARM.com * 2768528SAli.Saidi@ARM.com * The visitor should be a function (or object that behaves like a 2779826Sandreas.hansson@arm.com * function) that takes a cache block reference as its parameter 2789826Sandreas.hansson@arm.com * and returns a bool. A visitor can request the traversal to be 2798870SAli.Saidi@ARM.com * stopped by returning false, returning true causes it to be 2808528SAli.Saidi@ARM.com * called for the next block in the tag store. 2818528SAli.Saidi@ARM.com * 2828287SAli.Saidi@ARM.com * \param visitor Visitor to call on each block. 2838643Satgutier@umich.edu */ 2848595SAli.Saidi@ARM.com void forEachBlk(CacheBlkVisitor &visitor) override { 2858212SAli.Saidi@ARM.com for (int i = 0; i < numBlocks; i++) { 2868713Sandreas.hansson@arm.com if (!visitor(blks[i])) 2877586SAli.Saidi@arm.com return; 2887586SAli.Saidi@arm.com } 2897586SAli.Saidi@arm.com } 2907949SAli.Saidi@ARM.com 2917586SAli.Saidi@arm.com}; 2928839Sandreas.hansson@arm.com 2938706Sandreas.hansson@arm.com#endif // __MEM_CACHE_TAGS_FA_LRU_HH__ 2947586SAli.Saidi@arm.com