fa_lru.cc revision 12513:4dfc54394b5a 
1/*
2 * Copyright (c) 2013,2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Definitions a fully associative LRU tagstore.
46 */
47
48#include "mem/cache/tags/fa_lru.hh"
49
50#include <cassert>
51#include <sstream>
52
53#include "base/intmath.hh"
54#include "base/logging.hh"
55
56using namespace std;
57
58FALRU::FALRU(const Params *p)
59    : BaseTags(p), cacheBoundaries(nullptr)
60{
61    if (!isPowerOf2(blkSize))
62        fatal("cache block size (in bytes) `%d' must be a power of two",
63              blkSize);
64    if (!isPowerOf2(size))
65        fatal("Cache Size must be power of 2 for now");
66
67    // Track all cache sizes from 128K up by powers of 2
68    numCaches = floorLog2(size) - 17;
69    if (numCaches >0){
70        cacheBoundaries = new FALRUBlk *[numCaches];
71        cacheMask = (ULL(1) << numCaches) - 1;
72    } else {
73        cacheMask = 0;
74    }
75
76    numBlocks = size/blkSize;
77
78    blks = new FALRUBlk[numBlocks];
79    head = &(blks[0]);
80    tail = &(blks[numBlocks-1]);
81
82    head->prev = nullptr;
83    head->next = &(blks[1]);
84    head->inCache = cacheMask;
85
86    tail->prev = &(blks[numBlocks-2]);
87    tail->next = nullptr;
88    tail->inCache = 0;
89
90    unsigned index = (1 << 17) / blkSize;
91    unsigned j = 0;
92    int flags = cacheMask;
93    for (unsigned i = 1; i < numBlocks - 1; i++) {
94        blks[i].inCache = flags;
95        if (i == index - 1){
96            cacheBoundaries[j] = &(blks[i]);
97            flags &= ~ (1<<j);
98            ++j;
99            index = index << 1;
100        }
101        blks[i].prev = &(blks[i-1]);
102        blks[i].next = &(blks[i+1]);
103        blks[i].isTouched = false;
104        blks[i].set = 0;
105        blks[i].way = i;
106    }
107    assert(j == numCaches);
108    assert(index == numBlocks);
109    //assert(check());
110}
111
112FALRU::~FALRU()
113{
114    if (numCaches)
115        delete[] cacheBoundaries;
116
117    delete[] blks;
118}
119
120void
121FALRU::regStats()
122{
123    using namespace Stats;
124    BaseTags::regStats();
125    hits
126        .init(numCaches+1)
127        .name(name() + ".falru_hits")
128        .desc("The number of hits in each cache size.")
129        ;
130    misses
131        .init(numCaches+1)
132        .name(name() + ".falru_misses")
133        .desc("The number of misses in each cache size.")
134        ;
135    accesses
136        .name(name() + ".falru_accesses")
137        .desc("The number of accesses to the FA LRU cache.")
138        ;
139
140    for (unsigned i = 0; i <= numCaches; ++i) {
141        stringstream size_str;
142        if (i < 3){
143            size_str << (1<<(i+7)) <<"K";
144        } else {
145            size_str << (1<<(i-3)) <<"M";
146        }
147
148        hits.subname(i, size_str.str());
149        hits.subdesc(i, "Hits in a " + size_str.str() +" cache");
150        misses.subname(i, size_str.str());
151        misses.subdesc(i, "Misses in a " + size_str.str() +" cache");
152    }
153}
154
155FALRUBlk *
156FALRU::hashLookup(Addr addr) const
157{
158    tagIterator iter = tagHash.find(addr);
159    if (iter != tagHash.end()) {
160        return (*iter).second;
161    }
162    return nullptr;
163}
164
165void
166FALRU::invalidate(CacheBlk *blk)
167{
168    assert(blk);
169    tagsInUse--;
170}
171
172CacheBlk*
173FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat)
174{
175    return accessBlock(addr, is_secure, lat, 0);
176}
177
178CacheBlk*
179FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int *inCache)
180{
181    accesses++;
182    int tmp_in_cache = 0;
183    Addr blkAddr = blkAlign(addr);
184    FALRUBlk* blk = hashLookup(blkAddr);
185
186    if (blk && blk->isValid()) {
187        // If a cache hit
188        lat = accessLatency;
189        // Check if the block to be accessed is available. If not,
190        // apply the accessLatency on top of block->whenReady.
191        if (blk->whenReady > curTick() &&
192            cache->ticksToCycles(blk->whenReady - curTick()) >
193            accessLatency) {
194            lat = cache->ticksToCycles(blk->whenReady - curTick()) +
195            accessLatency;
196        }
197        assert(blk->tag == blkAddr);
198        tmp_in_cache = blk->inCache;
199        for (unsigned i = 0; i < numCaches; i++) {
200            if (1<<i & blk->inCache) {
201                hits[i]++;
202            } else {
203                misses[i]++;
204            }
205        }
206        hits[numCaches]++;
207        if (blk != head){
208            moveToHead(blk);
209        }
210    } else {
211        // If a cache miss
212        lat = lookupLatency;
213        blk = nullptr;
214        for (unsigned i = 0; i <= numCaches; ++i) {
215            misses[i]++;
216        }
217    }
218    if (inCache) {
219        *inCache = tmp_in_cache;
220    }
221
222    //assert(check());
223    return blk;
224}
225
226
227CacheBlk*
228FALRU::findBlock(Addr addr, bool is_secure) const
229{
230    Addr blkAddr = blkAlign(addr);
231    FALRUBlk* blk = hashLookup(blkAddr);
232
233    if (blk && blk->isValid()) {
234        assert(blk->tag == blkAddr);
235    } else {
236        blk = nullptr;
237    }
238    return blk;
239}
240
241CacheBlk*
242FALRU::findBlockBySetAndWay(int set, int way) const
243{
244    assert(set == 0);
245    return &blks[way];
246}
247
248CacheBlk*
249FALRU::findVictim(Addr addr)
250{
251    FALRUBlk * blk = tail;
252    assert(blk->inCache == 0);
253    moveToHead(blk);
254    tagHash.erase(blk->tag);
255    tagHash[blkAlign(addr)] = blk;
256    if (blk->isValid()) {
257        replacements[0]++;
258    } else {
259        tagsInUse++;
260        blk->isTouched = true;
261        if (!warmedUp && tagsInUse.value() >= warmupBound) {
262            warmedUp = true;
263            warmupCycle = curTick();
264        }
265    }
266    //assert(check());
267    return blk;
268}
269
270void
271FALRU::insertBlock(PacketPtr pkt, CacheBlk *blk)
272{
273}
274
275void
276FALRU::moveToHead(FALRUBlk *blk)
277{
278    int updateMask = blk->inCache ^ cacheMask;
279    for (unsigned i = 0; i < numCaches; i++){
280        if ((1<<i) & updateMask) {
281            cacheBoundaries[i]->inCache &= ~(1<<i);
282            cacheBoundaries[i] = cacheBoundaries[i]->prev;
283        } else if (cacheBoundaries[i] == blk) {
284            cacheBoundaries[i] = blk->prev;
285        }
286    }
287    blk->inCache = cacheMask;
288    if (blk != head) {
289        if (blk == tail){
290            assert(blk->next == nullptr);
291            tail = blk->prev;
292            tail->next = nullptr;
293        } else {
294            blk->prev->next = blk->next;
295            blk->next->prev = blk->prev;
296        }
297        blk->next = head;
298        blk->prev = nullptr;
299        head->prev = blk;
300        head = blk;
301    }
302}
303
304bool
305FALRU::check()
306{
307    FALRUBlk* blk = head;
308    int tot_size = 0;
309    int boundary = 1<<17;
310    int j = 0;
311    int flags = cacheMask;
312    while (blk) {
313        tot_size += blkSize;
314        if (blk->inCache != flags) {
315            return false;
316        }
317        if (tot_size == boundary && blk != tail) {
318            if (cacheBoundaries[j] != blk) {
319                return false;
320            }
321            flags &=~(1 << j);
322            boundary = boundary<<1;
323            ++j;
324        }
325        blk = blk->next;
326    }
327    return true;
328}
329
330FALRU *
331FALRUParams::create()
332{
333    return new FALRU(this);
334}
335
336